1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Support for IDE interfaces on PowerMacs.
5 * These IDE interfaces are memory-mapped and have a DBDMA channel
8 * Copyright (C) 1998-2003 Paul Mackerras & Ben. Herrenschmidt
9 * Copyright (C) 2007-2008 Bartlomiej Zolnierkiewicz
11 * Some code taken from drivers/ide/ide-dma.c:
13 * Copyright (c) 1995-1998 Mark Lord
15 * TODO: - Use pre-calculated (kauai) timing tables all the time and
16 * get rid of the "rounded" tables used previously, so we have the
17 * same table format for all controllers and can then just have one
20 #include <linux/types.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/delay.h>
24 #include <linux/ide.h>
25 #include <linux/notifier.h>
26 #include <linux/module.h>
27 #include <linux/reboot.h>
28 #include <linux/pci.h>
29 #include <linux/adb.h>
30 #include <linux/pmu.h>
31 #include <linux/scatterlist.h>
32 #include <linux/slab.h>
36 #include <asm/dbdma.h>
38 #include <asm/machdep.h>
39 #include <asm/pmac_feature.h>
40 #include <asm/sections.h>
42 #include <asm/mediabay.h>
44 #define DRV_NAME "ide-pmac"
48 #define DMA_WAIT_TIMEOUT 50
50 typedef struct pmac_ide_hwif
{
51 unsigned long regbase
;
55 unsigned broken_dma
: 1;
56 unsigned broken_dma_warn
: 1;
57 struct device_node
* node
;
58 struct macio_dev
*mdev
;
60 volatile u32 __iomem
* *kauai_fcr
;
63 /* Those fields are duplicating what is in hwif. We currently
64 * can't use the hwif ones because of some assumptions that are
65 * beeing done by the generic code about the kind of dma controller
66 * and format of the dma table. This will have to be fixed though.
68 volatile struct dbdma_regs __iomem
* dma_regs
;
69 struct dbdma_cmd
* dma_table_cpu
;
73 controller_ohare
, /* OHare based */
74 controller_heathrow
, /* Heathrow/Paddington */
75 controller_kl_ata3
, /* KeyLargo ATA-3 */
76 controller_kl_ata4
, /* KeyLargo ATA-4 */
77 controller_un_ata6
, /* UniNorth2 ATA-6 */
78 controller_k2_ata6
, /* K2 ATA-6 */
79 controller_sh_ata6
, /* Shasta ATA-6 */
82 static const char* model_name
[] = {
83 "OHare ATA", /* OHare based */
84 "Heathrow ATA", /* Heathrow/Paddington */
85 "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */
86 "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */
87 "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */
88 "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */
89 "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */
93 * Extra registers, both 32-bit little-endian
95 #define IDE_TIMING_CONFIG 0x200
96 #define IDE_INTERRUPT 0x300
98 /* Kauai (U2) ATA has different register setup */
99 #define IDE_KAUAI_PIO_CONFIG 0x200
100 #define IDE_KAUAI_ULTRA_CONFIG 0x210
101 #define IDE_KAUAI_POLL_CONFIG 0x220
104 * Timing configuration register definitions
107 /* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */
108 #define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
109 #define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
110 #define IDE_SYSCLK_NS 30 /* 33Mhz cell */
111 #define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */
113 /* 133Mhz cell, found in shasta.
114 * See comments about 100 Mhz Uninorth 2...
115 * Note that PIO_MASK and MDMA_MASK seem to overlap
117 #define TR_133_PIOREG_PIO_MASK 0xff000fff
118 #define TR_133_PIOREG_MDMA_MASK 0x00fff800
119 #define TR_133_UDMAREG_UDMA_MASK 0x0003ffff
120 #define TR_133_UDMAREG_UDMA_EN 0x00000001
122 /* 100Mhz cell, found in Uninorth 2. I don't have much infos about
123 * this one yet, it appears as a pci device (106b/0033) on uninorth
124 * internal PCI bus and it's clock is controlled like gem or fw. It
125 * appears to be an evolution of keylargo ATA4 with a timing register
126 * extended to 2 32bits registers and a similar DBDMA channel. Other
127 * registers seem to exist but I can't tell much about them.
129 * So far, I'm using pre-calculated tables for this extracted from
130 * the values used by the MacOS X driver.
132 * The "PIO" register controls PIO and MDMA timings, the "ULTRA"
133 * register controls the UDMA timings. At least, it seems bit 0
134 * of this one enables UDMA vs. MDMA, and bits 4..7 are the
135 * cycle time in units of 10ns. Bits 8..15 are used by I don't
136 * know their meaning yet
138 #define TR_100_PIOREG_PIO_MASK 0xff000fff
139 #define TR_100_PIOREG_MDMA_MASK 0x00fff000
140 #define TR_100_UDMAREG_UDMA_MASK 0x0000ffff
141 #define TR_100_UDMAREG_UDMA_EN 0x00000001
144 /* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
145 * 40 connector cable and to 4 on 80 connector one.
146 * Clock unit is 15ns (66Mhz)
148 * 3 Values can be programmed:
149 * - Write data setup, which appears to match the cycle time. They
150 * also call it DIOW setup.
151 * - Ready to pause time (from spec)
152 * - Address setup. That one is weird. I don't see where exactly
153 * it fits in UDMA cycles, I got it's name from an obscure piece
154 * of commented out code in Darwin. They leave it to 0, we do as
155 * well, despite a comment that would lead to think it has a
157 * Apple also add 60ns to the write data setup (or cycle time ?) on
160 #define TR_66_UDMA_MASK 0xfff00000
161 #define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */
162 #define TR_66_UDMA_ADDRSETUP_MASK 0xe0000000 /* Address setup */
163 #define TR_66_UDMA_ADDRSETUP_SHIFT 29
164 #define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */
165 #define TR_66_UDMA_RDY2PAUS_SHIFT 25
166 #define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */
167 #define TR_66_UDMA_WRDATASETUP_SHIFT 21
168 #define TR_66_MDMA_MASK 0x000ffc00
169 #define TR_66_MDMA_RECOVERY_MASK 0x000f8000
170 #define TR_66_MDMA_RECOVERY_SHIFT 15
171 #define TR_66_MDMA_ACCESS_MASK 0x00007c00
172 #define TR_66_MDMA_ACCESS_SHIFT 10
173 #define TR_66_PIO_MASK 0x000003ff
174 #define TR_66_PIO_RECOVERY_MASK 0x000003e0
175 #define TR_66_PIO_RECOVERY_SHIFT 5
176 #define TR_66_PIO_ACCESS_MASK 0x0000001f
177 #define TR_66_PIO_ACCESS_SHIFT 0
179 /* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo
180 * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
182 * The access time and recovery time can be programmed. Some older
183 * Darwin code base limit OHare to 150ns cycle time. I decided to do
184 * the same here fore safety against broken old hardware ;)
185 * The HalfTick bit, when set, adds half a clock (15ns) to the access
186 * time and removes one from recovery. It's not supported on KeyLargo
187 * implementation afaik. The E bit appears to be set for PIO mode 0 and
188 * is used to reach long timings used in this mode.
190 #define TR_33_MDMA_MASK 0x003ff800
191 #define TR_33_MDMA_RECOVERY_MASK 0x001f0000
192 #define TR_33_MDMA_RECOVERY_SHIFT 16
193 #define TR_33_MDMA_ACCESS_MASK 0x0000f800
194 #define TR_33_MDMA_ACCESS_SHIFT 11
195 #define TR_33_MDMA_HALFTICK 0x00200000
196 #define TR_33_PIO_MASK 0x000007ff
197 #define TR_33_PIO_E 0x00000400
198 #define TR_33_PIO_RECOVERY_MASK 0x000003e0
199 #define TR_33_PIO_RECOVERY_SHIFT 5
200 #define TR_33_PIO_ACCESS_MASK 0x0000001f
201 #define TR_33_PIO_ACCESS_SHIFT 0
204 * Interrupt register definitions
206 #define IDE_INTR_DMA 0x80000000
207 #define IDE_INTR_DEVICE 0x40000000
210 * FCR Register on Kauai. Not sure what bit 0x4 is ...
212 #define KAUAI_FCR_UATA_MAGIC 0x00000004
213 #define KAUAI_FCR_UATA_RESET_N 0x00000002
214 #define KAUAI_FCR_UATA_ENABLE 0x00000001
216 /* Rounded Multiword DMA timings
218 * I gave up finding a generic formula for all controller
219 * types and instead, built tables based on timing values
220 * used by Apple in Darwin's implementation.
222 struct mdma_timings_t
{
228 struct mdma_timings_t mdma_timings_33
[] =
241 struct mdma_timings_t mdma_timings_33k
[] =
254 struct mdma_timings_t mdma_timings_66
[] =
267 /* KeyLargo ATA-4 Ultra DMA timings (rounded) */
269 int addrSetup
; /* ??? */
272 } kl66_udma_timings
[] =
274 { 0, 180, 120 }, /* Mode 0 */
275 { 0, 150, 90 }, /* 1 */
276 { 0, 120, 60 }, /* 2 */
277 { 0, 90, 45 }, /* 3 */
278 { 0, 90, 30 } /* 4 */
281 /* UniNorth 2 ATA/100 timings */
282 struct kauai_timing
{
287 static struct kauai_timing kauai_pio_timings
[] =
289 { 930 , 0x08000fff },
290 { 600 , 0x08000a92 },
291 { 383 , 0x0800060f },
292 { 360 , 0x08000492 },
293 { 330 , 0x0800048f },
294 { 300 , 0x080003cf },
295 { 270 , 0x080003cc },
296 { 240 , 0x0800038b },
297 { 239 , 0x0800030c },
298 { 180 , 0x05000249 },
299 { 120 , 0x04000148 },
303 static struct kauai_timing kauai_mdma_timings
[] =
305 { 1260 , 0x00fff000 },
306 { 480 , 0x00618000 },
307 { 360 , 0x00492000 },
308 { 270 , 0x0038e000 },
309 { 240 , 0x0030c000 },
310 { 210 , 0x002cb000 },
311 { 180 , 0x00249000 },
312 { 150 , 0x00209000 },
313 { 120 , 0x00148000 },
317 static struct kauai_timing kauai_udma_timings
[] =
319 { 120 , 0x000070c0 },
328 static struct kauai_timing shasta_pio_timings
[] =
330 { 930 , 0x08000fff },
331 { 600 , 0x0A000c97 },
332 { 383 , 0x07000712 },
333 { 360 , 0x040003cd },
334 { 330 , 0x040003cd },
335 { 300 , 0x040003cd },
336 { 270 , 0x040003cd },
337 { 240 , 0x040003cd },
338 { 239 , 0x040003cd },
339 { 180 , 0x0400028b },
340 { 120 , 0x0400010a },
344 static struct kauai_timing shasta_mdma_timings
[] =
346 { 1260 , 0x00fff000 },
347 { 480 , 0x00820800 },
348 { 360 , 0x00820800 },
349 { 270 , 0x00820800 },
350 { 240 , 0x00820800 },
351 { 210 , 0x00820800 },
352 { 180 , 0x00820800 },
353 { 150 , 0x0028b000 },
354 { 120 , 0x001ca000 },
358 static struct kauai_timing shasta_udma133_timings
[] =
360 { 120 , 0x00035901, },
361 { 90 , 0x000348b1, },
362 { 60 , 0x00033881, },
363 { 45 , 0x00033861, },
364 { 30 , 0x00033841, },
365 { 20 , 0x00033031, },
366 { 15 , 0x00033021, },
372 kauai_lookup_timing(struct kauai_timing
* table
, int cycle_time
)
376 for (i
=0; table
[i
].cycle_time
; i
++)
377 if (cycle_time
> table
[i
+1].cycle_time
)
378 return table
[i
].timing_reg
;
383 /* allow up to 256 DBDMA commands per xfer */
384 #define MAX_DCMDS 256
387 * Wait 1s for disk to answer on IDE bus after a hard reset
388 * of the device (via GPIO/FCR).
390 * Some devices seem to "pollute" the bus even after dropping
391 * the BSY bit (typically some combo drives slave on the UDMA
392 * bus) after a hard reset. Since we hard reset all drives on
393 * KeyLargo ATA66, we have to keep that delay around. I may end
394 * up not hard resetting anymore on these and keep the delay only
395 * for older interfaces instead (we have to reset when coming
396 * from MacOS...) --BenH.
398 #define IDE_WAKEUP_DELAY (1*HZ)
400 static int pmac_ide_init_dma(ide_hwif_t
*, const struct ide_port_info
*);
402 #define PMAC_IDE_REG(x) \
403 ((void __iomem *)((drive)->hwif->io_ports.data_addr + (x)))
406 * Apply the timings of the proper unit (master/slave) to the shared
407 * timing register when selecting that unit. This version is for
408 * ASICs with a single timing register
410 static void pmac_ide_apply_timings(ide_drive_t
*drive
)
412 ide_hwif_t
*hwif
= drive
->hwif
;
413 pmac_ide_hwif_t
*pmif
= dev_get_drvdata(hwif
->gendev
.parent
);
416 writel(pmif
->timings
[1], PMAC_IDE_REG(IDE_TIMING_CONFIG
));
418 writel(pmif
->timings
[0], PMAC_IDE_REG(IDE_TIMING_CONFIG
));
419 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG
));
423 * Apply the timings of the proper unit (master/slave) to the shared
424 * timing register when selecting that unit. This version is for
425 * ASICs with a dual timing register (Kauai)
427 static void pmac_ide_kauai_apply_timings(ide_drive_t
*drive
)
429 ide_hwif_t
*hwif
= drive
->hwif
;
430 pmac_ide_hwif_t
*pmif
= dev_get_drvdata(hwif
->gendev
.parent
);
433 writel(pmif
->timings
[1], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG
));
434 writel(pmif
->timings
[3], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG
));
436 writel(pmif
->timings
[0], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG
));
437 writel(pmif
->timings
[2], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG
));
439 (void)readl(PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG
));
443 * Force an update of controller timing values for a given drive
446 pmac_ide_do_update_timings(ide_drive_t
*drive
)
448 ide_hwif_t
*hwif
= drive
->hwif
;
449 pmac_ide_hwif_t
*pmif
= dev_get_drvdata(hwif
->gendev
.parent
);
451 if (pmif
->kind
== controller_sh_ata6
||
452 pmif
->kind
== controller_un_ata6
||
453 pmif
->kind
== controller_k2_ata6
)
454 pmac_ide_kauai_apply_timings(drive
);
456 pmac_ide_apply_timings(drive
);
459 static void pmac_dev_select(ide_drive_t
*drive
)
461 pmac_ide_apply_timings(drive
);
463 writeb(drive
->select
| ATA_DEVICE_OBS
,
464 (void __iomem
*)drive
->hwif
->io_ports
.device_addr
);
467 static void pmac_kauai_dev_select(ide_drive_t
*drive
)
469 pmac_ide_kauai_apply_timings(drive
);
471 writeb(drive
->select
| ATA_DEVICE_OBS
,
472 (void __iomem
*)drive
->hwif
->io_ports
.device_addr
);
475 static void pmac_exec_command(ide_hwif_t
*hwif
, u8 cmd
)
477 writeb(cmd
, (void __iomem
*)hwif
->io_ports
.command_addr
);
478 (void)readl((void __iomem
*)(hwif
->io_ports
.data_addr
479 + IDE_TIMING_CONFIG
));
482 static void pmac_write_devctl(ide_hwif_t
*hwif
, u8 ctl
)
484 writeb(ctl
, (void __iomem
*)hwif
->io_ports
.ctl_addr
);
485 (void)readl((void __iomem
*)(hwif
->io_ports
.data_addr
486 + IDE_TIMING_CONFIG
));
490 * Old tuning functions (called on hdparm -p), sets up drive PIO timings
492 static void pmac_ide_set_pio_mode(ide_hwif_t
*hwif
, ide_drive_t
*drive
)
494 pmac_ide_hwif_t
*pmif
= dev_get_drvdata(hwif
->gendev
.parent
);
495 const u8 pio
= drive
->pio_mode
- XFER_PIO_0
;
496 struct ide_timing
*tim
= ide_timing_find_mode(XFER_PIO_0
+ pio
);
498 unsigned accessTicks
, recTicks
;
499 unsigned accessTime
, recTime
;
500 unsigned int cycle_time
;
502 /* which drive is it ? */
503 timings
= &pmif
->timings
[drive
->dn
& 1];
506 cycle_time
= ide_pio_cycle_time(drive
, pio
);
508 switch (pmif
->kind
) {
509 case controller_sh_ata6
: {
511 u32 tr
= kauai_lookup_timing(shasta_pio_timings
, cycle_time
);
512 t
= (t
& ~TR_133_PIOREG_PIO_MASK
) | tr
;
515 case controller_un_ata6
:
516 case controller_k2_ata6
: {
518 u32 tr
= kauai_lookup_timing(kauai_pio_timings
, cycle_time
);
519 t
= (t
& ~TR_100_PIOREG_PIO_MASK
) | tr
;
522 case controller_kl_ata4
:
524 recTime
= cycle_time
- tim
->active
- tim
->setup
;
525 recTime
= max(recTime
, 150U);
526 accessTime
= tim
->active
;
527 accessTime
= max(accessTime
, 150U);
528 accessTicks
= SYSCLK_TICKS_66(accessTime
);
529 accessTicks
= min(accessTicks
, 0x1fU
);
530 recTicks
= SYSCLK_TICKS_66(recTime
);
531 recTicks
= min(recTicks
, 0x1fU
);
532 t
= (t
& ~TR_66_PIO_MASK
) |
533 (accessTicks
<< TR_66_PIO_ACCESS_SHIFT
) |
534 (recTicks
<< TR_66_PIO_RECOVERY_SHIFT
);
539 recTime
= cycle_time
- tim
->active
- tim
->setup
;
540 recTime
= max(recTime
, 150U);
541 accessTime
= tim
->active
;
542 accessTime
= max(accessTime
, 150U);
543 accessTicks
= SYSCLK_TICKS(accessTime
);
544 accessTicks
= min(accessTicks
, 0x1fU
);
545 accessTicks
= max(accessTicks
, 4U);
546 recTicks
= SYSCLK_TICKS(recTime
);
547 recTicks
= min(recTicks
, 0x1fU
);
548 recTicks
= max(recTicks
, 5U) - 4;
550 recTicks
--; /* guess, but it's only for PIO0, so... */
553 t
= (t
& ~TR_33_PIO_MASK
) |
554 (accessTicks
<< TR_33_PIO_ACCESS_SHIFT
) |
555 (recTicks
<< TR_33_PIO_RECOVERY_SHIFT
);
562 #ifdef IDE_PMAC_DEBUG
563 printk(KERN_ERR
"%s: Set PIO timing for mode %d, reg: 0x%08x\n",
564 drive
->name
, pio
, *timings
);
568 pmac_ide_do_update_timings(drive
);
572 * Calculate KeyLargo ATA/66 UDMA timings
575 set_timings_udma_ata4(u32
*timings
, u8 speed
)
577 unsigned rdyToPauseTicks
, wrDataSetupTicks
, addrTicks
;
579 if (speed
> XFER_UDMA_4
)
582 rdyToPauseTicks
= SYSCLK_TICKS_66(kl66_udma_timings
[speed
& 0xf].rdy2pause
);
583 wrDataSetupTicks
= SYSCLK_TICKS_66(kl66_udma_timings
[speed
& 0xf].wrDataSetup
);
584 addrTicks
= SYSCLK_TICKS_66(kl66_udma_timings
[speed
& 0xf].addrSetup
);
586 *timings
= ((*timings
) & ~(TR_66_UDMA_MASK
| TR_66_MDMA_MASK
)) |
587 (wrDataSetupTicks
<< TR_66_UDMA_WRDATASETUP_SHIFT
) |
588 (rdyToPauseTicks
<< TR_66_UDMA_RDY2PAUS_SHIFT
) |
589 (addrTicks
<<TR_66_UDMA_ADDRSETUP_SHIFT
) |
591 #ifdef IDE_PMAC_DEBUG
592 printk(KERN_ERR
"ide_pmac: Set UDMA timing for mode %d, reg: 0x%08x\n",
593 speed
& 0xf, *timings
);
600 * Calculate Kauai ATA/100 UDMA timings
603 set_timings_udma_ata6(u32
*pio_timings
, u32
*ultra_timings
, u8 speed
)
605 struct ide_timing
*t
= ide_timing_find_mode(speed
);
608 if (speed
> XFER_UDMA_5
|| t
== NULL
)
610 tr
= kauai_lookup_timing(kauai_udma_timings
, (int)t
->udma
);
611 *ultra_timings
= ((*ultra_timings
) & ~TR_100_UDMAREG_UDMA_MASK
) | tr
;
612 *ultra_timings
= (*ultra_timings
) | TR_100_UDMAREG_UDMA_EN
;
618 * Calculate Shasta ATA/133 UDMA timings
621 set_timings_udma_shasta(u32
*pio_timings
, u32
*ultra_timings
, u8 speed
)
623 struct ide_timing
*t
= ide_timing_find_mode(speed
);
626 if (speed
> XFER_UDMA_6
|| t
== NULL
)
628 tr
= kauai_lookup_timing(shasta_udma133_timings
, (int)t
->udma
);
629 *ultra_timings
= ((*ultra_timings
) & ~TR_133_UDMAREG_UDMA_MASK
) | tr
;
630 *ultra_timings
= (*ultra_timings
) | TR_133_UDMAREG_UDMA_EN
;
636 * Calculate MDMA timings for all cells
639 set_timings_mdma(ide_drive_t
*drive
, int intf_type
, u32
*timings
, u32
*timings2
,
643 int cycleTime
, accessTime
= 0, recTime
= 0;
644 unsigned accessTicks
, recTicks
;
645 struct mdma_timings_t
* tm
= NULL
;
648 /* Get default cycle time for mode */
649 switch(speed
& 0xf) {
650 case 0: cycleTime
= 480; break;
651 case 1: cycleTime
= 150; break;
652 case 2: cycleTime
= 120; break;
658 /* Check if drive provides explicit DMA cycle time */
659 if ((id
[ATA_ID_FIELD_VALID
] & 2) && id
[ATA_ID_EIDE_DMA_TIME
])
660 cycleTime
= max_t(int, id
[ATA_ID_EIDE_DMA_TIME
], cycleTime
);
662 /* OHare limits according to some old Apple sources */
663 if ((intf_type
== controller_ohare
) && (cycleTime
< 150))
665 /* Get the proper timing array for this controller */
667 case controller_sh_ata6
:
668 case controller_un_ata6
:
669 case controller_k2_ata6
:
671 case controller_kl_ata4
:
672 tm
= mdma_timings_66
;
674 case controller_kl_ata3
:
675 tm
= mdma_timings_33k
;
678 tm
= mdma_timings_33
;
682 /* Lookup matching access & recovery times */
685 if (tm
[i
+1].cycleTime
< cycleTime
)
689 cycleTime
= tm
[i
].cycleTime
;
690 accessTime
= tm
[i
].accessTime
;
691 recTime
= tm
[i
].recoveryTime
;
693 #ifdef IDE_PMAC_DEBUG
694 printk(KERN_ERR
"%s: MDMA, cycleTime: %d, accessTime: %d, recTime: %d\n",
695 drive
->name
, cycleTime
, accessTime
, recTime
);
699 case controller_sh_ata6
: {
701 u32 tr
= kauai_lookup_timing(shasta_mdma_timings
, cycleTime
);
702 *timings
= ((*timings
) & ~TR_133_PIOREG_MDMA_MASK
) | tr
;
703 *timings2
= (*timings2
) & ~TR_133_UDMAREG_UDMA_EN
;
706 case controller_un_ata6
:
707 case controller_k2_ata6
: {
709 u32 tr
= kauai_lookup_timing(kauai_mdma_timings
, cycleTime
);
710 *timings
= ((*timings
) & ~TR_100_PIOREG_MDMA_MASK
) | tr
;
711 *timings2
= (*timings2
) & ~TR_100_UDMAREG_UDMA_EN
;
714 case controller_kl_ata4
:
716 accessTicks
= SYSCLK_TICKS_66(accessTime
);
717 accessTicks
= min(accessTicks
, 0x1fU
);
718 accessTicks
= max(accessTicks
, 0x1U
);
719 recTicks
= SYSCLK_TICKS_66(recTime
);
720 recTicks
= min(recTicks
, 0x1fU
);
721 recTicks
= max(recTicks
, 0x3U
);
722 /* Clear out mdma bits and disable udma */
723 *timings
= ((*timings
) & ~(TR_66_MDMA_MASK
| TR_66_UDMA_MASK
)) |
724 (accessTicks
<< TR_66_MDMA_ACCESS_SHIFT
) |
725 (recTicks
<< TR_66_MDMA_RECOVERY_SHIFT
);
727 case controller_kl_ata3
:
728 /* 33Mhz cell on KeyLargo */
729 accessTicks
= SYSCLK_TICKS(accessTime
);
730 accessTicks
= max(accessTicks
, 1U);
731 accessTicks
= min(accessTicks
, 0x1fU
);
732 accessTime
= accessTicks
* IDE_SYSCLK_NS
;
733 recTicks
= SYSCLK_TICKS(recTime
);
734 recTicks
= max(recTicks
, 1U);
735 recTicks
= min(recTicks
, 0x1fU
);
736 *timings
= ((*timings
) & ~TR_33_MDMA_MASK
) |
737 (accessTicks
<< TR_33_MDMA_ACCESS_SHIFT
) |
738 (recTicks
<< TR_33_MDMA_RECOVERY_SHIFT
);
741 /* 33Mhz cell on others */
743 int origAccessTime
= accessTime
;
744 int origRecTime
= recTime
;
746 accessTicks
= SYSCLK_TICKS(accessTime
);
747 accessTicks
= max(accessTicks
, 1U);
748 accessTicks
= min(accessTicks
, 0x1fU
);
749 accessTime
= accessTicks
* IDE_SYSCLK_NS
;
750 recTicks
= SYSCLK_TICKS(recTime
);
751 recTicks
= max(recTicks
, 2U) - 1;
752 recTicks
= min(recTicks
, 0x1fU
);
753 recTime
= (recTicks
+ 1) * IDE_SYSCLK_NS
;
754 if ((accessTicks
> 1) &&
755 ((accessTime
- IDE_SYSCLK_NS
/2) >= origAccessTime
) &&
756 ((recTime
- IDE_SYSCLK_NS
/2) >= origRecTime
)) {
760 *timings
= ((*timings
) & ~TR_33_MDMA_MASK
) |
761 (accessTicks
<< TR_33_MDMA_ACCESS_SHIFT
) |
762 (recTicks
<< TR_33_MDMA_RECOVERY_SHIFT
);
764 *timings
|= TR_33_MDMA_HALFTICK
;
767 #ifdef IDE_PMAC_DEBUG
768 printk(KERN_ERR
"%s: Set MDMA timing for mode %d, reg: 0x%08x\n",
769 drive
->name
, speed
& 0xf, *timings
);
773 static void pmac_ide_set_dma_mode(ide_hwif_t
*hwif
, ide_drive_t
*drive
)
775 pmac_ide_hwif_t
*pmif
= dev_get_drvdata(hwif
->gendev
.parent
);
777 u32
*timings
, *timings2
, tl
[2];
778 u8 unit
= drive
->dn
& 1;
779 const u8 speed
= drive
->dma_mode
;
781 timings
= &pmif
->timings
[unit
];
782 timings2
= &pmif
->timings
[unit
+2];
784 /* Copy timings to local image */
788 if (speed
>= XFER_UDMA_0
) {
789 if (pmif
->kind
== controller_kl_ata4
)
790 ret
= set_timings_udma_ata4(&tl
[0], speed
);
791 else if (pmif
->kind
== controller_un_ata6
792 || pmif
->kind
== controller_k2_ata6
)
793 ret
= set_timings_udma_ata6(&tl
[0], &tl
[1], speed
);
794 else if (pmif
->kind
== controller_sh_ata6
)
795 ret
= set_timings_udma_shasta(&tl
[0], &tl
[1], speed
);
799 set_timings_mdma(drive
, pmif
->kind
, &tl
[0], &tl
[1], speed
);
804 /* Apply timings to controller */
808 pmac_ide_do_update_timings(drive
);
812 * Blast some well known "safe" values to the timing registers at init or
813 * wakeup from sleep time, before we do real calculation
816 sanitize_timings(pmac_ide_hwif_t
*pmif
)
818 unsigned int value
, value2
= 0;
821 case controller_sh_ata6
:
825 case controller_un_ata6
:
826 case controller_k2_ata6
:
830 case controller_kl_ata4
:
833 case controller_kl_ata3
:
836 case controller_heathrow
:
837 case controller_ohare
:
842 pmif
->timings
[0] = pmif
->timings
[1] = value
;
843 pmif
->timings
[2] = pmif
->timings
[3] = value2
;
846 static int on_media_bay(pmac_ide_hwif_t
*pmif
)
848 return pmif
->mdev
&& pmif
->mdev
->media_bay
!= NULL
;
851 /* Suspend call back, should be called after the child devices
852 * have actually been suspended
854 static int pmac_ide_do_suspend(pmac_ide_hwif_t
*pmif
)
856 /* We clear the timings */
857 pmif
->timings
[0] = 0;
858 pmif
->timings
[1] = 0;
860 disable_irq(pmif
->irq
);
862 /* The media bay will handle itself just fine */
863 if (on_media_bay(pmif
))
866 /* Kauai has bus control FCRs directly here */
867 if (pmif
->kauai_fcr
) {
868 u32 fcr
= readl(pmif
->kauai_fcr
);
869 fcr
&= ~(KAUAI_FCR_UATA_RESET_N
| KAUAI_FCR_UATA_ENABLE
);
870 writel(fcr
, pmif
->kauai_fcr
);
873 /* Disable the bus on older machines and the cell on kauai */
874 ppc_md
.feature_call(PMAC_FTR_IDE_ENABLE
, pmif
->node
, pmif
->aapl_bus_id
,
880 /* Resume call back, should be called before the child devices
883 static int pmac_ide_do_resume(pmac_ide_hwif_t
*pmif
)
885 /* Hard reset & re-enable controller (do we really need to reset ? -BenH) */
886 if (!on_media_bay(pmif
)) {
887 ppc_md
.feature_call(PMAC_FTR_IDE_RESET
, pmif
->node
, pmif
->aapl_bus_id
, 1);
888 ppc_md
.feature_call(PMAC_FTR_IDE_ENABLE
, pmif
->node
, pmif
->aapl_bus_id
, 1);
890 ppc_md
.feature_call(PMAC_FTR_IDE_RESET
, pmif
->node
, pmif
->aapl_bus_id
, 0);
892 /* Kauai has it different */
893 if (pmif
->kauai_fcr
) {
894 u32 fcr
= readl(pmif
->kauai_fcr
);
895 fcr
|= KAUAI_FCR_UATA_RESET_N
| KAUAI_FCR_UATA_ENABLE
;
896 writel(fcr
, pmif
->kauai_fcr
);
899 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY
));
902 /* Sanitize drive timings */
903 sanitize_timings(pmif
);
905 enable_irq(pmif
->irq
);
910 static u8
pmac_ide_cable_detect(ide_hwif_t
*hwif
)
912 pmac_ide_hwif_t
*pmif
= dev_get_drvdata(hwif
->gendev
.parent
);
913 struct device_node
*np
= pmif
->node
;
914 const char *cable
= of_get_property(np
, "cable-type", NULL
);
915 struct device_node
*root
= of_find_node_by_path("/");
916 const char *model
= of_get_property(root
, "model", NULL
);
919 /* Get cable type from device-tree. */
920 if (cable
&& !strncmp(cable
, "80-", 3)) {
921 /* Some drives fail to detect 80c cable in PowerBook */
922 /* These machine use proprietary short IDE cable anyway */
923 if (!strncmp(model
, "PowerBook", 9))
924 return ATA_CBL_PATA40_SHORT
;
926 return ATA_CBL_PATA80
;
930 * G5's seem to have incorrect cable type in device-tree.
931 * Let's assume they have a 80 conductor cable, this seem
932 * to be always the case unless the user mucked around.
934 if (of_device_is_compatible(np
, "K2-UATA") ||
935 of_device_is_compatible(np
, "shasta-ata"))
936 return ATA_CBL_PATA80
;
938 return ATA_CBL_PATA40
;
941 static void pmac_ide_init_dev(ide_drive_t
*drive
)
943 ide_hwif_t
*hwif
= drive
->hwif
;
944 pmac_ide_hwif_t
*pmif
= dev_get_drvdata(hwif
->gendev
.parent
);
946 if (on_media_bay(pmif
)) {
947 if (check_media_bay(pmif
->mdev
->media_bay
) == MB_CD
) {
948 drive
->dev_flags
&= ~IDE_DFLAG_NOPROBE
;
951 drive
->dev_flags
|= IDE_DFLAG_NOPROBE
;
955 static const struct ide_tp_ops pmac_tp_ops
= {
956 .exec_command
= pmac_exec_command
,
957 .read_status
= ide_read_status
,
958 .read_altstatus
= ide_read_altstatus
,
959 .write_devctl
= pmac_write_devctl
,
961 .dev_select
= pmac_dev_select
,
962 .tf_load
= ide_tf_load
,
963 .tf_read
= ide_tf_read
,
965 .input_data
= ide_input_data
,
966 .output_data
= ide_output_data
,
969 static const struct ide_tp_ops pmac_ata6_tp_ops
= {
970 .exec_command
= pmac_exec_command
,
971 .read_status
= ide_read_status
,
972 .read_altstatus
= ide_read_altstatus
,
973 .write_devctl
= pmac_write_devctl
,
975 .dev_select
= pmac_kauai_dev_select
,
976 .tf_load
= ide_tf_load
,
977 .tf_read
= ide_tf_read
,
979 .input_data
= ide_input_data
,
980 .output_data
= ide_output_data
,
983 static const struct ide_port_ops pmac_ide_ata4_port_ops
= {
984 .init_dev
= pmac_ide_init_dev
,
985 .set_pio_mode
= pmac_ide_set_pio_mode
,
986 .set_dma_mode
= pmac_ide_set_dma_mode
,
987 .cable_detect
= pmac_ide_cable_detect
,
990 static const struct ide_port_ops pmac_ide_port_ops
= {
991 .init_dev
= pmac_ide_init_dev
,
992 .set_pio_mode
= pmac_ide_set_pio_mode
,
993 .set_dma_mode
= pmac_ide_set_dma_mode
,
996 static const struct ide_dma_ops pmac_dma_ops
;
998 static const struct ide_port_info pmac_port_info
= {
1000 .init_dma
= pmac_ide_init_dma
,
1001 .chipset
= ide_pmac
,
1002 .tp_ops
= &pmac_tp_ops
,
1003 .port_ops
= &pmac_ide_port_ops
,
1004 .dma_ops
= &pmac_dma_ops
,
1005 .host_flags
= IDE_HFLAG_SET_PIO_MODE_KEEP_DMA
|
1006 IDE_HFLAG_POST_SET_MODE
|
1008 IDE_HFLAG_UNMASK_IRQS
,
1009 .pio_mask
= ATA_PIO4
,
1010 .mwdma_mask
= ATA_MWDMA2
,
1014 * Setup, register & probe an IDE channel driven by this driver, this is
1015 * called by one of the 2 probe functions (macio or PCI).
1017 static int pmac_ide_setup_device(pmac_ide_hwif_t
*pmif
, struct ide_hw
*hw
)
1019 struct device_node
*np
= pmif
->node
;
1021 struct ide_host
*host
;
1023 struct ide_hw
*hws
[] = { hw
};
1024 struct ide_port_info d
= pmac_port_info
;
1027 pmif
->broken_dma
= pmif
->broken_dma_warn
= 0;
1028 if (of_device_is_compatible(np
, "shasta-ata")) {
1029 pmif
->kind
= controller_sh_ata6
;
1030 d
.tp_ops
= &pmac_ata6_tp_ops
;
1031 d
.port_ops
= &pmac_ide_ata4_port_ops
;
1032 d
.udma_mask
= ATA_UDMA6
;
1033 } else if (of_device_is_compatible(np
, "kauai-ata")) {
1034 pmif
->kind
= controller_un_ata6
;
1035 d
.tp_ops
= &pmac_ata6_tp_ops
;
1036 d
.port_ops
= &pmac_ide_ata4_port_ops
;
1037 d
.udma_mask
= ATA_UDMA5
;
1038 } else if (of_device_is_compatible(np
, "K2-UATA")) {
1039 pmif
->kind
= controller_k2_ata6
;
1040 d
.tp_ops
= &pmac_ata6_tp_ops
;
1041 d
.port_ops
= &pmac_ide_ata4_port_ops
;
1042 d
.udma_mask
= ATA_UDMA5
;
1043 } else if (of_device_is_compatible(np
, "keylargo-ata")) {
1044 if (of_node_name_eq(np
, "ata-4")) {
1045 pmif
->kind
= controller_kl_ata4
;
1046 d
.port_ops
= &pmac_ide_ata4_port_ops
;
1047 d
.udma_mask
= ATA_UDMA4
;
1049 pmif
->kind
= controller_kl_ata3
;
1050 } else if (of_device_is_compatible(np
, "heathrow-ata")) {
1051 pmif
->kind
= controller_heathrow
;
1053 pmif
->kind
= controller_ohare
;
1054 pmif
->broken_dma
= 1;
1057 bidp
= of_get_property(np
, "AAPL,bus-id", NULL
);
1058 pmif
->aapl_bus_id
= bidp
? *bidp
: 0;
1060 /* On Kauai-type controllers, we make sure the FCR is correct */
1061 if (pmif
->kauai_fcr
)
1062 writel(KAUAI_FCR_UATA_MAGIC
|
1063 KAUAI_FCR_UATA_RESET_N
|
1064 KAUAI_FCR_UATA_ENABLE
, pmif
->kauai_fcr
);
1066 /* Make sure we have sane timings */
1067 sanitize_timings(pmif
);
1069 /* If we are on a media bay, wait for it to settle and lock it */
1071 lock_media_bay(pmif
->mdev
->media_bay
);
1073 host
= ide_host_alloc(&d
, hws
, 1);
1078 hwif
= pmif
->hwif
= host
->ports
[0];
1080 if (on_media_bay(pmif
)) {
1081 /* Fixup bus ID for media bay */
1083 pmif
->aapl_bus_id
= 1;
1084 } else if (pmif
->kind
== controller_ohare
) {
1085 /* The code below is having trouble on some ohare machines
1086 * (timing related ?). Until I can put my hand on one of these
1087 * units, I keep the old way
1089 ppc_md
.feature_call(PMAC_FTR_IDE_ENABLE
, np
, 0, 1);
1091 /* This is necessary to enable IDE when net-booting */
1092 ppc_md
.feature_call(PMAC_FTR_IDE_RESET
, np
, pmif
->aapl_bus_id
, 1);
1093 ppc_md
.feature_call(PMAC_FTR_IDE_ENABLE
, np
, pmif
->aapl_bus_id
, 1);
1095 ppc_md
.feature_call(PMAC_FTR_IDE_RESET
, np
, pmif
->aapl_bus_id
, 0);
1096 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY
));
1099 printk(KERN_INFO DRV_NAME
": Found Apple %s controller (%s), "
1100 "bus ID %d%s, irq %d\n", model_name
[pmif
->kind
],
1101 pmif
->mdev
? "macio" : "PCI", pmif
->aapl_bus_id
,
1102 on_media_bay(pmif
) ? " (mediabay)" : "", hw
->irq
);
1104 rc
= ide_host_register(host
, &d
, hws
);
1109 unlock_media_bay(pmif
->mdev
->media_bay
);
1113 ide_host_free(host
);
1117 static void pmac_ide_init_ports(struct ide_hw
*hw
, unsigned long base
)
1121 for (i
= 0; i
< 8; ++i
)
1122 hw
->io_ports_array
[i
] = base
+ i
* 0x10;
1124 hw
->io_ports
.ctl_addr
= base
+ 0x160;
1128 * Attach to a macio probed interface
1130 static int pmac_ide_macio_attach(struct macio_dev
*mdev
,
1131 const struct of_device_id
*match
)
1134 unsigned long regbase
;
1135 pmac_ide_hwif_t
*pmif
;
1139 pmif
= kzalloc(sizeof(*pmif
), GFP_KERNEL
);
1143 if (macio_resource_count(mdev
) == 0) {
1144 printk(KERN_WARNING
"ide-pmac: no address for %pOF\n",
1145 mdev
->ofdev
.dev
.of_node
);
1150 /* Request memory resource for IO ports */
1151 if (macio_request_resource(mdev
, 0, "ide-pmac (ports)")) {
1152 printk(KERN_ERR
"ide-pmac: can't request MMIO resource for "
1153 "%pOF!\n", mdev
->ofdev
.dev
.of_node
);
1158 /* XXX This is bogus. Should be fixed in the registry by checking
1159 * the kind of host interrupt controller, a bit like gatwick
1160 * fixes in irq.c. That works well enough for the single case
1161 * where that happens though...
1163 if (macio_irq_count(mdev
) == 0) {
1164 printk(KERN_WARNING
"ide-pmac: no intrs for device %pOF, using "
1165 "13\n", mdev
->ofdev
.dev
.of_node
);
1166 irq
= irq_create_mapping(NULL
, 13);
1168 irq
= macio_irq(mdev
, 0);
1170 base
= ioremap(macio_resource_start(mdev
, 0), 0x400);
1171 regbase
= (unsigned long) base
;
1174 pmif
->node
= mdev
->ofdev
.dev
.of_node
;
1175 pmif
->regbase
= regbase
;
1177 pmif
->kauai_fcr
= NULL
;
1179 if (macio_resource_count(mdev
) >= 2) {
1180 if (macio_request_resource(mdev
, 1, "ide-pmac (dma)"))
1181 printk(KERN_WARNING
"ide-pmac: can't request DMA "
1182 "resource for %pOF!\n",
1183 mdev
->ofdev
.dev
.of_node
);
1185 pmif
->dma_regs
= ioremap(macio_resource_start(mdev
, 1), 0x1000);
1187 pmif
->dma_regs
= NULL
;
1189 dev_set_drvdata(&mdev
->ofdev
.dev
, pmif
);
1191 memset(&hw
, 0, sizeof(hw
));
1192 pmac_ide_init_ports(&hw
, pmif
->regbase
);
1194 hw
.dev
= &mdev
->bus
->pdev
->dev
;
1195 hw
.parent
= &mdev
->ofdev
.dev
;
1197 rc
= pmac_ide_setup_device(pmif
, &hw
);
1199 /* The inteface is released to the common IDE layer */
1200 dev_set_drvdata(&mdev
->ofdev
.dev
, NULL
);
1202 if (pmif
->dma_regs
) {
1203 iounmap(pmif
->dma_regs
);
1204 macio_release_resource(mdev
, 1);
1206 macio_release_resource(mdev
, 0);
1218 pmac_ide_macio_suspend(struct macio_dev
*mdev
, pm_message_t mesg
)
1220 pmac_ide_hwif_t
*pmif
= dev_get_drvdata(&mdev
->ofdev
.dev
);
1223 if (mesg
.event
!= mdev
->ofdev
.dev
.power
.power_state
.event
1224 && (mesg
.event
& PM_EVENT_SLEEP
)) {
1225 rc
= pmac_ide_do_suspend(pmif
);
1227 mdev
->ofdev
.dev
.power
.power_state
= mesg
;
1234 pmac_ide_macio_resume(struct macio_dev
*mdev
)
1236 pmac_ide_hwif_t
*pmif
= dev_get_drvdata(&mdev
->ofdev
.dev
);
1239 if (mdev
->ofdev
.dev
.power
.power_state
.event
!= PM_EVENT_ON
) {
1240 rc
= pmac_ide_do_resume(pmif
);
1242 mdev
->ofdev
.dev
.power
.power_state
= PMSG_ON
;
1249 * Attach to a PCI probed interface
1251 static int pmac_ide_pci_attach(struct pci_dev
*pdev
,
1252 const struct pci_device_id
*id
)
1254 struct device_node
*np
;
1255 pmac_ide_hwif_t
*pmif
;
1257 unsigned long rbase
, rlen
;
1261 np
= pci_device_to_OF_node(pdev
);
1263 printk(KERN_ERR
"ide-pmac: cannot find MacIO node for Kauai ATA interface\n");
1267 pmif
= kzalloc(sizeof(*pmif
), GFP_KERNEL
);
1271 if (pci_enable_device(pdev
)) {
1272 printk(KERN_WARNING
"ide-pmac: Can't enable PCI device for "
1277 pci_set_master(pdev
);
1279 if (pci_request_regions(pdev
, "Kauai ATA")) {
1280 printk(KERN_ERR
"ide-pmac: Cannot obtain PCI resources for "
1289 rbase
= pci_resource_start(pdev
, 0);
1290 rlen
= pci_resource_len(pdev
, 0);
1292 base
= ioremap(rbase
, rlen
);
1293 pmif
->regbase
= (unsigned long) base
+ 0x2000;
1294 pmif
->dma_regs
= base
+ 0x1000;
1295 pmif
->kauai_fcr
= base
;
1296 pmif
->irq
= pdev
->irq
;
1298 pci_set_drvdata(pdev
, pmif
);
1300 memset(&hw
, 0, sizeof(hw
));
1301 pmac_ide_init_ports(&hw
, pmif
->regbase
);
1303 hw
.dev
= &pdev
->dev
;
1305 rc
= pmac_ide_setup_device(pmif
, &hw
);
1307 /* The inteface is released to the common IDE layer */
1309 pci_release_regions(pdev
);
1321 pmac_ide_pci_suspend(struct pci_dev
*pdev
, pm_message_t mesg
)
1323 pmac_ide_hwif_t
*pmif
= pci_get_drvdata(pdev
);
1326 if (mesg
.event
!= pdev
->dev
.power
.power_state
.event
1327 && (mesg
.event
& PM_EVENT_SLEEP
)) {
1328 rc
= pmac_ide_do_suspend(pmif
);
1330 pdev
->dev
.power
.power_state
= mesg
;
1337 pmac_ide_pci_resume(struct pci_dev
*pdev
)
1339 pmac_ide_hwif_t
*pmif
= pci_get_drvdata(pdev
);
1342 if (pdev
->dev
.power
.power_state
.event
!= PM_EVENT_ON
) {
1343 rc
= pmac_ide_do_resume(pmif
);
1345 pdev
->dev
.power
.power_state
= PMSG_ON
;
1351 #ifdef CONFIG_PMAC_MEDIABAY
1352 static void pmac_ide_macio_mb_event(struct macio_dev
* mdev
, int mb_state
)
1354 pmac_ide_hwif_t
*pmif
= dev_get_drvdata(&mdev
->ofdev
.dev
);
1358 if (!pmif
->hwif
->present
)
1359 ide_port_scan(pmif
->hwif
);
1362 if (pmif
->hwif
->present
)
1363 ide_port_unregister_devices(pmif
->hwif
);
1366 #endif /* CONFIG_PMAC_MEDIABAY */
1369 static struct of_device_id pmac_ide_macio_match
[] =
1386 static struct macio_driver pmac_ide_macio_driver
=
1390 .owner
= THIS_MODULE
,
1391 .of_match_table
= pmac_ide_macio_match
,
1393 .probe
= pmac_ide_macio_attach
,
1394 .suspend
= pmac_ide_macio_suspend
,
1395 .resume
= pmac_ide_macio_resume
,
1396 #ifdef CONFIG_PMAC_MEDIABAY
1397 .mediabay_event
= pmac_ide_macio_mb_event
,
1401 static const struct pci_device_id pmac_ide_pci_match
[] = {
1402 { PCI_VDEVICE(APPLE
, PCI_DEVICE_ID_APPLE_UNI_N_ATA
), 0 },
1403 { PCI_VDEVICE(APPLE
, PCI_DEVICE_ID_APPLE_IPID_ATA100
), 0 },
1404 { PCI_VDEVICE(APPLE
, PCI_DEVICE_ID_APPLE_K2_ATA100
), 0 },
1405 { PCI_VDEVICE(APPLE
, PCI_DEVICE_ID_APPLE_SH_ATA
), 0 },
1406 { PCI_VDEVICE(APPLE
, PCI_DEVICE_ID_APPLE_IPID2_ATA
), 0 },
1410 static struct pci_driver pmac_ide_pci_driver
= {
1412 .id_table
= pmac_ide_pci_match
,
1413 .probe
= pmac_ide_pci_attach
,
1414 .suspend
= pmac_ide_pci_suspend
,
1415 .resume
= pmac_ide_pci_resume
,
1417 MODULE_DEVICE_TABLE(pci
, pmac_ide_pci_match
);
1419 int __init
pmac_ide_probe(void)
1423 if (!machine_is(powermac
))
1426 #ifdef CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST
1427 error
= pci_register_driver(&pmac_ide_pci_driver
);
1430 error
= macio_register_driver(&pmac_ide_macio_driver
);
1432 pci_unregister_driver(&pmac_ide_pci_driver
);
1436 error
= macio_register_driver(&pmac_ide_macio_driver
);
1439 error
= pci_register_driver(&pmac_ide_pci_driver
);
1441 macio_unregister_driver(&pmac_ide_macio_driver
);
1450 * pmac_ide_build_dmatable builds the DBDMA command list
1451 * for a transfer and sets the DBDMA channel to point to it.
1453 static int pmac_ide_build_dmatable(ide_drive_t
*drive
, struct ide_cmd
*cmd
)
1455 ide_hwif_t
*hwif
= drive
->hwif
;
1456 pmac_ide_hwif_t
*pmif
= dev_get_drvdata(hwif
->gendev
.parent
);
1457 struct dbdma_cmd
*table
;
1458 volatile struct dbdma_regs __iomem
*dma
= pmif
->dma_regs
;
1459 struct scatterlist
*sg
;
1460 int wr
= !!(cmd
->tf_flags
& IDE_TFLAG_WRITE
);
1461 int i
= cmd
->sg_nents
, count
= 0;
1463 /* DMA table is already aligned */
1464 table
= (struct dbdma_cmd
*) pmif
->dma_table_cpu
;
1466 /* Make sure DMA controller is stopped (necessary ?) */
1467 writel((RUN
|PAUSE
|FLUSH
|WAKE
|DEAD
) << 16, &dma
->control
);
1468 while (readl(&dma
->status
) & RUN
)
1471 /* Build DBDMA commands list */
1472 sg
= hwif
->sg_table
;
1473 while (i
&& sg_dma_len(sg
)) {
1477 cur_addr
= sg_dma_address(sg
);
1478 cur_len
= sg_dma_len(sg
);
1480 if (pmif
->broken_dma
&& cur_addr
& (L1_CACHE_BYTES
- 1)) {
1481 if (pmif
->broken_dma_warn
== 0) {
1482 printk(KERN_WARNING
"%s: DMA on non aligned address, "
1483 "switching to PIO on Ohare chipset\n", drive
->name
);
1484 pmif
->broken_dma_warn
= 1;
1489 unsigned int tc
= (cur_len
< 0xfe00)? cur_len
: 0xfe00;
1491 if (count
++ >= MAX_DCMDS
) {
1492 printk(KERN_WARNING
"%s: DMA table too small\n",
1496 table
->command
= cpu_to_le16(wr
? OUTPUT_MORE
: INPUT_MORE
);
1497 table
->req_count
= cpu_to_le16(tc
);
1498 table
->phy_addr
= cpu_to_le32(cur_addr
);
1500 table
->xfer_status
= 0;
1501 table
->res_count
= 0;
1510 /* convert the last command to an input/output last command */
1512 table
[-1].command
= cpu_to_le16(wr
? OUTPUT_LAST
: INPUT_LAST
);
1513 /* add the stop command to the end of the list */
1514 memset(table
, 0, sizeof(struct dbdma_cmd
));
1515 table
->command
= cpu_to_le16(DBDMA_STOP
);
1517 writel(hwif
->dmatable_dma
, &dma
->cmdptr
);
1521 printk(KERN_DEBUG
"%s: empty DMA table?\n", drive
->name
);
1523 return 0; /* revert to PIO for this request */
1527 * Prepare a DMA transfer. We build the DMA table, adjust the timings for
1528 * a read on KeyLargo ATA/66 and mark us as waiting for DMA completion
1530 static int pmac_ide_dma_setup(ide_drive_t
*drive
, struct ide_cmd
*cmd
)
1532 ide_hwif_t
*hwif
= drive
->hwif
;
1533 pmac_ide_hwif_t
*pmif
= dev_get_drvdata(hwif
->gendev
.parent
);
1534 u8 unit
= drive
->dn
& 1, ata4
= (pmif
->kind
== controller_kl_ata4
);
1535 u8 write
= !!(cmd
->tf_flags
& IDE_TFLAG_WRITE
);
1537 if (pmac_ide_build_dmatable(drive
, cmd
) == 0)
1540 /* Apple adds 60ns to wrDataSetup on reads */
1541 if (ata4
&& (pmif
->timings
[unit
] & TR_66_UDMA_EN
)) {
1542 writel(pmif
->timings
[unit
] + (write
? 0 : 0x00800000UL
),
1543 PMAC_IDE_REG(IDE_TIMING_CONFIG
));
1544 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG
));
1551 * Kick the DMA controller into life after the DMA command has been issued
1555 pmac_ide_dma_start(ide_drive_t
*drive
)
1557 ide_hwif_t
*hwif
= drive
->hwif
;
1558 pmac_ide_hwif_t
*pmif
= dev_get_drvdata(hwif
->gendev
.parent
);
1559 volatile struct dbdma_regs __iomem
*dma
;
1561 dma
= pmif
->dma_regs
;
1563 writel((RUN
<< 16) | RUN
, &dma
->control
);
1564 /* Make sure it gets to the controller right now */
1565 (void)readl(&dma
->control
);
1569 * After a DMA transfer, make sure the controller is stopped
1572 pmac_ide_dma_end (ide_drive_t
*drive
)
1574 ide_hwif_t
*hwif
= drive
->hwif
;
1575 pmac_ide_hwif_t
*pmif
= dev_get_drvdata(hwif
->gendev
.parent
);
1576 volatile struct dbdma_regs __iomem
*dma
= pmif
->dma_regs
;
1579 dstat
= readl(&dma
->status
);
1580 writel(((RUN
|WAKE
|DEAD
) << 16), &dma
->control
);
1582 /* verify good dma status. we don't check for ACTIVE beeing 0. We should...
1583 * in theory, but with ATAPI decices doing buffer underruns, that would
1584 * cause us to disable DMA, which isn't what we want
1586 return (dstat
& (RUN
|DEAD
)) != RUN
;
1590 * Check out that the interrupt we got was for us. We can't always know this
1591 * for sure with those Apple interfaces (well, we could on the recent ones but
1592 * that's not implemented yet), on the other hand, we don't have shared interrupts
1593 * so it's not really a problem
1596 pmac_ide_dma_test_irq (ide_drive_t
*drive
)
1598 ide_hwif_t
*hwif
= drive
->hwif
;
1599 pmac_ide_hwif_t
*pmif
= dev_get_drvdata(hwif
->gendev
.parent
);
1600 volatile struct dbdma_regs __iomem
*dma
= pmif
->dma_regs
;
1601 unsigned long status
, timeout
;
1603 /* We have to things to deal with here:
1605 * - The dbdma won't stop if the command was started
1606 * but completed with an error without transferring all
1607 * datas. This happens when bad blocks are met during
1608 * a multi-block transfer.
1610 * - The dbdma fifo hasn't yet finished flushing to
1611 * to system memory when the disk interrupt occurs.
1615 /* If ACTIVE is cleared, the STOP command have passed and
1616 * transfer is complete.
1618 status
= readl(&dma
->status
);
1619 if (!(status
& ACTIVE
))
1622 /* If dbdma didn't execute the STOP command yet, the
1623 * active bit is still set. We consider that we aren't
1624 * sharing interrupts (which is hopefully the case with
1625 * those controllers) and so we just try to flush the
1626 * channel for pending data in the fifo
1629 writel((FLUSH
<< 16) | FLUSH
, &dma
->control
);
1633 status
= readl(&dma
->status
);
1634 if ((status
& FLUSH
) == 0)
1636 if (++timeout
> 100) {
1637 printk(KERN_WARNING
"ide%d, ide_dma_test_irq timeout flushing channel\n",
1645 static void pmac_ide_dma_host_set(ide_drive_t
*drive
, int on
)
1650 pmac_ide_dma_lost_irq (ide_drive_t
*drive
)
1652 ide_hwif_t
*hwif
= drive
->hwif
;
1653 pmac_ide_hwif_t
*pmif
= dev_get_drvdata(hwif
->gendev
.parent
);
1654 volatile struct dbdma_regs __iomem
*dma
= pmif
->dma_regs
;
1655 unsigned long status
= readl(&dma
->status
);
1657 printk(KERN_ERR
"ide-pmac lost interrupt, dma status: %lx\n", status
);
1660 static const struct ide_dma_ops pmac_dma_ops
= {
1661 .dma_host_set
= pmac_ide_dma_host_set
,
1662 .dma_setup
= pmac_ide_dma_setup
,
1663 .dma_start
= pmac_ide_dma_start
,
1664 .dma_end
= pmac_ide_dma_end
,
1665 .dma_test_irq
= pmac_ide_dma_test_irq
,
1666 .dma_lost_irq
= pmac_ide_dma_lost_irq
,
1670 * Allocate the data structures needed for using DMA with an interface
1671 * and fill the proper list of functions pointers
1673 static int pmac_ide_init_dma(ide_hwif_t
*hwif
, const struct ide_port_info
*d
)
1675 pmac_ide_hwif_t
*pmif
= dev_get_drvdata(hwif
->gendev
.parent
);
1676 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
1678 /* We won't need pci_dev if we switch to generic consistent
1681 if (dev
== NULL
|| pmif
->dma_regs
== 0)
1684 * Allocate space for the DBDMA commands.
1685 * The +2 is +1 for the stop command and +1 to allow for
1686 * aligning the start address to a multiple of 16 bytes.
1688 pmif
->dma_table_cpu
= dma_alloc_coherent(&dev
->dev
,
1689 (MAX_DCMDS
+ 2) * sizeof(struct dbdma_cmd
),
1690 &hwif
->dmatable_dma
, GFP_KERNEL
);
1691 if (pmif
->dma_table_cpu
== NULL
) {
1692 printk(KERN_ERR
"%s: unable to allocate DMA command list\n",
1697 hwif
->sg_max_nents
= MAX_DCMDS
;
1702 module_init(pmac_ide_probe
);
1704 MODULE_LICENSE("GPL");