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[ATM]: Fix dereference of uninitialized pointer in zatm
[mirror_ubuntu-bionic-kernel.git] / drivers / ide / ppc / pmac.c
1 /*
2 * linux/drivers/ide/ide-pmac.c
3 *
4 * Support for IDE interfaces on PowerMacs.
5 * These IDE interfaces are memory-mapped and have a DBDMA channel
6 * for doing DMA.
7 *
8 * Copyright (C) 1998-2003 Paul Mackerras & Ben. Herrenschmidt
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 *
15 * Some code taken from drivers/ide/ide-dma.c:
16 *
17 * Copyright (c) 1995-1998 Mark Lord
18 *
19 * TODO: - Use pre-calculated (kauai) timing tables all the time and
20 * get rid of the "rounded" tables used previously, so we have the
21 * same table format for all controllers and can then just have one
22 * big table
23 *
24 */
25 #include <linux/config.h>
26 #include <linux/types.h>
27 #include <linux/kernel.h>
28 #include <linux/sched.h>
29 #include <linux/init.h>
30 #include <linux/delay.h>
31 #include <linux/ide.h>
32 #include <linux/notifier.h>
33 #include <linux/reboot.h>
34 #include <linux/pci.h>
35 #include <linux/adb.h>
36 #include <linux/pmu.h>
37 #include <linux/scatterlist.h>
38
39 #include <asm/prom.h>
40 #include <asm/io.h>
41 #include <asm/dbdma.h>
42 #include <asm/ide.h>
43 #include <asm/pci-bridge.h>
44 #include <asm/machdep.h>
45 #include <asm/pmac_feature.h>
46 #include <asm/sections.h>
47 #include <asm/irq.h>
48
49 #ifndef CONFIG_PPC64
50 #include <asm/mediabay.h>
51 #endif
52
53 #include "ide-timing.h"
54
55 #undef IDE_PMAC_DEBUG
56
57 #define DMA_WAIT_TIMEOUT 50
58
59 typedef struct pmac_ide_hwif {
60 unsigned long regbase;
61 int irq;
62 int kind;
63 int aapl_bus_id;
64 unsigned cable_80 : 1;
65 unsigned mediabay : 1;
66 unsigned broken_dma : 1;
67 unsigned broken_dma_warn : 1;
68 struct device_node* node;
69 struct macio_dev *mdev;
70 u32 timings[4];
71 volatile u32 __iomem * *kauai_fcr;
72 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
73 /* Those fields are duplicating what is in hwif. We currently
74 * can't use the hwif ones because of some assumptions that are
75 * beeing done by the generic code about the kind of dma controller
76 * and format of the dma table. This will have to be fixed though.
77 */
78 volatile struct dbdma_regs __iomem * dma_regs;
79 struct dbdma_cmd* dma_table_cpu;
80 #endif
81
82 } pmac_ide_hwif_t;
83
84 static pmac_ide_hwif_t pmac_ide[MAX_HWIFS] __pmacdata;
85 static int pmac_ide_count;
86
87 enum {
88 controller_ohare, /* OHare based */
89 controller_heathrow, /* Heathrow/Paddington */
90 controller_kl_ata3, /* KeyLargo ATA-3 */
91 controller_kl_ata4, /* KeyLargo ATA-4 */
92 controller_un_ata6, /* UniNorth2 ATA-6 */
93 controller_k2_ata6, /* K2 ATA-6 */
94 controller_sh_ata6, /* Shasta ATA-6 */
95 };
96
97 static const char* model_name[] = {
98 "OHare ATA", /* OHare based */
99 "Heathrow ATA", /* Heathrow/Paddington */
100 "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */
101 "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */
102 "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */
103 "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */
104 "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */
105 };
106
107 /*
108 * Extra registers, both 32-bit little-endian
109 */
110 #define IDE_TIMING_CONFIG 0x200
111 #define IDE_INTERRUPT 0x300
112
113 /* Kauai (U2) ATA has different register setup */
114 #define IDE_KAUAI_PIO_CONFIG 0x200
115 #define IDE_KAUAI_ULTRA_CONFIG 0x210
116 #define IDE_KAUAI_POLL_CONFIG 0x220
117
118 /*
119 * Timing configuration register definitions
120 */
121
122 /* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */
123 #define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
124 #define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
125 #define IDE_SYSCLK_NS 30 /* 33Mhz cell */
126 #define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */
127
128 /* 133Mhz cell, found in shasta.
129 * See comments about 100 Mhz Uninorth 2...
130 * Note that PIO_MASK and MDMA_MASK seem to overlap
131 */
132 #define TR_133_PIOREG_PIO_MASK 0xff000fff
133 #define TR_133_PIOREG_MDMA_MASK 0x00fff800
134 #define TR_133_UDMAREG_UDMA_MASK 0x0003ffff
135 #define TR_133_UDMAREG_UDMA_EN 0x00000001
136
137 /* 100Mhz cell, found in Uninorth 2. I don't have much infos about
138 * this one yet, it appears as a pci device (106b/0033) on uninorth
139 * internal PCI bus and it's clock is controlled like gem or fw. It
140 * appears to be an evolution of keylargo ATA4 with a timing register
141 * extended to 2 32bits registers and a similar DBDMA channel. Other
142 * registers seem to exist but I can't tell much about them.
143 *
144 * So far, I'm using pre-calculated tables for this extracted from
145 * the values used by the MacOS X driver.
146 *
147 * The "PIO" register controls PIO and MDMA timings, the "ULTRA"
148 * register controls the UDMA timings. At least, it seems bit 0
149 * of this one enables UDMA vs. MDMA, and bits 4..7 are the
150 * cycle time in units of 10ns. Bits 8..15 are used by I don't
151 * know their meaning yet
152 */
153 #define TR_100_PIOREG_PIO_MASK 0xff000fff
154 #define TR_100_PIOREG_MDMA_MASK 0x00fff000
155 #define TR_100_UDMAREG_UDMA_MASK 0x0000ffff
156 #define TR_100_UDMAREG_UDMA_EN 0x00000001
157
158
159 /* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
160 * 40 connector cable and to 4 on 80 connector one.
161 * Clock unit is 15ns (66Mhz)
162 *
163 * 3 Values can be programmed:
164 * - Write data setup, which appears to match the cycle time. They
165 * also call it DIOW setup.
166 * - Ready to pause time (from spec)
167 * - Address setup. That one is weird. I don't see where exactly
168 * it fits in UDMA cycles, I got it's name from an obscure piece
169 * of commented out code in Darwin. They leave it to 0, we do as
170 * well, despite a comment that would lead to think it has a
171 * min value of 45ns.
172 * Apple also add 60ns to the write data setup (or cycle time ?) on
173 * reads.
174 */
175 #define TR_66_UDMA_MASK 0xfff00000
176 #define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */
177 #define TR_66_UDMA_ADDRSETUP_MASK 0xe0000000 /* Address setup */
178 #define TR_66_UDMA_ADDRSETUP_SHIFT 29
179 #define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */
180 #define TR_66_UDMA_RDY2PAUS_SHIFT 25
181 #define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */
182 #define TR_66_UDMA_WRDATASETUP_SHIFT 21
183 #define TR_66_MDMA_MASK 0x000ffc00
184 #define TR_66_MDMA_RECOVERY_MASK 0x000f8000
185 #define TR_66_MDMA_RECOVERY_SHIFT 15
186 #define TR_66_MDMA_ACCESS_MASK 0x00007c00
187 #define TR_66_MDMA_ACCESS_SHIFT 10
188 #define TR_66_PIO_MASK 0x000003ff
189 #define TR_66_PIO_RECOVERY_MASK 0x000003e0
190 #define TR_66_PIO_RECOVERY_SHIFT 5
191 #define TR_66_PIO_ACCESS_MASK 0x0000001f
192 #define TR_66_PIO_ACCESS_SHIFT 0
193
194 /* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo
195 * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
196 *
197 * The access time and recovery time can be programmed. Some older
198 * Darwin code base limit OHare to 150ns cycle time. I decided to do
199 * the same here fore safety against broken old hardware ;)
200 * The HalfTick bit, when set, adds half a clock (15ns) to the access
201 * time and removes one from recovery. It's not supported on KeyLargo
202 * implementation afaik. The E bit appears to be set for PIO mode 0 and
203 * is used to reach long timings used in this mode.
204 */
205 #define TR_33_MDMA_MASK 0x003ff800
206 #define TR_33_MDMA_RECOVERY_MASK 0x001f0000
207 #define TR_33_MDMA_RECOVERY_SHIFT 16
208 #define TR_33_MDMA_ACCESS_MASK 0x0000f800
209 #define TR_33_MDMA_ACCESS_SHIFT 11
210 #define TR_33_MDMA_HALFTICK 0x00200000
211 #define TR_33_PIO_MASK 0x000007ff
212 #define TR_33_PIO_E 0x00000400
213 #define TR_33_PIO_RECOVERY_MASK 0x000003e0
214 #define TR_33_PIO_RECOVERY_SHIFT 5
215 #define TR_33_PIO_ACCESS_MASK 0x0000001f
216 #define TR_33_PIO_ACCESS_SHIFT 0
217
218 /*
219 * Interrupt register definitions
220 */
221 #define IDE_INTR_DMA 0x80000000
222 #define IDE_INTR_DEVICE 0x40000000
223
224 /*
225 * FCR Register on Kauai. Not sure what bit 0x4 is ...
226 */
227 #define KAUAI_FCR_UATA_MAGIC 0x00000004
228 #define KAUAI_FCR_UATA_RESET_N 0x00000002
229 #define KAUAI_FCR_UATA_ENABLE 0x00000001
230
231 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
232
233 /* Rounded Multiword DMA timings
234 *
235 * I gave up finding a generic formula for all controller
236 * types and instead, built tables based on timing values
237 * used by Apple in Darwin's implementation.
238 */
239 struct mdma_timings_t {
240 int accessTime;
241 int recoveryTime;
242 int cycleTime;
243 };
244
245 struct mdma_timings_t mdma_timings_33[] __pmacdata =
246 {
247 { 240, 240, 480 },
248 { 180, 180, 360 },
249 { 135, 135, 270 },
250 { 120, 120, 240 },
251 { 105, 105, 210 },
252 { 90, 90, 180 },
253 { 75, 75, 150 },
254 { 75, 45, 120 },
255 { 0, 0, 0 }
256 };
257
258 struct mdma_timings_t mdma_timings_33k[] __pmacdata =
259 {
260 { 240, 240, 480 },
261 { 180, 180, 360 },
262 { 150, 150, 300 },
263 { 120, 120, 240 },
264 { 90, 120, 210 },
265 { 90, 90, 180 },
266 { 90, 60, 150 },
267 { 90, 30, 120 },
268 { 0, 0, 0 }
269 };
270
271 struct mdma_timings_t mdma_timings_66[] __pmacdata =
272 {
273 { 240, 240, 480 },
274 { 180, 180, 360 },
275 { 135, 135, 270 },
276 { 120, 120, 240 },
277 { 105, 105, 210 },
278 { 90, 90, 180 },
279 { 90, 75, 165 },
280 { 75, 45, 120 },
281 { 0, 0, 0 }
282 };
283
284 /* KeyLargo ATA-4 Ultra DMA timings (rounded) */
285 struct {
286 int addrSetup; /* ??? */
287 int rdy2pause;
288 int wrDataSetup;
289 } kl66_udma_timings[] __pmacdata =
290 {
291 { 0, 180, 120 }, /* Mode 0 */
292 { 0, 150, 90 }, /* 1 */
293 { 0, 120, 60 }, /* 2 */
294 { 0, 90, 45 }, /* 3 */
295 { 0, 90, 30 } /* 4 */
296 };
297
298 /* UniNorth 2 ATA/100 timings */
299 struct kauai_timing {
300 int cycle_time;
301 u32 timing_reg;
302 };
303
304 static struct kauai_timing kauai_pio_timings[] __pmacdata =
305 {
306 { 930 , 0x08000fff },
307 { 600 , 0x08000a92 },
308 { 383 , 0x0800060f },
309 { 360 , 0x08000492 },
310 { 330 , 0x0800048f },
311 { 300 , 0x080003cf },
312 { 270 , 0x080003cc },
313 { 240 , 0x0800038b },
314 { 239 , 0x0800030c },
315 { 180 , 0x05000249 },
316 { 120 , 0x04000148 }
317 };
318
319 static struct kauai_timing kauai_mdma_timings[] __pmacdata =
320 {
321 { 1260 , 0x00fff000 },
322 { 480 , 0x00618000 },
323 { 360 , 0x00492000 },
324 { 270 , 0x0038e000 },
325 { 240 , 0x0030c000 },
326 { 210 , 0x002cb000 },
327 { 180 , 0x00249000 },
328 { 150 , 0x00209000 },
329 { 120 , 0x00148000 },
330 { 0 , 0 },
331 };
332
333 static struct kauai_timing kauai_udma_timings[] __pmacdata =
334 {
335 { 120 , 0x000070c0 },
336 { 90 , 0x00005d80 },
337 { 60 , 0x00004a60 },
338 { 45 , 0x00003a50 },
339 { 30 , 0x00002a30 },
340 { 20 , 0x00002921 },
341 { 0 , 0 },
342 };
343
344 static struct kauai_timing shasta_pio_timings[] __pmacdata =
345 {
346 { 930 , 0x08000fff },
347 { 600 , 0x0A000c97 },
348 { 383 , 0x07000712 },
349 { 360 , 0x040003cd },
350 { 330 , 0x040003cd },
351 { 300 , 0x040003cd },
352 { 270 , 0x040003cd },
353 { 240 , 0x040003cd },
354 { 239 , 0x040003cd },
355 { 180 , 0x0400028b },
356 { 120 , 0x0400010a }
357 };
358
359 static struct kauai_timing shasta_mdma_timings[] __pmacdata =
360 {
361 { 1260 , 0x00fff000 },
362 { 480 , 0x00820800 },
363 { 360 , 0x00820800 },
364 { 270 , 0x00820800 },
365 { 240 , 0x00820800 },
366 { 210 , 0x00820800 },
367 { 180 , 0x00820800 },
368 { 150 , 0x0028b000 },
369 { 120 , 0x001ca000 },
370 { 0 , 0 },
371 };
372
373 static struct kauai_timing shasta_udma133_timings[] __pmacdata =
374 {
375 { 120 , 0x00035901, },
376 { 90 , 0x000348b1, },
377 { 60 , 0x00033881, },
378 { 45 , 0x00033861, },
379 { 30 , 0x00033841, },
380 { 20 , 0x00033031, },
381 { 15 , 0x00033021, },
382 { 0 , 0 },
383 };
384
385
386 static inline u32
387 kauai_lookup_timing(struct kauai_timing* table, int cycle_time)
388 {
389 int i;
390
391 for (i=0; table[i].cycle_time; i++)
392 if (cycle_time > table[i+1].cycle_time)
393 return table[i].timing_reg;
394 return 0;
395 }
396
397 /* allow up to 256 DBDMA commands per xfer */
398 #define MAX_DCMDS 256
399
400 /*
401 * Wait 1s for disk to answer on IDE bus after a hard reset
402 * of the device (via GPIO/FCR).
403 *
404 * Some devices seem to "pollute" the bus even after dropping
405 * the BSY bit (typically some combo drives slave on the UDMA
406 * bus) after a hard reset. Since we hard reset all drives on
407 * KeyLargo ATA66, we have to keep that delay around. I may end
408 * up not hard resetting anymore on these and keep the delay only
409 * for older interfaces instead (we have to reset when coming
410 * from MacOS...) --BenH.
411 */
412 #define IDE_WAKEUP_DELAY (1*HZ)
413
414 static void pmac_ide_setup_dma(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif);
415 static int pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq);
416 static int pmac_ide_tune_chipset(ide_drive_t *drive, u8 speed);
417 static void pmac_ide_tuneproc(ide_drive_t *drive, u8 pio);
418 static void pmac_ide_selectproc(ide_drive_t *drive);
419 static void pmac_ide_kauai_selectproc(ide_drive_t *drive);
420
421 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
422
423 /*
424 * Below is the code for blinking the laptop LED along with hard
425 * disk activity.
426 */
427
428 #ifdef CONFIG_BLK_DEV_IDE_PMAC_BLINK
429
430 /* Set to 50ms minimum led-on time (also used to limit frequency
431 * of requests sent to the PMU
432 */
433 #define PMU_HD_BLINK_TIME (HZ/50)
434
435 static struct adb_request pmu_blink_on, pmu_blink_off;
436 static spinlock_t pmu_blink_lock;
437 static unsigned long pmu_blink_stoptime;
438 static int pmu_blink_ledstate;
439 static struct timer_list pmu_blink_timer;
440 static int pmu_ide_blink_enabled;
441
442
443 static void
444 pmu_hd_blink_timeout(unsigned long data)
445 {
446 unsigned long flags;
447
448 spin_lock_irqsave(&pmu_blink_lock, flags);
449
450 /* We may have been triggered again in a racy way, check
451 * that we really want to switch it off
452 */
453 if (time_after(pmu_blink_stoptime, jiffies))
454 goto done;
455
456 /* Previous req. not complete, try 100ms more */
457 if (pmu_blink_off.complete == 0)
458 mod_timer(&pmu_blink_timer, jiffies + PMU_HD_BLINK_TIME);
459 else if (pmu_blink_ledstate) {
460 pmu_request(&pmu_blink_off, NULL, 4, 0xee, 4, 0, 0);
461 pmu_blink_ledstate = 0;
462 }
463 done:
464 spin_unlock_irqrestore(&pmu_blink_lock, flags);
465 }
466
467 static void
468 pmu_hd_kick_blink(void *data, int rw)
469 {
470 unsigned long flags;
471
472 pmu_blink_stoptime = jiffies + PMU_HD_BLINK_TIME;
473 wmb();
474 mod_timer(&pmu_blink_timer, pmu_blink_stoptime);
475 /* Fast path when LED is already ON */
476 if (pmu_blink_ledstate == 1)
477 return;
478 spin_lock_irqsave(&pmu_blink_lock, flags);
479 if (pmu_blink_on.complete && !pmu_blink_ledstate) {
480 pmu_request(&pmu_blink_on, NULL, 4, 0xee, 4, 0, 1);
481 pmu_blink_ledstate = 1;
482 }
483 spin_unlock_irqrestore(&pmu_blink_lock, flags);
484 }
485
486 static int
487 pmu_hd_blink_init(void)
488 {
489 struct device_node *dt;
490 const char *model;
491
492 /* Currently, I only enable this feature on KeyLargo based laptops,
493 * older laptops may support it (at least heathrow/paddington) but
494 * I don't feel like loading those venerable old machines with so
495 * much additional interrupt & PMU activity...
496 */
497 if (pmu_get_model() != PMU_KEYLARGO_BASED)
498 return 0;
499
500 dt = find_devices("device-tree");
501 if (dt == NULL)
502 return 0;
503 model = (const char *)get_property(dt, "model", NULL);
504 if (model == NULL)
505 return 0;
506 if (strncmp(model, "PowerBook", strlen("PowerBook")) != 0 &&
507 strncmp(model, "iBook", strlen("iBook")) != 0)
508 return 0;
509
510 pmu_blink_on.complete = 1;
511 pmu_blink_off.complete = 1;
512 spin_lock_init(&pmu_blink_lock);
513 init_timer(&pmu_blink_timer);
514 pmu_blink_timer.function = pmu_hd_blink_timeout;
515
516 return 1;
517 }
518
519 #endif /* CONFIG_BLK_DEV_IDE_PMAC_BLINK */
520
521 /*
522 * N.B. this can't be an initfunc, because the media-bay task can
523 * call ide_[un]register at any time.
524 */
525 void __pmac
526 pmac_ide_init_hwif_ports(hw_regs_t *hw,
527 unsigned long data_port, unsigned long ctrl_port,
528 int *irq)
529 {
530 int i, ix;
531
532 if (data_port == 0)
533 return;
534
535 for (ix = 0; ix < MAX_HWIFS; ++ix)
536 if (data_port == pmac_ide[ix].regbase)
537 break;
538
539 if (ix >= MAX_HWIFS) {
540 /* Probably a PCI interface... */
541 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; ++i)
542 hw->io_ports[i] = data_port + i - IDE_DATA_OFFSET;
543 hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
544 return;
545 }
546
547 for (i = 0; i < 8; ++i)
548 hw->io_ports[i] = data_port + i * 0x10;
549 hw->io_ports[8] = data_port + 0x160;
550
551 if (irq != NULL)
552 *irq = pmac_ide[ix].irq;
553 }
554
555 #define PMAC_IDE_REG(x) ((void __iomem *)(IDE_DATA_REG+(x)))
556
557 /*
558 * Apply the timings of the proper unit (master/slave) to the shared
559 * timing register when selecting that unit. This version is for
560 * ASICs with a single timing register
561 */
562 static void __pmac
563 pmac_ide_selectproc(ide_drive_t *drive)
564 {
565 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
566
567 if (pmif == NULL)
568 return;
569
570 if (drive->select.b.unit & 0x01)
571 writel(pmif->timings[1], PMAC_IDE_REG(IDE_TIMING_CONFIG));
572 else
573 writel(pmif->timings[0], PMAC_IDE_REG(IDE_TIMING_CONFIG));
574 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
575 }
576
577 /*
578 * Apply the timings of the proper unit (master/slave) to the shared
579 * timing register when selecting that unit. This version is for
580 * ASICs with a dual timing register (Kauai)
581 */
582 static void __pmac
583 pmac_ide_kauai_selectproc(ide_drive_t *drive)
584 {
585 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
586
587 if (pmif == NULL)
588 return;
589
590 if (drive->select.b.unit & 0x01) {
591 writel(pmif->timings[1], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
592 writel(pmif->timings[3], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
593 } else {
594 writel(pmif->timings[0], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
595 writel(pmif->timings[2], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
596 }
597 (void)readl(PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
598 }
599
600 /*
601 * Force an update of controller timing values for a given drive
602 */
603 static void __pmac
604 pmac_ide_do_update_timings(ide_drive_t *drive)
605 {
606 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
607
608 if (pmif == NULL)
609 return;
610
611 if (pmif->kind == controller_sh_ata6 ||
612 pmif->kind == controller_un_ata6 ||
613 pmif->kind == controller_k2_ata6)
614 pmac_ide_kauai_selectproc(drive);
615 else
616 pmac_ide_selectproc(drive);
617 }
618
619 static void
620 pmac_outbsync(ide_drive_t *drive, u8 value, unsigned long port)
621 {
622 u32 tmp;
623
624 writeb(value, (void __iomem *) port);
625 tmp = readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
626 }
627
628 /*
629 * Send the SET_FEATURE IDE command to the drive and update drive->id with
630 * the new state. We currently don't use the generic routine as it used to
631 * cause various trouble, especially with older mediabays.
632 * This code is sometimes triggering a spurrious interrupt though, I need
633 * to sort that out sooner or later and see if I can finally get the
634 * common version to work properly in all cases
635 */
636 static int __pmac
637 pmac_ide_do_setfeature(ide_drive_t *drive, u8 command)
638 {
639 ide_hwif_t *hwif = HWIF(drive);
640 int result = 1;
641
642 disable_irq_nosync(hwif->irq);
643 udelay(1);
644 SELECT_DRIVE(drive);
645 SELECT_MASK(drive, 0);
646 udelay(1);
647 /* Get rid of pending error state */
648 (void) hwif->INB(IDE_STATUS_REG);
649 /* Timeout bumped for some powerbooks */
650 if (wait_for_ready(drive, 2000)) {
651 /* Timeout bumped for some powerbooks */
652 printk(KERN_ERR "%s: pmac_ide_do_setfeature disk not ready "
653 "before SET_FEATURE!\n", drive->name);
654 goto out;
655 }
656 udelay(10);
657 hwif->OUTB(drive->ctl | 2, IDE_CONTROL_REG);
658 hwif->OUTB(command, IDE_NSECTOR_REG);
659 hwif->OUTB(SETFEATURES_XFER, IDE_FEATURE_REG);
660 hwif->OUTBSYNC(drive, WIN_SETFEATURES, IDE_COMMAND_REG);
661 udelay(1);
662 /* Timeout bumped for some powerbooks */
663 result = wait_for_ready(drive, 2000);
664 hwif->OUTB(drive->ctl, IDE_CONTROL_REG);
665 if (result)
666 printk(KERN_ERR "%s: pmac_ide_do_setfeature disk not ready "
667 "after SET_FEATURE !\n", drive->name);
668 out:
669 SELECT_MASK(drive, 0);
670 if (result == 0) {
671 drive->id->dma_ultra &= ~0xFF00;
672 drive->id->dma_mword &= ~0x0F00;
673 drive->id->dma_1word &= ~0x0F00;
674 switch(command) {
675 case XFER_UDMA_7:
676 drive->id->dma_ultra |= 0x8080; break;
677 case XFER_UDMA_6:
678 drive->id->dma_ultra |= 0x4040; break;
679 case XFER_UDMA_5:
680 drive->id->dma_ultra |= 0x2020; break;
681 case XFER_UDMA_4:
682 drive->id->dma_ultra |= 0x1010; break;
683 case XFER_UDMA_3:
684 drive->id->dma_ultra |= 0x0808; break;
685 case XFER_UDMA_2:
686 drive->id->dma_ultra |= 0x0404; break;
687 case XFER_UDMA_1:
688 drive->id->dma_ultra |= 0x0202; break;
689 case XFER_UDMA_0:
690 drive->id->dma_ultra |= 0x0101; break;
691 case XFER_MW_DMA_2:
692 drive->id->dma_mword |= 0x0404; break;
693 case XFER_MW_DMA_1:
694 drive->id->dma_mword |= 0x0202; break;
695 case XFER_MW_DMA_0:
696 drive->id->dma_mword |= 0x0101; break;
697 case XFER_SW_DMA_2:
698 drive->id->dma_1word |= 0x0404; break;
699 case XFER_SW_DMA_1:
700 drive->id->dma_1word |= 0x0202; break;
701 case XFER_SW_DMA_0:
702 drive->id->dma_1word |= 0x0101; break;
703 default: break;
704 }
705 }
706 enable_irq(hwif->irq);
707 return result;
708 }
709
710 /*
711 * Old tuning functions (called on hdparm -p), sets up drive PIO timings
712 */
713 static void __pmac
714 pmac_ide_tuneproc(ide_drive_t *drive, u8 pio)
715 {
716 ide_pio_data_t d;
717 u32 *timings;
718 unsigned accessTicks, recTicks;
719 unsigned accessTime, recTime;
720 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
721
722 if (pmif == NULL)
723 return;
724
725 /* which drive is it ? */
726 timings = &pmif->timings[drive->select.b.unit & 0x01];
727
728 pio = ide_get_best_pio_mode(drive, pio, 4, &d);
729
730 switch (pmif->kind) {
731 case controller_sh_ata6: {
732 /* 133Mhz cell */
733 u32 tr = kauai_lookup_timing(shasta_pio_timings, d.cycle_time);
734 if (tr == 0)
735 return;
736 *timings = ((*timings) & ~TR_133_PIOREG_PIO_MASK) | tr;
737 break;
738 }
739 case controller_un_ata6:
740 case controller_k2_ata6: {
741 /* 100Mhz cell */
742 u32 tr = kauai_lookup_timing(kauai_pio_timings, d.cycle_time);
743 if (tr == 0)
744 return;
745 *timings = ((*timings) & ~TR_100_PIOREG_PIO_MASK) | tr;
746 break;
747 }
748 case controller_kl_ata4:
749 /* 66Mhz cell */
750 recTime = d.cycle_time - ide_pio_timings[pio].active_time
751 - ide_pio_timings[pio].setup_time;
752 recTime = max(recTime, 150U);
753 accessTime = ide_pio_timings[pio].active_time;
754 accessTime = max(accessTime, 150U);
755 accessTicks = SYSCLK_TICKS_66(accessTime);
756 accessTicks = min(accessTicks, 0x1fU);
757 recTicks = SYSCLK_TICKS_66(recTime);
758 recTicks = min(recTicks, 0x1fU);
759 *timings = ((*timings) & ~TR_66_PIO_MASK) |
760 (accessTicks << TR_66_PIO_ACCESS_SHIFT) |
761 (recTicks << TR_66_PIO_RECOVERY_SHIFT);
762 break;
763 default: {
764 /* 33Mhz cell */
765 int ebit = 0;
766 recTime = d.cycle_time - ide_pio_timings[pio].active_time
767 - ide_pio_timings[pio].setup_time;
768 recTime = max(recTime, 150U);
769 accessTime = ide_pio_timings[pio].active_time;
770 accessTime = max(accessTime, 150U);
771 accessTicks = SYSCLK_TICKS(accessTime);
772 accessTicks = min(accessTicks, 0x1fU);
773 accessTicks = max(accessTicks, 4U);
774 recTicks = SYSCLK_TICKS(recTime);
775 recTicks = min(recTicks, 0x1fU);
776 recTicks = max(recTicks, 5U) - 4;
777 if (recTicks > 9) {
778 recTicks--; /* guess, but it's only for PIO0, so... */
779 ebit = 1;
780 }
781 *timings = ((*timings) & ~TR_33_PIO_MASK) |
782 (accessTicks << TR_33_PIO_ACCESS_SHIFT) |
783 (recTicks << TR_33_PIO_RECOVERY_SHIFT);
784 if (ebit)
785 *timings |= TR_33_PIO_E;
786 break;
787 }
788 }
789
790 #ifdef IDE_PMAC_DEBUG
791 printk(KERN_ERR "%s: Set PIO timing for mode %d, reg: 0x%08x\n",
792 drive->name, pio, *timings);
793 #endif
794
795 if (drive->select.all == HWIF(drive)->INB(IDE_SELECT_REG))
796 pmac_ide_do_update_timings(drive);
797 }
798
799 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
800
801 /*
802 * Calculate KeyLargo ATA/66 UDMA timings
803 */
804 static int __pmac
805 set_timings_udma_ata4(u32 *timings, u8 speed)
806 {
807 unsigned rdyToPauseTicks, wrDataSetupTicks, addrTicks;
808
809 if (speed > XFER_UDMA_4)
810 return 1;
811
812 rdyToPauseTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].rdy2pause);
813 wrDataSetupTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].wrDataSetup);
814 addrTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].addrSetup);
815
816 *timings = ((*timings) & ~(TR_66_UDMA_MASK | TR_66_MDMA_MASK)) |
817 (wrDataSetupTicks << TR_66_UDMA_WRDATASETUP_SHIFT) |
818 (rdyToPauseTicks << TR_66_UDMA_RDY2PAUS_SHIFT) |
819 (addrTicks <<TR_66_UDMA_ADDRSETUP_SHIFT) |
820 TR_66_UDMA_EN;
821 #ifdef IDE_PMAC_DEBUG
822 printk(KERN_ERR "ide_pmac: Set UDMA timing for mode %d, reg: 0x%08x\n",
823 speed & 0xf, *timings);
824 #endif
825
826 return 0;
827 }
828
829 /*
830 * Calculate Kauai ATA/100 UDMA timings
831 */
832 static int __pmac
833 set_timings_udma_ata6(u32 *pio_timings, u32 *ultra_timings, u8 speed)
834 {
835 struct ide_timing *t = ide_timing_find_mode(speed);
836 u32 tr;
837
838 if (speed > XFER_UDMA_5 || t == NULL)
839 return 1;
840 tr = kauai_lookup_timing(kauai_udma_timings, (int)t->udma);
841 if (tr == 0)
842 return 1;
843 *ultra_timings = ((*ultra_timings) & ~TR_100_UDMAREG_UDMA_MASK) | tr;
844 *ultra_timings = (*ultra_timings) | TR_100_UDMAREG_UDMA_EN;
845
846 return 0;
847 }
848
849 /*
850 * Calculate Shasta ATA/133 UDMA timings
851 */
852 static int __pmac
853 set_timings_udma_shasta(u32 *pio_timings, u32 *ultra_timings, u8 speed)
854 {
855 struct ide_timing *t = ide_timing_find_mode(speed);
856 u32 tr;
857
858 if (speed > XFER_UDMA_6 || t == NULL)
859 return 1;
860 tr = kauai_lookup_timing(shasta_udma133_timings, (int)t->udma);
861 if (tr == 0)
862 return 1;
863 *ultra_timings = ((*ultra_timings) & ~TR_133_UDMAREG_UDMA_MASK) | tr;
864 *ultra_timings = (*ultra_timings) | TR_133_UDMAREG_UDMA_EN;
865
866 return 0;
867 }
868
869 /*
870 * Calculate MDMA timings for all cells
871 */
872 static int __pmac
873 set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2,
874 u8 speed, int drive_cycle_time)
875 {
876 int cycleTime, accessTime = 0, recTime = 0;
877 unsigned accessTicks, recTicks;
878 struct mdma_timings_t* tm = NULL;
879 int i;
880
881 /* Get default cycle time for mode */
882 switch(speed & 0xf) {
883 case 0: cycleTime = 480; break;
884 case 1: cycleTime = 150; break;
885 case 2: cycleTime = 120; break;
886 default:
887 return 1;
888 }
889 /* Adjust for drive */
890 if (drive_cycle_time && drive_cycle_time > cycleTime)
891 cycleTime = drive_cycle_time;
892 /* OHare limits according to some old Apple sources */
893 if ((intf_type == controller_ohare) && (cycleTime < 150))
894 cycleTime = 150;
895 /* Get the proper timing array for this controller */
896 switch(intf_type) {
897 case controller_sh_ata6:
898 case controller_un_ata6:
899 case controller_k2_ata6:
900 break;
901 case controller_kl_ata4:
902 tm = mdma_timings_66;
903 break;
904 case controller_kl_ata3:
905 tm = mdma_timings_33k;
906 break;
907 default:
908 tm = mdma_timings_33;
909 break;
910 }
911 if (tm != NULL) {
912 /* Lookup matching access & recovery times */
913 i = -1;
914 for (;;) {
915 if (tm[i+1].cycleTime < cycleTime)
916 break;
917 i++;
918 }
919 if (i < 0)
920 return 1;
921 cycleTime = tm[i].cycleTime;
922 accessTime = tm[i].accessTime;
923 recTime = tm[i].recoveryTime;
924
925 #ifdef IDE_PMAC_DEBUG
926 printk(KERN_ERR "%s: MDMA, cycleTime: %d, accessTime: %d, recTime: %d\n",
927 drive->name, cycleTime, accessTime, recTime);
928 #endif
929 }
930 switch(intf_type) {
931 case controller_sh_ata6: {
932 /* 133Mhz cell */
933 u32 tr = kauai_lookup_timing(shasta_mdma_timings, cycleTime);
934 if (tr == 0)
935 return 1;
936 *timings = ((*timings) & ~TR_133_PIOREG_MDMA_MASK) | tr;
937 *timings2 = (*timings2) & ~TR_133_UDMAREG_UDMA_EN;
938 }
939 case controller_un_ata6:
940 case controller_k2_ata6: {
941 /* 100Mhz cell */
942 u32 tr = kauai_lookup_timing(kauai_mdma_timings, cycleTime);
943 if (tr == 0)
944 return 1;
945 *timings = ((*timings) & ~TR_100_PIOREG_MDMA_MASK) | tr;
946 *timings2 = (*timings2) & ~TR_100_UDMAREG_UDMA_EN;
947 }
948 break;
949 case controller_kl_ata4:
950 /* 66Mhz cell */
951 accessTicks = SYSCLK_TICKS_66(accessTime);
952 accessTicks = min(accessTicks, 0x1fU);
953 accessTicks = max(accessTicks, 0x1U);
954 recTicks = SYSCLK_TICKS_66(recTime);
955 recTicks = min(recTicks, 0x1fU);
956 recTicks = max(recTicks, 0x3U);
957 /* Clear out mdma bits and disable udma */
958 *timings = ((*timings) & ~(TR_66_MDMA_MASK | TR_66_UDMA_MASK)) |
959 (accessTicks << TR_66_MDMA_ACCESS_SHIFT) |
960 (recTicks << TR_66_MDMA_RECOVERY_SHIFT);
961 break;
962 case controller_kl_ata3:
963 /* 33Mhz cell on KeyLargo */
964 accessTicks = SYSCLK_TICKS(accessTime);
965 accessTicks = max(accessTicks, 1U);
966 accessTicks = min(accessTicks, 0x1fU);
967 accessTime = accessTicks * IDE_SYSCLK_NS;
968 recTicks = SYSCLK_TICKS(recTime);
969 recTicks = max(recTicks, 1U);
970 recTicks = min(recTicks, 0x1fU);
971 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
972 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
973 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
974 break;
975 default: {
976 /* 33Mhz cell on others */
977 int halfTick = 0;
978 int origAccessTime = accessTime;
979 int origRecTime = recTime;
980
981 accessTicks = SYSCLK_TICKS(accessTime);
982 accessTicks = max(accessTicks, 1U);
983 accessTicks = min(accessTicks, 0x1fU);
984 accessTime = accessTicks * IDE_SYSCLK_NS;
985 recTicks = SYSCLK_TICKS(recTime);
986 recTicks = max(recTicks, 2U) - 1;
987 recTicks = min(recTicks, 0x1fU);
988 recTime = (recTicks + 1) * IDE_SYSCLK_NS;
989 if ((accessTicks > 1) &&
990 ((accessTime - IDE_SYSCLK_NS/2) >= origAccessTime) &&
991 ((recTime - IDE_SYSCLK_NS/2) >= origRecTime)) {
992 halfTick = 1;
993 accessTicks--;
994 }
995 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
996 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
997 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
998 if (halfTick)
999 *timings |= TR_33_MDMA_HALFTICK;
1000 }
1001 }
1002 #ifdef IDE_PMAC_DEBUG
1003 printk(KERN_ERR "%s: Set MDMA timing for mode %d, reg: 0x%08x\n",
1004 drive->name, speed & 0xf, *timings);
1005 #endif
1006 return 0;
1007 }
1008 #endif /* #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC */
1009
1010 /*
1011 * Speedproc. This function is called by the core to set any of the standard
1012 * timing (PIO, MDMA or UDMA) to both the drive and the controller.
1013 * You may notice we don't use this function on normal "dma check" operation,
1014 * our dedicated function is more precise as it uses the drive provided
1015 * cycle time value. We should probably fix this one to deal with that too...
1016 */
1017 static int __pmac
1018 pmac_ide_tune_chipset (ide_drive_t *drive, byte speed)
1019 {
1020 int unit = (drive->select.b.unit & 0x01);
1021 int ret = 0;
1022 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1023 u32 *timings, *timings2;
1024
1025 if (pmif == NULL)
1026 return 1;
1027
1028 timings = &pmif->timings[unit];
1029 timings2 = &pmif->timings[unit+2];
1030
1031 switch(speed) {
1032 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1033 case XFER_UDMA_6:
1034 if (pmif->kind != controller_sh_ata6)
1035 return 1;
1036 case XFER_UDMA_5:
1037 if (pmif->kind != controller_un_ata6 &&
1038 pmif->kind != controller_k2_ata6 &&
1039 pmif->kind != controller_sh_ata6)
1040 return 1;
1041 case XFER_UDMA_4:
1042 case XFER_UDMA_3:
1043 if (HWIF(drive)->udma_four == 0)
1044 return 1;
1045 case XFER_UDMA_2:
1046 case XFER_UDMA_1:
1047 case XFER_UDMA_0:
1048 if (pmif->kind == controller_kl_ata4)
1049 ret = set_timings_udma_ata4(timings, speed);
1050 else if (pmif->kind == controller_un_ata6
1051 || pmif->kind == controller_k2_ata6)
1052 ret = set_timings_udma_ata6(timings, timings2, speed);
1053 else if (pmif->kind == controller_sh_ata6)
1054 ret = set_timings_udma_shasta(timings, timings2, speed);
1055 else
1056 ret = 1;
1057 break;
1058 case XFER_MW_DMA_2:
1059 case XFER_MW_DMA_1:
1060 case XFER_MW_DMA_0:
1061 ret = set_timings_mdma(drive, pmif->kind, timings, timings2, speed, 0);
1062 break;
1063 case XFER_SW_DMA_2:
1064 case XFER_SW_DMA_1:
1065 case XFER_SW_DMA_0:
1066 return 1;
1067 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1068 case XFER_PIO_4:
1069 case XFER_PIO_3:
1070 case XFER_PIO_2:
1071 case XFER_PIO_1:
1072 case XFER_PIO_0:
1073 pmac_ide_tuneproc(drive, speed & 0x07);
1074 break;
1075 default:
1076 ret = 1;
1077 }
1078 if (ret)
1079 return ret;
1080
1081 ret = pmac_ide_do_setfeature(drive, speed);
1082 if (ret)
1083 return ret;
1084
1085 pmac_ide_do_update_timings(drive);
1086 drive->current_speed = speed;
1087
1088 return 0;
1089 }
1090
1091 /*
1092 * Blast some well known "safe" values to the timing registers at init or
1093 * wakeup from sleep time, before we do real calculation
1094 */
1095 static void __pmac
1096 sanitize_timings(pmac_ide_hwif_t *pmif)
1097 {
1098 unsigned int value, value2 = 0;
1099
1100 switch(pmif->kind) {
1101 case controller_sh_ata6:
1102 value = 0x0a820c97;
1103 value2 = 0x00033031;
1104 break;
1105 case controller_un_ata6:
1106 case controller_k2_ata6:
1107 value = 0x08618a92;
1108 value2 = 0x00002921;
1109 break;
1110 case controller_kl_ata4:
1111 value = 0x0008438c;
1112 break;
1113 case controller_kl_ata3:
1114 value = 0x00084526;
1115 break;
1116 case controller_heathrow:
1117 case controller_ohare:
1118 default:
1119 value = 0x00074526;
1120 break;
1121 }
1122 pmif->timings[0] = pmif->timings[1] = value;
1123 pmif->timings[2] = pmif->timings[3] = value2;
1124 }
1125
1126 unsigned long __pmac
1127 pmac_ide_get_base(int index)
1128 {
1129 return pmac_ide[index].regbase;
1130 }
1131
1132 int __pmac
1133 pmac_ide_check_base(unsigned long base)
1134 {
1135 int ix;
1136
1137 for (ix = 0; ix < MAX_HWIFS; ++ix)
1138 if (base == pmac_ide[ix].regbase)
1139 return ix;
1140 return -1;
1141 }
1142
1143 int __pmac
1144 pmac_ide_get_irq(unsigned long base)
1145 {
1146 int ix;
1147
1148 for (ix = 0; ix < MAX_HWIFS; ++ix)
1149 if (base == pmac_ide[ix].regbase)
1150 return pmac_ide[ix].irq;
1151 return 0;
1152 }
1153
1154 static int ide_majors[] __pmacdata = { 3, 22, 33, 34, 56, 57 };
1155
1156 dev_t __init
1157 pmac_find_ide_boot(char *bootdevice, int n)
1158 {
1159 int i;
1160
1161 /*
1162 * Look through the list of IDE interfaces for this one.
1163 */
1164 for (i = 0; i < pmac_ide_count; ++i) {
1165 char *name;
1166 if (!pmac_ide[i].node || !pmac_ide[i].node->full_name)
1167 continue;
1168 name = pmac_ide[i].node->full_name;
1169 if (memcmp(name, bootdevice, n) == 0 && name[n] == 0) {
1170 /* XXX should cope with the 2nd drive as well... */
1171 return MKDEV(ide_majors[i], 0);
1172 }
1173 }
1174
1175 return 0;
1176 }
1177
1178 /* Suspend call back, should be called after the child devices
1179 * have actually been suspended
1180 */
1181 static int
1182 pmac_ide_do_suspend(ide_hwif_t *hwif)
1183 {
1184 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1185
1186 /* We clear the timings */
1187 pmif->timings[0] = 0;
1188 pmif->timings[1] = 0;
1189
1190 #ifdef CONFIG_BLK_DEV_IDE_PMAC_BLINK
1191 /* Note: This code will be called for every hwif, thus we'll
1192 * try several time to stop the LED blinker timer, but that
1193 * should be harmless
1194 */
1195 if (pmu_ide_blink_enabled) {
1196 unsigned long flags;
1197
1198 /* Make sure we don't hit the PMU blink */
1199 spin_lock_irqsave(&pmu_blink_lock, flags);
1200 if (pmu_blink_ledstate)
1201 del_timer(&pmu_blink_timer);
1202 pmu_blink_ledstate = 0;
1203 spin_unlock_irqrestore(&pmu_blink_lock, flags);
1204 }
1205 #endif /* CONFIG_BLK_DEV_IDE_PMAC_BLINK */
1206
1207 disable_irq(pmif->irq);
1208
1209 /* The media bay will handle itself just fine */
1210 if (pmif->mediabay)
1211 return 0;
1212
1213 /* Kauai has bus control FCRs directly here */
1214 if (pmif->kauai_fcr) {
1215 u32 fcr = readl(pmif->kauai_fcr);
1216 fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE);
1217 writel(fcr, pmif->kauai_fcr);
1218 }
1219
1220 /* Disable the bus on older machines and the cell on kauai */
1221 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id,
1222 0);
1223
1224 return 0;
1225 }
1226
1227 /* Resume call back, should be called before the child devices
1228 * are resumed
1229 */
1230 static int
1231 pmac_ide_do_resume(ide_hwif_t *hwif)
1232 {
1233 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1234
1235 /* Hard reset & re-enable controller (do we really need to reset ? -BenH) */
1236 if (!pmif->mediabay) {
1237 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 1);
1238 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id, 1);
1239 msleep(10);
1240 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 0);
1241
1242 /* Kauai has it different */
1243 if (pmif->kauai_fcr) {
1244 u32 fcr = readl(pmif->kauai_fcr);
1245 fcr |= KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE;
1246 writel(fcr, pmif->kauai_fcr);
1247 }
1248
1249 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
1250 }
1251
1252 /* Sanitize drive timings */
1253 sanitize_timings(pmif);
1254
1255 enable_irq(pmif->irq);
1256
1257 return 0;
1258 }
1259
1260 /*
1261 * Setup, register & probe an IDE channel driven by this driver, this is
1262 * called by one of the 2 probe functions (macio or PCI). Note that a channel
1263 * that ends up beeing free of any device is not kept around by this driver
1264 * (it is kept in 2.4). This introduce an interface numbering change on some
1265 * rare machines unfortunately, but it's better this way.
1266 */
1267 static int
1268 pmac_ide_setup_device(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif)
1269 {
1270 struct device_node *np = pmif->node;
1271 int *bidp, i;
1272
1273 pmif->cable_80 = 0;
1274 pmif->broken_dma = pmif->broken_dma_warn = 0;
1275 if (device_is_compatible(np, "shasta-ata"))
1276 pmif->kind = controller_sh_ata6;
1277 else if (device_is_compatible(np, "kauai-ata"))
1278 pmif->kind = controller_un_ata6;
1279 else if (device_is_compatible(np, "K2-UATA"))
1280 pmif->kind = controller_k2_ata6;
1281 else if (device_is_compatible(np, "keylargo-ata")) {
1282 if (strcmp(np->name, "ata-4") == 0)
1283 pmif->kind = controller_kl_ata4;
1284 else
1285 pmif->kind = controller_kl_ata3;
1286 } else if (device_is_compatible(np, "heathrow-ata"))
1287 pmif->kind = controller_heathrow;
1288 else {
1289 pmif->kind = controller_ohare;
1290 pmif->broken_dma = 1;
1291 }
1292
1293 bidp = (int *)get_property(np, "AAPL,bus-id", NULL);
1294 pmif->aapl_bus_id = bidp ? *bidp : 0;
1295
1296 /* Get cable type from device-tree */
1297 if (pmif->kind == controller_kl_ata4 || pmif->kind == controller_un_ata6
1298 || pmif->kind == controller_k2_ata6
1299 || pmif->kind == controller_sh_ata6) {
1300 char* cable = get_property(np, "cable-type", NULL);
1301 if (cable && !strncmp(cable, "80-", 3))
1302 pmif->cable_80 = 1;
1303 }
1304 /* G5's seem to have incorrect cable type in device-tree. Let's assume
1305 * they have a 80 conductor cable, this seem to be always the case unless
1306 * the user mucked around
1307 */
1308 if (device_is_compatible(np, "K2-UATA") ||
1309 device_is_compatible(np, "shasta-ata"))
1310 pmif->cable_80 = 1;
1311
1312 /* On Kauai-type controllers, we make sure the FCR is correct */
1313 if (pmif->kauai_fcr)
1314 writel(KAUAI_FCR_UATA_MAGIC |
1315 KAUAI_FCR_UATA_RESET_N |
1316 KAUAI_FCR_UATA_ENABLE, pmif->kauai_fcr);
1317
1318 pmif->mediabay = 0;
1319
1320 /* Make sure we have sane timings */
1321 sanitize_timings(pmif);
1322
1323 #ifndef CONFIG_PPC64
1324 /* XXX FIXME: Media bay stuff need re-organizing */
1325 if (np->parent && np->parent->name
1326 && strcasecmp(np->parent->name, "media-bay") == 0) {
1327 #ifdef CONFIG_PMAC_MEDIABAY
1328 media_bay_set_ide_infos(np->parent, pmif->regbase, pmif->irq, hwif->index);
1329 #endif /* CONFIG_PMAC_MEDIABAY */
1330 pmif->mediabay = 1;
1331 if (!bidp)
1332 pmif->aapl_bus_id = 1;
1333 } else if (pmif->kind == controller_ohare) {
1334 /* The code below is having trouble on some ohare machines
1335 * (timing related ?). Until I can put my hand on one of these
1336 * units, I keep the old way
1337 */
1338 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, 0, 1);
1339 } else
1340 #endif
1341 {
1342 /* This is necessary to enable IDE when net-booting */
1343 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 1);
1344 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, pmif->aapl_bus_id, 1);
1345 msleep(10);
1346 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 0);
1347 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
1348 }
1349
1350 /* Setup MMIO ops */
1351 default_hwif_mmiops(hwif);
1352 hwif->OUTBSYNC = pmac_outbsync;
1353
1354 /* Tell common code _not_ to mess with resources */
1355 hwif->mmio = 2;
1356 hwif->hwif_data = pmif;
1357 pmac_ide_init_hwif_ports(&hwif->hw, pmif->regbase, 0, &hwif->irq);
1358 memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->io_ports));
1359 hwif->chipset = ide_pmac;
1360 hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET] || pmif->mediabay;
1361 hwif->hold = pmif->mediabay;
1362 hwif->udma_four = pmif->cable_80;
1363 hwif->drives[0].unmask = 1;
1364 hwif->drives[1].unmask = 1;
1365 hwif->tuneproc = pmac_ide_tuneproc;
1366 if (pmif->kind == controller_un_ata6
1367 || pmif->kind == controller_k2_ata6
1368 || pmif->kind == controller_sh_ata6)
1369 hwif->selectproc = pmac_ide_kauai_selectproc;
1370 else
1371 hwif->selectproc = pmac_ide_selectproc;
1372 hwif->speedproc = pmac_ide_tune_chipset;
1373
1374 #ifdef CONFIG_BLK_DEV_IDE_PMAC_BLINK
1375 pmu_ide_blink_enabled = pmu_hd_blink_init();
1376
1377 if (pmu_ide_blink_enabled)
1378 hwif->led_act = pmu_hd_kick_blink;
1379 #endif
1380
1381 printk(KERN_INFO "ide%d: Found Apple %s controller, bus ID %d%s, irq %d\n",
1382 hwif->index, model_name[pmif->kind], pmif->aapl_bus_id,
1383 pmif->mediabay ? " (mediabay)" : "", hwif->irq);
1384
1385 #ifdef CONFIG_PMAC_MEDIABAY
1386 if (pmif->mediabay && check_media_bay_by_base(pmif->regbase, MB_CD) == 0)
1387 hwif->noprobe = 0;
1388 #endif /* CONFIG_PMAC_MEDIABAY */
1389
1390 hwif->sg_max_nents = MAX_DCMDS;
1391
1392 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1393 /* has a DBDMA controller channel */
1394 if (pmif->dma_regs)
1395 pmac_ide_setup_dma(pmif, hwif);
1396 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1397
1398 /* We probe the hwif now */
1399 probe_hwif_init(hwif);
1400
1401 /* The code IDE code will have set hwif->present if we have devices attached,
1402 * if we don't, the discard the interface except if we are on a media bay slot
1403 */
1404 if (!hwif->present && !pmif->mediabay) {
1405 printk(KERN_INFO "ide%d: Bus empty, interface released.\n",
1406 hwif->index);
1407 default_hwif_iops(hwif);
1408 for (i = IDE_DATA_OFFSET; i <= IDE_CONTROL_OFFSET; ++i)
1409 hwif->io_ports[i] = 0;
1410 hwif->chipset = ide_unknown;
1411 hwif->noprobe = 1;
1412 return -ENODEV;
1413 }
1414
1415 return 0;
1416 }
1417
1418 /*
1419 * Attach to a macio probed interface
1420 */
1421 static int __devinit
1422 pmac_ide_macio_attach(struct macio_dev *mdev, const struct of_device_id *match)
1423 {
1424 void __iomem *base;
1425 unsigned long regbase;
1426 int irq;
1427 ide_hwif_t *hwif;
1428 pmac_ide_hwif_t *pmif;
1429 int i, rc;
1430
1431 i = 0;
1432 while (i < MAX_HWIFS && (ide_hwifs[i].io_ports[IDE_DATA_OFFSET] != 0
1433 || pmac_ide[i].node != NULL))
1434 ++i;
1435 if (i >= MAX_HWIFS) {
1436 printk(KERN_ERR "ide-pmac: MacIO interface attach with no slot\n");
1437 printk(KERN_ERR " %s\n", mdev->ofdev.node->full_name);
1438 return -ENODEV;
1439 }
1440
1441 pmif = &pmac_ide[i];
1442 hwif = &ide_hwifs[i];
1443
1444 if (mdev->ofdev.node->n_addrs == 0) {
1445 printk(KERN_WARNING "ide%d: no address for %s\n",
1446 i, mdev->ofdev.node->full_name);
1447 return -ENXIO;
1448 }
1449
1450 /* Request memory resource for IO ports */
1451 if (macio_request_resource(mdev, 0, "ide-pmac (ports)")) {
1452 printk(KERN_ERR "ide%d: can't request mmio resource !\n", i);
1453 return -EBUSY;
1454 }
1455
1456 /* XXX This is bogus. Should be fixed in the registry by checking
1457 * the kind of host interrupt controller, a bit like gatwick
1458 * fixes in irq.c. That works well enough for the single case
1459 * where that happens though...
1460 */
1461 if (macio_irq_count(mdev) == 0) {
1462 printk(KERN_WARNING "ide%d: no intrs for device %s, using 13\n",
1463 i, mdev->ofdev.node->full_name);
1464 irq = 13;
1465 } else
1466 irq = macio_irq(mdev, 0);
1467
1468 base = ioremap(macio_resource_start(mdev, 0), 0x400);
1469 regbase = (unsigned long) base;
1470
1471 hwif->pci_dev = mdev->bus->pdev;
1472 hwif->gendev.parent = &mdev->ofdev.dev;
1473
1474 pmif->mdev = mdev;
1475 pmif->node = mdev->ofdev.node;
1476 pmif->regbase = regbase;
1477 pmif->irq = irq;
1478 pmif->kauai_fcr = NULL;
1479 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1480 if (macio_resource_count(mdev) >= 2) {
1481 if (macio_request_resource(mdev, 1, "ide-pmac (dma)"))
1482 printk(KERN_WARNING "ide%d: can't request DMA resource !\n", i);
1483 else
1484 pmif->dma_regs = ioremap(macio_resource_start(mdev, 1), 0x1000);
1485 } else
1486 pmif->dma_regs = NULL;
1487 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1488 dev_set_drvdata(&mdev->ofdev.dev, hwif);
1489
1490 rc = pmac_ide_setup_device(pmif, hwif);
1491 if (rc != 0) {
1492 /* The inteface is released to the common IDE layer */
1493 dev_set_drvdata(&mdev->ofdev.dev, NULL);
1494 iounmap(base);
1495 if (pmif->dma_regs)
1496 iounmap(pmif->dma_regs);
1497 memset(pmif, 0, sizeof(*pmif));
1498 macio_release_resource(mdev, 0);
1499 if (pmif->dma_regs)
1500 macio_release_resource(mdev, 1);
1501 }
1502
1503 return rc;
1504 }
1505
1506 static int
1507 pmac_ide_macio_suspend(struct macio_dev *mdev, u32 state)
1508 {
1509 ide_hwif_t *hwif = (ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1510 int rc = 0;
1511
1512 if (state != mdev->ofdev.dev.power.power_state && state >= 2) {
1513 rc = pmac_ide_do_suspend(hwif);
1514 if (rc == 0)
1515 mdev->ofdev.dev.power.power_state = state;
1516 }
1517
1518 return rc;
1519 }
1520
1521 static int
1522 pmac_ide_macio_resume(struct macio_dev *mdev)
1523 {
1524 ide_hwif_t *hwif = (ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1525 int rc = 0;
1526
1527 if (mdev->ofdev.dev.power.power_state != 0) {
1528 rc = pmac_ide_do_resume(hwif);
1529 if (rc == 0)
1530 mdev->ofdev.dev.power.power_state = 0;
1531 }
1532
1533 return rc;
1534 }
1535
1536 /*
1537 * Attach to a PCI probed interface
1538 */
1539 static int __devinit
1540 pmac_ide_pci_attach(struct pci_dev *pdev, const struct pci_device_id *id)
1541 {
1542 ide_hwif_t *hwif;
1543 struct device_node *np;
1544 pmac_ide_hwif_t *pmif;
1545 void __iomem *base;
1546 unsigned long rbase, rlen;
1547 int i, rc;
1548
1549 np = pci_device_to_OF_node(pdev);
1550 if (np == NULL) {
1551 printk(KERN_ERR "ide-pmac: cannot find MacIO node for Kauai ATA interface\n");
1552 return -ENODEV;
1553 }
1554 i = 0;
1555 while (i < MAX_HWIFS && (ide_hwifs[i].io_ports[IDE_DATA_OFFSET] != 0
1556 || pmac_ide[i].node != NULL))
1557 ++i;
1558 if (i >= MAX_HWIFS) {
1559 printk(KERN_ERR "ide-pmac: PCI interface attach with no slot\n");
1560 printk(KERN_ERR " %s\n", np->full_name);
1561 return -ENODEV;
1562 }
1563
1564 pmif = &pmac_ide[i];
1565 hwif = &ide_hwifs[i];
1566
1567 if (pci_enable_device(pdev)) {
1568 printk(KERN_WARNING "ide%i: Can't enable PCI device for %s\n",
1569 i, np->full_name);
1570 return -ENXIO;
1571 }
1572 pci_set_master(pdev);
1573
1574 if (pci_request_regions(pdev, "Kauai ATA")) {
1575 printk(KERN_ERR "ide%d: Cannot obtain PCI resources for %s\n",
1576 i, np->full_name);
1577 return -ENXIO;
1578 }
1579
1580 hwif->pci_dev = pdev;
1581 hwif->gendev.parent = &pdev->dev;
1582 pmif->mdev = NULL;
1583 pmif->node = np;
1584
1585 rbase = pci_resource_start(pdev, 0);
1586 rlen = pci_resource_len(pdev, 0);
1587
1588 base = ioremap(rbase, rlen);
1589 pmif->regbase = (unsigned long) base + 0x2000;
1590 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1591 pmif->dma_regs = base + 0x1000;
1592 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1593 pmif->kauai_fcr = base;
1594 pmif->irq = pdev->irq;
1595
1596 pci_set_drvdata(pdev, hwif);
1597
1598 rc = pmac_ide_setup_device(pmif, hwif);
1599 if (rc != 0) {
1600 /* The inteface is released to the common IDE layer */
1601 pci_set_drvdata(pdev, NULL);
1602 iounmap(base);
1603 memset(pmif, 0, sizeof(*pmif));
1604 pci_release_regions(pdev);
1605 }
1606
1607 return rc;
1608 }
1609
1610 static int
1611 pmac_ide_pci_suspend(struct pci_dev *pdev, u32 state)
1612 {
1613 ide_hwif_t *hwif = (ide_hwif_t *)pci_get_drvdata(pdev);
1614 int rc = 0;
1615
1616 if (state != pdev->dev.power.power_state && state >= 2) {
1617 rc = pmac_ide_do_suspend(hwif);
1618 if (rc == 0)
1619 pdev->dev.power.power_state = state;
1620 }
1621
1622 return rc;
1623 }
1624
1625 static int
1626 pmac_ide_pci_resume(struct pci_dev *pdev)
1627 {
1628 ide_hwif_t *hwif = (ide_hwif_t *)pci_get_drvdata(pdev);
1629 int rc = 0;
1630
1631 if (pdev->dev.power.power_state != 0) {
1632 rc = pmac_ide_do_resume(hwif);
1633 if (rc == 0)
1634 pdev->dev.power.power_state = 0;
1635 }
1636
1637 return rc;
1638 }
1639
1640 static struct of_device_id pmac_ide_macio_match[] =
1641 {
1642 {
1643 .name = "IDE",
1644 },
1645 {
1646 .name = "ATA",
1647 },
1648 {
1649 .type = "ide",
1650 },
1651 {
1652 .type = "ata",
1653 },
1654 {},
1655 };
1656
1657 static struct macio_driver pmac_ide_macio_driver =
1658 {
1659 .name = "ide-pmac",
1660 .match_table = pmac_ide_macio_match,
1661 .probe = pmac_ide_macio_attach,
1662 .suspend = pmac_ide_macio_suspend,
1663 .resume = pmac_ide_macio_resume,
1664 };
1665
1666 static struct pci_device_id pmac_ide_pci_match[] = {
1667 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1668 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1669 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1670 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_SH_ATA,
1671 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1672 };
1673
1674 static struct pci_driver pmac_ide_pci_driver = {
1675 .name = "ide-pmac",
1676 .id_table = pmac_ide_pci_match,
1677 .probe = pmac_ide_pci_attach,
1678 .suspend = pmac_ide_pci_suspend,
1679 .resume = pmac_ide_pci_resume,
1680 };
1681 MODULE_DEVICE_TABLE(pci, pmac_ide_pci_match);
1682
1683 void __init
1684 pmac_ide_probe(void)
1685 {
1686 if (_machine != _MACH_Pmac)
1687 return;
1688
1689 #ifdef CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST
1690 pci_register_driver(&pmac_ide_pci_driver);
1691 macio_register_driver(&pmac_ide_macio_driver);
1692 #else
1693 macio_register_driver(&pmac_ide_macio_driver);
1694 pci_register_driver(&pmac_ide_pci_driver);
1695 #endif
1696 }
1697
1698 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1699
1700 /*
1701 * pmac_ide_build_dmatable builds the DBDMA command list
1702 * for a transfer and sets the DBDMA channel to point to it.
1703 */
1704 static int __pmac
1705 pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq)
1706 {
1707 struct dbdma_cmd *table;
1708 int i, count = 0;
1709 ide_hwif_t *hwif = HWIF(drive);
1710 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1711 volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1712 struct scatterlist *sg;
1713 int wr = (rq_data_dir(rq) == WRITE);
1714
1715 /* DMA table is already aligned */
1716 table = (struct dbdma_cmd *) pmif->dma_table_cpu;
1717
1718 /* Make sure DMA controller is stopped (necessary ?) */
1719 writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma->control);
1720 while (readl(&dma->status) & RUN)
1721 udelay(1);
1722
1723 hwif->sg_nents = i = ide_build_sglist(drive, rq);
1724
1725 if (!i)
1726 return 0;
1727
1728 /* Build DBDMA commands list */
1729 sg = hwif->sg_table;
1730 while (i && sg_dma_len(sg)) {
1731 u32 cur_addr;
1732 u32 cur_len;
1733
1734 cur_addr = sg_dma_address(sg);
1735 cur_len = sg_dma_len(sg);
1736
1737 if (pmif->broken_dma && cur_addr & (L1_CACHE_BYTES - 1)) {
1738 if (pmif->broken_dma_warn == 0) {
1739 printk(KERN_WARNING "%s: DMA on non aligned address,"
1740 "switching to PIO on Ohare chipset\n", drive->name);
1741 pmif->broken_dma_warn = 1;
1742 }
1743 goto use_pio_instead;
1744 }
1745 while (cur_len) {
1746 unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
1747
1748 if (count++ >= MAX_DCMDS) {
1749 printk(KERN_WARNING "%s: DMA table too small\n",
1750 drive->name);
1751 goto use_pio_instead;
1752 }
1753 st_le16(&table->command, wr? OUTPUT_MORE: INPUT_MORE);
1754 st_le16(&table->req_count, tc);
1755 st_le32(&table->phy_addr, cur_addr);
1756 table->cmd_dep = 0;
1757 table->xfer_status = 0;
1758 table->res_count = 0;
1759 cur_addr += tc;
1760 cur_len -= tc;
1761 ++table;
1762 }
1763 sg++;
1764 i--;
1765 }
1766
1767 /* convert the last command to an input/output last command */
1768 if (count) {
1769 st_le16(&table[-1].command, wr? OUTPUT_LAST: INPUT_LAST);
1770 /* add the stop command to the end of the list */
1771 memset(table, 0, sizeof(struct dbdma_cmd));
1772 st_le16(&table->command, DBDMA_STOP);
1773 mb();
1774 writel(hwif->dmatable_dma, &dma->cmdptr);
1775 return 1;
1776 }
1777
1778 printk(KERN_DEBUG "%s: empty DMA table?\n", drive->name);
1779 use_pio_instead:
1780 pci_unmap_sg(hwif->pci_dev,
1781 hwif->sg_table,
1782 hwif->sg_nents,
1783 hwif->sg_dma_direction);
1784 return 0; /* revert to PIO for this request */
1785 }
1786
1787 /* Teardown mappings after DMA has completed. */
1788 static void __pmac
1789 pmac_ide_destroy_dmatable (ide_drive_t *drive)
1790 {
1791 ide_hwif_t *hwif = drive->hwif;
1792 struct pci_dev *dev = HWIF(drive)->pci_dev;
1793 struct scatterlist *sg = hwif->sg_table;
1794 int nents = hwif->sg_nents;
1795
1796 if (nents) {
1797 pci_unmap_sg(dev, sg, nents, hwif->sg_dma_direction);
1798 hwif->sg_nents = 0;
1799 }
1800 }
1801
1802 /*
1803 * Pick up best MDMA timing for the drive and apply it
1804 */
1805 static int __pmac
1806 pmac_ide_mdma_enable(ide_drive_t *drive, u16 mode)
1807 {
1808 ide_hwif_t *hwif = HWIF(drive);
1809 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1810 int drive_cycle_time;
1811 struct hd_driveid *id = drive->id;
1812 u32 *timings, *timings2;
1813 u32 timing_local[2];
1814 int ret;
1815
1816 /* which drive is it ? */
1817 timings = &pmif->timings[drive->select.b.unit & 0x01];
1818 timings2 = &pmif->timings[(drive->select.b.unit & 0x01) + 2];
1819
1820 /* Check if drive provide explicit cycle time */
1821 if ((id->field_valid & 2) && (id->eide_dma_time))
1822 drive_cycle_time = id->eide_dma_time;
1823 else
1824 drive_cycle_time = 0;
1825
1826 /* Copy timings to local image */
1827 timing_local[0] = *timings;
1828 timing_local[1] = *timings2;
1829
1830 /* Calculate controller timings */
1831 ret = set_timings_mdma( drive, pmif->kind,
1832 &timing_local[0],
1833 &timing_local[1],
1834 mode,
1835 drive_cycle_time);
1836 if (ret)
1837 return 0;
1838
1839 /* Set feature on drive */
1840 printk(KERN_INFO "%s: Enabling MultiWord DMA %d\n", drive->name, mode & 0xf);
1841 ret = pmac_ide_do_setfeature(drive, mode);
1842 if (ret) {
1843 printk(KERN_WARNING "%s: Failed !\n", drive->name);
1844 return 0;
1845 }
1846
1847 /* Apply timings to controller */
1848 *timings = timing_local[0];
1849 *timings2 = timing_local[1];
1850
1851 /* Set speed info in drive */
1852 drive->current_speed = mode;
1853 if (!drive->init_speed)
1854 drive->init_speed = mode;
1855
1856 return 1;
1857 }
1858
1859 /*
1860 * Pick up best UDMA timing for the drive and apply it
1861 */
1862 static int __pmac
1863 pmac_ide_udma_enable(ide_drive_t *drive, u16 mode)
1864 {
1865 ide_hwif_t *hwif = HWIF(drive);
1866 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1867 u32 *timings, *timings2;
1868 u32 timing_local[2];
1869 int ret;
1870
1871 /* which drive is it ? */
1872 timings = &pmif->timings[drive->select.b.unit & 0x01];
1873 timings2 = &pmif->timings[(drive->select.b.unit & 0x01) + 2];
1874
1875 /* Copy timings to local image */
1876 timing_local[0] = *timings;
1877 timing_local[1] = *timings2;
1878
1879 /* Calculate timings for interface */
1880 if (pmif->kind == controller_un_ata6
1881 || pmif->kind == controller_k2_ata6)
1882 ret = set_timings_udma_ata6( &timing_local[0],
1883 &timing_local[1],
1884 mode);
1885 else if (pmif->kind == controller_sh_ata6)
1886 ret = set_timings_udma_shasta( &timing_local[0],
1887 &timing_local[1],
1888 mode);
1889 else
1890 ret = set_timings_udma_ata4(&timing_local[0], mode);
1891 if (ret)
1892 return 0;
1893
1894 /* Set feature on drive */
1895 printk(KERN_INFO "%s: Enabling Ultra DMA %d\n", drive->name, mode & 0x0f);
1896 ret = pmac_ide_do_setfeature(drive, mode);
1897 if (ret) {
1898 printk(KERN_WARNING "%s: Failed !\n", drive->name);
1899 return 0;
1900 }
1901
1902 /* Apply timings to controller */
1903 *timings = timing_local[0];
1904 *timings2 = timing_local[1];
1905
1906 /* Set speed info in drive */
1907 drive->current_speed = mode;
1908 if (!drive->init_speed)
1909 drive->init_speed = mode;
1910
1911 return 1;
1912 }
1913
1914 /*
1915 * Check what is the best DMA timing setting for the drive and
1916 * call appropriate functions to apply it.
1917 */
1918 static int __pmac
1919 pmac_ide_dma_check(ide_drive_t *drive)
1920 {
1921 struct hd_driveid *id = drive->id;
1922 ide_hwif_t *hwif = HWIF(drive);
1923 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1924 int enable = 1;
1925 int map;
1926 drive->using_dma = 0;
1927
1928 if (drive->media == ide_floppy)
1929 enable = 0;
1930 if (((id->capability & 1) == 0) && !__ide_dma_good_drive(drive))
1931 enable = 0;
1932 if (__ide_dma_bad_drive(drive))
1933 enable = 0;
1934
1935 if (enable) {
1936 short mode;
1937
1938 map = XFER_MWDMA;
1939 if (pmif->kind == controller_kl_ata4
1940 || pmif->kind == controller_un_ata6
1941 || pmif->kind == controller_k2_ata6
1942 || pmif->kind == controller_sh_ata6) {
1943 map |= XFER_UDMA;
1944 if (pmif->cable_80) {
1945 map |= XFER_UDMA_66;
1946 if (pmif->kind == controller_un_ata6 ||
1947 pmif->kind == controller_k2_ata6 ||
1948 pmif->kind == controller_sh_ata6)
1949 map |= XFER_UDMA_100;
1950 if (pmif->kind == controller_sh_ata6)
1951 map |= XFER_UDMA_133;
1952 }
1953 }
1954 mode = ide_find_best_mode(drive, map);
1955 if (mode & XFER_UDMA)
1956 drive->using_dma = pmac_ide_udma_enable(drive, mode);
1957 else if (mode & XFER_MWDMA)
1958 drive->using_dma = pmac_ide_mdma_enable(drive, mode);
1959 hwif->OUTB(0, IDE_CONTROL_REG);
1960 /* Apply settings to controller */
1961 pmac_ide_do_update_timings(drive);
1962 }
1963 return 0;
1964 }
1965
1966 /*
1967 * Prepare a DMA transfer. We build the DMA table, adjust the timings for
1968 * a read on KeyLargo ATA/66 and mark us as waiting for DMA completion
1969 */
1970 static int __pmac
1971 pmac_ide_dma_setup(ide_drive_t *drive)
1972 {
1973 ide_hwif_t *hwif = HWIF(drive);
1974 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1975 struct request *rq = HWGROUP(drive)->rq;
1976 u8 unit = (drive->select.b.unit & 0x01);
1977 u8 ata4;
1978
1979 if (pmif == NULL)
1980 return 1;
1981 ata4 = (pmif->kind == controller_kl_ata4);
1982
1983 if (!pmac_ide_build_dmatable(drive, rq)) {
1984 ide_map_sg(drive, rq);
1985 return 1;
1986 }
1987
1988 /* Apple adds 60ns to wrDataSetup on reads */
1989 if (ata4 && (pmif->timings[unit] & TR_66_UDMA_EN)) {
1990 writel(pmif->timings[unit] + (!rq_data_dir(rq) ? 0x00800000UL : 0),
1991 PMAC_IDE_REG(IDE_TIMING_CONFIG));
1992 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
1993 }
1994
1995 drive->waiting_for_dma = 1;
1996
1997 return 0;
1998 }
1999
2000 static void __pmac
2001 pmac_ide_dma_exec_cmd(ide_drive_t *drive, u8 command)
2002 {
2003 /* issue cmd to drive */
2004 ide_execute_command(drive, command, &ide_dma_intr, 2*WAIT_CMD, NULL);
2005 }
2006
2007 /*
2008 * Kick the DMA controller into life after the DMA command has been issued
2009 * to the drive.
2010 */
2011 static void __pmac
2012 pmac_ide_dma_start(ide_drive_t *drive)
2013 {
2014 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
2015 volatile struct dbdma_regs __iomem *dma;
2016
2017 dma = pmif->dma_regs;
2018
2019 writel((RUN << 16) | RUN, &dma->control);
2020 /* Make sure it gets to the controller right now */
2021 (void)readl(&dma->control);
2022 }
2023
2024 /*
2025 * After a DMA transfer, make sure the controller is stopped
2026 */
2027 static int __pmac
2028 pmac_ide_dma_end (ide_drive_t *drive)
2029 {
2030 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
2031 volatile struct dbdma_regs __iomem *dma;
2032 u32 dstat;
2033
2034 if (pmif == NULL)
2035 return 0;
2036 dma = pmif->dma_regs;
2037
2038 drive->waiting_for_dma = 0;
2039 dstat = readl(&dma->status);
2040 writel(((RUN|WAKE|DEAD) << 16), &dma->control);
2041 pmac_ide_destroy_dmatable(drive);
2042 /* verify good dma status. we don't check for ACTIVE beeing 0. We should...
2043 * in theory, but with ATAPI decices doing buffer underruns, that would
2044 * cause us to disable DMA, which isn't what we want
2045 */
2046 return (dstat & (RUN|DEAD)) != RUN;
2047 }
2048
2049 /*
2050 * Check out that the interrupt we got was for us. We can't always know this
2051 * for sure with those Apple interfaces (well, we could on the recent ones but
2052 * that's not implemented yet), on the other hand, we don't have shared interrupts
2053 * so it's not really a problem
2054 */
2055 static int __pmac
2056 pmac_ide_dma_test_irq (ide_drive_t *drive)
2057 {
2058 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
2059 volatile struct dbdma_regs __iomem *dma;
2060 unsigned long status, timeout;
2061
2062 if (pmif == NULL)
2063 return 0;
2064 dma = pmif->dma_regs;
2065
2066 /* We have to things to deal with here:
2067 *
2068 * - The dbdma won't stop if the command was started
2069 * but completed with an error without transferring all
2070 * datas. This happens when bad blocks are met during
2071 * a multi-block transfer.
2072 *
2073 * - The dbdma fifo hasn't yet finished flushing to
2074 * to system memory when the disk interrupt occurs.
2075 *
2076 */
2077
2078 /* If ACTIVE is cleared, the STOP command have passed and
2079 * transfer is complete.
2080 */
2081 status = readl(&dma->status);
2082 if (!(status & ACTIVE))
2083 return 1;
2084 if (!drive->waiting_for_dma)
2085 printk(KERN_WARNING "ide%d, ide_dma_test_irq \
2086 called while not waiting\n", HWIF(drive)->index);
2087
2088 /* If dbdma didn't execute the STOP command yet, the
2089 * active bit is still set. We consider that we aren't
2090 * sharing interrupts (which is hopefully the case with
2091 * those controllers) and so we just try to flush the
2092 * channel for pending data in the fifo
2093 */
2094 udelay(1);
2095 writel((FLUSH << 16) | FLUSH, &dma->control);
2096 timeout = 0;
2097 for (;;) {
2098 udelay(1);
2099 status = readl(&dma->status);
2100 if ((status & FLUSH) == 0)
2101 break;
2102 if (++timeout > 100) {
2103 printk(KERN_WARNING "ide%d, ide_dma_test_irq \
2104 timeout flushing channel\n", HWIF(drive)->index);
2105 break;
2106 }
2107 }
2108 return 1;
2109 }
2110
2111 static int __pmac
2112 pmac_ide_dma_host_off (ide_drive_t *drive)
2113 {
2114 return 0;
2115 }
2116
2117 static int __pmac
2118 pmac_ide_dma_host_on (ide_drive_t *drive)
2119 {
2120 return 0;
2121 }
2122
2123 static int __pmac
2124 pmac_ide_dma_lostirq (ide_drive_t *drive)
2125 {
2126 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
2127 volatile struct dbdma_regs __iomem *dma;
2128 unsigned long status;
2129
2130 if (pmif == NULL)
2131 return 0;
2132 dma = pmif->dma_regs;
2133
2134 status = readl(&dma->status);
2135 printk(KERN_ERR "ide-pmac lost interrupt, dma status: %lx\n", status);
2136 return 0;
2137 }
2138
2139 /*
2140 * Allocate the data structures needed for using DMA with an interface
2141 * and fill the proper list of functions pointers
2142 */
2143 static void __init
2144 pmac_ide_setup_dma(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif)
2145 {
2146 /* We won't need pci_dev if we switch to generic consistent
2147 * DMA routines ...
2148 */
2149 if (hwif->pci_dev == NULL)
2150 return;
2151 /*
2152 * Allocate space for the DBDMA commands.
2153 * The +2 is +1 for the stop command and +1 to allow for
2154 * aligning the start address to a multiple of 16 bytes.
2155 */
2156 pmif->dma_table_cpu = (struct dbdma_cmd*)pci_alloc_consistent(
2157 hwif->pci_dev,
2158 (MAX_DCMDS + 2) * sizeof(struct dbdma_cmd),
2159 &hwif->dmatable_dma);
2160 if (pmif->dma_table_cpu == NULL) {
2161 printk(KERN_ERR "%s: unable to allocate DMA command list\n",
2162 hwif->name);
2163 return;
2164 }
2165
2166 hwif->ide_dma_off_quietly = &__ide_dma_off_quietly;
2167 hwif->ide_dma_on = &__ide_dma_on;
2168 hwif->ide_dma_check = &pmac_ide_dma_check;
2169 hwif->dma_setup = &pmac_ide_dma_setup;
2170 hwif->dma_exec_cmd = &pmac_ide_dma_exec_cmd;
2171 hwif->dma_start = &pmac_ide_dma_start;
2172 hwif->ide_dma_end = &pmac_ide_dma_end;
2173 hwif->ide_dma_test_irq = &pmac_ide_dma_test_irq;
2174 hwif->ide_dma_host_off = &pmac_ide_dma_host_off;
2175 hwif->ide_dma_host_on = &pmac_ide_dma_host_on;
2176 hwif->ide_dma_timeout = &__ide_dma_timeout;
2177 hwif->ide_dma_lostirq = &pmac_ide_dma_lostirq;
2178
2179 hwif->atapi_dma = 1;
2180 switch(pmif->kind) {
2181 case controller_sh_ata6:
2182 hwif->ultra_mask = pmif->cable_80 ? 0x7f : 0x07;
2183 hwif->mwdma_mask = 0x07;
2184 hwif->swdma_mask = 0x00;
2185 break;
2186 case controller_un_ata6:
2187 case controller_k2_ata6:
2188 hwif->ultra_mask = pmif->cable_80 ? 0x3f : 0x07;
2189 hwif->mwdma_mask = 0x07;
2190 hwif->swdma_mask = 0x00;
2191 break;
2192 case controller_kl_ata4:
2193 hwif->ultra_mask = pmif->cable_80 ? 0x1f : 0x07;
2194 hwif->mwdma_mask = 0x07;
2195 hwif->swdma_mask = 0x00;
2196 break;
2197 default:
2198 hwif->ultra_mask = 0x00;
2199 hwif->mwdma_mask = 0x07;
2200 hwif->swdma_mask = 0x00;
2201 break;
2202 }
2203 }
2204
2205 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
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