2 * Support for IDE interfaces on PowerMacs.
4 * These IDE interfaces are memory-mapped and have a DBDMA channel
7 * Copyright (C) 1998-2003 Paul Mackerras & Ben. Herrenschmidt
8 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
15 * Some code taken from drivers/ide/ide-dma.c:
17 * Copyright (c) 1995-1998 Mark Lord
19 * TODO: - Use pre-calculated (kauai) timing tables all the time and
20 * get rid of the "rounded" tables used previously, so we have the
21 * same table format for all controllers and can then just have one
25 #include <linux/types.h>
26 #include <linux/kernel.h>
27 #include <linux/init.h>
28 #include <linux/delay.h>
29 #include <linux/ide.h>
30 #include <linux/notifier.h>
31 #include <linux/reboot.h>
32 #include <linux/pci.h>
33 #include <linux/adb.h>
34 #include <linux/pmu.h>
35 #include <linux/scatterlist.h>
39 #include <asm/dbdma.h>
41 #include <asm/pci-bridge.h>
42 #include <asm/machdep.h>
43 #include <asm/pmac_feature.h>
44 #include <asm/sections.h>
48 #include <asm/mediabay.h>
51 #include "../ide-timing.h"
55 #define DMA_WAIT_TIMEOUT 50
57 typedef struct pmac_ide_hwif
{
58 unsigned long regbase
;
62 unsigned cable_80
: 1;
63 unsigned mediabay
: 1;
64 unsigned broken_dma
: 1;
65 unsigned broken_dma_warn
: 1;
66 struct device_node
* node
;
67 struct macio_dev
*mdev
;
69 volatile u32 __iomem
* *kauai_fcr
;
70 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
71 /* Those fields are duplicating what is in hwif. We currently
72 * can't use the hwif ones because of some assumptions that are
73 * beeing done by the generic code about the kind of dma controller
74 * and format of the dma table. This will have to be fixed though.
76 volatile struct dbdma_regs __iomem
* dma_regs
;
77 struct dbdma_cmd
* dma_table_cpu
;
83 controller_ohare
, /* OHare based */
84 controller_heathrow
, /* Heathrow/Paddington */
85 controller_kl_ata3
, /* KeyLargo ATA-3 */
86 controller_kl_ata4
, /* KeyLargo ATA-4 */
87 controller_un_ata6
, /* UniNorth2 ATA-6 */
88 controller_k2_ata6
, /* K2 ATA-6 */
89 controller_sh_ata6
, /* Shasta ATA-6 */
92 static const char* model_name
[] = {
93 "OHare ATA", /* OHare based */
94 "Heathrow ATA", /* Heathrow/Paddington */
95 "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */
96 "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */
97 "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */
98 "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */
99 "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */
103 * Extra registers, both 32-bit little-endian
105 #define IDE_TIMING_CONFIG 0x200
106 #define IDE_INTERRUPT 0x300
108 /* Kauai (U2) ATA has different register setup */
109 #define IDE_KAUAI_PIO_CONFIG 0x200
110 #define IDE_KAUAI_ULTRA_CONFIG 0x210
111 #define IDE_KAUAI_POLL_CONFIG 0x220
114 * Timing configuration register definitions
117 /* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */
118 #define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
119 #define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
120 #define IDE_SYSCLK_NS 30 /* 33Mhz cell */
121 #define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */
123 /* 133Mhz cell, found in shasta.
124 * See comments about 100 Mhz Uninorth 2...
125 * Note that PIO_MASK and MDMA_MASK seem to overlap
127 #define TR_133_PIOREG_PIO_MASK 0xff000fff
128 #define TR_133_PIOREG_MDMA_MASK 0x00fff800
129 #define TR_133_UDMAREG_UDMA_MASK 0x0003ffff
130 #define TR_133_UDMAREG_UDMA_EN 0x00000001
132 /* 100Mhz cell, found in Uninorth 2. I don't have much infos about
133 * this one yet, it appears as a pci device (106b/0033) on uninorth
134 * internal PCI bus and it's clock is controlled like gem or fw. It
135 * appears to be an evolution of keylargo ATA4 with a timing register
136 * extended to 2 32bits registers and a similar DBDMA channel. Other
137 * registers seem to exist but I can't tell much about them.
139 * So far, I'm using pre-calculated tables for this extracted from
140 * the values used by the MacOS X driver.
142 * The "PIO" register controls PIO and MDMA timings, the "ULTRA"
143 * register controls the UDMA timings. At least, it seems bit 0
144 * of this one enables UDMA vs. MDMA, and bits 4..7 are the
145 * cycle time in units of 10ns. Bits 8..15 are used by I don't
146 * know their meaning yet
148 #define TR_100_PIOREG_PIO_MASK 0xff000fff
149 #define TR_100_PIOREG_MDMA_MASK 0x00fff000
150 #define TR_100_UDMAREG_UDMA_MASK 0x0000ffff
151 #define TR_100_UDMAREG_UDMA_EN 0x00000001
154 /* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
155 * 40 connector cable and to 4 on 80 connector one.
156 * Clock unit is 15ns (66Mhz)
158 * 3 Values can be programmed:
159 * - Write data setup, which appears to match the cycle time. They
160 * also call it DIOW setup.
161 * - Ready to pause time (from spec)
162 * - Address setup. That one is weird. I don't see where exactly
163 * it fits in UDMA cycles, I got it's name from an obscure piece
164 * of commented out code in Darwin. They leave it to 0, we do as
165 * well, despite a comment that would lead to think it has a
167 * Apple also add 60ns to the write data setup (or cycle time ?) on
170 #define TR_66_UDMA_MASK 0xfff00000
171 #define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */
172 #define TR_66_UDMA_ADDRSETUP_MASK 0xe0000000 /* Address setup */
173 #define TR_66_UDMA_ADDRSETUP_SHIFT 29
174 #define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */
175 #define TR_66_UDMA_RDY2PAUS_SHIFT 25
176 #define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */
177 #define TR_66_UDMA_WRDATASETUP_SHIFT 21
178 #define TR_66_MDMA_MASK 0x000ffc00
179 #define TR_66_MDMA_RECOVERY_MASK 0x000f8000
180 #define TR_66_MDMA_RECOVERY_SHIFT 15
181 #define TR_66_MDMA_ACCESS_MASK 0x00007c00
182 #define TR_66_MDMA_ACCESS_SHIFT 10
183 #define TR_66_PIO_MASK 0x000003ff
184 #define TR_66_PIO_RECOVERY_MASK 0x000003e0
185 #define TR_66_PIO_RECOVERY_SHIFT 5
186 #define TR_66_PIO_ACCESS_MASK 0x0000001f
187 #define TR_66_PIO_ACCESS_SHIFT 0
189 /* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo
190 * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
192 * The access time and recovery time can be programmed. Some older
193 * Darwin code base limit OHare to 150ns cycle time. I decided to do
194 * the same here fore safety against broken old hardware ;)
195 * The HalfTick bit, when set, adds half a clock (15ns) to the access
196 * time and removes one from recovery. It's not supported on KeyLargo
197 * implementation afaik. The E bit appears to be set for PIO mode 0 and
198 * is used to reach long timings used in this mode.
200 #define TR_33_MDMA_MASK 0x003ff800
201 #define TR_33_MDMA_RECOVERY_MASK 0x001f0000
202 #define TR_33_MDMA_RECOVERY_SHIFT 16
203 #define TR_33_MDMA_ACCESS_MASK 0x0000f800
204 #define TR_33_MDMA_ACCESS_SHIFT 11
205 #define TR_33_MDMA_HALFTICK 0x00200000
206 #define TR_33_PIO_MASK 0x000007ff
207 #define TR_33_PIO_E 0x00000400
208 #define TR_33_PIO_RECOVERY_MASK 0x000003e0
209 #define TR_33_PIO_RECOVERY_SHIFT 5
210 #define TR_33_PIO_ACCESS_MASK 0x0000001f
211 #define TR_33_PIO_ACCESS_SHIFT 0
214 * Interrupt register definitions
216 #define IDE_INTR_DMA 0x80000000
217 #define IDE_INTR_DEVICE 0x40000000
220 * FCR Register on Kauai. Not sure what bit 0x4 is ...
222 #define KAUAI_FCR_UATA_MAGIC 0x00000004
223 #define KAUAI_FCR_UATA_RESET_N 0x00000002
224 #define KAUAI_FCR_UATA_ENABLE 0x00000001
226 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
228 /* Rounded Multiword DMA timings
230 * I gave up finding a generic formula for all controller
231 * types and instead, built tables based on timing values
232 * used by Apple in Darwin's implementation.
234 struct mdma_timings_t
{
240 struct mdma_timings_t mdma_timings_33
[] =
253 struct mdma_timings_t mdma_timings_33k
[] =
266 struct mdma_timings_t mdma_timings_66
[] =
279 /* KeyLargo ATA-4 Ultra DMA timings (rounded) */
281 int addrSetup
; /* ??? */
284 } kl66_udma_timings
[] =
286 { 0, 180, 120 }, /* Mode 0 */
287 { 0, 150, 90 }, /* 1 */
288 { 0, 120, 60 }, /* 2 */
289 { 0, 90, 45 }, /* 3 */
290 { 0, 90, 30 } /* 4 */
293 /* UniNorth 2 ATA/100 timings */
294 struct kauai_timing
{
299 static struct kauai_timing kauai_pio_timings
[] =
301 { 930 , 0x08000fff },
302 { 600 , 0x08000a92 },
303 { 383 , 0x0800060f },
304 { 360 , 0x08000492 },
305 { 330 , 0x0800048f },
306 { 300 , 0x080003cf },
307 { 270 , 0x080003cc },
308 { 240 , 0x0800038b },
309 { 239 , 0x0800030c },
310 { 180 , 0x05000249 },
311 { 120 , 0x04000148 },
315 static struct kauai_timing kauai_mdma_timings
[] =
317 { 1260 , 0x00fff000 },
318 { 480 , 0x00618000 },
319 { 360 , 0x00492000 },
320 { 270 , 0x0038e000 },
321 { 240 , 0x0030c000 },
322 { 210 , 0x002cb000 },
323 { 180 , 0x00249000 },
324 { 150 , 0x00209000 },
325 { 120 , 0x00148000 },
329 static struct kauai_timing kauai_udma_timings
[] =
331 { 120 , 0x000070c0 },
340 static struct kauai_timing shasta_pio_timings
[] =
342 { 930 , 0x08000fff },
343 { 600 , 0x0A000c97 },
344 { 383 , 0x07000712 },
345 { 360 , 0x040003cd },
346 { 330 , 0x040003cd },
347 { 300 , 0x040003cd },
348 { 270 , 0x040003cd },
349 { 240 , 0x040003cd },
350 { 239 , 0x040003cd },
351 { 180 , 0x0400028b },
352 { 120 , 0x0400010a },
356 static struct kauai_timing shasta_mdma_timings
[] =
358 { 1260 , 0x00fff000 },
359 { 480 , 0x00820800 },
360 { 360 , 0x00820800 },
361 { 270 , 0x00820800 },
362 { 240 , 0x00820800 },
363 { 210 , 0x00820800 },
364 { 180 , 0x00820800 },
365 { 150 , 0x0028b000 },
366 { 120 , 0x001ca000 },
370 static struct kauai_timing shasta_udma133_timings
[] =
372 { 120 , 0x00035901, },
373 { 90 , 0x000348b1, },
374 { 60 , 0x00033881, },
375 { 45 , 0x00033861, },
376 { 30 , 0x00033841, },
377 { 20 , 0x00033031, },
378 { 15 , 0x00033021, },
384 kauai_lookup_timing(struct kauai_timing
* table
, int cycle_time
)
388 for (i
=0; table
[i
].cycle_time
; i
++)
389 if (cycle_time
> table
[i
+1].cycle_time
)
390 return table
[i
].timing_reg
;
395 /* allow up to 256 DBDMA commands per xfer */
396 #define MAX_DCMDS 256
399 * Wait 1s for disk to answer on IDE bus after a hard reset
400 * of the device (via GPIO/FCR).
402 * Some devices seem to "pollute" the bus even after dropping
403 * the BSY bit (typically some combo drives slave on the UDMA
404 * bus) after a hard reset. Since we hard reset all drives on
405 * KeyLargo ATA66, we have to keep that delay around. I may end
406 * up not hard resetting anymore on these and keep the delay only
407 * for older interfaces instead (we have to reset when coming
408 * from MacOS...) --BenH.
410 #define IDE_WAKEUP_DELAY (1*HZ)
412 static int pmac_ide_setup_dma(pmac_ide_hwif_t
*pmif
, ide_hwif_t
*hwif
);
413 static int pmac_ide_build_dmatable(ide_drive_t
*drive
, struct request
*rq
);
414 static void pmac_ide_selectproc(ide_drive_t
*drive
);
415 static void pmac_ide_kauai_selectproc(ide_drive_t
*drive
);
417 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
419 #define PMAC_IDE_REG(x) \
420 ((void __iomem *)((drive)->hwif->io_ports[IDE_DATA_OFFSET] + (x)))
423 * Apply the timings of the proper unit (master/slave) to the shared
424 * timing register when selecting that unit. This version is for
425 * ASICs with a single timing register
428 pmac_ide_selectproc(ide_drive_t
*drive
)
430 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)HWIF(drive
)->hwif_data
;
435 if (drive
->select
.b
.unit
& 0x01)
436 writel(pmif
->timings
[1], PMAC_IDE_REG(IDE_TIMING_CONFIG
));
438 writel(pmif
->timings
[0], PMAC_IDE_REG(IDE_TIMING_CONFIG
));
439 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG
));
443 * Apply the timings of the proper unit (master/slave) to the shared
444 * timing register when selecting that unit. This version is for
445 * ASICs with a dual timing register (Kauai)
448 pmac_ide_kauai_selectproc(ide_drive_t
*drive
)
450 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)HWIF(drive
)->hwif_data
;
455 if (drive
->select
.b
.unit
& 0x01) {
456 writel(pmif
->timings
[1], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG
));
457 writel(pmif
->timings
[3], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG
));
459 writel(pmif
->timings
[0], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG
));
460 writel(pmif
->timings
[2], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG
));
462 (void)readl(PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG
));
466 * Force an update of controller timing values for a given drive
469 pmac_ide_do_update_timings(ide_drive_t
*drive
)
471 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)HWIF(drive
)->hwif_data
;
476 if (pmif
->kind
== controller_sh_ata6
||
477 pmif
->kind
== controller_un_ata6
||
478 pmif
->kind
== controller_k2_ata6
)
479 pmac_ide_kauai_selectproc(drive
);
481 pmac_ide_selectproc(drive
);
485 pmac_outbsync(ide_drive_t
*drive
, u8 value
, unsigned long port
)
489 writeb(value
, (void __iomem
*) port
);
490 tmp
= readl(PMAC_IDE_REG(IDE_TIMING_CONFIG
));
494 * Old tuning functions (called on hdparm -p), sets up drive PIO timings
497 pmac_ide_set_pio_mode(ide_drive_t
*drive
, const u8 pio
)
500 unsigned accessTicks
, recTicks
;
501 unsigned accessTime
, recTime
;
502 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)HWIF(drive
)->hwif_data
;
503 unsigned int cycle_time
;
508 /* which drive is it ? */
509 timings
= &pmif
->timings
[drive
->select
.b
.unit
& 0x01];
512 cycle_time
= ide_pio_cycle_time(drive
, pio
);
514 switch (pmif
->kind
) {
515 case controller_sh_ata6
: {
517 u32 tr
= kauai_lookup_timing(shasta_pio_timings
, cycle_time
);
518 t
= (t
& ~TR_133_PIOREG_PIO_MASK
) | tr
;
521 case controller_un_ata6
:
522 case controller_k2_ata6
: {
524 u32 tr
= kauai_lookup_timing(kauai_pio_timings
, cycle_time
);
525 t
= (t
& ~TR_100_PIOREG_PIO_MASK
) | tr
;
528 case controller_kl_ata4
:
530 recTime
= cycle_time
- ide_pio_timings
[pio
].active_time
531 - ide_pio_timings
[pio
].setup_time
;
532 recTime
= max(recTime
, 150U);
533 accessTime
= ide_pio_timings
[pio
].active_time
;
534 accessTime
= max(accessTime
, 150U);
535 accessTicks
= SYSCLK_TICKS_66(accessTime
);
536 accessTicks
= min(accessTicks
, 0x1fU
);
537 recTicks
= SYSCLK_TICKS_66(recTime
);
538 recTicks
= min(recTicks
, 0x1fU
);
539 t
= (t
& ~TR_66_PIO_MASK
) |
540 (accessTicks
<< TR_66_PIO_ACCESS_SHIFT
) |
541 (recTicks
<< TR_66_PIO_RECOVERY_SHIFT
);
546 recTime
= cycle_time
- ide_pio_timings
[pio
].active_time
547 - ide_pio_timings
[pio
].setup_time
;
548 recTime
= max(recTime
, 150U);
549 accessTime
= ide_pio_timings
[pio
].active_time
;
550 accessTime
= max(accessTime
, 150U);
551 accessTicks
= SYSCLK_TICKS(accessTime
);
552 accessTicks
= min(accessTicks
, 0x1fU
);
553 accessTicks
= max(accessTicks
, 4U);
554 recTicks
= SYSCLK_TICKS(recTime
);
555 recTicks
= min(recTicks
, 0x1fU
);
556 recTicks
= max(recTicks
, 5U) - 4;
558 recTicks
--; /* guess, but it's only for PIO0, so... */
561 t
= (t
& ~TR_33_PIO_MASK
) |
562 (accessTicks
<< TR_33_PIO_ACCESS_SHIFT
) |
563 (recTicks
<< TR_33_PIO_RECOVERY_SHIFT
);
570 #ifdef IDE_PMAC_DEBUG
571 printk(KERN_ERR
"%s: Set PIO timing for mode %d, reg: 0x%08x\n",
572 drive
->name
, pio
, *timings
);
576 pmac_ide_do_update_timings(drive
);
579 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
582 * Calculate KeyLargo ATA/66 UDMA timings
585 set_timings_udma_ata4(u32
*timings
, u8 speed
)
587 unsigned rdyToPauseTicks
, wrDataSetupTicks
, addrTicks
;
589 if (speed
> XFER_UDMA_4
)
592 rdyToPauseTicks
= SYSCLK_TICKS_66(kl66_udma_timings
[speed
& 0xf].rdy2pause
);
593 wrDataSetupTicks
= SYSCLK_TICKS_66(kl66_udma_timings
[speed
& 0xf].wrDataSetup
);
594 addrTicks
= SYSCLK_TICKS_66(kl66_udma_timings
[speed
& 0xf].addrSetup
);
596 *timings
= ((*timings
) & ~(TR_66_UDMA_MASK
| TR_66_MDMA_MASK
)) |
597 (wrDataSetupTicks
<< TR_66_UDMA_WRDATASETUP_SHIFT
) |
598 (rdyToPauseTicks
<< TR_66_UDMA_RDY2PAUS_SHIFT
) |
599 (addrTicks
<<TR_66_UDMA_ADDRSETUP_SHIFT
) |
601 #ifdef IDE_PMAC_DEBUG
602 printk(KERN_ERR
"ide_pmac: Set UDMA timing for mode %d, reg: 0x%08x\n",
603 speed
& 0xf, *timings
);
610 * Calculate Kauai ATA/100 UDMA timings
613 set_timings_udma_ata6(u32
*pio_timings
, u32
*ultra_timings
, u8 speed
)
615 struct ide_timing
*t
= ide_timing_find_mode(speed
);
618 if (speed
> XFER_UDMA_5
|| t
== NULL
)
620 tr
= kauai_lookup_timing(kauai_udma_timings
, (int)t
->udma
);
621 *ultra_timings
= ((*ultra_timings
) & ~TR_100_UDMAREG_UDMA_MASK
) | tr
;
622 *ultra_timings
= (*ultra_timings
) | TR_100_UDMAREG_UDMA_EN
;
628 * Calculate Shasta ATA/133 UDMA timings
631 set_timings_udma_shasta(u32
*pio_timings
, u32
*ultra_timings
, u8 speed
)
633 struct ide_timing
*t
= ide_timing_find_mode(speed
);
636 if (speed
> XFER_UDMA_6
|| t
== NULL
)
638 tr
= kauai_lookup_timing(shasta_udma133_timings
, (int)t
->udma
);
639 *ultra_timings
= ((*ultra_timings
) & ~TR_133_UDMAREG_UDMA_MASK
) | tr
;
640 *ultra_timings
= (*ultra_timings
) | TR_133_UDMAREG_UDMA_EN
;
646 * Calculate MDMA timings for all cells
649 set_timings_mdma(ide_drive_t
*drive
, int intf_type
, u32
*timings
, u32
*timings2
,
652 int cycleTime
, accessTime
= 0, recTime
= 0;
653 unsigned accessTicks
, recTicks
;
654 struct hd_driveid
*id
= drive
->id
;
655 struct mdma_timings_t
* tm
= NULL
;
658 /* Get default cycle time for mode */
659 switch(speed
& 0xf) {
660 case 0: cycleTime
= 480; break;
661 case 1: cycleTime
= 150; break;
662 case 2: cycleTime
= 120; break;
668 /* Check if drive provides explicit DMA cycle time */
669 if ((id
->field_valid
& 2) && id
->eide_dma_time
)
670 cycleTime
= max_t(int, id
->eide_dma_time
, cycleTime
);
672 /* OHare limits according to some old Apple sources */
673 if ((intf_type
== controller_ohare
) && (cycleTime
< 150))
675 /* Get the proper timing array for this controller */
677 case controller_sh_ata6
:
678 case controller_un_ata6
:
679 case controller_k2_ata6
:
681 case controller_kl_ata4
:
682 tm
= mdma_timings_66
;
684 case controller_kl_ata3
:
685 tm
= mdma_timings_33k
;
688 tm
= mdma_timings_33
;
692 /* Lookup matching access & recovery times */
695 if (tm
[i
+1].cycleTime
< cycleTime
)
699 cycleTime
= tm
[i
].cycleTime
;
700 accessTime
= tm
[i
].accessTime
;
701 recTime
= tm
[i
].recoveryTime
;
703 #ifdef IDE_PMAC_DEBUG
704 printk(KERN_ERR
"%s: MDMA, cycleTime: %d, accessTime: %d, recTime: %d\n",
705 drive
->name
, cycleTime
, accessTime
, recTime
);
709 case controller_sh_ata6
: {
711 u32 tr
= kauai_lookup_timing(shasta_mdma_timings
, cycleTime
);
712 *timings
= ((*timings
) & ~TR_133_PIOREG_MDMA_MASK
) | tr
;
713 *timings2
= (*timings2
) & ~TR_133_UDMAREG_UDMA_EN
;
715 case controller_un_ata6
:
716 case controller_k2_ata6
: {
718 u32 tr
= kauai_lookup_timing(kauai_mdma_timings
, cycleTime
);
719 *timings
= ((*timings
) & ~TR_100_PIOREG_MDMA_MASK
) | tr
;
720 *timings2
= (*timings2
) & ~TR_100_UDMAREG_UDMA_EN
;
723 case controller_kl_ata4
:
725 accessTicks
= SYSCLK_TICKS_66(accessTime
);
726 accessTicks
= min(accessTicks
, 0x1fU
);
727 accessTicks
= max(accessTicks
, 0x1U
);
728 recTicks
= SYSCLK_TICKS_66(recTime
);
729 recTicks
= min(recTicks
, 0x1fU
);
730 recTicks
= max(recTicks
, 0x3U
);
731 /* Clear out mdma bits and disable udma */
732 *timings
= ((*timings
) & ~(TR_66_MDMA_MASK
| TR_66_UDMA_MASK
)) |
733 (accessTicks
<< TR_66_MDMA_ACCESS_SHIFT
) |
734 (recTicks
<< TR_66_MDMA_RECOVERY_SHIFT
);
736 case controller_kl_ata3
:
737 /* 33Mhz cell on KeyLargo */
738 accessTicks
= SYSCLK_TICKS(accessTime
);
739 accessTicks
= max(accessTicks
, 1U);
740 accessTicks
= min(accessTicks
, 0x1fU
);
741 accessTime
= accessTicks
* IDE_SYSCLK_NS
;
742 recTicks
= SYSCLK_TICKS(recTime
);
743 recTicks
= max(recTicks
, 1U);
744 recTicks
= min(recTicks
, 0x1fU
);
745 *timings
= ((*timings
) & ~TR_33_MDMA_MASK
) |
746 (accessTicks
<< TR_33_MDMA_ACCESS_SHIFT
) |
747 (recTicks
<< TR_33_MDMA_RECOVERY_SHIFT
);
750 /* 33Mhz cell on others */
752 int origAccessTime
= accessTime
;
753 int origRecTime
= recTime
;
755 accessTicks
= SYSCLK_TICKS(accessTime
);
756 accessTicks
= max(accessTicks
, 1U);
757 accessTicks
= min(accessTicks
, 0x1fU
);
758 accessTime
= accessTicks
* IDE_SYSCLK_NS
;
759 recTicks
= SYSCLK_TICKS(recTime
);
760 recTicks
= max(recTicks
, 2U) - 1;
761 recTicks
= min(recTicks
, 0x1fU
);
762 recTime
= (recTicks
+ 1) * IDE_SYSCLK_NS
;
763 if ((accessTicks
> 1) &&
764 ((accessTime
- IDE_SYSCLK_NS
/2) >= origAccessTime
) &&
765 ((recTime
- IDE_SYSCLK_NS
/2) >= origRecTime
)) {
769 *timings
= ((*timings
) & ~TR_33_MDMA_MASK
) |
770 (accessTicks
<< TR_33_MDMA_ACCESS_SHIFT
) |
771 (recTicks
<< TR_33_MDMA_RECOVERY_SHIFT
);
773 *timings
|= TR_33_MDMA_HALFTICK
;
776 #ifdef IDE_PMAC_DEBUG
777 printk(KERN_ERR
"%s: Set MDMA timing for mode %d, reg: 0x%08x\n",
778 drive
->name
, speed
& 0xf, *timings
);
781 #endif /* #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC */
783 static void pmac_ide_set_dma_mode(ide_drive_t
*drive
, const u8 speed
)
785 int unit
= (drive
->select
.b
.unit
& 0x01);
787 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)HWIF(drive
)->hwif_data
;
788 u32
*timings
, *timings2
, tl
[2];
790 timings
= &pmif
->timings
[unit
];
791 timings2
= &pmif
->timings
[unit
+2];
793 /* Copy timings to local image */
797 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
798 if (speed
>= XFER_UDMA_0
) {
799 if (pmif
->kind
== controller_kl_ata4
)
800 ret
= set_timings_udma_ata4(&tl
[0], speed
);
801 else if (pmif
->kind
== controller_un_ata6
802 || pmif
->kind
== controller_k2_ata6
)
803 ret
= set_timings_udma_ata6(&tl
[0], &tl
[1], speed
);
804 else if (pmif
->kind
== controller_sh_ata6
)
805 ret
= set_timings_udma_shasta(&tl
[0], &tl
[1], speed
);
809 set_timings_mdma(drive
, pmif
->kind
, &tl
[0], &tl
[1], speed
);
810 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
814 /* Apply timings to controller */
818 pmac_ide_do_update_timings(drive
);
822 * Blast some well known "safe" values to the timing registers at init or
823 * wakeup from sleep time, before we do real calculation
826 sanitize_timings(pmac_ide_hwif_t
*pmif
)
828 unsigned int value
, value2
= 0;
831 case controller_sh_ata6
:
835 case controller_un_ata6
:
836 case controller_k2_ata6
:
840 case controller_kl_ata4
:
843 case controller_kl_ata3
:
846 case controller_heathrow
:
847 case controller_ohare
:
852 pmif
->timings
[0] = pmif
->timings
[1] = value
;
853 pmif
->timings
[2] = pmif
->timings
[3] = value2
;
856 /* Suspend call back, should be called after the child devices
857 * have actually been suspended
860 pmac_ide_do_suspend(ide_hwif_t
*hwif
)
862 pmac_ide_hwif_t
*pmif
= (pmac_ide_hwif_t
*)hwif
->hwif_data
;
864 /* We clear the timings */
865 pmif
->timings
[0] = 0;
866 pmif
->timings
[1] = 0;
868 disable_irq(pmif
->irq
);
870 /* The media bay will handle itself just fine */
874 /* Kauai has bus control FCRs directly here */
875 if (pmif
->kauai_fcr
) {
876 u32 fcr
= readl(pmif
->kauai_fcr
);
877 fcr
&= ~(KAUAI_FCR_UATA_RESET_N
| KAUAI_FCR_UATA_ENABLE
);
878 writel(fcr
, pmif
->kauai_fcr
);
881 /* Disable the bus on older machines and the cell on kauai */
882 ppc_md
.feature_call(PMAC_FTR_IDE_ENABLE
, pmif
->node
, pmif
->aapl_bus_id
,
888 /* Resume call back, should be called before the child devices
892 pmac_ide_do_resume(ide_hwif_t
*hwif
)
894 pmac_ide_hwif_t
*pmif
= (pmac_ide_hwif_t
*)hwif
->hwif_data
;
896 /* Hard reset & re-enable controller (do we really need to reset ? -BenH) */
897 if (!pmif
->mediabay
) {
898 ppc_md
.feature_call(PMAC_FTR_IDE_RESET
, pmif
->node
, pmif
->aapl_bus_id
, 1);
899 ppc_md
.feature_call(PMAC_FTR_IDE_ENABLE
, pmif
->node
, pmif
->aapl_bus_id
, 1);
901 ppc_md
.feature_call(PMAC_FTR_IDE_RESET
, pmif
->node
, pmif
->aapl_bus_id
, 0);
903 /* Kauai has it different */
904 if (pmif
->kauai_fcr
) {
905 u32 fcr
= readl(pmif
->kauai_fcr
);
906 fcr
|= KAUAI_FCR_UATA_RESET_N
| KAUAI_FCR_UATA_ENABLE
;
907 writel(fcr
, pmif
->kauai_fcr
);
910 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY
));
913 /* Sanitize drive timings */
914 sanitize_timings(pmif
);
916 enable_irq(pmif
->irq
);
921 static const struct ide_port_info pmac_port_info
= {
923 .host_flags
= IDE_HFLAG_SET_PIO_MODE_KEEP_DMA
|
924 IDE_HFLAG_PIO_NO_DOWNGRADE
|
925 IDE_HFLAG_POST_SET_MODE
|
926 IDE_HFLAG_NO_DMA
| /* no SFF-style DMA */
927 IDE_HFLAG_UNMASK_IRQS
,
928 .pio_mask
= ATA_PIO4
,
929 .mwdma_mask
= ATA_MWDMA2
,
933 * Setup, register & probe an IDE channel driven by this driver, this is
934 * called by one of the 2 probe functions (macio or PCI). Note that a channel
935 * that ends up beeing free of any device is not kept around by this driver
936 * (it is kept in 2.4). This introduce an interface numbering change on some
937 * rare machines unfortunately, but it's better this way.
940 pmac_ide_setup_device(pmac_ide_hwif_t
*pmif
, ide_hwif_t
*hwif
, hw_regs_t
*hw
)
942 struct device_node
*np
= pmif
->node
;
944 u8 idx
[4] = { 0xff, 0xff, 0xff, 0xff };
945 struct ide_port_info d
= pmac_port_info
;
948 pmif
->broken_dma
= pmif
->broken_dma_warn
= 0;
949 if (of_device_is_compatible(np
, "shasta-ata")) {
950 pmif
->kind
= controller_sh_ata6
;
951 d
.udma_mask
= ATA_UDMA6
;
952 } else if (of_device_is_compatible(np
, "kauai-ata")) {
953 pmif
->kind
= controller_un_ata6
;
954 d
.udma_mask
= ATA_UDMA5
;
955 } else if (of_device_is_compatible(np
, "K2-UATA")) {
956 pmif
->kind
= controller_k2_ata6
;
957 d
.udma_mask
= ATA_UDMA5
;
958 } else if (of_device_is_compatible(np
, "keylargo-ata")) {
959 if (strcmp(np
->name
, "ata-4") == 0) {
960 pmif
->kind
= controller_kl_ata4
;
961 d
.udma_mask
= ATA_UDMA4
;
963 pmif
->kind
= controller_kl_ata3
;
964 } else if (of_device_is_compatible(np
, "heathrow-ata")) {
965 pmif
->kind
= controller_heathrow
;
967 pmif
->kind
= controller_ohare
;
968 pmif
->broken_dma
= 1;
971 bidp
= of_get_property(np
, "AAPL,bus-id", NULL
);
972 pmif
->aapl_bus_id
= bidp
? *bidp
: 0;
974 /* Get cable type from device-tree */
975 if (pmif
->kind
== controller_kl_ata4
|| pmif
->kind
== controller_un_ata6
976 || pmif
->kind
== controller_k2_ata6
977 || pmif
->kind
== controller_sh_ata6
) {
978 const char* cable
= of_get_property(np
, "cable-type", NULL
);
979 if (cable
&& !strncmp(cable
, "80-", 3))
982 /* G5's seem to have incorrect cable type in device-tree. Let's assume
983 * they have a 80 conductor cable, this seem to be always the case unless
984 * the user mucked around
986 if (of_device_is_compatible(np
, "K2-UATA") ||
987 of_device_is_compatible(np
, "shasta-ata"))
990 /* On Kauai-type controllers, we make sure the FCR is correct */
992 writel(KAUAI_FCR_UATA_MAGIC
|
993 KAUAI_FCR_UATA_RESET_N
|
994 KAUAI_FCR_UATA_ENABLE
, pmif
->kauai_fcr
);
998 /* Make sure we have sane timings */
999 sanitize_timings(pmif
);
1001 #ifndef CONFIG_PPC64
1002 /* XXX FIXME: Media bay stuff need re-organizing */
1003 if (np
->parent
&& np
->parent
->name
1004 && strcasecmp(np
->parent
->name
, "media-bay") == 0) {
1005 #ifdef CONFIG_PMAC_MEDIABAY
1006 media_bay_set_ide_infos(np
->parent
, pmif
->regbase
, pmif
->irq
,
1008 #endif /* CONFIG_PMAC_MEDIABAY */
1011 pmif
->aapl_bus_id
= 1;
1012 } else if (pmif
->kind
== controller_ohare
) {
1013 /* The code below is having trouble on some ohare machines
1014 * (timing related ?). Until I can put my hand on one of these
1015 * units, I keep the old way
1017 ppc_md
.feature_call(PMAC_FTR_IDE_ENABLE
, np
, 0, 1);
1021 /* This is necessary to enable IDE when net-booting */
1022 ppc_md
.feature_call(PMAC_FTR_IDE_RESET
, np
, pmif
->aapl_bus_id
, 1);
1023 ppc_md
.feature_call(PMAC_FTR_IDE_ENABLE
, np
, pmif
->aapl_bus_id
, 1);
1025 ppc_md
.feature_call(PMAC_FTR_IDE_RESET
, np
, pmif
->aapl_bus_id
, 0);
1026 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY
));
1029 /* Setup MMIO ops */
1030 default_hwif_mmiops(hwif
);
1031 hwif
->OUTBSYNC
= pmac_outbsync
;
1033 /* Tell common code _not_ to mess with resources */
1035 hwif
->hwif_data
= pmif
;
1036 ide_init_port_hw(hwif
, hw
);
1037 hwif
->noprobe
= pmif
->mediabay
;
1038 hwif
->cbl
= pmif
->cable_80
? ATA_CBL_PATA80
: ATA_CBL_PATA40
;
1039 hwif
->set_pio_mode
= pmac_ide_set_pio_mode
;
1040 if (pmif
->kind
== controller_un_ata6
1041 || pmif
->kind
== controller_k2_ata6
1042 || pmif
->kind
== controller_sh_ata6
)
1043 hwif
->selectproc
= pmac_ide_kauai_selectproc
;
1045 hwif
->selectproc
= pmac_ide_selectproc
;
1046 hwif
->set_dma_mode
= pmac_ide_set_dma_mode
;
1048 printk(KERN_INFO
"ide%d: Found Apple %s controller, bus ID %d%s, irq %d\n",
1049 hwif
->index
, model_name
[pmif
->kind
], pmif
->aapl_bus_id
,
1050 pmif
->mediabay
? " (mediabay)" : "", hwif
->irq
);
1052 #ifdef CONFIG_PMAC_MEDIABAY
1053 if (pmif
->mediabay
&& check_media_bay_by_base(pmif
->regbase
, MB_CD
) == 0)
1055 #endif /* CONFIG_PMAC_MEDIABAY */
1057 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1058 if (pmif
->cable_80
== 0)
1059 d
.udma_mask
&= ATA_UDMA2
;
1060 /* has a DBDMA controller channel */
1061 if (pmif
->dma_regs
== 0 || pmac_ide_setup_dma(pmif
, hwif
) < 0)
1063 d
.udma_mask
= d
.mwdma_mask
= 0;
1065 idx
[0] = hwif
->index
;
1067 ide_device_add(idx
, &d
);
1072 static void __devinit
pmac_ide_init_ports(hw_regs_t
*hw
, unsigned long base
)
1076 for (i
= 0; i
< 8; ++i
)
1077 hw
->io_ports
[i
] = base
+ i
* 0x10;
1078 hw
->io_ports
[8] = base
+ 0x160;
1082 * Attach to a macio probed interface
1084 static int __devinit
1085 pmac_ide_macio_attach(struct macio_dev
*mdev
, const struct of_device_id
*match
)
1088 unsigned long regbase
;
1091 pmac_ide_hwif_t
*pmif
;
1095 pmif
= kzalloc(sizeof(*pmif
), GFP_KERNEL
);
1100 while (i
< MAX_HWIFS
&& (ide_hwifs
[i
].io_ports
[IDE_DATA_OFFSET
] != 0))
1102 if (i
>= MAX_HWIFS
) {
1103 printk(KERN_ERR
"ide-pmac: MacIO interface attach with no slot\n");
1104 printk(KERN_ERR
" %s\n", mdev
->ofdev
.node
->full_name
);
1109 hwif
= &ide_hwifs
[i
];
1111 if (macio_resource_count(mdev
) == 0) {
1112 printk(KERN_WARNING
"ide%d: no address for %s\n",
1113 i
, mdev
->ofdev
.node
->full_name
);
1118 /* Request memory resource for IO ports */
1119 if (macio_request_resource(mdev
, 0, "ide-pmac (ports)")) {
1120 printk(KERN_ERR
"ide%d: can't request mmio resource !\n", i
);
1125 /* XXX This is bogus. Should be fixed in the registry by checking
1126 * the kind of host interrupt controller, a bit like gatwick
1127 * fixes in irq.c. That works well enough for the single case
1128 * where that happens though...
1130 if (macio_irq_count(mdev
) == 0) {
1131 printk(KERN_WARNING
"ide%d: no intrs for device %s, using 13\n",
1132 i
, mdev
->ofdev
.node
->full_name
);
1133 irq
= irq_create_mapping(NULL
, 13);
1135 irq
= macio_irq(mdev
, 0);
1137 base
= ioremap(macio_resource_start(mdev
, 0), 0x400);
1138 regbase
= (unsigned long) base
;
1140 hwif
->dev
= &mdev
->bus
->pdev
->dev
;
1143 pmif
->node
= mdev
->ofdev
.node
;
1144 pmif
->regbase
= regbase
;
1146 pmif
->kauai_fcr
= NULL
;
1147 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1148 if (macio_resource_count(mdev
) >= 2) {
1149 if (macio_request_resource(mdev
, 1, "ide-pmac (dma)"))
1150 printk(KERN_WARNING
"ide%d: can't request DMA resource !\n", i
);
1152 pmif
->dma_regs
= ioremap(macio_resource_start(mdev
, 1), 0x1000);
1154 pmif
->dma_regs
= NULL
;
1155 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1156 dev_set_drvdata(&mdev
->ofdev
.dev
, hwif
);
1158 memset(&hw
, 0, sizeof(hw
));
1159 pmac_ide_init_ports(&hw
, pmif
->regbase
);
1161 hw
.dev
= &mdev
->ofdev
.dev
;
1163 rc
= pmac_ide_setup_device(pmif
, hwif
, &hw
);
1165 /* The inteface is released to the common IDE layer */
1166 dev_set_drvdata(&mdev
->ofdev
.dev
, NULL
);
1168 if (pmif
->dma_regs
) {
1169 iounmap(pmif
->dma_regs
);
1170 macio_release_resource(mdev
, 1);
1172 macio_release_resource(mdev
, 0);
1184 pmac_ide_macio_suspend(struct macio_dev
*mdev
, pm_message_t mesg
)
1186 ide_hwif_t
*hwif
= (ide_hwif_t
*)dev_get_drvdata(&mdev
->ofdev
.dev
);
1189 if (mesg
.event
!= mdev
->ofdev
.dev
.power
.power_state
.event
1190 && (mesg
.event
& PM_EVENT_SLEEP
)) {
1191 rc
= pmac_ide_do_suspend(hwif
);
1193 mdev
->ofdev
.dev
.power
.power_state
= mesg
;
1200 pmac_ide_macio_resume(struct macio_dev
*mdev
)
1202 ide_hwif_t
*hwif
= (ide_hwif_t
*)dev_get_drvdata(&mdev
->ofdev
.dev
);
1205 if (mdev
->ofdev
.dev
.power
.power_state
.event
!= PM_EVENT_ON
) {
1206 rc
= pmac_ide_do_resume(hwif
);
1208 mdev
->ofdev
.dev
.power
.power_state
= PMSG_ON
;
1215 * Attach to a PCI probed interface
1217 static int __devinit
1218 pmac_ide_pci_attach(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
1221 struct device_node
*np
;
1222 pmac_ide_hwif_t
*pmif
;
1224 unsigned long rbase
, rlen
;
1228 np
= pci_device_to_OF_node(pdev
);
1230 printk(KERN_ERR
"ide-pmac: cannot find MacIO node for Kauai ATA interface\n");
1234 pmif
= kzalloc(sizeof(*pmif
), GFP_KERNEL
);
1239 while (i
< MAX_HWIFS
&& (ide_hwifs
[i
].io_ports
[IDE_DATA_OFFSET
] != 0))
1241 if (i
>= MAX_HWIFS
) {
1242 printk(KERN_ERR
"ide-pmac: PCI interface attach with no slot\n");
1243 printk(KERN_ERR
" %s\n", np
->full_name
);
1248 hwif
= &ide_hwifs
[i
];
1250 if (pci_enable_device(pdev
)) {
1251 printk(KERN_WARNING
"ide%i: Can't enable PCI device for %s\n",
1256 pci_set_master(pdev
);
1258 if (pci_request_regions(pdev
, "Kauai ATA")) {
1259 printk(KERN_ERR
"ide%d: Cannot obtain PCI resources for %s\n",
1265 hwif
->dev
= &pdev
->dev
;
1269 rbase
= pci_resource_start(pdev
, 0);
1270 rlen
= pci_resource_len(pdev
, 0);
1272 base
= ioremap(rbase
, rlen
);
1273 pmif
->regbase
= (unsigned long) base
+ 0x2000;
1274 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1275 pmif
->dma_regs
= base
+ 0x1000;
1276 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1277 pmif
->kauai_fcr
= base
;
1278 pmif
->irq
= pdev
->irq
;
1280 pci_set_drvdata(pdev
, hwif
);
1282 memset(&hw
, 0, sizeof(hw
));
1283 pmac_ide_init_ports(&hw
, pmif
->regbase
);
1285 hw
.dev
= &pdev
->dev
;
1287 rc
= pmac_ide_setup_device(pmif
, hwif
, &hw
);
1289 /* The inteface is released to the common IDE layer */
1290 pci_set_drvdata(pdev
, NULL
);
1292 pci_release_regions(pdev
);
1304 pmac_ide_pci_suspend(struct pci_dev
*pdev
, pm_message_t mesg
)
1306 ide_hwif_t
*hwif
= (ide_hwif_t
*)pci_get_drvdata(pdev
);
1309 if (mesg
.event
!= pdev
->dev
.power
.power_state
.event
1310 && (mesg
.event
& PM_EVENT_SLEEP
)) {
1311 rc
= pmac_ide_do_suspend(hwif
);
1313 pdev
->dev
.power
.power_state
= mesg
;
1320 pmac_ide_pci_resume(struct pci_dev
*pdev
)
1322 ide_hwif_t
*hwif
= (ide_hwif_t
*)pci_get_drvdata(pdev
);
1325 if (pdev
->dev
.power
.power_state
.event
!= PM_EVENT_ON
) {
1326 rc
= pmac_ide_do_resume(hwif
);
1328 pdev
->dev
.power
.power_state
= PMSG_ON
;
1334 static struct of_device_id pmac_ide_macio_match
[] =
1351 static struct macio_driver pmac_ide_macio_driver
=
1354 .match_table
= pmac_ide_macio_match
,
1355 .probe
= pmac_ide_macio_attach
,
1356 .suspend
= pmac_ide_macio_suspend
,
1357 .resume
= pmac_ide_macio_resume
,
1360 static const struct pci_device_id pmac_ide_pci_match
[] = {
1361 { PCI_VDEVICE(APPLE
, PCI_DEVICE_ID_APPLE_UNI_N_ATA
), 0 },
1362 { PCI_VDEVICE(APPLE
, PCI_DEVICE_ID_APPLE_IPID_ATA100
), 0 },
1363 { PCI_VDEVICE(APPLE
, PCI_DEVICE_ID_APPLE_K2_ATA100
), 0 },
1364 { PCI_VDEVICE(APPLE
, PCI_DEVICE_ID_APPLE_SH_ATA
), 0 },
1365 { PCI_VDEVICE(APPLE
, PCI_DEVICE_ID_APPLE_IPID2_ATA
), 0 },
1369 static struct pci_driver pmac_ide_pci_driver
= {
1371 .id_table
= pmac_ide_pci_match
,
1372 .probe
= pmac_ide_pci_attach
,
1373 .suspend
= pmac_ide_pci_suspend
,
1374 .resume
= pmac_ide_pci_resume
,
1376 MODULE_DEVICE_TABLE(pci
, pmac_ide_pci_match
);
1378 int __init
pmac_ide_probe(void)
1382 if (!machine_is(powermac
))
1385 #ifdef CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST
1386 error
= pci_register_driver(&pmac_ide_pci_driver
);
1389 error
= macio_register_driver(&pmac_ide_macio_driver
);
1391 pci_unregister_driver(&pmac_ide_pci_driver
);
1395 error
= macio_register_driver(&pmac_ide_macio_driver
);
1398 error
= pci_register_driver(&pmac_ide_pci_driver
);
1400 macio_unregister_driver(&pmac_ide_macio_driver
);
1408 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1411 * pmac_ide_build_dmatable builds the DBDMA command list
1412 * for a transfer and sets the DBDMA channel to point to it.
1415 pmac_ide_build_dmatable(ide_drive_t
*drive
, struct request
*rq
)
1417 struct dbdma_cmd
*table
;
1419 ide_hwif_t
*hwif
= HWIF(drive
);
1420 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)hwif
->hwif_data
;
1421 volatile struct dbdma_regs __iomem
*dma
= pmif
->dma_regs
;
1422 struct scatterlist
*sg
;
1423 int wr
= (rq_data_dir(rq
) == WRITE
);
1425 /* DMA table is already aligned */
1426 table
= (struct dbdma_cmd
*) pmif
->dma_table_cpu
;
1428 /* Make sure DMA controller is stopped (necessary ?) */
1429 writel((RUN
|PAUSE
|FLUSH
|WAKE
|DEAD
) << 16, &dma
->control
);
1430 while (readl(&dma
->status
) & RUN
)
1433 hwif
->sg_nents
= i
= ide_build_sglist(drive
, rq
);
1438 /* Build DBDMA commands list */
1439 sg
= hwif
->sg_table
;
1440 while (i
&& sg_dma_len(sg
)) {
1444 cur_addr
= sg_dma_address(sg
);
1445 cur_len
= sg_dma_len(sg
);
1447 if (pmif
->broken_dma
&& cur_addr
& (L1_CACHE_BYTES
- 1)) {
1448 if (pmif
->broken_dma_warn
== 0) {
1449 printk(KERN_WARNING
"%s: DMA on non aligned address, "
1450 "switching to PIO on Ohare chipset\n", drive
->name
);
1451 pmif
->broken_dma_warn
= 1;
1453 goto use_pio_instead
;
1456 unsigned int tc
= (cur_len
< 0xfe00)? cur_len
: 0xfe00;
1458 if (count
++ >= MAX_DCMDS
) {
1459 printk(KERN_WARNING
"%s: DMA table too small\n",
1461 goto use_pio_instead
;
1463 st_le16(&table
->command
, wr
? OUTPUT_MORE
: INPUT_MORE
);
1464 st_le16(&table
->req_count
, tc
);
1465 st_le32(&table
->phy_addr
, cur_addr
);
1467 table
->xfer_status
= 0;
1468 table
->res_count
= 0;
1477 /* convert the last command to an input/output last command */
1479 st_le16(&table
[-1].command
, wr
? OUTPUT_LAST
: INPUT_LAST
);
1480 /* add the stop command to the end of the list */
1481 memset(table
, 0, sizeof(struct dbdma_cmd
));
1482 st_le16(&table
->command
, DBDMA_STOP
);
1484 writel(hwif
->dmatable_dma
, &dma
->cmdptr
);
1488 printk(KERN_DEBUG
"%s: empty DMA table?\n", drive
->name
);
1491 ide_destroy_dmatable(drive
);
1493 return 0; /* revert to PIO for this request */
1496 /* Teardown mappings after DMA has completed. */
1498 pmac_ide_destroy_dmatable (ide_drive_t
*drive
)
1500 ide_hwif_t
*hwif
= drive
->hwif
;
1502 if (hwif
->sg_nents
) {
1503 ide_destroy_dmatable(drive
);
1509 * Prepare a DMA transfer. We build the DMA table, adjust the timings for
1510 * a read on KeyLargo ATA/66 and mark us as waiting for DMA completion
1513 pmac_ide_dma_setup(ide_drive_t
*drive
)
1515 ide_hwif_t
*hwif
= HWIF(drive
);
1516 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)hwif
->hwif_data
;
1517 struct request
*rq
= HWGROUP(drive
)->rq
;
1518 u8 unit
= (drive
->select
.b
.unit
& 0x01);
1523 ata4
= (pmif
->kind
== controller_kl_ata4
);
1525 if (!pmac_ide_build_dmatable(drive
, rq
)) {
1526 ide_map_sg(drive
, rq
);
1530 /* Apple adds 60ns to wrDataSetup on reads */
1531 if (ata4
&& (pmif
->timings
[unit
] & TR_66_UDMA_EN
)) {
1532 writel(pmif
->timings
[unit
] + (!rq_data_dir(rq
) ? 0x00800000UL
: 0),
1533 PMAC_IDE_REG(IDE_TIMING_CONFIG
));
1534 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG
));
1537 drive
->waiting_for_dma
= 1;
1543 pmac_ide_dma_exec_cmd(ide_drive_t
*drive
, u8 command
)
1545 /* issue cmd to drive */
1546 ide_execute_command(drive
, command
, &ide_dma_intr
, 2*WAIT_CMD
, NULL
);
1550 * Kick the DMA controller into life after the DMA command has been issued
1554 pmac_ide_dma_start(ide_drive_t
*drive
)
1556 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)HWIF(drive
)->hwif_data
;
1557 volatile struct dbdma_regs __iomem
*dma
;
1559 dma
= pmif
->dma_regs
;
1561 writel((RUN
<< 16) | RUN
, &dma
->control
);
1562 /* Make sure it gets to the controller right now */
1563 (void)readl(&dma
->control
);
1567 * After a DMA transfer, make sure the controller is stopped
1570 pmac_ide_dma_end (ide_drive_t
*drive
)
1572 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)HWIF(drive
)->hwif_data
;
1573 volatile struct dbdma_regs __iomem
*dma
;
1578 dma
= pmif
->dma_regs
;
1580 drive
->waiting_for_dma
= 0;
1581 dstat
= readl(&dma
->status
);
1582 writel(((RUN
|WAKE
|DEAD
) << 16), &dma
->control
);
1583 pmac_ide_destroy_dmatable(drive
);
1584 /* verify good dma status. we don't check for ACTIVE beeing 0. We should...
1585 * in theory, but with ATAPI decices doing buffer underruns, that would
1586 * cause us to disable DMA, which isn't what we want
1588 return (dstat
& (RUN
|DEAD
)) != RUN
;
1592 * Check out that the interrupt we got was for us. We can't always know this
1593 * for sure with those Apple interfaces (well, we could on the recent ones but
1594 * that's not implemented yet), on the other hand, we don't have shared interrupts
1595 * so it's not really a problem
1598 pmac_ide_dma_test_irq (ide_drive_t
*drive
)
1600 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)HWIF(drive
)->hwif_data
;
1601 volatile struct dbdma_regs __iomem
*dma
;
1602 unsigned long status
, timeout
;
1606 dma
= pmif
->dma_regs
;
1608 /* We have to things to deal with here:
1610 * - The dbdma won't stop if the command was started
1611 * but completed with an error without transferring all
1612 * datas. This happens when bad blocks are met during
1613 * a multi-block transfer.
1615 * - The dbdma fifo hasn't yet finished flushing to
1616 * to system memory when the disk interrupt occurs.
1620 /* If ACTIVE is cleared, the STOP command have passed and
1621 * transfer is complete.
1623 status
= readl(&dma
->status
);
1624 if (!(status
& ACTIVE
))
1626 if (!drive
->waiting_for_dma
)
1627 printk(KERN_WARNING
"ide%d, ide_dma_test_irq \
1628 called while not waiting\n", HWIF(drive
)->index
);
1630 /* If dbdma didn't execute the STOP command yet, the
1631 * active bit is still set. We consider that we aren't
1632 * sharing interrupts (which is hopefully the case with
1633 * those controllers) and so we just try to flush the
1634 * channel for pending data in the fifo
1637 writel((FLUSH
<< 16) | FLUSH
, &dma
->control
);
1641 status
= readl(&dma
->status
);
1642 if ((status
& FLUSH
) == 0)
1644 if (++timeout
> 100) {
1645 printk(KERN_WARNING
"ide%d, ide_dma_test_irq \
1646 timeout flushing channel\n", HWIF(drive
)->index
);
1653 static void pmac_ide_dma_host_set(ide_drive_t
*drive
, int on
)
1658 pmac_ide_dma_lost_irq (ide_drive_t
*drive
)
1660 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)HWIF(drive
)->hwif_data
;
1661 volatile struct dbdma_regs __iomem
*dma
;
1662 unsigned long status
;
1666 dma
= pmif
->dma_regs
;
1668 status
= readl(&dma
->status
);
1669 printk(KERN_ERR
"ide-pmac lost interrupt, dma status: %lx\n", status
);
1673 * Allocate the data structures needed for using DMA with an interface
1674 * and fill the proper list of functions pointers
1676 static int __devinit
pmac_ide_setup_dma(pmac_ide_hwif_t
*pmif
, ide_hwif_t
*hwif
)
1678 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
1680 /* We won't need pci_dev if we switch to generic consistent
1686 * Allocate space for the DBDMA commands.
1687 * The +2 is +1 for the stop command and +1 to allow for
1688 * aligning the start address to a multiple of 16 bytes.
1690 pmif
->dma_table_cpu
= (struct dbdma_cmd
*)pci_alloc_consistent(
1692 (MAX_DCMDS
+ 2) * sizeof(struct dbdma_cmd
),
1693 &hwif
->dmatable_dma
);
1694 if (pmif
->dma_table_cpu
== NULL
) {
1695 printk(KERN_ERR
"%s: unable to allocate DMA command list\n",
1700 hwif
->sg_max_nents
= MAX_DCMDS
;
1702 hwif
->dma_host_set
= &pmac_ide_dma_host_set
;
1703 hwif
->dma_setup
= &pmac_ide_dma_setup
;
1704 hwif
->dma_exec_cmd
= &pmac_ide_dma_exec_cmd
;
1705 hwif
->dma_start
= &pmac_ide_dma_start
;
1706 hwif
->ide_dma_end
= &pmac_ide_dma_end
;
1707 hwif
->ide_dma_test_irq
= &pmac_ide_dma_test_irq
;
1708 hwif
->dma_timeout
= &ide_dma_timeout
;
1709 hwif
->dma_lost_irq
= &pmac_ide_dma_lost_irq
;
1714 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1716 module_init(pmac_ide_probe
);
1718 MODULE_LICENSE("GPL");