2 * linux/drivers/ide/ppc/pmac.c
4 * Support for IDE interfaces on PowerMacs.
5 * These IDE interfaces are memory-mapped and have a DBDMA channel
8 * Copyright (C) 1998-2003 Paul Mackerras & Ben. Herrenschmidt
9 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
16 * Some code taken from drivers/ide/ide-dma.c:
18 * Copyright (c) 1995-1998 Mark Lord
20 * TODO: - Use pre-calculated (kauai) timing tables all the time and
21 * get rid of the "rounded" tables used previously, so we have the
22 * same table format for all controllers and can then just have one
26 #include <linux/types.h>
27 #include <linux/kernel.h>
28 #include <linux/init.h>
29 #include <linux/delay.h>
30 #include <linux/ide.h>
31 #include <linux/notifier.h>
32 #include <linux/reboot.h>
33 #include <linux/pci.h>
34 #include <linux/adb.h>
35 #include <linux/pmu.h>
36 #include <linux/scatterlist.h>
40 #include <asm/dbdma.h>
42 #include <asm/pci-bridge.h>
43 #include <asm/machdep.h>
44 #include <asm/pmac_feature.h>
45 #include <asm/sections.h>
49 #include <asm/mediabay.h>
52 #include "../ide-timing.h"
56 #define DMA_WAIT_TIMEOUT 50
58 typedef struct pmac_ide_hwif
{
59 unsigned long regbase
;
63 unsigned cable_80
: 1;
64 unsigned mediabay
: 1;
65 unsigned broken_dma
: 1;
66 unsigned broken_dma_warn
: 1;
67 struct device_node
* node
;
68 struct macio_dev
*mdev
;
70 volatile u32 __iomem
* *kauai_fcr
;
71 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
72 /* Those fields are duplicating what is in hwif. We currently
73 * can't use the hwif ones because of some assumptions that are
74 * beeing done by the generic code about the kind of dma controller
75 * and format of the dma table. This will have to be fixed though.
77 volatile struct dbdma_regs __iomem
* dma_regs
;
78 struct dbdma_cmd
* dma_table_cpu
;
83 static pmac_ide_hwif_t pmac_ide
[MAX_HWIFS
];
84 static int pmac_ide_count
;
87 controller_ohare
, /* OHare based */
88 controller_heathrow
, /* Heathrow/Paddington */
89 controller_kl_ata3
, /* KeyLargo ATA-3 */
90 controller_kl_ata4
, /* KeyLargo ATA-4 */
91 controller_un_ata6
, /* UniNorth2 ATA-6 */
92 controller_k2_ata6
, /* K2 ATA-6 */
93 controller_sh_ata6
, /* Shasta ATA-6 */
96 static const char* model_name
[] = {
97 "OHare ATA", /* OHare based */
98 "Heathrow ATA", /* Heathrow/Paddington */
99 "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */
100 "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */
101 "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */
102 "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */
103 "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */
107 * Extra registers, both 32-bit little-endian
109 #define IDE_TIMING_CONFIG 0x200
110 #define IDE_INTERRUPT 0x300
112 /* Kauai (U2) ATA has different register setup */
113 #define IDE_KAUAI_PIO_CONFIG 0x200
114 #define IDE_KAUAI_ULTRA_CONFIG 0x210
115 #define IDE_KAUAI_POLL_CONFIG 0x220
118 * Timing configuration register definitions
121 /* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */
122 #define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
123 #define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
124 #define IDE_SYSCLK_NS 30 /* 33Mhz cell */
125 #define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */
127 /* 133Mhz cell, found in shasta.
128 * See comments about 100 Mhz Uninorth 2...
129 * Note that PIO_MASK and MDMA_MASK seem to overlap
131 #define TR_133_PIOREG_PIO_MASK 0xff000fff
132 #define TR_133_PIOREG_MDMA_MASK 0x00fff800
133 #define TR_133_UDMAREG_UDMA_MASK 0x0003ffff
134 #define TR_133_UDMAREG_UDMA_EN 0x00000001
136 /* 100Mhz cell, found in Uninorth 2. I don't have much infos about
137 * this one yet, it appears as a pci device (106b/0033) on uninorth
138 * internal PCI bus and it's clock is controlled like gem or fw. It
139 * appears to be an evolution of keylargo ATA4 with a timing register
140 * extended to 2 32bits registers and a similar DBDMA channel. Other
141 * registers seem to exist but I can't tell much about them.
143 * So far, I'm using pre-calculated tables for this extracted from
144 * the values used by the MacOS X driver.
146 * The "PIO" register controls PIO and MDMA timings, the "ULTRA"
147 * register controls the UDMA timings. At least, it seems bit 0
148 * of this one enables UDMA vs. MDMA, and bits 4..7 are the
149 * cycle time in units of 10ns. Bits 8..15 are used by I don't
150 * know their meaning yet
152 #define TR_100_PIOREG_PIO_MASK 0xff000fff
153 #define TR_100_PIOREG_MDMA_MASK 0x00fff000
154 #define TR_100_UDMAREG_UDMA_MASK 0x0000ffff
155 #define TR_100_UDMAREG_UDMA_EN 0x00000001
158 /* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
159 * 40 connector cable and to 4 on 80 connector one.
160 * Clock unit is 15ns (66Mhz)
162 * 3 Values can be programmed:
163 * - Write data setup, which appears to match the cycle time. They
164 * also call it DIOW setup.
165 * - Ready to pause time (from spec)
166 * - Address setup. That one is weird. I don't see where exactly
167 * it fits in UDMA cycles, I got it's name from an obscure piece
168 * of commented out code in Darwin. They leave it to 0, we do as
169 * well, despite a comment that would lead to think it has a
171 * Apple also add 60ns to the write data setup (or cycle time ?) on
174 #define TR_66_UDMA_MASK 0xfff00000
175 #define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */
176 #define TR_66_UDMA_ADDRSETUP_MASK 0xe0000000 /* Address setup */
177 #define TR_66_UDMA_ADDRSETUP_SHIFT 29
178 #define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */
179 #define TR_66_UDMA_RDY2PAUS_SHIFT 25
180 #define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */
181 #define TR_66_UDMA_WRDATASETUP_SHIFT 21
182 #define TR_66_MDMA_MASK 0x000ffc00
183 #define TR_66_MDMA_RECOVERY_MASK 0x000f8000
184 #define TR_66_MDMA_RECOVERY_SHIFT 15
185 #define TR_66_MDMA_ACCESS_MASK 0x00007c00
186 #define TR_66_MDMA_ACCESS_SHIFT 10
187 #define TR_66_PIO_MASK 0x000003ff
188 #define TR_66_PIO_RECOVERY_MASK 0x000003e0
189 #define TR_66_PIO_RECOVERY_SHIFT 5
190 #define TR_66_PIO_ACCESS_MASK 0x0000001f
191 #define TR_66_PIO_ACCESS_SHIFT 0
193 /* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo
194 * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
196 * The access time and recovery time can be programmed. Some older
197 * Darwin code base limit OHare to 150ns cycle time. I decided to do
198 * the same here fore safety against broken old hardware ;)
199 * The HalfTick bit, when set, adds half a clock (15ns) to the access
200 * time and removes one from recovery. It's not supported on KeyLargo
201 * implementation afaik. The E bit appears to be set for PIO mode 0 and
202 * is used to reach long timings used in this mode.
204 #define TR_33_MDMA_MASK 0x003ff800
205 #define TR_33_MDMA_RECOVERY_MASK 0x001f0000
206 #define TR_33_MDMA_RECOVERY_SHIFT 16
207 #define TR_33_MDMA_ACCESS_MASK 0x0000f800
208 #define TR_33_MDMA_ACCESS_SHIFT 11
209 #define TR_33_MDMA_HALFTICK 0x00200000
210 #define TR_33_PIO_MASK 0x000007ff
211 #define TR_33_PIO_E 0x00000400
212 #define TR_33_PIO_RECOVERY_MASK 0x000003e0
213 #define TR_33_PIO_RECOVERY_SHIFT 5
214 #define TR_33_PIO_ACCESS_MASK 0x0000001f
215 #define TR_33_PIO_ACCESS_SHIFT 0
218 * Interrupt register definitions
220 #define IDE_INTR_DMA 0x80000000
221 #define IDE_INTR_DEVICE 0x40000000
224 * FCR Register on Kauai. Not sure what bit 0x4 is ...
226 #define KAUAI_FCR_UATA_MAGIC 0x00000004
227 #define KAUAI_FCR_UATA_RESET_N 0x00000002
228 #define KAUAI_FCR_UATA_ENABLE 0x00000001
230 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
232 /* Rounded Multiword DMA timings
234 * I gave up finding a generic formula for all controller
235 * types and instead, built tables based on timing values
236 * used by Apple in Darwin's implementation.
238 struct mdma_timings_t
{
244 struct mdma_timings_t mdma_timings_33
[] =
257 struct mdma_timings_t mdma_timings_33k
[] =
270 struct mdma_timings_t mdma_timings_66
[] =
283 /* KeyLargo ATA-4 Ultra DMA timings (rounded) */
285 int addrSetup
; /* ??? */
288 } kl66_udma_timings
[] =
290 { 0, 180, 120 }, /* Mode 0 */
291 { 0, 150, 90 }, /* 1 */
292 { 0, 120, 60 }, /* 2 */
293 { 0, 90, 45 }, /* 3 */
294 { 0, 90, 30 } /* 4 */
297 /* UniNorth 2 ATA/100 timings */
298 struct kauai_timing
{
303 static struct kauai_timing kauai_pio_timings
[] =
305 { 930 , 0x08000fff },
306 { 600 , 0x08000a92 },
307 { 383 , 0x0800060f },
308 { 360 , 0x08000492 },
309 { 330 , 0x0800048f },
310 { 300 , 0x080003cf },
311 { 270 , 0x080003cc },
312 { 240 , 0x0800038b },
313 { 239 , 0x0800030c },
314 { 180 , 0x05000249 },
315 { 120 , 0x04000148 },
319 static struct kauai_timing kauai_mdma_timings
[] =
321 { 1260 , 0x00fff000 },
322 { 480 , 0x00618000 },
323 { 360 , 0x00492000 },
324 { 270 , 0x0038e000 },
325 { 240 , 0x0030c000 },
326 { 210 , 0x002cb000 },
327 { 180 , 0x00249000 },
328 { 150 , 0x00209000 },
329 { 120 , 0x00148000 },
333 static struct kauai_timing kauai_udma_timings
[] =
335 { 120 , 0x000070c0 },
344 static struct kauai_timing shasta_pio_timings
[] =
346 { 930 , 0x08000fff },
347 { 600 , 0x0A000c97 },
348 { 383 , 0x07000712 },
349 { 360 , 0x040003cd },
350 { 330 , 0x040003cd },
351 { 300 , 0x040003cd },
352 { 270 , 0x040003cd },
353 { 240 , 0x040003cd },
354 { 239 , 0x040003cd },
355 { 180 , 0x0400028b },
356 { 120 , 0x0400010a },
360 static struct kauai_timing shasta_mdma_timings
[] =
362 { 1260 , 0x00fff000 },
363 { 480 , 0x00820800 },
364 { 360 , 0x00820800 },
365 { 270 , 0x00820800 },
366 { 240 , 0x00820800 },
367 { 210 , 0x00820800 },
368 { 180 , 0x00820800 },
369 { 150 , 0x0028b000 },
370 { 120 , 0x001ca000 },
374 static struct kauai_timing shasta_udma133_timings
[] =
376 { 120 , 0x00035901, },
377 { 90 , 0x000348b1, },
378 { 60 , 0x00033881, },
379 { 45 , 0x00033861, },
380 { 30 , 0x00033841, },
381 { 20 , 0x00033031, },
382 { 15 , 0x00033021, },
388 kauai_lookup_timing(struct kauai_timing
* table
, int cycle_time
)
392 for (i
=0; table
[i
].cycle_time
; i
++)
393 if (cycle_time
> table
[i
+1].cycle_time
)
394 return table
[i
].timing_reg
;
398 /* allow up to 256 DBDMA commands per xfer */
399 #define MAX_DCMDS 256
402 * Wait 1s for disk to answer on IDE bus after a hard reset
403 * of the device (via GPIO/FCR).
405 * Some devices seem to "pollute" the bus even after dropping
406 * the BSY bit (typically some combo drives slave on the UDMA
407 * bus) after a hard reset. Since we hard reset all drives on
408 * KeyLargo ATA66, we have to keep that delay around. I may end
409 * up not hard resetting anymore on these and keep the delay only
410 * for older interfaces instead (we have to reset when coming
411 * from MacOS...) --BenH.
413 #define IDE_WAKEUP_DELAY (1*HZ)
415 static void pmac_ide_setup_dma(pmac_ide_hwif_t
*pmif
, ide_hwif_t
*hwif
);
416 static int pmac_ide_build_dmatable(ide_drive_t
*drive
, struct request
*rq
);
417 static void pmac_ide_selectproc(ide_drive_t
*drive
);
418 static void pmac_ide_kauai_selectproc(ide_drive_t
*drive
);
420 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
423 * N.B. this can't be an initfunc, because the media-bay task can
424 * call ide_[un]register at any time.
427 pmac_ide_init_hwif_ports(hw_regs_t
*hw
,
428 unsigned long data_port
, unsigned long ctrl_port
,
436 for (ix
= 0; ix
< MAX_HWIFS
; ++ix
)
437 if (data_port
== pmac_ide
[ix
].regbase
)
440 if (ix
>= MAX_HWIFS
) {
441 /* Probably a PCI interface... */
442 for (i
= IDE_DATA_OFFSET
; i
<= IDE_STATUS_OFFSET
; ++i
)
443 hw
->io_ports
[i
] = data_port
+ i
- IDE_DATA_OFFSET
;
444 hw
->io_ports
[IDE_CONTROL_OFFSET
] = ctrl_port
;
448 for (i
= 0; i
< 8; ++i
)
449 hw
->io_ports
[i
] = data_port
+ i
* 0x10;
450 hw
->io_ports
[8] = data_port
+ 0x160;
453 *irq
= pmac_ide
[ix
].irq
;
455 hw
->dev
= &pmac_ide
[ix
].mdev
->ofdev
.dev
;
458 #define PMAC_IDE_REG(x) ((void __iomem *)(IDE_DATA_REG+(x)))
461 * Apply the timings of the proper unit (master/slave) to the shared
462 * timing register when selecting that unit. This version is for
463 * ASICs with a single timing register
466 pmac_ide_selectproc(ide_drive_t
*drive
)
468 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)HWIF(drive
)->hwif_data
;
473 if (drive
->select
.b
.unit
& 0x01)
474 writel(pmif
->timings
[1], PMAC_IDE_REG(IDE_TIMING_CONFIG
));
476 writel(pmif
->timings
[0], PMAC_IDE_REG(IDE_TIMING_CONFIG
));
477 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG
));
481 * Apply the timings of the proper unit (master/slave) to the shared
482 * timing register when selecting that unit. This version is for
483 * ASICs with a dual timing register (Kauai)
486 pmac_ide_kauai_selectproc(ide_drive_t
*drive
)
488 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)HWIF(drive
)->hwif_data
;
493 if (drive
->select
.b
.unit
& 0x01) {
494 writel(pmif
->timings
[1], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG
));
495 writel(pmif
->timings
[3], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG
));
497 writel(pmif
->timings
[0], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG
));
498 writel(pmif
->timings
[2], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG
));
500 (void)readl(PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG
));
504 * Force an update of controller timing values for a given drive
507 pmac_ide_do_update_timings(ide_drive_t
*drive
)
509 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)HWIF(drive
)->hwif_data
;
514 if (pmif
->kind
== controller_sh_ata6
||
515 pmif
->kind
== controller_un_ata6
||
516 pmif
->kind
== controller_k2_ata6
)
517 pmac_ide_kauai_selectproc(drive
);
519 pmac_ide_selectproc(drive
);
523 pmac_outbsync(ide_drive_t
*drive
, u8 value
, unsigned long port
)
527 writeb(value
, (void __iomem
*) port
);
528 tmp
= readl(PMAC_IDE_REG(IDE_TIMING_CONFIG
));
532 * Send the SET_FEATURE IDE command to the drive and update drive->id with
533 * the new state. We currently don't use the generic routine as it used to
534 * cause various trouble, especially with older mediabays.
535 * This code is sometimes triggering a spurrious interrupt though, I need
536 * to sort that out sooner or later and see if I can finally get the
537 * common version to work properly in all cases
540 pmac_ide_do_setfeature(ide_drive_t
*drive
, u8 command
)
542 ide_hwif_t
*hwif
= HWIF(drive
);
545 disable_irq_nosync(hwif
->irq
);
548 SELECT_MASK(drive
, 0);
550 /* Get rid of pending error state */
551 (void) hwif
->INB(IDE_STATUS_REG
);
552 /* Timeout bumped for some powerbooks */
553 if (wait_for_ready(drive
, 2000)) {
554 /* Timeout bumped for some powerbooks */
555 printk(KERN_ERR
"%s: pmac_ide_do_setfeature disk not ready "
556 "before SET_FEATURE!\n", drive
->name
);
560 hwif
->OUTB(drive
->ctl
| 2, IDE_CONTROL_REG
);
561 hwif
->OUTB(command
, IDE_NSECTOR_REG
);
562 hwif
->OUTB(SETFEATURES_XFER
, IDE_FEATURE_REG
);
563 hwif
->OUTBSYNC(drive
, WIN_SETFEATURES
, IDE_COMMAND_REG
);
565 /* Timeout bumped for some powerbooks */
566 result
= wait_for_ready(drive
, 2000);
567 hwif
->OUTB(drive
->ctl
, IDE_CONTROL_REG
);
569 printk(KERN_ERR
"%s: pmac_ide_do_setfeature disk not ready "
570 "after SET_FEATURE !\n", drive
->name
);
572 SELECT_MASK(drive
, 0);
574 drive
->id
->dma_ultra
&= ~0xFF00;
575 drive
->id
->dma_mword
&= ~0x0F00;
576 drive
->id
->dma_1word
&= ~0x0F00;
579 drive
->id
->dma_ultra
|= 0x8080; break;
581 drive
->id
->dma_ultra
|= 0x4040; break;
583 drive
->id
->dma_ultra
|= 0x2020; break;
585 drive
->id
->dma_ultra
|= 0x1010; break;
587 drive
->id
->dma_ultra
|= 0x0808; break;
589 drive
->id
->dma_ultra
|= 0x0404; break;
591 drive
->id
->dma_ultra
|= 0x0202; break;
593 drive
->id
->dma_ultra
|= 0x0101; break;
595 drive
->id
->dma_mword
|= 0x0404; break;
597 drive
->id
->dma_mword
|= 0x0202; break;
599 drive
->id
->dma_mword
|= 0x0101; break;
601 drive
->id
->dma_1word
|= 0x0404; break;
603 drive
->id
->dma_1word
|= 0x0202; break;
605 drive
->id
->dma_1word
|= 0x0101; break;
608 if (!drive
->init_speed
)
609 drive
->init_speed
= command
;
610 drive
->current_speed
= command
;
612 enable_irq(hwif
->irq
);
617 * Old tuning functions (called on hdparm -p), sets up drive PIO timings
620 pmac_ide_set_pio_mode(ide_drive_t
*drive
, const u8 pio
)
623 unsigned accessTicks
, recTicks
;
624 unsigned accessTime
, recTime
;
625 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)HWIF(drive
)->hwif_data
;
626 unsigned int cycle_time
;
631 /* which drive is it ? */
632 timings
= &pmif
->timings
[drive
->select
.b
.unit
& 0x01];
634 cycle_time
= ide_pio_cycle_time(drive
, pio
);
636 switch (pmif
->kind
) {
637 case controller_sh_ata6
: {
639 u32 tr
= kauai_lookup_timing(shasta_pio_timings
, cycle_time
);
642 *timings
= ((*timings
) & ~TR_133_PIOREG_PIO_MASK
) | tr
;
645 case controller_un_ata6
:
646 case controller_k2_ata6
: {
648 u32 tr
= kauai_lookup_timing(kauai_pio_timings
, cycle_time
);
651 *timings
= ((*timings
) & ~TR_100_PIOREG_PIO_MASK
) | tr
;
654 case controller_kl_ata4
:
656 recTime
= cycle_time
- ide_pio_timings
[pio
].active_time
657 - ide_pio_timings
[pio
].setup_time
;
658 recTime
= max(recTime
, 150U);
659 accessTime
= ide_pio_timings
[pio
].active_time
;
660 accessTime
= max(accessTime
, 150U);
661 accessTicks
= SYSCLK_TICKS_66(accessTime
);
662 accessTicks
= min(accessTicks
, 0x1fU
);
663 recTicks
= SYSCLK_TICKS_66(recTime
);
664 recTicks
= min(recTicks
, 0x1fU
);
665 *timings
= ((*timings
) & ~TR_66_PIO_MASK
) |
666 (accessTicks
<< TR_66_PIO_ACCESS_SHIFT
) |
667 (recTicks
<< TR_66_PIO_RECOVERY_SHIFT
);
672 recTime
= cycle_time
- ide_pio_timings
[pio
].active_time
673 - ide_pio_timings
[pio
].setup_time
;
674 recTime
= max(recTime
, 150U);
675 accessTime
= ide_pio_timings
[pio
].active_time
;
676 accessTime
= max(accessTime
, 150U);
677 accessTicks
= SYSCLK_TICKS(accessTime
);
678 accessTicks
= min(accessTicks
, 0x1fU
);
679 accessTicks
= max(accessTicks
, 4U);
680 recTicks
= SYSCLK_TICKS(recTime
);
681 recTicks
= min(recTicks
, 0x1fU
);
682 recTicks
= max(recTicks
, 5U) - 4;
684 recTicks
--; /* guess, but it's only for PIO0, so... */
687 *timings
= ((*timings
) & ~TR_33_PIO_MASK
) |
688 (accessTicks
<< TR_33_PIO_ACCESS_SHIFT
) |
689 (recTicks
<< TR_33_PIO_RECOVERY_SHIFT
);
691 *timings
|= TR_33_PIO_E
;
696 #ifdef IDE_PMAC_DEBUG
697 printk(KERN_ERR
"%s: Set PIO timing for mode %d, reg: 0x%08x\n",
698 drive
->name
, pio
, *timings
);
701 if (pmac_ide_do_setfeature(drive
, XFER_PIO_0
+ pio
))
704 pmac_ide_do_update_timings(drive
);
707 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
710 * Calculate KeyLargo ATA/66 UDMA timings
713 set_timings_udma_ata4(u32
*timings
, u8 speed
)
715 unsigned rdyToPauseTicks
, wrDataSetupTicks
, addrTicks
;
717 if (speed
> XFER_UDMA_4
)
720 rdyToPauseTicks
= SYSCLK_TICKS_66(kl66_udma_timings
[speed
& 0xf].rdy2pause
);
721 wrDataSetupTicks
= SYSCLK_TICKS_66(kl66_udma_timings
[speed
& 0xf].wrDataSetup
);
722 addrTicks
= SYSCLK_TICKS_66(kl66_udma_timings
[speed
& 0xf].addrSetup
);
724 *timings
= ((*timings
) & ~(TR_66_UDMA_MASK
| TR_66_MDMA_MASK
)) |
725 (wrDataSetupTicks
<< TR_66_UDMA_WRDATASETUP_SHIFT
) |
726 (rdyToPauseTicks
<< TR_66_UDMA_RDY2PAUS_SHIFT
) |
727 (addrTicks
<<TR_66_UDMA_ADDRSETUP_SHIFT
) |
729 #ifdef IDE_PMAC_DEBUG
730 printk(KERN_ERR
"ide_pmac: Set UDMA timing for mode %d, reg: 0x%08x\n",
731 speed
& 0xf, *timings
);
738 * Calculate Kauai ATA/100 UDMA timings
741 set_timings_udma_ata6(u32
*pio_timings
, u32
*ultra_timings
, u8 speed
)
743 struct ide_timing
*t
= ide_timing_find_mode(speed
);
746 if (speed
> XFER_UDMA_5
|| t
== NULL
)
748 tr
= kauai_lookup_timing(kauai_udma_timings
, (int)t
->udma
);
751 *ultra_timings
= ((*ultra_timings
) & ~TR_100_UDMAREG_UDMA_MASK
) | tr
;
752 *ultra_timings
= (*ultra_timings
) | TR_100_UDMAREG_UDMA_EN
;
758 * Calculate Shasta ATA/133 UDMA timings
761 set_timings_udma_shasta(u32
*pio_timings
, u32
*ultra_timings
, u8 speed
)
763 struct ide_timing
*t
= ide_timing_find_mode(speed
);
766 if (speed
> XFER_UDMA_6
|| t
== NULL
)
768 tr
= kauai_lookup_timing(shasta_udma133_timings
, (int)t
->udma
);
771 *ultra_timings
= ((*ultra_timings
) & ~TR_133_UDMAREG_UDMA_MASK
) | tr
;
772 *ultra_timings
= (*ultra_timings
) | TR_133_UDMAREG_UDMA_EN
;
778 * Calculate MDMA timings for all cells
781 set_timings_mdma(ide_drive_t
*drive
, int intf_type
, u32
*timings
, u32
*timings2
,
782 u8 speed
, int drive_cycle_time
)
784 int cycleTime
, accessTime
= 0, recTime
= 0;
785 unsigned accessTicks
, recTicks
;
786 struct mdma_timings_t
* tm
= NULL
;
789 /* Get default cycle time for mode */
790 switch(speed
& 0xf) {
791 case 0: cycleTime
= 480; break;
792 case 1: cycleTime
= 150; break;
793 case 2: cycleTime
= 120; break;
797 /* Adjust for drive */
798 if (drive_cycle_time
&& drive_cycle_time
> cycleTime
)
799 cycleTime
= drive_cycle_time
;
800 /* OHare limits according to some old Apple sources */
801 if ((intf_type
== controller_ohare
) && (cycleTime
< 150))
803 /* Get the proper timing array for this controller */
805 case controller_sh_ata6
:
806 case controller_un_ata6
:
807 case controller_k2_ata6
:
809 case controller_kl_ata4
:
810 tm
= mdma_timings_66
;
812 case controller_kl_ata3
:
813 tm
= mdma_timings_33k
;
816 tm
= mdma_timings_33
;
820 /* Lookup matching access & recovery times */
823 if (tm
[i
+1].cycleTime
< cycleTime
)
829 cycleTime
= tm
[i
].cycleTime
;
830 accessTime
= tm
[i
].accessTime
;
831 recTime
= tm
[i
].recoveryTime
;
833 #ifdef IDE_PMAC_DEBUG
834 printk(KERN_ERR
"%s: MDMA, cycleTime: %d, accessTime: %d, recTime: %d\n",
835 drive
->name
, cycleTime
, accessTime
, recTime
);
839 case controller_sh_ata6
: {
841 u32 tr
= kauai_lookup_timing(shasta_mdma_timings
, cycleTime
);
844 *timings
= ((*timings
) & ~TR_133_PIOREG_MDMA_MASK
) | tr
;
845 *timings2
= (*timings2
) & ~TR_133_UDMAREG_UDMA_EN
;
847 case controller_un_ata6
:
848 case controller_k2_ata6
: {
850 u32 tr
= kauai_lookup_timing(kauai_mdma_timings
, cycleTime
);
853 *timings
= ((*timings
) & ~TR_100_PIOREG_MDMA_MASK
) | tr
;
854 *timings2
= (*timings2
) & ~TR_100_UDMAREG_UDMA_EN
;
857 case controller_kl_ata4
:
859 accessTicks
= SYSCLK_TICKS_66(accessTime
);
860 accessTicks
= min(accessTicks
, 0x1fU
);
861 accessTicks
= max(accessTicks
, 0x1U
);
862 recTicks
= SYSCLK_TICKS_66(recTime
);
863 recTicks
= min(recTicks
, 0x1fU
);
864 recTicks
= max(recTicks
, 0x3U
);
865 /* Clear out mdma bits and disable udma */
866 *timings
= ((*timings
) & ~(TR_66_MDMA_MASK
| TR_66_UDMA_MASK
)) |
867 (accessTicks
<< TR_66_MDMA_ACCESS_SHIFT
) |
868 (recTicks
<< TR_66_MDMA_RECOVERY_SHIFT
);
870 case controller_kl_ata3
:
871 /* 33Mhz cell on KeyLargo */
872 accessTicks
= SYSCLK_TICKS(accessTime
);
873 accessTicks
= max(accessTicks
, 1U);
874 accessTicks
= min(accessTicks
, 0x1fU
);
875 accessTime
= accessTicks
* IDE_SYSCLK_NS
;
876 recTicks
= SYSCLK_TICKS(recTime
);
877 recTicks
= max(recTicks
, 1U);
878 recTicks
= min(recTicks
, 0x1fU
);
879 *timings
= ((*timings
) & ~TR_33_MDMA_MASK
) |
880 (accessTicks
<< TR_33_MDMA_ACCESS_SHIFT
) |
881 (recTicks
<< TR_33_MDMA_RECOVERY_SHIFT
);
884 /* 33Mhz cell on others */
886 int origAccessTime
= accessTime
;
887 int origRecTime
= recTime
;
889 accessTicks
= SYSCLK_TICKS(accessTime
);
890 accessTicks
= max(accessTicks
, 1U);
891 accessTicks
= min(accessTicks
, 0x1fU
);
892 accessTime
= accessTicks
* IDE_SYSCLK_NS
;
893 recTicks
= SYSCLK_TICKS(recTime
);
894 recTicks
= max(recTicks
, 2U) - 1;
895 recTicks
= min(recTicks
, 0x1fU
);
896 recTime
= (recTicks
+ 1) * IDE_SYSCLK_NS
;
897 if ((accessTicks
> 1) &&
898 ((accessTime
- IDE_SYSCLK_NS
/2) >= origAccessTime
) &&
899 ((recTime
- IDE_SYSCLK_NS
/2) >= origRecTime
)) {
903 *timings
= ((*timings
) & ~TR_33_MDMA_MASK
) |
904 (accessTicks
<< TR_33_MDMA_ACCESS_SHIFT
) |
905 (recTicks
<< TR_33_MDMA_RECOVERY_SHIFT
);
907 *timings
|= TR_33_MDMA_HALFTICK
;
910 #ifdef IDE_PMAC_DEBUG
911 printk(KERN_ERR
"%s: Set MDMA timing for mode %d, reg: 0x%08x\n",
912 drive
->name
, speed
& 0xf, *timings
);
916 #endif /* #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC */
919 * Speedproc. This function is called by the core to set any of the standard
920 * DMA timing (MDMA or UDMA) to both the drive and the controller.
921 * You may notice we don't use this function on normal "dma check" operation,
922 * our dedicated function is more precise as it uses the drive provided
923 * cycle time value. We should probably fix this one to deal with that too...
925 static int pmac_ide_tune_chipset(ide_drive_t
*drive
, const u8 speed
)
927 int unit
= (drive
->select
.b
.unit
& 0x01);
929 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)HWIF(drive
)->hwif_data
;
930 u32
*timings
, *timings2
;
935 timings
= &pmif
->timings
[unit
];
936 timings2
= &pmif
->timings
[unit
+2];
939 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
947 if (pmif
->kind
== controller_kl_ata4
)
948 ret
= set_timings_udma_ata4(timings
, speed
);
949 else if (pmif
->kind
== controller_un_ata6
950 || pmif
->kind
== controller_k2_ata6
)
951 ret
= set_timings_udma_ata6(timings
, timings2
, speed
);
952 else if (pmif
->kind
== controller_sh_ata6
)
953 ret
= set_timings_udma_shasta(timings
, timings2
, speed
);
960 ret
= set_timings_mdma(drive
, pmif
->kind
, timings
, timings2
, speed
, 0);
966 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
973 ret
= pmac_ide_do_setfeature(drive
, speed
);
977 pmac_ide_do_update_timings(drive
);
983 * Blast some well known "safe" values to the timing registers at init or
984 * wakeup from sleep time, before we do real calculation
987 sanitize_timings(pmac_ide_hwif_t
*pmif
)
989 unsigned int value
, value2
= 0;
992 case controller_sh_ata6
:
996 case controller_un_ata6
:
997 case controller_k2_ata6
:
1001 case controller_kl_ata4
:
1004 case controller_kl_ata3
:
1007 case controller_heathrow
:
1008 case controller_ohare
:
1013 pmif
->timings
[0] = pmif
->timings
[1] = value
;
1014 pmif
->timings
[2] = pmif
->timings
[3] = value2
;
1018 pmac_ide_get_base(int index
)
1020 return pmac_ide
[index
].regbase
;
1024 pmac_ide_check_base(unsigned long base
)
1028 for (ix
= 0; ix
< MAX_HWIFS
; ++ix
)
1029 if (base
== pmac_ide
[ix
].regbase
)
1035 pmac_ide_get_irq(unsigned long base
)
1039 for (ix
= 0; ix
< MAX_HWIFS
; ++ix
)
1040 if (base
== pmac_ide
[ix
].regbase
)
1041 return pmac_ide
[ix
].irq
;
1045 static int ide_majors
[] = { 3, 22, 33, 34, 56, 57 };
1048 pmac_find_ide_boot(char *bootdevice
, int n
)
1053 * Look through the list of IDE interfaces for this one.
1055 for (i
= 0; i
< pmac_ide_count
; ++i
) {
1057 if (!pmac_ide
[i
].node
|| !pmac_ide
[i
].node
->full_name
)
1059 name
= pmac_ide
[i
].node
->full_name
;
1060 if (memcmp(name
, bootdevice
, n
) == 0 && name
[n
] == 0) {
1061 /* XXX should cope with the 2nd drive as well... */
1062 return MKDEV(ide_majors
[i
], 0);
1069 /* Suspend call back, should be called after the child devices
1070 * have actually been suspended
1073 pmac_ide_do_suspend(ide_hwif_t
*hwif
)
1075 pmac_ide_hwif_t
*pmif
= (pmac_ide_hwif_t
*)hwif
->hwif_data
;
1077 /* We clear the timings */
1078 pmif
->timings
[0] = 0;
1079 pmif
->timings
[1] = 0;
1081 disable_irq(pmif
->irq
);
1083 /* The media bay will handle itself just fine */
1087 /* Kauai has bus control FCRs directly here */
1088 if (pmif
->kauai_fcr
) {
1089 u32 fcr
= readl(pmif
->kauai_fcr
);
1090 fcr
&= ~(KAUAI_FCR_UATA_RESET_N
| KAUAI_FCR_UATA_ENABLE
);
1091 writel(fcr
, pmif
->kauai_fcr
);
1094 /* Disable the bus on older machines and the cell on kauai */
1095 ppc_md
.feature_call(PMAC_FTR_IDE_ENABLE
, pmif
->node
, pmif
->aapl_bus_id
,
1101 /* Resume call back, should be called before the child devices
1105 pmac_ide_do_resume(ide_hwif_t
*hwif
)
1107 pmac_ide_hwif_t
*pmif
= (pmac_ide_hwif_t
*)hwif
->hwif_data
;
1109 /* Hard reset & re-enable controller (do we really need to reset ? -BenH) */
1110 if (!pmif
->mediabay
) {
1111 ppc_md
.feature_call(PMAC_FTR_IDE_RESET
, pmif
->node
, pmif
->aapl_bus_id
, 1);
1112 ppc_md
.feature_call(PMAC_FTR_IDE_ENABLE
, pmif
->node
, pmif
->aapl_bus_id
, 1);
1114 ppc_md
.feature_call(PMAC_FTR_IDE_RESET
, pmif
->node
, pmif
->aapl_bus_id
, 0);
1116 /* Kauai has it different */
1117 if (pmif
->kauai_fcr
) {
1118 u32 fcr
= readl(pmif
->kauai_fcr
);
1119 fcr
|= KAUAI_FCR_UATA_RESET_N
| KAUAI_FCR_UATA_ENABLE
;
1120 writel(fcr
, pmif
->kauai_fcr
);
1123 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY
));
1126 /* Sanitize drive timings */
1127 sanitize_timings(pmif
);
1129 enable_irq(pmif
->irq
);
1135 * Setup, register & probe an IDE channel driven by this driver, this is
1136 * called by one of the 2 probe functions (macio or PCI). Note that a channel
1137 * that ends up beeing free of any device is not kept around by this driver
1138 * (it is kept in 2.4). This introduce an interface numbering change on some
1139 * rare machines unfortunately, but it's better this way.
1142 pmac_ide_setup_device(pmac_ide_hwif_t
*pmif
, ide_hwif_t
*hwif
)
1144 struct device_node
*np
= pmif
->node
;
1148 pmif
->broken_dma
= pmif
->broken_dma_warn
= 0;
1149 if (of_device_is_compatible(np
, "shasta-ata"))
1150 pmif
->kind
= controller_sh_ata6
;
1151 else if (of_device_is_compatible(np
, "kauai-ata"))
1152 pmif
->kind
= controller_un_ata6
;
1153 else if (of_device_is_compatible(np
, "K2-UATA"))
1154 pmif
->kind
= controller_k2_ata6
;
1155 else if (of_device_is_compatible(np
, "keylargo-ata")) {
1156 if (strcmp(np
->name
, "ata-4") == 0)
1157 pmif
->kind
= controller_kl_ata4
;
1159 pmif
->kind
= controller_kl_ata3
;
1160 } else if (of_device_is_compatible(np
, "heathrow-ata"))
1161 pmif
->kind
= controller_heathrow
;
1163 pmif
->kind
= controller_ohare
;
1164 pmif
->broken_dma
= 1;
1167 bidp
= of_get_property(np
, "AAPL,bus-id", NULL
);
1168 pmif
->aapl_bus_id
= bidp
? *bidp
: 0;
1170 /* Get cable type from device-tree */
1171 if (pmif
->kind
== controller_kl_ata4
|| pmif
->kind
== controller_un_ata6
1172 || pmif
->kind
== controller_k2_ata6
1173 || pmif
->kind
== controller_sh_ata6
) {
1174 const char* cable
= of_get_property(np
, "cable-type", NULL
);
1175 if (cable
&& !strncmp(cable
, "80-", 3))
1178 /* G5's seem to have incorrect cable type in device-tree. Let's assume
1179 * they have a 80 conductor cable, this seem to be always the case unless
1180 * the user mucked around
1182 if (of_device_is_compatible(np
, "K2-UATA") ||
1183 of_device_is_compatible(np
, "shasta-ata"))
1186 /* On Kauai-type controllers, we make sure the FCR is correct */
1187 if (pmif
->kauai_fcr
)
1188 writel(KAUAI_FCR_UATA_MAGIC
|
1189 KAUAI_FCR_UATA_RESET_N
|
1190 KAUAI_FCR_UATA_ENABLE
, pmif
->kauai_fcr
);
1194 /* Make sure we have sane timings */
1195 sanitize_timings(pmif
);
1197 #ifndef CONFIG_PPC64
1198 /* XXX FIXME: Media bay stuff need re-organizing */
1199 if (np
->parent
&& np
->parent
->name
1200 && strcasecmp(np
->parent
->name
, "media-bay") == 0) {
1201 #ifdef CONFIG_PMAC_MEDIABAY
1202 media_bay_set_ide_infos(np
->parent
, pmif
->regbase
, pmif
->irq
, hwif
->index
);
1203 #endif /* CONFIG_PMAC_MEDIABAY */
1206 pmif
->aapl_bus_id
= 1;
1207 } else if (pmif
->kind
== controller_ohare
) {
1208 /* The code below is having trouble on some ohare machines
1209 * (timing related ?). Until I can put my hand on one of these
1210 * units, I keep the old way
1212 ppc_md
.feature_call(PMAC_FTR_IDE_ENABLE
, np
, 0, 1);
1216 /* This is necessary to enable IDE when net-booting */
1217 ppc_md
.feature_call(PMAC_FTR_IDE_RESET
, np
, pmif
->aapl_bus_id
, 1);
1218 ppc_md
.feature_call(PMAC_FTR_IDE_ENABLE
, np
, pmif
->aapl_bus_id
, 1);
1220 ppc_md
.feature_call(PMAC_FTR_IDE_RESET
, np
, pmif
->aapl_bus_id
, 0);
1221 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY
));
1224 /* Setup MMIO ops */
1225 default_hwif_mmiops(hwif
);
1226 hwif
->OUTBSYNC
= pmac_outbsync
;
1228 /* Tell common code _not_ to mess with resources */
1230 hwif
->hwif_data
= pmif
;
1231 pmac_ide_init_hwif_ports(&hwif
->hw
, pmif
->regbase
, 0, &hwif
->irq
);
1232 memcpy(hwif
->io_ports
, hwif
->hw
.io_ports
, sizeof(hwif
->io_ports
));
1233 hwif
->chipset
= ide_pmac
;
1234 hwif
->noprobe
= !hwif
->io_ports
[IDE_DATA_OFFSET
] || pmif
->mediabay
;
1235 hwif
->hold
= pmif
->mediabay
;
1236 hwif
->cbl
= pmif
->cable_80
? ATA_CBL_PATA80
: ATA_CBL_PATA40
;
1237 hwif
->drives
[0].unmask
= 1;
1238 hwif
->drives
[1].unmask
= 1;
1239 hwif
->pio_mask
= ATA_PIO4
;
1240 hwif
->set_pio_mode
= pmac_ide_set_pio_mode
;
1241 if (pmif
->kind
== controller_un_ata6
1242 || pmif
->kind
== controller_k2_ata6
1243 || pmif
->kind
== controller_sh_ata6
)
1244 hwif
->selectproc
= pmac_ide_kauai_selectproc
;
1246 hwif
->selectproc
= pmac_ide_selectproc
;
1247 hwif
->speedproc
= pmac_ide_tune_chipset
;
1249 printk(KERN_INFO
"ide%d: Found Apple %s controller, bus ID %d%s, irq %d\n",
1250 hwif
->index
, model_name
[pmif
->kind
], pmif
->aapl_bus_id
,
1251 pmif
->mediabay
? " (mediabay)" : "", hwif
->irq
);
1253 #ifdef CONFIG_PMAC_MEDIABAY
1254 if (pmif
->mediabay
&& check_media_bay_by_base(pmif
->regbase
, MB_CD
) == 0)
1256 #endif /* CONFIG_PMAC_MEDIABAY */
1258 hwif
->sg_max_nents
= MAX_DCMDS
;
1260 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1261 /* has a DBDMA controller channel */
1263 pmac_ide_setup_dma(pmif
, hwif
);
1264 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1266 /* We probe the hwif now */
1267 probe_hwif_init(hwif
);
1269 ide_proc_register_port(hwif
);
1275 * Attach to a macio probed interface
1277 static int __devinit
1278 pmac_ide_macio_attach(struct macio_dev
*mdev
, const struct of_device_id
*match
)
1281 unsigned long regbase
;
1284 pmac_ide_hwif_t
*pmif
;
1288 while (i
< MAX_HWIFS
&& (ide_hwifs
[i
].io_ports
[IDE_DATA_OFFSET
] != 0
1289 || pmac_ide
[i
].node
!= NULL
))
1291 if (i
>= MAX_HWIFS
) {
1292 printk(KERN_ERR
"ide-pmac: MacIO interface attach with no slot\n");
1293 printk(KERN_ERR
" %s\n", mdev
->ofdev
.node
->full_name
);
1297 pmif
= &pmac_ide
[i
];
1298 hwif
= &ide_hwifs
[i
];
1300 if (macio_resource_count(mdev
) == 0) {
1301 printk(KERN_WARNING
"ide%d: no address for %s\n",
1302 i
, mdev
->ofdev
.node
->full_name
);
1306 /* Request memory resource for IO ports */
1307 if (macio_request_resource(mdev
, 0, "ide-pmac (ports)")) {
1308 printk(KERN_ERR
"ide%d: can't request mmio resource !\n", i
);
1312 /* XXX This is bogus. Should be fixed in the registry by checking
1313 * the kind of host interrupt controller, a bit like gatwick
1314 * fixes in irq.c. That works well enough for the single case
1315 * where that happens though...
1317 if (macio_irq_count(mdev
) == 0) {
1318 printk(KERN_WARNING
"ide%d: no intrs for device %s, using 13\n",
1319 i
, mdev
->ofdev
.node
->full_name
);
1320 irq
= irq_create_mapping(NULL
, 13);
1322 irq
= macio_irq(mdev
, 0);
1324 base
= ioremap(macio_resource_start(mdev
, 0), 0x400);
1325 regbase
= (unsigned long) base
;
1327 hwif
->pci_dev
= mdev
->bus
->pdev
;
1328 hwif
->gendev
.parent
= &mdev
->ofdev
.dev
;
1331 pmif
->node
= mdev
->ofdev
.node
;
1332 pmif
->regbase
= regbase
;
1334 pmif
->kauai_fcr
= NULL
;
1335 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1336 if (macio_resource_count(mdev
) >= 2) {
1337 if (macio_request_resource(mdev
, 1, "ide-pmac (dma)"))
1338 printk(KERN_WARNING
"ide%d: can't request DMA resource !\n", i
);
1340 pmif
->dma_regs
= ioremap(macio_resource_start(mdev
, 1), 0x1000);
1342 pmif
->dma_regs
= NULL
;
1343 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1344 dev_set_drvdata(&mdev
->ofdev
.dev
, hwif
);
1346 rc
= pmac_ide_setup_device(pmif
, hwif
);
1348 /* The inteface is released to the common IDE layer */
1349 dev_set_drvdata(&mdev
->ofdev
.dev
, NULL
);
1352 iounmap(pmif
->dma_regs
);
1353 memset(pmif
, 0, sizeof(*pmif
));
1354 macio_release_resource(mdev
, 0);
1356 macio_release_resource(mdev
, 1);
1363 pmac_ide_macio_suspend(struct macio_dev
*mdev
, pm_message_t mesg
)
1365 ide_hwif_t
*hwif
= (ide_hwif_t
*)dev_get_drvdata(&mdev
->ofdev
.dev
);
1368 if (mesg
.event
!= mdev
->ofdev
.dev
.power
.power_state
.event
1369 && mesg
.event
== PM_EVENT_SUSPEND
) {
1370 rc
= pmac_ide_do_suspend(hwif
);
1372 mdev
->ofdev
.dev
.power
.power_state
= mesg
;
1379 pmac_ide_macio_resume(struct macio_dev
*mdev
)
1381 ide_hwif_t
*hwif
= (ide_hwif_t
*)dev_get_drvdata(&mdev
->ofdev
.dev
);
1384 if (mdev
->ofdev
.dev
.power
.power_state
.event
!= PM_EVENT_ON
) {
1385 rc
= pmac_ide_do_resume(hwif
);
1387 mdev
->ofdev
.dev
.power
.power_state
= PMSG_ON
;
1394 * Attach to a PCI probed interface
1396 static int __devinit
1397 pmac_ide_pci_attach(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
1400 struct device_node
*np
;
1401 pmac_ide_hwif_t
*pmif
;
1403 unsigned long rbase
, rlen
;
1406 np
= pci_device_to_OF_node(pdev
);
1408 printk(KERN_ERR
"ide-pmac: cannot find MacIO node for Kauai ATA interface\n");
1412 while (i
< MAX_HWIFS
&& (ide_hwifs
[i
].io_ports
[IDE_DATA_OFFSET
] != 0
1413 || pmac_ide
[i
].node
!= NULL
))
1415 if (i
>= MAX_HWIFS
) {
1416 printk(KERN_ERR
"ide-pmac: PCI interface attach with no slot\n");
1417 printk(KERN_ERR
" %s\n", np
->full_name
);
1421 pmif
= &pmac_ide
[i
];
1422 hwif
= &ide_hwifs
[i
];
1424 if (pci_enable_device(pdev
)) {
1425 printk(KERN_WARNING
"ide%i: Can't enable PCI device for %s\n",
1429 pci_set_master(pdev
);
1431 if (pci_request_regions(pdev
, "Kauai ATA")) {
1432 printk(KERN_ERR
"ide%d: Cannot obtain PCI resources for %s\n",
1437 hwif
->pci_dev
= pdev
;
1438 hwif
->gendev
.parent
= &pdev
->dev
;
1442 rbase
= pci_resource_start(pdev
, 0);
1443 rlen
= pci_resource_len(pdev
, 0);
1445 base
= ioremap(rbase
, rlen
);
1446 pmif
->regbase
= (unsigned long) base
+ 0x2000;
1447 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1448 pmif
->dma_regs
= base
+ 0x1000;
1449 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1450 pmif
->kauai_fcr
= base
;
1451 pmif
->irq
= pdev
->irq
;
1453 pci_set_drvdata(pdev
, hwif
);
1455 rc
= pmac_ide_setup_device(pmif
, hwif
);
1457 /* The inteface is released to the common IDE layer */
1458 pci_set_drvdata(pdev
, NULL
);
1460 memset(pmif
, 0, sizeof(*pmif
));
1461 pci_release_regions(pdev
);
1468 pmac_ide_pci_suspend(struct pci_dev
*pdev
, pm_message_t mesg
)
1470 ide_hwif_t
*hwif
= (ide_hwif_t
*)pci_get_drvdata(pdev
);
1473 if (mesg
.event
!= pdev
->dev
.power
.power_state
.event
1474 && mesg
.event
== PM_EVENT_SUSPEND
) {
1475 rc
= pmac_ide_do_suspend(hwif
);
1477 pdev
->dev
.power
.power_state
= mesg
;
1484 pmac_ide_pci_resume(struct pci_dev
*pdev
)
1486 ide_hwif_t
*hwif
= (ide_hwif_t
*)pci_get_drvdata(pdev
);
1489 if (pdev
->dev
.power
.power_state
.event
!= PM_EVENT_ON
) {
1490 rc
= pmac_ide_do_resume(hwif
);
1492 pdev
->dev
.power
.power_state
= PMSG_ON
;
1498 static struct of_device_id pmac_ide_macio_match
[] =
1515 static struct macio_driver pmac_ide_macio_driver
=
1518 .match_table
= pmac_ide_macio_match
,
1519 .probe
= pmac_ide_macio_attach
,
1520 .suspend
= pmac_ide_macio_suspend
,
1521 .resume
= pmac_ide_macio_resume
,
1524 static struct pci_device_id pmac_ide_pci_match
[] = {
1525 { PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_UNI_N_ATA
,
1526 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
1527 { PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_IPID_ATA100
,
1528 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
1529 { PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_K2_ATA100
,
1530 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
1531 { PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_SH_ATA
,
1532 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
1533 { PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_IPID2_ATA
,
1534 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
1538 static struct pci_driver pmac_ide_pci_driver
= {
1540 .id_table
= pmac_ide_pci_match
,
1541 .probe
= pmac_ide_pci_attach
,
1542 .suspend
= pmac_ide_pci_suspend
,
1543 .resume
= pmac_ide_pci_resume
,
1545 MODULE_DEVICE_TABLE(pci
, pmac_ide_pci_match
);
1547 int __init
pmac_ide_probe(void)
1551 if (!machine_is(powermac
))
1554 #ifdef CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST
1555 error
= pci_register_driver(&pmac_ide_pci_driver
);
1558 error
= macio_register_driver(&pmac_ide_macio_driver
);
1560 pci_unregister_driver(&pmac_ide_pci_driver
);
1564 error
= macio_register_driver(&pmac_ide_macio_driver
);
1567 error
= pci_register_driver(&pmac_ide_pci_driver
);
1569 macio_unregister_driver(&pmac_ide_macio_driver
);
1577 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1580 * pmac_ide_build_dmatable builds the DBDMA command list
1581 * for a transfer and sets the DBDMA channel to point to it.
1584 pmac_ide_build_dmatable(ide_drive_t
*drive
, struct request
*rq
)
1586 struct dbdma_cmd
*table
;
1588 ide_hwif_t
*hwif
= HWIF(drive
);
1589 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)hwif
->hwif_data
;
1590 volatile struct dbdma_regs __iomem
*dma
= pmif
->dma_regs
;
1591 struct scatterlist
*sg
;
1592 int wr
= (rq_data_dir(rq
) == WRITE
);
1594 /* DMA table is already aligned */
1595 table
= (struct dbdma_cmd
*) pmif
->dma_table_cpu
;
1597 /* Make sure DMA controller is stopped (necessary ?) */
1598 writel((RUN
|PAUSE
|FLUSH
|WAKE
|DEAD
) << 16, &dma
->control
);
1599 while (readl(&dma
->status
) & RUN
)
1602 hwif
->sg_nents
= i
= ide_build_sglist(drive
, rq
);
1607 /* Build DBDMA commands list */
1608 sg
= hwif
->sg_table
;
1609 while (i
&& sg_dma_len(sg
)) {
1613 cur_addr
= sg_dma_address(sg
);
1614 cur_len
= sg_dma_len(sg
);
1616 if (pmif
->broken_dma
&& cur_addr
& (L1_CACHE_BYTES
- 1)) {
1617 if (pmif
->broken_dma_warn
== 0) {
1618 printk(KERN_WARNING
"%s: DMA on non aligned address,"
1619 "switching to PIO on Ohare chipset\n", drive
->name
);
1620 pmif
->broken_dma_warn
= 1;
1622 goto use_pio_instead
;
1625 unsigned int tc
= (cur_len
< 0xfe00)? cur_len
: 0xfe00;
1627 if (count
++ >= MAX_DCMDS
) {
1628 printk(KERN_WARNING
"%s: DMA table too small\n",
1630 goto use_pio_instead
;
1632 st_le16(&table
->command
, wr
? OUTPUT_MORE
: INPUT_MORE
);
1633 st_le16(&table
->req_count
, tc
);
1634 st_le32(&table
->phy_addr
, cur_addr
);
1636 table
->xfer_status
= 0;
1637 table
->res_count
= 0;
1646 /* convert the last command to an input/output last command */
1648 st_le16(&table
[-1].command
, wr
? OUTPUT_LAST
: INPUT_LAST
);
1649 /* add the stop command to the end of the list */
1650 memset(table
, 0, sizeof(struct dbdma_cmd
));
1651 st_le16(&table
->command
, DBDMA_STOP
);
1653 writel(hwif
->dmatable_dma
, &dma
->cmdptr
);
1657 printk(KERN_DEBUG
"%s: empty DMA table?\n", drive
->name
);
1659 pci_unmap_sg(hwif
->pci_dev
,
1662 hwif
->sg_dma_direction
);
1663 return 0; /* revert to PIO for this request */
1666 /* Teardown mappings after DMA has completed. */
1668 pmac_ide_destroy_dmatable (ide_drive_t
*drive
)
1670 ide_hwif_t
*hwif
= drive
->hwif
;
1671 struct pci_dev
*dev
= HWIF(drive
)->pci_dev
;
1672 struct scatterlist
*sg
= hwif
->sg_table
;
1673 int nents
= hwif
->sg_nents
;
1676 pci_unmap_sg(dev
, sg
, nents
, hwif
->sg_dma_direction
);
1682 * Pick up best MDMA timing for the drive and apply it
1685 pmac_ide_mdma_enable(ide_drive_t
*drive
, u16 mode
)
1687 ide_hwif_t
*hwif
= HWIF(drive
);
1688 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)hwif
->hwif_data
;
1689 int drive_cycle_time
;
1690 struct hd_driveid
*id
= drive
->id
;
1691 u32
*timings
, *timings2
;
1692 u32 timing_local
[2];
1695 /* which drive is it ? */
1696 timings
= &pmif
->timings
[drive
->select
.b
.unit
& 0x01];
1697 timings2
= &pmif
->timings
[(drive
->select
.b
.unit
& 0x01) + 2];
1699 /* Check if drive provide explicit cycle time */
1700 if ((id
->field_valid
& 2) && (id
->eide_dma_time
))
1701 drive_cycle_time
= id
->eide_dma_time
;
1703 drive_cycle_time
= 0;
1705 /* Copy timings to local image */
1706 timing_local
[0] = *timings
;
1707 timing_local
[1] = *timings2
;
1709 /* Calculate controller timings */
1710 ret
= set_timings_mdma( drive
, pmif
->kind
,
1718 /* Set feature on drive */
1719 printk(KERN_INFO
"%s: Enabling MultiWord DMA %d\n", drive
->name
, mode
& 0xf);
1720 ret
= pmac_ide_do_setfeature(drive
, mode
);
1722 printk(KERN_WARNING
"%s: Failed !\n", drive
->name
);
1726 /* Apply timings to controller */
1727 *timings
= timing_local
[0];
1728 *timings2
= timing_local
[1];
1734 * Pick up best UDMA timing for the drive and apply it
1737 pmac_ide_udma_enable(ide_drive_t
*drive
, u16 mode
)
1739 ide_hwif_t
*hwif
= HWIF(drive
);
1740 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)hwif
->hwif_data
;
1741 u32
*timings
, *timings2
;
1742 u32 timing_local
[2];
1745 /* which drive is it ? */
1746 timings
= &pmif
->timings
[drive
->select
.b
.unit
& 0x01];
1747 timings2
= &pmif
->timings
[(drive
->select
.b
.unit
& 0x01) + 2];
1749 /* Copy timings to local image */
1750 timing_local
[0] = *timings
;
1751 timing_local
[1] = *timings2
;
1753 /* Calculate timings for interface */
1754 if (pmif
->kind
== controller_un_ata6
1755 || pmif
->kind
== controller_k2_ata6
)
1756 ret
= set_timings_udma_ata6( &timing_local
[0],
1759 else if (pmif
->kind
== controller_sh_ata6
)
1760 ret
= set_timings_udma_shasta( &timing_local
[0],
1764 ret
= set_timings_udma_ata4(&timing_local
[0], mode
);
1768 /* Set feature on drive */
1769 printk(KERN_INFO
"%s: Enabling Ultra DMA %d\n", drive
->name
, mode
& 0x0f);
1770 ret
= pmac_ide_do_setfeature(drive
, mode
);
1772 printk(KERN_WARNING
"%s: Failed !\n", drive
->name
);
1776 /* Apply timings to controller */
1777 *timings
= timing_local
[0];
1778 *timings2
= timing_local
[1];
1784 * Check what is the best DMA timing setting for the drive and
1785 * call appropriate functions to apply it.
1788 pmac_ide_dma_check(ide_drive_t
*drive
)
1790 struct hd_driveid
*id
= drive
->id
;
1791 ide_hwif_t
*hwif
= HWIF(drive
);
1793 drive
->using_dma
= 0;
1795 if (drive
->media
== ide_floppy
)
1797 if (((id
->capability
& 1) == 0) && !__ide_dma_good_drive(drive
))
1799 if (__ide_dma_bad_drive(drive
))
1803 u8 mode
= ide_max_dma_mode(drive
);
1805 if (mode
>= XFER_UDMA_0
)
1806 drive
->using_dma
= pmac_ide_udma_enable(drive
, mode
);
1807 else if (mode
>= XFER_MW_DMA_0
)
1808 drive
->using_dma
= pmac_ide_mdma_enable(drive
, mode
);
1809 hwif
->OUTB(0, IDE_CONTROL_REG
);
1810 /* Apply settings to controller */
1811 pmac_ide_do_update_timings(drive
);
1817 * Prepare a DMA transfer. We build the DMA table, adjust the timings for
1818 * a read on KeyLargo ATA/66 and mark us as waiting for DMA completion
1821 pmac_ide_dma_setup(ide_drive_t
*drive
)
1823 ide_hwif_t
*hwif
= HWIF(drive
);
1824 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)hwif
->hwif_data
;
1825 struct request
*rq
= HWGROUP(drive
)->rq
;
1826 u8 unit
= (drive
->select
.b
.unit
& 0x01);
1831 ata4
= (pmif
->kind
== controller_kl_ata4
);
1833 if (!pmac_ide_build_dmatable(drive
, rq
)) {
1834 ide_map_sg(drive
, rq
);
1838 /* Apple adds 60ns to wrDataSetup on reads */
1839 if (ata4
&& (pmif
->timings
[unit
] & TR_66_UDMA_EN
)) {
1840 writel(pmif
->timings
[unit
] + (!rq_data_dir(rq
) ? 0x00800000UL
: 0),
1841 PMAC_IDE_REG(IDE_TIMING_CONFIG
));
1842 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG
));
1845 drive
->waiting_for_dma
= 1;
1851 pmac_ide_dma_exec_cmd(ide_drive_t
*drive
, u8 command
)
1853 /* issue cmd to drive */
1854 ide_execute_command(drive
, command
, &ide_dma_intr
, 2*WAIT_CMD
, NULL
);
1858 * Kick the DMA controller into life after the DMA command has been issued
1862 pmac_ide_dma_start(ide_drive_t
*drive
)
1864 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)HWIF(drive
)->hwif_data
;
1865 volatile struct dbdma_regs __iomem
*dma
;
1867 dma
= pmif
->dma_regs
;
1869 writel((RUN
<< 16) | RUN
, &dma
->control
);
1870 /* Make sure it gets to the controller right now */
1871 (void)readl(&dma
->control
);
1875 * After a DMA transfer, make sure the controller is stopped
1878 pmac_ide_dma_end (ide_drive_t
*drive
)
1880 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)HWIF(drive
)->hwif_data
;
1881 volatile struct dbdma_regs __iomem
*dma
;
1886 dma
= pmif
->dma_regs
;
1888 drive
->waiting_for_dma
= 0;
1889 dstat
= readl(&dma
->status
);
1890 writel(((RUN
|WAKE
|DEAD
) << 16), &dma
->control
);
1891 pmac_ide_destroy_dmatable(drive
);
1892 /* verify good dma status. we don't check for ACTIVE beeing 0. We should...
1893 * in theory, but with ATAPI decices doing buffer underruns, that would
1894 * cause us to disable DMA, which isn't what we want
1896 return (dstat
& (RUN
|DEAD
)) != RUN
;
1900 * Check out that the interrupt we got was for us. We can't always know this
1901 * for sure with those Apple interfaces (well, we could on the recent ones but
1902 * that's not implemented yet), on the other hand, we don't have shared interrupts
1903 * so it's not really a problem
1906 pmac_ide_dma_test_irq (ide_drive_t
*drive
)
1908 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)HWIF(drive
)->hwif_data
;
1909 volatile struct dbdma_regs __iomem
*dma
;
1910 unsigned long status
, timeout
;
1914 dma
= pmif
->dma_regs
;
1916 /* We have to things to deal with here:
1918 * - The dbdma won't stop if the command was started
1919 * but completed with an error without transferring all
1920 * datas. This happens when bad blocks are met during
1921 * a multi-block transfer.
1923 * - The dbdma fifo hasn't yet finished flushing to
1924 * to system memory when the disk interrupt occurs.
1928 /* If ACTIVE is cleared, the STOP command have passed and
1929 * transfer is complete.
1931 status
= readl(&dma
->status
);
1932 if (!(status
& ACTIVE
))
1934 if (!drive
->waiting_for_dma
)
1935 printk(KERN_WARNING
"ide%d, ide_dma_test_irq \
1936 called while not waiting\n", HWIF(drive
)->index
);
1938 /* If dbdma didn't execute the STOP command yet, the
1939 * active bit is still set. We consider that we aren't
1940 * sharing interrupts (which is hopefully the case with
1941 * those controllers) and so we just try to flush the
1942 * channel for pending data in the fifo
1945 writel((FLUSH
<< 16) | FLUSH
, &dma
->control
);
1949 status
= readl(&dma
->status
);
1950 if ((status
& FLUSH
) == 0)
1952 if (++timeout
> 100) {
1953 printk(KERN_WARNING
"ide%d, ide_dma_test_irq \
1954 timeout flushing channel\n", HWIF(drive
)->index
);
1961 static void pmac_ide_dma_host_off(ide_drive_t
*drive
)
1965 static void pmac_ide_dma_host_on(ide_drive_t
*drive
)
1970 pmac_ide_dma_lost_irq (ide_drive_t
*drive
)
1972 pmac_ide_hwif_t
* pmif
= (pmac_ide_hwif_t
*)HWIF(drive
)->hwif_data
;
1973 volatile struct dbdma_regs __iomem
*dma
;
1974 unsigned long status
;
1978 dma
= pmif
->dma_regs
;
1980 status
= readl(&dma
->status
);
1981 printk(KERN_ERR
"ide-pmac lost interrupt, dma status: %lx\n", status
);
1985 * Allocate the data structures needed for using DMA with an interface
1986 * and fill the proper list of functions pointers
1989 pmac_ide_setup_dma(pmac_ide_hwif_t
*pmif
, ide_hwif_t
*hwif
)
1991 /* We won't need pci_dev if we switch to generic consistent
1994 if (hwif
->pci_dev
== NULL
)
1997 * Allocate space for the DBDMA commands.
1998 * The +2 is +1 for the stop command and +1 to allow for
1999 * aligning the start address to a multiple of 16 bytes.
2001 pmif
->dma_table_cpu
= (struct dbdma_cmd
*)pci_alloc_consistent(
2003 (MAX_DCMDS
+ 2) * sizeof(struct dbdma_cmd
),
2004 &hwif
->dmatable_dma
);
2005 if (pmif
->dma_table_cpu
== NULL
) {
2006 printk(KERN_ERR
"%s: unable to allocate DMA command list\n",
2011 hwif
->dma_off_quietly
= &ide_dma_off_quietly
;
2012 hwif
->ide_dma_on
= &__ide_dma_on
;
2013 hwif
->ide_dma_check
= &pmac_ide_dma_check
;
2014 hwif
->dma_setup
= &pmac_ide_dma_setup
;
2015 hwif
->dma_exec_cmd
= &pmac_ide_dma_exec_cmd
;
2016 hwif
->dma_start
= &pmac_ide_dma_start
;
2017 hwif
->ide_dma_end
= &pmac_ide_dma_end
;
2018 hwif
->ide_dma_test_irq
= &pmac_ide_dma_test_irq
;
2019 hwif
->dma_host_off
= &pmac_ide_dma_host_off
;
2020 hwif
->dma_host_on
= &pmac_ide_dma_host_on
;
2021 hwif
->dma_timeout
= &ide_dma_timeout
;
2022 hwif
->dma_lost_irq
= &pmac_ide_dma_lost_irq
;
2024 hwif
->atapi_dma
= 1;
2025 switch(pmif
->kind
) {
2026 case controller_sh_ata6
:
2027 hwif
->ultra_mask
= pmif
->cable_80
? 0x7f : 0x07;
2028 hwif
->mwdma_mask
= 0x07;
2029 hwif
->swdma_mask
= 0x00;
2031 case controller_un_ata6
:
2032 case controller_k2_ata6
:
2033 hwif
->ultra_mask
= pmif
->cable_80
? 0x3f : 0x07;
2034 hwif
->mwdma_mask
= 0x07;
2035 hwif
->swdma_mask
= 0x00;
2037 case controller_kl_ata4
:
2038 hwif
->ultra_mask
= pmif
->cable_80
? 0x1f : 0x07;
2039 hwif
->mwdma_mask
= 0x07;
2040 hwif
->swdma_mask
= 0x00;
2043 hwif
->ultra_mask
= 0x00;
2044 hwif
->mwdma_mask
= 0x07;
2045 hwif
->swdma_mask
= 0x00;
2050 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */