2 * SL82C105/Winbond 553 IDE driver
6 * Drive tuning added from Rebel.com's kernel sources
7 * -- Russell King (15/11/98) linux@arm.linux.org.uk
9 * Merge in Russell's HW workarounds, fix various problems
10 * with the timing registers setup.
11 * -- Benjamin Herrenschmidt (01/11/03) benh@kernel.crashing.org
13 * Copyright (C) 2006-2007,2009 MontaVista Software, Inc. <source@mvista.com>
14 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
17 #include <linux/types.h>
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/ide.h>
25 #define DRV_NAME "sl82c105"
30 #define DBG(arg) printk arg
35 * SL82C105 PCI config register 0x40 bits.
37 #define CTRL_IDE_IRQB (1 << 30)
38 #define CTRL_IDE_IRQA (1 << 28)
39 #define CTRL_LEGIRQ (1 << 11)
40 #define CTRL_P1F16 (1 << 5)
41 #define CTRL_P1EN (1 << 4)
42 #define CTRL_P0F16 (1 << 1)
43 #define CTRL_P0EN (1 << 0)
46 * Convert a PIO mode and cycle time to the required on/off times
47 * for the interface. This has protection against runaway timings.
49 static unsigned int get_pio_timings(ide_drive_t
*drive
, u8 pio
)
51 struct ide_timing
*t
= ide_timing_find_mode(XFER_PIO_0
+ pio
);
52 unsigned int cmd_on
, cmd_off
;
55 cmd_on
= (t
->active
+ 29) / 30;
56 cmd_off
= (ide_pio_cycle_time(drive
, pio
) - 30 * cmd_on
+ 29) / 30;
64 if (ide_pio_need_iordy(drive
, pio
))
67 return (cmd_on
- 1) << 8 | (cmd_off
- 1) | iordy
;
71 * Configure the chipset for PIO mode.
73 static void sl82c105_set_pio_mode(ide_drive_t
*drive
, const u8 pio
)
75 struct pci_dev
*dev
= to_pci_dev(drive
->hwif
->dev
);
76 int reg
= 0x44 + drive
->dn
* 4;
79 drv_ctrl
= get_pio_timings(drive
, pio
);
82 * Store the PIO timings so that we can restore them
83 * in case DMA will be turned off...
85 drive
->drive_data
&= 0xffff0000;
86 drive
->drive_data
|= drv_ctrl
;
88 pci_write_config_word(dev
, reg
, drv_ctrl
);
89 pci_read_config_word (dev
, reg
, &drv_ctrl
);
91 printk(KERN_DEBUG
"%s: selected %s (%dns) (%04X)\n", drive
->name
,
92 ide_xfer_verbose(pio
+ XFER_PIO_0
),
93 ide_pio_cycle_time(drive
, pio
), drv_ctrl
);
97 * Configure the chipset for DMA mode.
99 static void sl82c105_set_dma_mode(ide_drive_t
*drive
, const u8 speed
)
101 static u16 mwdma_timings
[] = {0x0707, 0x0201, 0x0200};
104 DBG(("sl82c105_tune_chipset(drive:%s, speed:%s)\n",
105 drive
->name
, ide_xfer_verbose(speed
)));
107 drv_ctrl
= mwdma_timings
[speed
- XFER_MW_DMA_0
];
110 * Store the DMA timings so that we can actually program
111 * them when DMA will be turned on...
113 drive
->drive_data
&= 0x0000ffff;
114 drive
->drive_data
|= (unsigned long)drv_ctrl
<< 16;
117 static int sl82c105_test_irq(ide_hwif_t
*hwif
)
119 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
120 u32 val
, mask
= hwif
->channel
? CTRL_IDE_IRQB
: CTRL_IDE_IRQA
;
122 pci_read_config_dword(dev
, 0x40, &val
);
124 return (val
& mask
) ? 1 : 0;
128 * The SL82C105 holds off all IDE interrupts while in DMA mode until
129 * all DMA activity is completed. Sometimes this causes problems (eg,
130 * when the drive wants to report an error condition).
132 * 0x7e is a "chip testing" register. Bit 2 resets the DMA controller
133 * state machine. We need to kick this to work around various bugs.
135 static inline void sl82c105_reset_host(struct pci_dev
*dev
)
139 pci_read_config_word(dev
, 0x7e, &val
);
140 pci_write_config_word(dev
, 0x7e, val
| (1 << 2));
141 pci_write_config_word(dev
, 0x7e, val
& ~(1 << 2));
145 * If we get an IRQ timeout, it might be that the DMA state machine
146 * got confused. Fix from Todd Inglett. Details from Winbond.
148 * This function is called when the IDE timer expires, the drive
149 * indicates that it is READY, and we were waiting for DMA to complete.
151 static void sl82c105_dma_lost_irq(ide_drive_t
*drive
)
153 ide_hwif_t
*hwif
= drive
->hwif
;
154 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
155 u32 val
, mask
= hwif
->channel
? CTRL_IDE_IRQB
: CTRL_IDE_IRQA
;
158 printk(KERN_WARNING
"sl82c105: lost IRQ, resetting host\n");
161 * Check the raw interrupt from the drive.
163 pci_read_config_dword(dev
, 0x40, &val
);
165 printk(KERN_INFO
"sl82c105: drive was requesting IRQ, "
166 "but host lost it\n");
169 * Was DMA enabled? If so, disable it - we're resetting the
170 * host. The IDE layer will be handling the drive for us.
172 dma_cmd
= inb(hwif
->dma_base
+ ATA_DMA_CMD
);
174 outb(dma_cmd
& ~1, hwif
->dma_base
+ ATA_DMA_CMD
);
175 printk(KERN_INFO
"sl82c105: DMA was enabled\n");
178 sl82c105_reset_host(dev
);
182 * ATAPI devices can cause the SL82C105 DMA state machine to go gaga.
183 * Winbond recommend that the DMA state machine is reset prior to
184 * setting the bus master DMA enable bit.
186 * The generic IDE core will have disabled the BMEN bit before this
187 * function is called.
189 static void sl82c105_dma_start(ide_drive_t
*drive
)
191 ide_hwif_t
*hwif
= drive
->hwif
;
192 struct pci_dev
*dev
= to_pci_dev(hwif
->dev
);
193 int reg
= 0x44 + drive
->dn
* 4;
195 DBG(("%s(drive:%s)\n", __func__
, drive
->name
));
197 pci_write_config_word(dev
, reg
, drive
->drive_data
>> 16);
199 sl82c105_reset_host(dev
);
200 ide_dma_start(drive
);
203 static void sl82c105_dma_clear(ide_drive_t
*drive
)
205 struct pci_dev
*dev
= to_pci_dev(drive
->hwif
->dev
);
207 DBG(("sl82c105_dma_clear(drive:%s)\n", drive
->name
));
209 sl82c105_reset_host(dev
);
212 static int sl82c105_dma_end(ide_drive_t
*drive
)
214 struct pci_dev
*dev
= to_pci_dev(drive
->hwif
->dev
);
215 int reg
= 0x44 + drive
->dn
* 4;
218 DBG(("%s(drive:%s)\n", __func__
, drive
->name
));
220 ret
= ide_dma_end(drive
);
222 pci_write_config_word(dev
, reg
, drive
->drive_data
);
228 * ATA reset will clear the 16 bits mode in the control
229 * register, we need to reprogram it
231 static void sl82c105_resetproc(ide_drive_t
*drive
)
233 struct pci_dev
*dev
= to_pci_dev(drive
->hwif
->dev
);
236 DBG(("sl82c105_resetproc(drive:%s)\n", drive
->name
));
238 pci_read_config_dword(dev
, 0x40, &val
);
239 val
|= (CTRL_P1F16
| CTRL_P0F16
);
240 pci_write_config_dword(dev
, 0x40, val
);
244 * Return the revision of the Winbond bridge
245 * which this function is part of.
247 static u8
sl82c105_bridge_revision(struct pci_dev
*dev
)
249 struct pci_dev
*bridge
;
252 * The bridge should be part of the same device, but function 0.
254 bridge
= pci_get_bus_and_slot(dev
->bus
->number
,
255 PCI_DEVFN(PCI_SLOT(dev
->devfn
), 0));
260 * Make sure it is a Winbond 553 and is an ISA bridge.
262 if (bridge
->vendor
!= PCI_VENDOR_ID_WINBOND
||
263 bridge
->device
!= PCI_DEVICE_ID_WINBOND_83C553
||
264 bridge
->class >> 8 != PCI_CLASS_BRIDGE_ISA
) {
269 * We need to find function 0's revision, not function 1
273 return bridge
->revision
;
277 * Enable the PCI device
279 * --BenH: It's arch fixup code that should enable channels that
280 * have not been enabled by firmware. I decided we can still enable
281 * channel 0 here at least, but channel 1 has to be enabled by
282 * firmware or arch code. We still set both to 16 bits mode.
284 static int init_chipset_sl82c105(struct pci_dev
*dev
)
288 DBG(("init_chipset_sl82c105()\n"));
290 pci_read_config_dword(dev
, 0x40, &val
);
291 val
|= CTRL_P0EN
| CTRL_P0F16
| CTRL_P1F16
;
292 pci_write_config_dword(dev
, 0x40, val
);
297 static const struct ide_port_ops sl82c105_port_ops
= {
298 .set_pio_mode
= sl82c105_set_pio_mode
,
299 .set_dma_mode
= sl82c105_set_dma_mode
,
300 .resetproc
= sl82c105_resetproc
,
301 .test_irq
= sl82c105_test_irq
,
304 static const struct ide_dma_ops sl82c105_dma_ops
= {
305 .dma_host_set
= ide_dma_host_set
,
306 .dma_setup
= ide_dma_setup
,
307 .dma_start
= sl82c105_dma_start
,
308 .dma_end
= sl82c105_dma_end
,
309 .dma_test_irq
= ide_dma_test_irq
,
310 .dma_lost_irq
= sl82c105_dma_lost_irq
,
311 .dma_timer_expiry
= ide_dma_sff_timer_expiry
,
312 .dma_clear
= sl82c105_dma_clear
,
313 .dma_sff_read_status
= ide_dma_sff_read_status
,
316 static const struct ide_port_info sl82c105_chipset __devinitdata
= {
318 .init_chipset
= init_chipset_sl82c105
,
319 .enablebits
= {{0x40,0x01,0x01}, {0x40,0x10,0x10}},
320 .port_ops
= &sl82c105_port_ops
,
321 .dma_ops
= &sl82c105_dma_ops
,
322 .host_flags
= IDE_HFLAG_IO_32BIT
|
323 IDE_HFLAG_UNMASK_IRQS
|
324 IDE_HFLAG_SERIALIZE_DMA
|
325 IDE_HFLAG_NO_AUTODMA
,
326 .pio_mask
= ATA_PIO5
,
327 .mwdma_mask
= ATA_MWDMA2
,
330 static int __devinit
sl82c105_init_one(struct pci_dev
*dev
, const struct pci_device_id
*id
)
332 struct ide_port_info d
= sl82c105_chipset
;
333 u8 rev
= sl82c105_bridge_revision(dev
);
337 * Never ever EVER under any circumstances enable
338 * DMA when the bridge is this old.
340 printk(KERN_INFO DRV_NAME
": Winbond W83C553 bridge "
341 "revision %d, BM-DMA disabled\n", rev
);
344 d
.host_flags
&= ~IDE_HFLAG_SERIALIZE_DMA
;
347 return ide_pci_init_one(dev
, &d
, NULL
);
350 static const struct pci_device_id sl82c105_pci_tbl
[] = {
351 { PCI_VDEVICE(WINBOND
, PCI_DEVICE_ID_WINBOND_82C105
), 0 },
354 MODULE_DEVICE_TABLE(pci
, sl82c105_pci_tbl
);
356 static struct pci_driver sl82c105_pci_driver
= {
357 .name
= "W82C105_IDE",
358 .id_table
= sl82c105_pci_tbl
,
359 .probe
= sl82c105_init_one
,
360 .remove
= ide_pci_remove
,
361 .suspend
= ide_pci_suspend
,
362 .resume
= ide_pci_resume
,
365 static int __init
sl82c105_ide_init(void)
367 return ide_pci_register_driver(&sl82c105_pci_driver
);
370 static void __exit
sl82c105_ide_exit(void)
372 pci_unregister_driver(&sl82c105_pci_driver
);
375 module_init(sl82c105_ide_init
);
376 module_exit(sl82c105_ide_exit
);
378 MODULE_DESCRIPTION("PCI driver module for W82C105 IDE");
379 MODULE_LICENSE("GPL");