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ide: add "flagged" taskfile flags to struct ide_taskfile (v2)
[mirror_ubuntu-bionic-kernel.git] / drivers / ide / tx4939ide.c
1 /*
2 * TX4939 internal IDE driver
3 * Based on RBTX49xx patch from CELF patch archive.
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
7 * for more details.
8 *
9 * (C) Copyright TOSHIBA CORPORATION 2005-2007
10 */
11
12 #include <linux/module.h>
13 #include <linux/types.h>
14 #include <linux/ide.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/platform_device.h>
18 #include <linux/io.h>
19 #include <linux/scatterlist.h>
20
21 #include <asm/ide.h>
22
23 #define MODNAME "tx4939ide"
24
25 /* ATA Shadow Registers (8-bit except for Data which is 16-bit) */
26 #define TX4939IDE_Data 0x000
27 #define TX4939IDE_Error_Feature 0x001
28 #define TX4939IDE_Sec 0x002
29 #define TX4939IDE_LBA0 0x003
30 #define TX4939IDE_LBA1 0x004
31 #define TX4939IDE_LBA2 0x005
32 #define TX4939IDE_DevHead 0x006
33 #define TX4939IDE_Stat_Cmd 0x007
34 #define TX4939IDE_AltStat_DevCtl 0x402
35 /* H/W DMA Registers */
36 #define TX4939IDE_DMA_Cmd 0x800 /* 8-bit */
37 #define TX4939IDE_DMA_Stat 0x802 /* 8-bit */
38 #define TX4939IDE_PRD_Ptr 0x804 /* 32-bit */
39 /* ATA100 CORE Registers (16-bit) */
40 #define TX4939IDE_Sys_Ctl 0xc00
41 #define TX4939IDE_Xfer_Cnt_1 0xc08
42 #define TX4939IDE_Xfer_Cnt_2 0xc0a
43 #define TX4939IDE_Sec_Cnt 0xc10
44 #define TX4939IDE_Start_Lo_Addr 0xc18
45 #define TX4939IDE_Start_Up_Addr 0xc20
46 #define TX4939IDE_Add_Ctl 0xc28
47 #define TX4939IDE_Lo_Burst_Cnt 0xc30
48 #define TX4939IDE_Up_Burst_Cnt 0xc38
49 #define TX4939IDE_PIO_Addr 0xc88
50 #define TX4939IDE_H_Rst_Tim 0xc90
51 #define TX4939IDE_Int_Ctl 0xc98
52 #define TX4939IDE_Pkt_Cmd 0xcb8
53 #define TX4939IDE_Bxfer_Cnt_Hi 0xcc0
54 #define TX4939IDE_Bxfer_Cnt_Lo 0xcc8
55 #define TX4939IDE_Dev_TErr 0xcd0
56 #define TX4939IDE_Pkt_Xfer_Ctl 0xcd8
57 #define TX4939IDE_Start_TAddr 0xce0
58
59 /* bits for Int_Ctl */
60 #define TX4939IDE_INT_ADDRERR 0x80
61 #define TX4939IDE_INT_REACHMUL 0x40
62 #define TX4939IDE_INT_DEVTIMING 0x20
63 #define TX4939IDE_INT_UDMATERM 0x10
64 #define TX4939IDE_INT_TIMER 0x08
65 #define TX4939IDE_INT_BUSERR 0x04
66 #define TX4939IDE_INT_XFEREND 0x02
67 #define TX4939IDE_INT_HOST 0x01
68
69 #define TX4939IDE_IGNORE_INTS \
70 (TX4939IDE_INT_ADDRERR | TX4939IDE_INT_REACHMUL | \
71 TX4939IDE_INT_DEVTIMING | TX4939IDE_INT_UDMATERM | \
72 TX4939IDE_INT_TIMER | TX4939IDE_INT_XFEREND)
73
74 #ifdef __BIG_ENDIAN
75 #define tx4939ide_swizzlel(a) ((a) ^ 4)
76 #define tx4939ide_swizzlew(a) ((a) ^ 6)
77 #define tx4939ide_swizzleb(a) ((a) ^ 7)
78 #else
79 #define tx4939ide_swizzlel(a) (a)
80 #define tx4939ide_swizzlew(a) (a)
81 #define tx4939ide_swizzleb(a) (a)
82 #endif
83
84 static u16 tx4939ide_readw(void __iomem *base, u32 reg)
85 {
86 return __raw_readw(base + tx4939ide_swizzlew(reg));
87 }
88 static u8 tx4939ide_readb(void __iomem *base, u32 reg)
89 {
90 return __raw_readb(base + tx4939ide_swizzleb(reg));
91 }
92 static void tx4939ide_writel(u32 val, void __iomem *base, u32 reg)
93 {
94 __raw_writel(val, base + tx4939ide_swizzlel(reg));
95 }
96 static void tx4939ide_writew(u16 val, void __iomem *base, u32 reg)
97 {
98 __raw_writew(val, base + tx4939ide_swizzlew(reg));
99 }
100 static void tx4939ide_writeb(u8 val, void __iomem *base, u32 reg)
101 {
102 __raw_writeb(val, base + tx4939ide_swizzleb(reg));
103 }
104
105 #define TX4939IDE_BASE(hwif) ((void __iomem *)(hwif)->extra_base)
106
107 static void tx4939ide_set_pio_mode(ide_drive_t *drive, const u8 pio)
108 {
109 ide_hwif_t *hwif = drive->hwif;
110 int is_slave = drive->dn;
111 u32 mask, val;
112 u8 safe = pio;
113 ide_drive_t *pair;
114
115 pair = ide_get_pair_dev(drive);
116 if (pair)
117 safe = min(safe, ide_get_best_pio_mode(pair, 255, 4));
118 /*
119 * Update Command Transfer Mode for master/slave and Data
120 * Transfer Mode for this drive.
121 */
122 mask = is_slave ? 0x07f00000 : 0x000007f0;
123 val = ((safe << 8) | (pio << 4)) << (is_slave ? 16 : 0);
124 hwif->select_data = (hwif->select_data & ~mask) | val;
125 /* tx4939ide_tf_load_fixup() will set the Sys_Ctl register */
126 }
127
128 static void tx4939ide_set_dma_mode(ide_drive_t *drive, const u8 mode)
129 {
130 ide_hwif_t *hwif = drive->hwif;
131 u32 mask, val;
132
133 /* Update Data Transfer Mode for this drive. */
134 if (mode >= XFER_UDMA_0)
135 val = mode - XFER_UDMA_0 + 8;
136 else
137 val = mode - XFER_MW_DMA_0 + 5;
138 if (drive->dn) {
139 mask = 0x00f00000;
140 val <<= 20;
141 } else {
142 mask = 0x000000f0;
143 val <<= 4;
144 }
145 hwif->select_data = (hwif->select_data & ~mask) | val;
146 /* tx4939ide_tf_load_fixup() will set the Sys_Ctl register */
147 }
148
149 static u16 tx4939ide_check_error_ints(ide_hwif_t *hwif)
150 {
151 void __iomem *base = TX4939IDE_BASE(hwif);
152 u16 ctl = tx4939ide_readw(base, TX4939IDE_Int_Ctl);
153
154 if (ctl & TX4939IDE_INT_BUSERR) {
155 /* reset FIFO */
156 u16 sysctl = tx4939ide_readw(base, TX4939IDE_Sys_Ctl);
157
158 tx4939ide_writew(sysctl | 0x4000, base, TX4939IDE_Sys_Ctl);
159 mmiowb();
160 /* wait 12GBUSCLK (typ. 60ns @ GBUS200MHz, max 270ns) */
161 ndelay(270);
162 tx4939ide_writew(sysctl, base, TX4939IDE_Sys_Ctl);
163 }
164 if (ctl & (TX4939IDE_INT_ADDRERR |
165 TX4939IDE_INT_DEVTIMING | TX4939IDE_INT_BUSERR))
166 pr_err("%s: Error interrupt %#x (%s%s%s )\n",
167 hwif->name, ctl,
168 ctl & TX4939IDE_INT_ADDRERR ? " Address-Error" : "",
169 ctl & TX4939IDE_INT_DEVTIMING ? " DEV-Timing" : "",
170 ctl & TX4939IDE_INT_BUSERR ? " Bus-Error" : "");
171 return ctl;
172 }
173
174 static void tx4939ide_clear_irq(ide_drive_t *drive)
175 {
176 ide_hwif_t *hwif;
177 void __iomem *base;
178 u16 ctl;
179
180 /*
181 * tx4939ide_dma_test_irq() and tx4939ide_dma_end() do all job
182 * for DMA case.
183 */
184 if (drive->waiting_for_dma)
185 return;
186 hwif = drive->hwif;
187 base = TX4939IDE_BASE(hwif);
188 ctl = tx4939ide_check_error_ints(hwif);
189 tx4939ide_writew(ctl, base, TX4939IDE_Int_Ctl);
190 }
191
192 static u8 tx4939ide_cable_detect(ide_hwif_t *hwif)
193 {
194 void __iomem *base = TX4939IDE_BASE(hwif);
195
196 return tx4939ide_readw(base, TX4939IDE_Sys_Ctl) & 0x2000 ?
197 ATA_CBL_PATA40 : ATA_CBL_PATA80;
198 }
199
200 #ifdef __BIG_ENDIAN
201 static void tx4939ide_dma_host_set(ide_drive_t *drive, int on)
202 {
203 ide_hwif_t *hwif = drive->hwif;
204 u8 unit = drive->dn;
205 void __iomem *base = TX4939IDE_BASE(hwif);
206 u8 dma_stat = tx4939ide_readb(base, TX4939IDE_DMA_Stat);
207
208 if (on)
209 dma_stat |= (1 << (5 + unit));
210 else
211 dma_stat &= ~(1 << (5 + unit));
212
213 tx4939ide_writeb(dma_stat, base, TX4939IDE_DMA_Stat);
214 }
215 #else
216 #define tx4939ide_dma_host_set ide_dma_host_set
217 #endif
218
219 static u8 tx4939ide_clear_dma_status(void __iomem *base)
220 {
221 u8 dma_stat;
222
223 /* read DMA status for INTR & ERROR flags */
224 dma_stat = tx4939ide_readb(base, TX4939IDE_DMA_Stat);
225 /* clear INTR & ERROR flags */
226 tx4939ide_writeb(dma_stat | ATA_DMA_INTR | ATA_DMA_ERR, base,
227 TX4939IDE_DMA_Stat);
228 /* recover intmask cleared by writing to bit2 of DMA_Stat */
229 tx4939ide_writew(TX4939IDE_IGNORE_INTS << 8, base, TX4939IDE_Int_Ctl);
230 return dma_stat;
231 }
232
233 #ifdef __BIG_ENDIAN
234 /* custom ide_build_dmatable to handle swapped layout */
235 static int tx4939ide_build_dmatable(ide_drive_t *drive, struct request *rq)
236 {
237 ide_hwif_t *hwif = drive->hwif;
238 u32 *table = (u32 *)hwif->dmatable_cpu;
239 unsigned int count = 0;
240 int i;
241 struct scatterlist *sg;
242
243 hwif->sg_nents = ide_build_sglist(drive, rq);
244 if (hwif->sg_nents == 0)
245 return 0;
246
247 for_each_sg(hwif->sg_table, sg, hwif->sg_nents, i) {
248 u32 cur_addr, cur_len, bcount;
249
250 cur_addr = sg_dma_address(sg);
251 cur_len = sg_dma_len(sg);
252
253 /*
254 * Fill in the DMA table, without crossing any 64kB boundaries.
255 */
256
257 while (cur_len) {
258 if (count++ >= PRD_ENTRIES)
259 goto use_pio_instead;
260
261 bcount = 0x10000 - (cur_addr & 0xffff);
262 if (bcount > cur_len)
263 bcount = cur_len;
264 /*
265 * This workaround for zero count seems required.
266 * (standard ide_build_dmatable does it too)
267 */
268 if (bcount == 0x10000)
269 bcount = 0x8000;
270 *table++ = bcount & 0xffff;
271 *table++ = cur_addr;
272 cur_addr += bcount;
273 cur_len -= bcount;
274 }
275 }
276
277 if (count) {
278 *(table - 2) |= 0x80000000;
279 return count;
280 }
281
282 use_pio_instead:
283 printk(KERN_ERR "%s: %s\n", drive->name,
284 count ? "DMA table too small" : "empty DMA table?");
285
286 ide_destroy_dmatable(drive);
287
288 return 0; /* revert to PIO for this request */
289 }
290 #else
291 #define tx4939ide_build_dmatable ide_build_dmatable
292 #endif
293
294 static int tx4939ide_dma_setup(ide_drive_t *drive)
295 {
296 ide_hwif_t *hwif = drive->hwif;
297 void __iomem *base = TX4939IDE_BASE(hwif);
298 struct request *rq = hwif->rq;
299 u8 reading;
300 int nent;
301
302 if (rq_data_dir(rq))
303 reading = 0;
304 else
305 reading = ATA_DMA_WR;
306
307 /* fall back to PIO! */
308 nent = tx4939ide_build_dmatable(drive, rq);
309 if (!nent) {
310 ide_map_sg(drive, rq);
311 return 1;
312 }
313
314 /* PRD table */
315 tx4939ide_writel(hwif->dmatable_dma, base, TX4939IDE_PRD_Ptr);
316
317 /* specify r/w */
318 tx4939ide_writeb(reading, base, TX4939IDE_DMA_Cmd);
319
320 /* clear INTR & ERROR flags */
321 tx4939ide_clear_dma_status(base);
322
323 drive->waiting_for_dma = 1;
324
325 tx4939ide_writew(SECTOR_SIZE / 2, base, drive->dn ?
326 TX4939IDE_Xfer_Cnt_2 : TX4939IDE_Xfer_Cnt_1);
327 tx4939ide_writew(rq->nr_sectors, base, TX4939IDE_Sec_Cnt);
328 return 0;
329 }
330
331 static int tx4939ide_dma_end(ide_drive_t *drive)
332 {
333 ide_hwif_t *hwif = drive->hwif;
334 u8 dma_stat, dma_cmd;
335 void __iomem *base = TX4939IDE_BASE(hwif);
336 u16 ctl = tx4939ide_readw(base, TX4939IDE_Int_Ctl);
337
338 drive->waiting_for_dma = 0;
339
340 /* get DMA command mode */
341 dma_cmd = tx4939ide_readb(base, TX4939IDE_DMA_Cmd);
342 /* stop DMA */
343 tx4939ide_writeb(dma_cmd & ~ATA_DMA_START, base, TX4939IDE_DMA_Cmd);
344
345 /* read and clear the INTR & ERROR bits */
346 dma_stat = tx4939ide_clear_dma_status(base);
347
348 /* purge DMA mappings */
349 ide_destroy_dmatable(drive);
350 /* verify good DMA status */
351 wmb();
352
353 if ((dma_stat & (ATA_DMA_INTR | ATA_DMA_ERR | ATA_DMA_ACTIVE)) == 0 &&
354 (ctl & (TX4939IDE_INT_XFEREND | TX4939IDE_INT_HOST)) ==
355 (TX4939IDE_INT_XFEREND | TX4939IDE_INT_HOST))
356 /* INT_IDE lost... bug? */
357 return 0;
358 return ((dma_stat & (ATA_DMA_INTR | ATA_DMA_ERR | ATA_DMA_ACTIVE)) !=
359 ATA_DMA_INTR) ? 0x10 | dma_stat : 0;
360 }
361
362 /* returns 1 if DMA IRQ issued, 0 otherwise */
363 static int tx4939ide_dma_test_irq(ide_drive_t *drive)
364 {
365 ide_hwif_t *hwif = drive->hwif;
366 void __iomem *base = TX4939IDE_BASE(hwif);
367 u16 ctl, ide_int;
368 u8 dma_stat, stat;
369 int found = 0;
370
371 ctl = tx4939ide_check_error_ints(hwif);
372 ide_int = ctl & (TX4939IDE_INT_XFEREND | TX4939IDE_INT_HOST);
373 switch (ide_int) {
374 case TX4939IDE_INT_HOST:
375 /* On error, XFEREND might not be asserted. */
376 stat = tx4939ide_readb(base, TX4939IDE_AltStat_DevCtl);
377 if ((stat & (ATA_BUSY | ATA_DRQ | ATA_ERR)) == ATA_ERR)
378 found = 1;
379 else
380 /* Wait for XFEREND (Mask HOST and unmask XFEREND) */
381 ctl &= ~TX4939IDE_INT_XFEREND << 8;
382 ctl |= ide_int << 8;
383 break;
384 case TX4939IDE_INT_HOST | TX4939IDE_INT_XFEREND:
385 dma_stat = tx4939ide_readb(base, TX4939IDE_DMA_Stat);
386 if (!(dma_stat & ATA_DMA_INTR))
387 pr_warning("%s: weird interrupt status. "
388 "DMA_Stat %#02x int_ctl %#04x\n",
389 hwif->name, dma_stat, ctl);
390 found = 1;
391 break;
392 }
393 /*
394 * Do not clear XFEREND, HOST now. They will be cleared by
395 * clearing bit2 of DMA_Stat.
396 */
397 ctl &= ~ide_int;
398 tx4939ide_writew(ctl, base, TX4939IDE_Int_Ctl);
399 return found;
400 }
401
402 #ifdef __BIG_ENDIAN
403 static u8 tx4939ide_dma_sff_read_status(ide_hwif_t *hwif)
404 {
405 void __iomem *base = TX4939IDE_BASE(hwif);
406
407 return tx4939ide_readb(base, TX4939IDE_DMA_Stat);
408 }
409 #else
410 #define tx4939ide_dma_sff_read_status ide_dma_sff_read_status
411 #endif
412
413 static void tx4939ide_init_hwif(ide_hwif_t *hwif)
414 {
415 void __iomem *base = TX4939IDE_BASE(hwif);
416
417 /* Soft Reset */
418 tx4939ide_writew(0x8000, base, TX4939IDE_Sys_Ctl);
419 mmiowb();
420 /* at least 20 GBUSCLK (typ. 100ns @ GBUS200MHz, max 450ns) */
421 ndelay(450);
422 tx4939ide_writew(0x0000, base, TX4939IDE_Sys_Ctl);
423 /* mask some interrupts and clear all interrupts */
424 tx4939ide_writew((TX4939IDE_IGNORE_INTS << 8) | 0xff, base,
425 TX4939IDE_Int_Ctl);
426
427 tx4939ide_writew(0x0008, base, TX4939IDE_Lo_Burst_Cnt);
428 tx4939ide_writew(0, base, TX4939IDE_Up_Burst_Cnt);
429 }
430
431 static int tx4939ide_init_dma(ide_hwif_t *hwif, const struct ide_port_info *d)
432 {
433 hwif->dma_base =
434 hwif->extra_base + tx4939ide_swizzleb(TX4939IDE_DMA_Cmd);
435 /*
436 * Note that we cannot use ATA_DMA_TABLE_OFS, ATA_DMA_STATUS
437 * for big endian.
438 */
439 return ide_allocate_dma_engine(hwif);
440 }
441
442 static void tx4939ide_tf_load_fixup(ide_drive_t *drive, ide_task_t *task)
443 {
444 ide_hwif_t *hwif = drive->hwif;
445 void __iomem *base = TX4939IDE_BASE(hwif);
446 u16 sysctl = hwif->select_data >> (drive->dn ? 16 : 0);
447
448 /*
449 * Fix ATA100 CORE System Control Register. (The write to the
450 * Device/Head register may write wrong data to the System
451 * Control Register)
452 * While Sys_Ctl is written here, selectproc is not needed.
453 */
454 tx4939ide_writew(sysctl, base, TX4939IDE_Sys_Ctl);
455 }
456
457 #ifdef __BIG_ENDIAN
458
459 /* custom iops (independent from SWAP_IO_SPACE) */
460 static u8 tx4939ide_inb(unsigned long port)
461 {
462 return __raw_readb((void __iomem *)port);
463 }
464
465 static void tx4939ide_outb(u8 value, unsigned long port)
466 {
467 __raw_writeb(value, (void __iomem *)port);
468 }
469
470 static void tx4939ide_tf_load(ide_drive_t *drive, ide_task_t *task)
471 {
472 ide_hwif_t *hwif = drive->hwif;
473 struct ide_io_ports *io_ports = &hwif->io_ports;
474 struct ide_taskfile *tf = &task->tf;
475 u8 HIHI = task->tf_flags & IDE_TFLAG_LBA48 ? 0xE0 : 0xEF;
476
477 if (task->ftf_flags & IDE_FTFLAG_FLAGGED)
478 HIHI = 0xFF;
479
480 if (task->ftf_flags & IDE_FTFLAG_OUT_DATA) {
481 u16 data = (tf->hob_data << 8) | tf->data;
482
483 /* no endian swap */
484 __raw_writew(data, (void __iomem *)io_ports->data_addr);
485 }
486
487 if (task->tf_flags & IDE_TFLAG_OUT_HOB_FEATURE)
488 tx4939ide_outb(tf->hob_feature, io_ports->feature_addr);
489 if (task->tf_flags & IDE_TFLAG_OUT_HOB_NSECT)
490 tx4939ide_outb(tf->hob_nsect, io_ports->nsect_addr);
491 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAL)
492 tx4939ide_outb(tf->hob_lbal, io_ports->lbal_addr);
493 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAM)
494 tx4939ide_outb(tf->hob_lbam, io_ports->lbam_addr);
495 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAH)
496 tx4939ide_outb(tf->hob_lbah, io_ports->lbah_addr);
497
498 if (task->tf_flags & IDE_TFLAG_OUT_FEATURE)
499 tx4939ide_outb(tf->feature, io_ports->feature_addr);
500 if (task->tf_flags & IDE_TFLAG_OUT_NSECT)
501 tx4939ide_outb(tf->nsect, io_ports->nsect_addr);
502 if (task->tf_flags & IDE_TFLAG_OUT_LBAL)
503 tx4939ide_outb(tf->lbal, io_ports->lbal_addr);
504 if (task->tf_flags & IDE_TFLAG_OUT_LBAM)
505 tx4939ide_outb(tf->lbam, io_ports->lbam_addr);
506 if (task->tf_flags & IDE_TFLAG_OUT_LBAH)
507 tx4939ide_outb(tf->lbah, io_ports->lbah_addr);
508
509 if (task->tf_flags & IDE_TFLAG_OUT_DEVICE) {
510 tx4939ide_outb((tf->device & HIHI) | drive->select,
511 io_ports->device_addr);
512 tx4939ide_tf_load_fixup(drive, task);
513 }
514 }
515
516 static void tx4939ide_tf_read(ide_drive_t *drive, ide_task_t *task)
517 {
518 ide_hwif_t *hwif = drive->hwif;
519 struct ide_io_ports *io_ports = &hwif->io_ports;
520 struct ide_taskfile *tf = &task->tf;
521
522 if (task->ftf_flags & IDE_FTFLAG_IN_DATA) {
523 u16 data;
524
525 /* no endian swap */
526 data = __raw_readw((void __iomem *)io_ports->data_addr);
527 tf->data = data & 0xff;
528 tf->hob_data = (data >> 8) & 0xff;
529 }
530
531 /* be sure we're looking at the low order bits */
532 tx4939ide_outb(ATA_DEVCTL_OBS & ~0x80, io_ports->ctl_addr);
533
534 if (task->tf_flags & IDE_TFLAG_IN_FEATURE)
535 tf->feature = tx4939ide_inb(io_ports->feature_addr);
536 if (task->tf_flags & IDE_TFLAG_IN_NSECT)
537 tf->nsect = tx4939ide_inb(io_ports->nsect_addr);
538 if (task->tf_flags & IDE_TFLAG_IN_LBAL)
539 tf->lbal = tx4939ide_inb(io_ports->lbal_addr);
540 if (task->tf_flags & IDE_TFLAG_IN_LBAM)
541 tf->lbam = tx4939ide_inb(io_ports->lbam_addr);
542 if (task->tf_flags & IDE_TFLAG_IN_LBAH)
543 tf->lbah = tx4939ide_inb(io_ports->lbah_addr);
544 if (task->tf_flags & IDE_TFLAG_IN_DEVICE)
545 tf->device = tx4939ide_inb(io_ports->device_addr);
546
547 if (task->tf_flags & IDE_TFLAG_LBA48) {
548 tx4939ide_outb(ATA_DEVCTL_OBS | 0x80, io_ports->ctl_addr);
549
550 if (task->tf_flags & IDE_TFLAG_IN_HOB_FEATURE)
551 tf->hob_feature =
552 tx4939ide_inb(io_ports->feature_addr);
553 if (task->tf_flags & IDE_TFLAG_IN_HOB_NSECT)
554 tf->hob_nsect = tx4939ide_inb(io_ports->nsect_addr);
555 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAL)
556 tf->hob_lbal = tx4939ide_inb(io_ports->lbal_addr);
557 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAM)
558 tf->hob_lbam = tx4939ide_inb(io_ports->lbam_addr);
559 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAH)
560 tf->hob_lbah = tx4939ide_inb(io_ports->lbah_addr);
561 }
562 }
563
564 static void tx4939ide_input_data_swap(ide_drive_t *drive, struct request *rq,
565 void *buf, unsigned int len)
566 {
567 unsigned long port = drive->hwif->io_ports.data_addr;
568 unsigned short *ptr = buf;
569 unsigned int count = (len + 1) / 2;
570
571 while (count--)
572 *ptr++ = cpu_to_le16(__raw_readw((void __iomem *)port));
573 __ide_flush_dcache_range((unsigned long)buf, roundup(len, 2));
574 }
575
576 static void tx4939ide_output_data_swap(ide_drive_t *drive, struct request *rq,
577 void *buf, unsigned int len)
578 {
579 unsigned long port = drive->hwif->io_ports.data_addr;
580 unsigned short *ptr = buf;
581 unsigned int count = (len + 1) / 2;
582
583 while (count--) {
584 __raw_writew(le16_to_cpu(*ptr), (void __iomem *)port);
585 ptr++;
586 }
587 __ide_flush_dcache_range((unsigned long)buf, roundup(len, 2));
588 }
589
590 static const struct ide_tp_ops tx4939ide_tp_ops = {
591 .exec_command = ide_exec_command,
592 .read_status = ide_read_status,
593 .read_altstatus = ide_read_altstatus,
594
595 .set_irq = ide_set_irq,
596
597 .tf_load = tx4939ide_tf_load,
598 .tf_read = tx4939ide_tf_read,
599
600 .input_data = tx4939ide_input_data_swap,
601 .output_data = tx4939ide_output_data_swap,
602 };
603
604 #else /* __LITTLE_ENDIAN */
605
606 static void tx4939ide_tf_load(ide_drive_t *drive, ide_task_t *task)
607 {
608 ide_tf_load(drive, task);
609 if (task->tf_flags & IDE_TFLAG_OUT_DEVICE)
610 tx4939ide_tf_load_fixup(drive, task);
611 }
612
613 static const struct ide_tp_ops tx4939ide_tp_ops = {
614 .exec_command = ide_exec_command,
615 .read_status = ide_read_status,
616 .read_altstatus = ide_read_altstatus,
617
618 .set_irq = ide_set_irq,
619
620 .tf_load = tx4939ide_tf_load,
621 .tf_read = ide_tf_read,
622
623 .input_data = ide_input_data,
624 .output_data = ide_output_data,
625 };
626
627 #endif /* __LITTLE_ENDIAN */
628
629 static const struct ide_port_ops tx4939ide_port_ops = {
630 .set_pio_mode = tx4939ide_set_pio_mode,
631 .set_dma_mode = tx4939ide_set_dma_mode,
632 .clear_irq = tx4939ide_clear_irq,
633 .cable_detect = tx4939ide_cable_detect,
634 };
635
636 static const struct ide_dma_ops tx4939ide_dma_ops = {
637 .dma_host_set = tx4939ide_dma_host_set,
638 .dma_setup = tx4939ide_dma_setup,
639 .dma_exec_cmd = ide_dma_exec_cmd,
640 .dma_start = ide_dma_start,
641 .dma_end = tx4939ide_dma_end,
642 .dma_test_irq = tx4939ide_dma_test_irq,
643 .dma_lost_irq = ide_dma_lost_irq,
644 .dma_timeout = ide_dma_timeout,
645 .dma_sff_read_status = tx4939ide_dma_sff_read_status,
646 };
647
648 static const struct ide_port_info tx4939ide_port_info __initdata = {
649 .init_hwif = tx4939ide_init_hwif,
650 .init_dma = tx4939ide_init_dma,
651 .port_ops = &tx4939ide_port_ops,
652 .dma_ops = &tx4939ide_dma_ops,
653 .tp_ops = &tx4939ide_tp_ops,
654 .host_flags = IDE_HFLAG_MMIO,
655 .pio_mask = ATA_PIO4,
656 .mwdma_mask = ATA_MWDMA2,
657 .udma_mask = ATA_UDMA5,
658 .chipset = ide_generic,
659 };
660
661 static int __init tx4939ide_probe(struct platform_device *pdev)
662 {
663 hw_regs_t hw;
664 hw_regs_t *hws[] = { &hw, NULL, NULL, NULL };
665 struct ide_host *host;
666 struct resource *res;
667 int irq, ret;
668 unsigned long mapbase;
669
670 irq = platform_get_irq(pdev, 0);
671 if (irq < 0)
672 return -ENODEV;
673 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
674 if (!res)
675 return -ENODEV;
676
677 if (!devm_request_mem_region(&pdev->dev, res->start,
678 res->end - res->start + 1, "tx4938ide"))
679 return -EBUSY;
680 mapbase = (unsigned long)devm_ioremap(&pdev->dev, res->start,
681 res->end - res->start + 1);
682 if (!mapbase)
683 return -EBUSY;
684 memset(&hw, 0, sizeof(hw));
685 hw.io_ports.data_addr =
686 mapbase + tx4939ide_swizzlew(TX4939IDE_Data);
687 hw.io_ports.error_addr =
688 mapbase + tx4939ide_swizzleb(TX4939IDE_Error_Feature);
689 hw.io_ports.nsect_addr =
690 mapbase + tx4939ide_swizzleb(TX4939IDE_Sec);
691 hw.io_ports.lbal_addr =
692 mapbase + tx4939ide_swizzleb(TX4939IDE_LBA0);
693 hw.io_ports.lbam_addr =
694 mapbase + tx4939ide_swizzleb(TX4939IDE_LBA1);
695 hw.io_ports.lbah_addr =
696 mapbase + tx4939ide_swizzleb(TX4939IDE_LBA2);
697 hw.io_ports.device_addr =
698 mapbase + tx4939ide_swizzleb(TX4939IDE_DevHead);
699 hw.io_ports.command_addr =
700 mapbase + tx4939ide_swizzleb(TX4939IDE_Stat_Cmd);
701 hw.io_ports.ctl_addr =
702 mapbase + tx4939ide_swizzleb(TX4939IDE_AltStat_DevCtl);
703 hw.irq = irq;
704 hw.dev = &pdev->dev;
705
706 pr_info("TX4939 IDE interface (base %#lx, irq %d)\n", mapbase, irq);
707 host = ide_host_alloc(&tx4939ide_port_info, hws);
708 if (!host)
709 return -ENOMEM;
710 /* use extra_base for base address of the all registers */
711 host->ports[0]->extra_base = mapbase;
712 ret = ide_host_register(host, &tx4939ide_port_info, hws);
713 if (ret) {
714 ide_host_free(host);
715 return ret;
716 }
717 platform_set_drvdata(pdev, host);
718 return 0;
719 }
720
721 static int __exit tx4939ide_remove(struct platform_device *pdev)
722 {
723 struct ide_host *host = platform_get_drvdata(pdev);
724
725 ide_host_remove(host);
726 return 0;
727 }
728
729 #ifdef CONFIG_PM
730 static int tx4939ide_resume(struct platform_device *dev)
731 {
732 struct ide_host *host = platform_get_drvdata(dev);
733 ide_hwif_t *hwif = host->ports[0];
734
735 tx4939ide_init_hwif(hwif);
736 return 0;
737 }
738 #else
739 #define tx4939ide_resume NULL
740 #endif
741
742 static struct platform_driver tx4939ide_driver = {
743 .driver = {
744 .name = MODNAME,
745 .owner = THIS_MODULE,
746 },
747 .remove = __exit_p(tx4939ide_remove),
748 .resume = tx4939ide_resume,
749 };
750
751 static int __init tx4939ide_init(void)
752 {
753 return platform_driver_probe(&tx4939ide_driver, tx4939ide_probe);
754 }
755
756 static void __exit tx4939ide_exit(void)
757 {
758 platform_driver_unregister(&tx4939ide_driver);
759 }
760
761 module_init(tx4939ide_init);
762 module_exit(tx4939ide_exit);
763
764 MODULE_DESCRIPTION("TX4939 internal IDE driver");
765 MODULE_LICENSE("GPL");
766 MODULE_ALIAS("platform:tx4939ide");
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