drivers/idle/intel_idle.c

   1 /*
   2  * intel_idle.c - native hardware idle loop for modern Intel processors
   3  *
   4  * Copyright (c) 2013, Intel Corporation.
   5  * Len Brown <len.brown@intel.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program; if not, write to the Free Software Foundation, Inc.,
  18  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19  */
  20
  21 /*
  22  * intel_idle is a cpuidle driver that loads on specific Intel processors
  23  * in lieu of the legacy ACPI processor_idle driver.  The intent is to
  24  * make Linux more efficient on these processors, as intel_idle knows
  25  * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
  26  */
  27
  28 /*
  29  * Design Assumptions
  30  *
  31  * All CPUs have same idle states as boot CPU
  32  *
  33  * Chipset BM_STS (bus master status) bit is a NOP
  34  *      for preventing entry into deep C-stats
  35  */
  36
  37 /*
  38  * Known limitations
  39  *
  40  * The driver currently initializes for_each_online_cpu() upon modprobe.
  41  * It it unaware of subsequent processors hot-added to the system.
  42  * This means that if you boot with maxcpus=n and later online
  43  * processors above n, those processors will use C1 only.
  44  *
  45  * ACPI has a .suspend hack to turn off deep c-statees during suspend
  46  * to avoid complications with the lapic timer workaround.
  47  * Have not seen issues with suspend, but may need same workaround here.
  48  *
  49  * There is currently no kernel-based automatic probing/loading mechanism
  50  * if the driver is built as a module.
  51  */
  52
  53 /* un-comment DEBUG to enable pr_debug() statements */
  54 #define DEBUG
  55
  56 #include <linux/kernel.h>
  57 #include <linux/cpuidle.h>
  58 #include <linux/clockchips.h>
  59 #include <trace/events/power.h>
  60 #include <linux/sched.h>
  61 #include <linux/notifier.h>
  62 #include <linux/cpu.h>
  63 #include <linux/module.h>
  64 #include <asm/cpu_device_id.h>
  65 #include <asm/mwait.h>
  66 #include <asm/msr.h>
  67
  68 #define INTEL_IDLE_VERSION "0.4"
  69 #define PREFIX "intel_idle: "
  70
  71 static struct cpuidle_driver intel_idle_driver = {
  72         .name = "intel_idle",
  73         .owner = THIS_MODULE,
  74 };
  75 /* intel_idle.max_cstate=0 disables driver */
  76 static int max_cstate = CPUIDLE_STATE_MAX - 1;
  77
  78 static unsigned int mwait_substates;
  79
  80 #define LAPIC_TIMER_ALWAYS_RELIABLE 0xFFFFFFFF
  81 /* Reliable LAPIC Timer States, bit 1 for C1 etc.  */
  82 static unsigned int lapic_timer_reliable_states = (1 << 1);      /* Default to only C1 */
  83
  84 struct idle_cpu {
  85         struct cpuidle_state *state_table;
  86
  87         /*
  88          * Hardware C-state auto-demotion may not always be optimal.
  89          * Indicate which enable bits to clear here.
  90          */
  91         unsigned long auto_demotion_disable_flags;
  92         bool disable_promotion_to_c1e;
  93 };
  94
  95 static const struct idle_cpu *icpu;
  96 static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
  97 static int intel_idle(struct cpuidle_device *dev,
  98                         struct cpuidle_driver *drv, int index);
  99 static int intel_idle_cpu_init(int cpu);
 100
 101 static struct cpuidle_state *cpuidle_state_table;
 102
 103 /*
 104  * Set this flag for states where the HW flushes the TLB for us
 105  * and so we don't need cross-calls to keep it consistent.
 106  * If this flag is set, SW flushes the TLB, so even if the
 107  * HW doesn't do the flushing, this flag is safe to use.
 108  */
 109 #define CPUIDLE_FLAG_TLB_FLUSHED        0x10000
 110
 111 /*
 112  * MWAIT takes an 8-bit "hint" in EAX "suggesting"
 113  * the C-state (top nibble) and sub-state (bottom nibble)
 114  * 0x00 means "MWAIT(C1)", 0x10 means "MWAIT(C2)" etc.
 115  *
 116  * We store the hint at the top of our "flags" for each state.
 117  */
 118 #define flg2MWAIT(flags) (((flags) >> 24) & 0xFF)
 119 #define MWAIT2flg(eax) ((eax & 0xFF) << 24)
 120
 121 /*
 122  * States are indexed by the cstate number,
 123  * which is also the index into the MWAIT hint array.
 124  * Thus C0 is a dummy.
 125  */
 126 static struct cpuidle_state nehalem_cstates[] = {
 127         {
 128                 .name = "C1-NHM",
 129                 .desc = "MWAIT 0x00",
 130                 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
 131                 .exit_latency = 3,
 132                 .target_residency = 6,
 133                 .enter = &intel_idle },
 134         {
 135                 .name = "C1E-NHM",
 136                 .desc = "MWAIT 0x01",
 137                 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
 138                 .exit_latency = 10,
 139                 .target_residency = 20,
 140                 .enter = &intel_idle },
 141         {
 142                 .name = "C3-NHM",
 143                 .desc = "MWAIT 0x10",
 144                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 145                 .exit_latency = 20,
 146                 .target_residency = 80,
 147                 .enter = &intel_idle },
 148         {
 149                 .name = "C6-NHM",
 150                 .desc = "MWAIT 0x20",
 151                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 152                 .exit_latency = 200,
 153                 .target_residency = 800,
 154                 .enter = &intel_idle },
 155         {
 156                 .enter = NULL }
 157 };
 158
 159 static struct cpuidle_state snb_cstates[] = {
 160         {
 161                 .name = "C1-SNB",
 162                 .desc = "MWAIT 0x00",
 163                 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
 164                 .exit_latency = 2,
 165                 .target_residency = 2,
 166                 .enter = &intel_idle },
 167         {
 168                 .name = "C1E-SNB",
 169                 .desc = "MWAIT 0x01",
 170                 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
 171                 .exit_latency = 10,
 172                 .target_residency = 20,
 173                 .enter = &intel_idle },
 174         {
 175                 .name = "C3-SNB",
 176                 .desc = "MWAIT 0x10",
 177                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 178                 .exit_latency = 80,
 179                 .target_residency = 211,
 180                 .enter = &intel_idle },
 181         {
 182                 .name = "C6-SNB",
 183                 .desc = "MWAIT 0x20",
 184                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 185                 .exit_latency = 104,
 186                 .target_residency = 345,
 187                 .enter = &intel_idle },
 188         {
 189                 .name = "C7-SNB",
 190                 .desc = "MWAIT 0x30",
 191                 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 192                 .exit_latency = 109,
 193                 .target_residency = 345,
 194                 .enter = &intel_idle },
 195         {
 196                 .enter = NULL }
 197 };
 198
 199 static struct cpuidle_state byt_cstates[] = {
 200         {
 201                 .name = "C1-BYT",
 202                 .desc = "MWAIT 0x00",
 203                 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
 204                 .exit_latency = 1,
 205                 .target_residency = 1,
 206                 .enter = &intel_idle },
 207         {
 208                 .name = "C1E-BYT",
 209                 .desc = "MWAIT 0x01",
 210                 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
 211                 .exit_latency = 15,
 212                 .target_residency = 30,
 213                 .enter = &intel_idle },
 214         {
 215                 .name = "C6N-BYT",
 216                 .desc = "MWAIT 0x58",
 217                 .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 218                 .exit_latency = 40,
 219                 .target_residency = 275,
 220                 .enter = &intel_idle },
 221         {
 222                 .name = "C6S-BYT",
 223                 .desc = "MWAIT 0x52",
 224                 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 225                 .exit_latency = 140,
 226                 .target_residency = 560,
 227                 .enter = &intel_idle },
 228         {
 229                 .name = "C7-BYT",
 230                 .desc = "MWAIT 0x60",
 231                 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 232                 .exit_latency = 1200,
 233                 .target_residency = 1500,
 234                 .enter = &intel_idle },
 235         {
 236                 .name = "C7S-BYT",
 237                 .desc = "MWAIT 0x64",
 238                 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 239                 .exit_latency = 10000,
 240                 .target_residency = 20000,
 241                 .enter = &intel_idle },
 242         {
 243                 .enter = NULL }
 244 };
 245
 246 static struct cpuidle_state ivb_cstates[] = {
 247         {
 248                 .name = "C1-IVB",
 249                 .desc = "MWAIT 0x00",
 250                 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
 251                 .exit_latency = 1,
 252                 .target_residency = 1,
 253                 .enter = &intel_idle },
 254         {
 255                 .name = "C1E-IVB",
 256                 .desc = "MWAIT 0x01",
 257                 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
 258                 .exit_latency = 10,
 259                 .target_residency = 20,
 260                 .enter = &intel_idle },
 261         {
 262                 .name = "C3-IVB",
 263                 .desc = "MWAIT 0x10",
 264                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 265                 .exit_latency = 59,
 266                 .target_residency = 156,
 267                 .enter = &intel_idle },
 268         {
 269                 .name = "C6-IVB",
 270                 .desc = "MWAIT 0x20",
 271                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 272                 .exit_latency = 80,
 273                 .target_residency = 300,
 274                 .enter = &intel_idle },
 275         {
 276                 .name = "C7-IVB",
 277                 .desc = "MWAIT 0x30",
 278                 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 279                 .exit_latency = 87,
 280                 .target_residency = 300,
 281                 .enter = &intel_idle },
 282         {
 283                 .enter = NULL }
 284 };
 285
 286 static struct cpuidle_state ivt_cstates[] = {
 287         {
 288                 .name = "C1-IVT",
 289                 .desc = "MWAIT 0x00",
 290                 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
 291                 .exit_latency = 1,
 292                 .target_residency = 1,
 293                 .enter = &intel_idle },
 294         {
 295                 .name = "C1E-IVT",
 296                 .desc = "MWAIT 0x01",
 297                 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
 298                 .exit_latency = 10,
 299                 .target_residency = 80,
 300                 .enter = &intel_idle },
 301         {
 302                 .name = "C3-IVT",
 303                 .desc = "MWAIT 0x10",
 304                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 305                 .exit_latency = 59,
 306                 .target_residency = 156,
 307                 .enter = &intel_idle },
 308         {
 309                 .name = "C6-IVT",
 310                 .desc = "MWAIT 0x20",
 311                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 312                 .exit_latency = 82,
 313                 .target_residency = 300,
 314                 .enter = &intel_idle },
 315         {
 316                 .enter = NULL }
 317 };
 318
 319 static struct cpuidle_state ivt_cstates_4s[] = {
 320         {
 321                 .name = "C1-IVT-4S",
 322                 .desc = "MWAIT 0x00",
 323                 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
 324                 .exit_latency = 1,
 325                 .target_residency = 1,
 326                 .enter = &intel_idle },
 327         {
 328                 .name = "C1E-IVT-4S",
 329                 .desc = "MWAIT 0x01",
 330                 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
 331                 .exit_latency = 10,
 332                 .target_residency = 250,
 333                 .enter = &intel_idle },
 334         {
 335                 .name = "C3-IVT-4S",
 336                 .desc = "MWAIT 0x10",
 337                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 338                 .exit_latency = 59,
 339                 .target_residency = 300,
 340                 .enter = &intel_idle },
 341         {
 342                 .name = "C6-IVT-4S",
 343                 .desc = "MWAIT 0x20",
 344                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 345                 .exit_latency = 84,
 346                 .target_residency = 400,
 347                 .enter = &intel_idle },
 348         {
 349                 .enter = NULL }
 350 };
 351
 352 static struct cpuidle_state ivt_cstates_8s[] = {
 353         {
 354                 .name = "C1-IVT-8S",
 355                 .desc = "MWAIT 0x00",
 356                 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
 357                 .exit_latency = 1,
 358                 .target_residency = 1,
 359                 .enter = &intel_idle },
 360         {
 361                 .name = "C1E-IVT-8S",
 362                 .desc = "MWAIT 0x01",
 363                 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
 364                 .exit_latency = 10,
 365                 .target_residency = 500,
 366                 .enter = &intel_idle },
 367         {
 368                 .name = "C3-IVT-8S",
 369                 .desc = "MWAIT 0x10",
 370                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 371                 .exit_latency = 59,
 372                 .target_residency = 600,
 373                 .enter = &intel_idle },
 374         {
 375                 .name = "C6-IVT-8S",
 376                 .desc = "MWAIT 0x20",
 377                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 378                 .exit_latency = 88,
 379                 .target_residency = 700,
 380                 .enter = &intel_idle },
 381         {
 382                 .enter = NULL }
 383 };
 384
 385 static struct cpuidle_state hsw_cstates[] = {
 386         {
 387                 .name = "C1-HSW",
 388                 .desc = "MWAIT 0x00",
 389                 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
 390                 .exit_latency = 2,
 391                 .target_residency = 2,
 392                 .enter = &intel_idle },
 393         {
 394                 .name = "C1E-HSW",
 395                 .desc = "MWAIT 0x01",
 396                 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
 397                 .exit_latency = 10,
 398                 .target_residency = 20,
 399                 .enter = &intel_idle },
 400         {
 401                 .name = "C3-HSW",
 402                 .desc = "MWAIT 0x10",
 403                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 404                 .exit_latency = 33,
 405                 .target_residency = 100,
 406                 .enter = &intel_idle },
 407         {
 408                 .name = "C6-HSW",
 409                 .desc = "MWAIT 0x20",
 410                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 411                 .exit_latency = 133,
 412                 .target_residency = 400,
 413                 .enter = &intel_idle },
 414         {
 415                 .name = "C7s-HSW",
 416                 .desc = "MWAIT 0x32",
 417                 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 418                 .exit_latency = 166,
 419                 .target_residency = 500,
 420                 .enter = &intel_idle },
 421         {
 422                 .name = "C8-HSW",
 423                 .desc = "MWAIT 0x40",
 424                 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 425                 .exit_latency = 300,
 426                 .target_residency = 900,
 427                 .enter = &intel_idle },
 428         {
 429                 .name = "C9-HSW",
 430                 .desc = "MWAIT 0x50",
 431                 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 432                 .exit_latency = 600,
 433                 .target_residency = 1800,
 434                 .enter = &intel_idle },
 435         {
 436                 .name = "C10-HSW",
 437                 .desc = "MWAIT 0x60",
 438                 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 439                 .exit_latency = 2600,
 440                 .target_residency = 7700,
 441                 .enter = &intel_idle },
 442         {
 443                 .enter = NULL }
 444 };
 445
 446 static struct cpuidle_state atom_cstates[] = {
 447         {
 448                 .name = "C1E-ATM",
 449                 .desc = "MWAIT 0x00",
 450                 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
 451                 .exit_latency = 10,
 452                 .target_residency = 20,
 453                 .enter = &intel_idle },
 454         {
 455                 .name = "C2-ATM",
 456                 .desc = "MWAIT 0x10",
 457                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID,
 458                 .exit_latency = 20,
 459                 .target_residency = 80,
 460                 .enter = &intel_idle },
 461         {
 462                 .name = "C4-ATM",
 463                 .desc = "MWAIT 0x30",
 464                 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 465                 .exit_latency = 100,
 466                 .target_residency = 400,
 467                 .enter = &intel_idle },
 468         {
 469                 .name = "C6-ATM",
 470                 .desc = "MWAIT 0x52",
 471                 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 472                 .exit_latency = 140,
 473                 .target_residency = 560,
 474                 .enter = &intel_idle },
 475         {
 476                 .enter = NULL }
 477 };
 478 static struct cpuidle_state avn_cstates[] = {
 479         {
 480                 .name = "C1-AVN",
 481                 .desc = "MWAIT 0x00",
 482                 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
 483                 .exit_latency = 2,
 484                 .target_residency = 2,
 485                 .enter = &intel_idle },
 486         {
 487                 .name = "C6-AVN",
 488                 .desc = "MWAIT 0x51",
 489                 .flags = MWAIT2flg(0x51) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 490                 .exit_latency = 15,
 491                 .target_residency = 45,
 492                 .enter = &intel_idle },
 493         {
 494                 .enter = NULL }
 495 };
 496
 497 /**
 498  * intel_idle
 499  * @dev: cpuidle_device
 500  * @drv: cpuidle driver
 501  * @index: index of cpuidle state
 502  *
 503  * Must be called under local_irq_disable().
 504  */
 505 static int intel_idle(struct cpuidle_device *dev,
 506                 struct cpuidle_driver *drv, int index)
 507 {
 508         unsigned long ecx = 1; /* break on interrupt flag */
 509         struct cpuidle_state *state = &drv->states[index];
 510         unsigned long eax = flg2MWAIT(state->flags);
 511         unsigned int cstate;
 512         int cpu = smp_processor_id();
 513
 514         cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1;
 515
 516         /*
 517          * leave_mm() to avoid costly and often unnecessary wakeups
 518          * for flushing the user TLB's associated with the active mm.
 519          */
 520         if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED)
 521                 leave_mm(cpu);
 522
 523         if (!(lapic_timer_reliable_states & (1 << (cstate))))
 524                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
 525
 526         mwait_idle_with_hints(eax, ecx);
 527
 528         if (!(lapic_timer_reliable_states & (1 << (cstate))))
 529                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
 530
 531         return index;
 532 }
 533
 534 static void __setup_broadcast_timer(void *arg)
 535 {
 536         unsigned long reason = (unsigned long)arg;
 537         int cpu = smp_processor_id();
 538
 539         reason = reason ?
 540                 CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF;
 541
 542         clockevents_notify(reason, &cpu);
 543 }
 544
 545 static int cpu_hotplug_notify(struct notifier_block *n,
 546                               unsigned long action, void *hcpu)
 547 {
 548         int hotcpu = (unsigned long)hcpu;
 549         struct cpuidle_device *dev;
 550
 551         switch (action & ~CPU_TASKS_FROZEN) {
 552         case CPU_ONLINE:
 553
 554                 if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
 555                         smp_call_function_single(hotcpu, __setup_broadcast_timer,
 556                                                  (void *)true, 1);
 557
 558                 /*
 559                  * Some systems can hotplug a cpu at runtime after
 560                  * the kernel has booted, we have to initialize the
 561                  * driver in this case
 562                  */
 563                 dev = per_cpu_ptr(intel_idle_cpuidle_devices, hotcpu);
 564                 if (!dev->registered)
 565                         intel_idle_cpu_init(hotcpu);
 566
 567                 break;
 568         }
 569         return NOTIFY_OK;
 570 }
 571
 572 static struct notifier_block cpu_hotplug_notifier = {
 573         .notifier_call = cpu_hotplug_notify,
 574 };
 575
 576 static void auto_demotion_disable(void *dummy)
 577 {
 578         unsigned long long msr_bits;
 579
 580         rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
 581         msr_bits &= ~(icpu->auto_demotion_disable_flags);
 582         wrmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
 583 }
 584 static void c1e_promotion_disable(void *dummy)
 585 {
 586         unsigned long long msr_bits;
 587
 588         rdmsrl(MSR_IA32_POWER_CTL, msr_bits);
 589         msr_bits &= ~0x2;
 590         wrmsrl(MSR_IA32_POWER_CTL, msr_bits);
 591 }
 592
 593 static const struct idle_cpu idle_cpu_nehalem = {
 594         .state_table = nehalem_cstates,
 595         .auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
 596         .disable_promotion_to_c1e = true,
 597 };
 598
 599 static const struct idle_cpu idle_cpu_atom = {
 600         .state_table = atom_cstates,
 601 };
 602
 603 static const struct idle_cpu idle_cpu_lincroft = {
 604         .state_table = atom_cstates,
 605         .auto_demotion_disable_flags = ATM_LNC_C6_AUTO_DEMOTE,
 606 };
 607
 608 static const struct idle_cpu idle_cpu_snb = {
 609         .state_table = snb_cstates,
 610         .disable_promotion_to_c1e = true,
 611 };
 612
 613 static const struct idle_cpu idle_cpu_byt = {
 614         .state_table = byt_cstates,
 615         .disable_promotion_to_c1e = true,
 616 };
 617
 618 static const struct idle_cpu idle_cpu_ivb = {
 619         .state_table = ivb_cstates,
 620         .disable_promotion_to_c1e = true,
 621 };
 622
 623 static const struct idle_cpu idle_cpu_ivt = {
 624         .state_table = ivt_cstates,
 625         .disable_promotion_to_c1e = true,
 626 };
 627
 628 static const struct idle_cpu idle_cpu_hsw = {
 629         .state_table = hsw_cstates,
 630         .disable_promotion_to_c1e = true,
 631 };
 632
 633 static const struct idle_cpu idle_cpu_avn = {
 634         .state_table = avn_cstates,
 635         .disable_promotion_to_c1e = true,
 636 };
 637
 638 #define ICPU(model, cpu) \
 639         { X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu }
 640
 641 static const struct x86_cpu_id intel_idle_ids[] = {
 642         ICPU(0x1a, idle_cpu_nehalem),
 643         ICPU(0x1e, idle_cpu_nehalem),
 644         ICPU(0x1f, idle_cpu_nehalem),
 645         ICPU(0x25, idle_cpu_nehalem),
 646         ICPU(0x2c, idle_cpu_nehalem),
 647         ICPU(0x2e, idle_cpu_nehalem),
 648         ICPU(0x1c, idle_cpu_atom),
 649         ICPU(0x26, idle_cpu_lincroft),
 650         ICPU(0x2f, idle_cpu_nehalem),
 651         ICPU(0x2a, idle_cpu_snb),
 652         ICPU(0x2d, idle_cpu_snb),
 653         ICPU(0x36, idle_cpu_atom),
 654         ICPU(0x37, idle_cpu_byt),
 655         ICPU(0x3a, idle_cpu_ivb),
 656         ICPU(0x3e, idle_cpu_ivt),
 657         ICPU(0x3c, idle_cpu_hsw),
 658         ICPU(0x3f, idle_cpu_hsw),
 659         ICPU(0x45, idle_cpu_hsw),
 660         ICPU(0x46, idle_cpu_hsw),
 661         ICPU(0x4D, idle_cpu_avn),
 662         {}
 663 };
 664 MODULE_DEVICE_TABLE(x86cpu, intel_idle_ids);
 665
 666 /*
 667  * intel_idle_probe()
 668  */
 669 static int __init intel_idle_probe(void)
 670 {
 671         unsigned int eax, ebx, ecx;
 672         const struct x86_cpu_id *id;
 673
 674         if (max_cstate == 0) {
 675                 pr_debug(PREFIX "disabled\n");
 676                 return -EPERM;
 677         }
 678
 679         id = x86_match_cpu(intel_idle_ids);
 680         if (!id) {
 681                 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
 682                     boot_cpu_data.x86 == 6)
 683                         pr_debug(PREFIX "does not run on family %d model %d\n",
 684                                 boot_cpu_data.x86, boot_cpu_data.x86_model);
 685                 return -ENODEV;
 686         }
 687
 688         if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
 689                 return -ENODEV;
 690
 691         cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
 692
 693         if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
 694             !(ecx & CPUID5_ECX_INTERRUPT_BREAK) ||
 695             !mwait_substates)
 696                         return -ENODEV;
 697
 698         pr_debug(PREFIX "MWAIT substates: 0x%x\n", mwait_substates);
 699
 700         icpu = (const struct idle_cpu *)id->driver_data;
 701         cpuidle_state_table = icpu->state_table;
 702
 703         if (boot_cpu_has(X86_FEATURE_ARAT))     /* Always Reliable APIC Timer */
 704                 lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE;
 705         else
 706                 on_each_cpu(__setup_broadcast_timer, (void *)true, 1);
 707
 708         pr_debug(PREFIX "v" INTEL_IDLE_VERSION
 709                 " model 0x%X\n", boot_cpu_data.x86_model);
 710
 711         pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n",
 712                 lapic_timer_reliable_states);
 713         return 0;
 714 }
 715
 716 /*
 717  * intel_idle_cpuidle_devices_uninit()
 718  * unregister, free cpuidle_devices
 719  */
 720 static void intel_idle_cpuidle_devices_uninit(void)
 721 {
 722         int i;
 723         struct cpuidle_device *dev;
 724
 725         for_each_online_cpu(i) {
 726                 dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
 727                 cpuidle_unregister_device(dev);
 728         }
 729
 730         free_percpu(intel_idle_cpuidle_devices);
 731         return;
 732 }
 733
 734 /*
 735  * intel_idle_state_table_update()
 736  *
 737  * Update the default state_table for this CPU-id
 738  *
 739  * Currently used to access tuned IVT multi-socket targets
 740  * Assumption: num_sockets == (max_package_num + 1)
 741  */
 742 void intel_idle_state_table_update(void)
 743 {
 744         /* IVT uses a different table for 1-2, 3-4, and > 4 sockets */
 745         if (boot_cpu_data.x86_model == 0x3e) { /* IVT */
 746                 int cpu, package_num, num_sockets = 1;
 747
 748                 for_each_online_cpu(cpu) {
 749                         package_num = topology_physical_package_id(cpu);
 750                         if (package_num + 1 > num_sockets) {
 751                                 num_sockets = package_num + 1;
 752
 753                                 if (num_sockets > 4) {
 754                                         cpuidle_state_table = ivt_cstates_8s;
 755                                         return;
 756                                 }
 757                         }
 758                 }
 759
 760                 if (num_sockets > 2)
 761                         cpuidle_state_table = ivt_cstates_4s;
 762                 /* else, 1 and 2 socket systems use default ivt_cstates */
 763         }
 764         return;
 765 }
 766
 767 /*
 768  * intel_idle_cpuidle_driver_init()
 769  * allocate, initialize cpuidle_states
 770  */
 771 static int __init intel_idle_cpuidle_driver_init(void)
 772 {
 773         int cstate;
 774         struct cpuidle_driver *drv = &intel_idle_driver;
 775
 776         intel_idle_state_table_update();
 777
 778         drv->state_count = 1;
 779
 780         for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) {
 781                 int num_substates, mwait_hint, mwait_cstate;
 782
 783                 if (cpuidle_state_table[cstate].enter == NULL)
 784                         break;
 785
 786                 if (cstate + 1 > max_cstate) {
 787                         printk(PREFIX "max_cstate %d reached\n",
 788                                 max_cstate);
 789                         break;
 790                 }
 791
 792                 mwait_hint = flg2MWAIT(cpuidle_state_table[cstate].flags);
 793                 mwait_cstate = MWAIT_HINT2CSTATE(mwait_hint);
 794
 795                 /* number of sub-states for this state in CPUID.MWAIT */
 796                 num_substates = (mwait_substates >> ((mwait_cstate + 1) * 4))
 797                                         & MWAIT_SUBSTATE_MASK;
 798
 799                 /* if NO sub-states for this state in CPUID, skip it */
 800                 if (num_substates == 0)
 801                         continue;
 802
 803                 if (((mwait_cstate + 1) > 2) &&
 804                         !boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
 805                         mark_tsc_unstable("TSC halts in idle"
 806                                         " states deeper than C2");
 807
 808                 drv->states[drv->state_count] = /* structure copy */
 809                         cpuidle_state_table[cstate];
 810
 811                 drv->state_count += 1;
 812         }
 813
 814         if (icpu->auto_demotion_disable_flags)
 815                 on_each_cpu(auto_demotion_disable, NULL, 1);
 816
 817         if (icpu->disable_promotion_to_c1e)     /* each-cpu is redundant */
 818                 on_each_cpu(c1e_promotion_disable, NULL, 1);
 819
 820         return 0;
 821 }
 822
 823
 824 /*
 825  * intel_idle_cpu_init()
 826  * allocate, initialize, register cpuidle_devices
 827  * @cpu: cpu/core to initialize
 828  */
 829 static int intel_idle_cpu_init(int cpu)
 830 {
 831         struct cpuidle_device *dev;
 832
 833         dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu);
 834
 835         dev->cpu = cpu;
 836
 837         if (cpuidle_register_device(dev)) {
 838                 pr_debug(PREFIX "cpuidle_register_device %d failed!\n", cpu);
 839                 intel_idle_cpuidle_devices_uninit();
 840                 return -EIO;
 841         }
 842
 843         if (icpu->auto_demotion_disable_flags)
 844                 smp_call_function_single(cpu, auto_demotion_disable, NULL, 1);
 845
 846         if (icpu->disable_promotion_to_c1e)
 847                 smp_call_function_single(cpu, c1e_promotion_disable, NULL, 1);
 848
 849         return 0;
 850 }
 851
 852 static int __init intel_idle_init(void)
 853 {
 854         int retval, i;
 855
 856         /* Do not load intel_idle at all for now if idle= is passed */
 857         if (boot_option_idle_override != IDLE_NO_OVERRIDE)
 858                 return -ENODEV;
 859
 860         retval = intel_idle_probe();
 861         if (retval)
 862                 return retval;
 863
 864         intel_idle_cpuidle_driver_init();
 865         retval = cpuidle_register_driver(&intel_idle_driver);
 866         if (retval) {
 867                 struct cpuidle_driver *drv = cpuidle_get_driver();
 868                 printk(KERN_DEBUG PREFIX "intel_idle yielding to %s",
 869                         drv ? drv->name : "none");
 870                 return retval;
 871         }
 872
 873         intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
 874         if (intel_idle_cpuidle_devices == NULL)
 875                 return -ENOMEM;
 876
 877         cpu_notifier_register_begin();
 878
 879         for_each_online_cpu(i) {
 880                 retval = intel_idle_cpu_init(i);
 881                 if (retval) {
 882                         cpu_notifier_register_done();
 883                         cpuidle_unregister_driver(&intel_idle_driver);
 884                         return retval;
 885                 }
 886         }
 887         __register_cpu_notifier(&cpu_hotplug_notifier);
 888
 889         cpu_notifier_register_done();
 890
 891         return 0;
 892 }
 893
 894 static void __exit intel_idle_exit(void)
 895 {
 896         intel_idle_cpuidle_devices_uninit();
 897         cpuidle_unregister_driver(&intel_idle_driver);
 898
 899         cpu_notifier_register_begin();
 900
 901         if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
 902                 on_each_cpu(__setup_broadcast_timer, (void *)false, 1);
 903         __unregister_cpu_notifier(&cpu_hotplug_notifier);
 904
 905         cpu_notifier_register_done();
 906
 907         return;
 908 }
 909
 910 module_init(intel_idle_init);
 911 module_exit(intel_idle_exit);
 912
 913 module_param(max_cstate, int, 0444);
 914
 915 MODULE_AUTHOR("Len Brown <len.brown@intel.com>");
 916 MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION);
 917 MODULE_LICENSE("GPL");