drivers/idle/intel_idle.c

   1 /*
   2  * intel_idle.c - native hardware idle loop for modern Intel processors
   3  *
   4  * Copyright (c) 2013, Intel Corporation.
   5  * Len Brown <len.brown@intel.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program; if not, write to the Free Software Foundation, Inc.,
  18  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19  */
  20
  21 /*
  22  * intel_idle is a cpuidle driver that loads on specific Intel processors
  23  * in lieu of the legacy ACPI processor_idle driver.  The intent is to
  24  * make Linux more efficient on these processors, as intel_idle knows
  25  * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
  26  */
  27
  28 /*
  29  * Design Assumptions
  30  *
  31  * All CPUs have same idle states as boot CPU
  32  *
  33  * Chipset BM_STS (bus master status) bit is a NOP
  34  *      for preventing entry into deep C-stats
  35  */
  36
  37 /*
  38  * Known limitations
  39  *
  40  * The driver currently initializes for_each_online_cpu() upon modprobe.
  41  * It it unaware of subsequent processors hot-added to the system.
  42  * This means that if you boot with maxcpus=n and later online
  43  * processors above n, those processors will use C1 only.
  44  *
  45  * ACPI has a .suspend hack to turn off deep c-statees during suspend
  46  * to avoid complications with the lapic timer workaround.
  47  * Have not seen issues with suspend, but may need same workaround here.
  48  *
  49  * There is currently no kernel-based automatic probing/loading mechanism
  50  * if the driver is built as a module.
  51  */
  52
  53 /* un-comment DEBUG to enable pr_debug() statements */
  54 #define DEBUG
  55
  56 #include <linux/kernel.h>
  57 #include <linux/cpuidle.h>
  58 #include <linux/clockchips.h>
  59 #include <trace/events/power.h>
  60 #include <linux/sched.h>
  61 #include <linux/notifier.h>
  62 #include <linux/cpu.h>
  63 #include <linux/module.h>
  64 #include <asm/cpu_device_id.h>
  65 #include <asm/mwait.h>
  66 #include <asm/msr.h>
  67
  68 #define INTEL_IDLE_VERSION "0.4"
  69 #define PREFIX "intel_idle: "
  70
  71 static struct cpuidle_driver intel_idle_driver = {
  72         .name = "intel_idle",
  73         .owner = THIS_MODULE,
  74 };
  75 /* intel_idle.max_cstate=0 disables driver */
  76 static int max_cstate = CPUIDLE_STATE_MAX - 1;
  77
  78 static unsigned int mwait_substates;
  79
  80 #define LAPIC_TIMER_ALWAYS_RELIABLE 0xFFFFFFFF
  81 /* Reliable LAPIC Timer States, bit 1 for C1 etc.  */
  82 static unsigned int lapic_timer_reliable_states = (1 << 1);      /* Default to only C1 */
  83
  84 struct idle_cpu {
  85         struct cpuidle_state *state_table;
  86
  87         /*
  88          * Hardware C-state auto-demotion may not always be optimal.
  89          * Indicate which enable bits to clear here.
  90          */
  91         unsigned long auto_demotion_disable_flags;
  92         bool byt_auto_demotion_disable_flag;
  93         bool disable_promotion_to_c1e;
  94 };
  95
  96 static const struct idle_cpu *icpu;
  97 static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
  98 static int intel_idle(struct cpuidle_device *dev,
  99                         struct cpuidle_driver *drv, int index);
 100 static int intel_idle_cpu_init(int cpu);
 101
 102 static struct cpuidle_state *cpuidle_state_table;
 103
 104 /*
 105  * Set this flag for states where the HW flushes the TLB for us
 106  * and so we don't need cross-calls to keep it consistent.
 107  * If this flag is set, SW flushes the TLB, so even if the
 108  * HW doesn't do the flushing, this flag is safe to use.
 109  */
 110 #define CPUIDLE_FLAG_TLB_FLUSHED        0x10000
 111
 112 /*
 113  * MWAIT takes an 8-bit "hint" in EAX "suggesting"
 114  * the C-state (top nibble) and sub-state (bottom nibble)
 115  * 0x00 means "MWAIT(C1)", 0x10 means "MWAIT(C2)" etc.
 116  *
 117  * We store the hint at the top of our "flags" for each state.
 118  */
 119 #define flg2MWAIT(flags) (((flags) >> 24) & 0xFF)
 120 #define MWAIT2flg(eax) ((eax & 0xFF) << 24)
 121
 122 /*
 123  * States are indexed by the cstate number,
 124  * which is also the index into the MWAIT hint array.
 125  * Thus C0 is a dummy.
 126  */
 127 static struct cpuidle_state nehalem_cstates[] = {
 128         {
 129                 .name = "C1-NHM",
 130                 .desc = "MWAIT 0x00",
 131                 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
 132                 .exit_latency = 3,
 133                 .target_residency = 6,
 134                 .enter = &intel_idle },
 135         {
 136                 .name = "C1E-NHM",
 137                 .desc = "MWAIT 0x01",
 138                 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
 139                 .exit_latency = 10,
 140                 .target_residency = 20,
 141                 .enter = &intel_idle },
 142         {
 143                 .name = "C3-NHM",
 144                 .desc = "MWAIT 0x10",
 145                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 146                 .exit_latency = 20,
 147                 .target_residency = 80,
 148                 .enter = &intel_idle },
 149         {
 150                 .name = "C6-NHM",
 151                 .desc = "MWAIT 0x20",
 152                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 153                 .exit_latency = 200,
 154                 .target_residency = 800,
 155                 .enter = &intel_idle },
 156         {
 157                 .enter = NULL }
 158 };
 159
 160 static struct cpuidle_state snb_cstates[] = {
 161         {
 162                 .name = "C1-SNB",
 163                 .desc = "MWAIT 0x00",
 164                 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
 165                 .exit_latency = 2,
 166                 .target_residency = 2,
 167                 .enter = &intel_idle },
 168         {
 169                 .name = "C1E-SNB",
 170                 .desc = "MWAIT 0x01",
 171                 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
 172                 .exit_latency = 10,
 173                 .target_residency = 20,
 174                 .enter = &intel_idle },
 175         {
 176                 .name = "C3-SNB",
 177                 .desc = "MWAIT 0x10",
 178                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 179                 .exit_latency = 80,
 180                 .target_residency = 211,
 181                 .enter = &intel_idle },
 182         {
 183                 .name = "C6-SNB",
 184                 .desc = "MWAIT 0x20",
 185                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 186                 .exit_latency = 104,
 187                 .target_residency = 345,
 188                 .enter = &intel_idle },
 189         {
 190                 .name = "C7-SNB",
 191                 .desc = "MWAIT 0x30",
 192                 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 193                 .exit_latency = 109,
 194                 .target_residency = 345,
 195                 .enter = &intel_idle },
 196         {
 197                 .enter = NULL }
 198 };
 199
 200 static struct cpuidle_state byt_cstates[] = {
 201         {
 202                 .name = "C1-BYT",
 203                 .desc = "MWAIT 0x00",
 204                 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
 205                 .exit_latency = 1,
 206                 .target_residency = 1,
 207                 .enter = &intel_idle },
 208         {
 209                 .name = "C1E-BYT",
 210                 .desc = "MWAIT 0x01",
 211                 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
 212                 .exit_latency = 15,
 213                 .target_residency = 30,
 214                 .enter = &intel_idle },
 215         {
 216                 .name = "C6N-BYT",
 217                 .desc = "MWAIT 0x58",
 218                 .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 219                 .exit_latency = 40,
 220                 .target_residency = 275,
 221                 .enter = &intel_idle },
 222         {
 223                 .name = "C6S-BYT",
 224                 .desc = "MWAIT 0x52",
 225                 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 226                 .exit_latency = 140,
 227                 .target_residency = 560,
 228                 .enter = &intel_idle },
 229         {
 230                 .name = "C7-BYT",
 231                 .desc = "MWAIT 0x60",
 232                 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 233                 .exit_latency = 1200,
 234                 .target_residency = 1500,
 235                 .enter = &intel_idle },
 236         {
 237                 .name = "C7S-BYT",
 238                 .desc = "MWAIT 0x64",
 239                 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 240                 .exit_latency = 10000,
 241                 .target_residency = 20000,
 242                 .enter = &intel_idle },
 243         {
 244                 .enter = NULL }
 245 };
 246
 247 static struct cpuidle_state ivb_cstates[] = {
 248         {
 249                 .name = "C1-IVB",
 250                 .desc = "MWAIT 0x00",
 251                 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
 252                 .exit_latency = 1,
 253                 .target_residency = 1,
 254                 .enter = &intel_idle },
 255         {
 256                 .name = "C1E-IVB",
 257                 .desc = "MWAIT 0x01",
 258                 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
 259                 .exit_latency = 10,
 260                 .target_residency = 20,
 261                 .enter = &intel_idle },
 262         {
 263                 .name = "C3-IVB",
 264                 .desc = "MWAIT 0x10",
 265                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 266                 .exit_latency = 59,
 267                 .target_residency = 156,
 268                 .enter = &intel_idle },
 269         {
 270                 .name = "C6-IVB",
 271                 .desc = "MWAIT 0x20",
 272                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 273                 .exit_latency = 80,
 274                 .target_residency = 300,
 275                 .enter = &intel_idle },
 276         {
 277                 .name = "C7-IVB",
 278                 .desc = "MWAIT 0x30",
 279                 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 280                 .exit_latency = 87,
 281                 .target_residency = 300,
 282                 .enter = &intel_idle },
 283         {
 284                 .enter = NULL }
 285 };
 286
 287 static struct cpuidle_state ivt_cstates[] = {
 288         {
 289                 .name = "C1-IVT",
 290                 .desc = "MWAIT 0x00",
 291                 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
 292                 .exit_latency = 1,
 293                 .target_residency = 1,
 294                 .enter = &intel_idle },
 295         {
 296                 .name = "C1E-IVT",
 297                 .desc = "MWAIT 0x01",
 298                 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
 299                 .exit_latency = 10,
 300                 .target_residency = 80,
 301                 .enter = &intel_idle },
 302         {
 303                 .name = "C3-IVT",
 304                 .desc = "MWAIT 0x10",
 305                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 306                 .exit_latency = 59,
 307                 .target_residency = 156,
 308                 .enter = &intel_idle },
 309         {
 310                 .name = "C6-IVT",
 311                 .desc = "MWAIT 0x20",
 312                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 313                 .exit_latency = 82,
 314                 .target_residency = 300,
 315                 .enter = &intel_idle },
 316         {
 317                 .enter = NULL }
 318 };
 319
 320 static struct cpuidle_state ivt_cstates_4s[] = {
 321         {
 322                 .name = "C1-IVT-4S",
 323                 .desc = "MWAIT 0x00",
 324                 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
 325                 .exit_latency = 1,
 326                 .target_residency = 1,
 327                 .enter = &intel_idle },
 328         {
 329                 .name = "C1E-IVT-4S",
 330                 .desc = "MWAIT 0x01",
 331                 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
 332                 .exit_latency = 10,
 333                 .target_residency = 250,
 334                 .enter = &intel_idle },
 335         {
 336                 .name = "C3-IVT-4S",
 337                 .desc = "MWAIT 0x10",
 338                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 339                 .exit_latency = 59,
 340                 .target_residency = 300,
 341                 .enter = &intel_idle },
 342         {
 343                 .name = "C6-IVT-4S",
 344                 .desc = "MWAIT 0x20",
 345                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 346                 .exit_latency = 84,
 347                 .target_residency = 400,
 348                 .enter = &intel_idle },
 349         {
 350                 .enter = NULL }
 351 };
 352
 353 static struct cpuidle_state ivt_cstates_8s[] = {
 354         {
 355                 .name = "C1-IVT-8S",
 356                 .desc = "MWAIT 0x00",
 357                 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
 358                 .exit_latency = 1,
 359                 .target_residency = 1,
 360                 .enter = &intel_idle },
 361         {
 362                 .name = "C1E-IVT-8S",
 363                 .desc = "MWAIT 0x01",
 364                 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
 365                 .exit_latency = 10,
 366                 .target_residency = 500,
 367                 .enter = &intel_idle },
 368         {
 369                 .name = "C3-IVT-8S",
 370                 .desc = "MWAIT 0x10",
 371                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 372                 .exit_latency = 59,
 373                 .target_residency = 600,
 374                 .enter = &intel_idle },
 375         {
 376                 .name = "C6-IVT-8S",
 377                 .desc = "MWAIT 0x20",
 378                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 379                 .exit_latency = 88,
 380                 .target_residency = 700,
 381                 .enter = &intel_idle },
 382         {
 383                 .enter = NULL }
 384 };
 385
 386 static struct cpuidle_state hsw_cstates[] = {
 387         {
 388                 .name = "C1-HSW",
 389                 .desc = "MWAIT 0x00",
 390                 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
 391                 .exit_latency = 2,
 392                 .target_residency = 2,
 393                 .enter = &intel_idle },
 394         {
 395                 .name = "C1E-HSW",
 396                 .desc = "MWAIT 0x01",
 397                 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
 398                 .exit_latency = 10,
 399                 .target_residency = 20,
 400                 .enter = &intel_idle },
 401         {
 402                 .name = "C3-HSW",
 403                 .desc = "MWAIT 0x10",
 404                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 405                 .exit_latency = 33,
 406                 .target_residency = 100,
 407                 .enter = &intel_idle },
 408         {
 409                 .name = "C6-HSW",
 410                 .desc = "MWAIT 0x20",
 411                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 412                 .exit_latency = 133,
 413                 .target_residency = 400,
 414                 .enter = &intel_idle },
 415         {
 416                 .name = "C7s-HSW",
 417                 .desc = "MWAIT 0x32",
 418                 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 419                 .exit_latency = 166,
 420                 .target_residency = 500,
 421                 .enter = &intel_idle },
 422         {
 423                 .name = "C8-HSW",
 424                 .desc = "MWAIT 0x40",
 425                 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 426                 .exit_latency = 300,
 427                 .target_residency = 900,
 428                 .enter = &intel_idle },
 429         {
 430                 .name = "C9-HSW",
 431                 .desc = "MWAIT 0x50",
 432                 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 433                 .exit_latency = 600,
 434                 .target_residency = 1800,
 435                 .enter = &intel_idle },
 436         {
 437                 .name = "C10-HSW",
 438                 .desc = "MWAIT 0x60",
 439                 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 440                 .exit_latency = 2600,
 441                 .target_residency = 7700,
 442                 .enter = &intel_idle },
 443         {
 444                 .enter = NULL }
 445 };
 446 static struct cpuidle_state bdw_cstates[] = {
 447         {
 448                 .name = "C1-BDW",
 449                 .desc = "MWAIT 0x00",
 450                 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
 451                 .exit_latency = 2,
 452                 .target_residency = 2,
 453                 .enter = &intel_idle },
 454         {
 455                 .name = "C1E-BDW",
 456                 .desc = "MWAIT 0x01",
 457                 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID,
 458                 .exit_latency = 10,
 459                 .target_residency = 20,
 460                 .enter = &intel_idle },
 461         {
 462                 .name = "C3-BDW",
 463                 .desc = "MWAIT 0x10",
 464                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 465                 .exit_latency = 40,
 466                 .target_residency = 100,
 467                 .enter = &intel_idle },
 468         {
 469                 .name = "C6-BDW",
 470                 .desc = "MWAIT 0x20",
 471                 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 472                 .exit_latency = 133,
 473                 .target_residency = 400,
 474                 .enter = &intel_idle },
 475         {
 476                 .name = "C7s-BDW",
 477                 .desc = "MWAIT 0x32",
 478                 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 479                 .exit_latency = 166,
 480                 .target_residency = 500,
 481                 .enter = &intel_idle },
 482         {
 483                 .name = "C8-BDW",
 484                 .desc = "MWAIT 0x40",
 485                 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 486                 .exit_latency = 300,
 487                 .target_residency = 900,
 488                 .enter = &intel_idle },
 489         {
 490                 .name = "C9-BDW",
 491                 .desc = "MWAIT 0x50",
 492                 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 493                 .exit_latency = 600,
 494                 .target_residency = 1800,
 495                 .enter = &intel_idle },
 496         {
 497                 .name = "C10-BDW",
 498                 .desc = "MWAIT 0x60",
 499                 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 500                 .exit_latency = 2600,
 501                 .target_residency = 7700,
 502                 .enter = &intel_idle },
 503         {
 504                 .enter = NULL }
 505 };
 506
 507 static struct cpuidle_state atom_cstates[] = {
 508         {
 509                 .name = "C1E-ATM",
 510                 .desc = "MWAIT 0x00",
 511                 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
 512                 .exit_latency = 10,
 513                 .target_residency = 20,
 514                 .enter = &intel_idle },
 515         {
 516                 .name = "C2-ATM",
 517                 .desc = "MWAIT 0x10",
 518                 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID,
 519                 .exit_latency = 20,
 520                 .target_residency = 80,
 521                 .enter = &intel_idle },
 522         {
 523                 .name = "C4-ATM",
 524                 .desc = "MWAIT 0x30",
 525                 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 526                 .exit_latency = 100,
 527                 .target_residency = 400,
 528                 .enter = &intel_idle },
 529         {
 530                 .name = "C6-ATM",
 531                 .desc = "MWAIT 0x52",
 532                 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 533                 .exit_latency = 140,
 534                 .target_residency = 560,
 535                 .enter = &intel_idle },
 536         {
 537                 .enter = NULL }
 538 };
 539 static struct cpuidle_state avn_cstates[] = {
 540         {
 541                 .name = "C1-AVN",
 542                 .desc = "MWAIT 0x00",
 543                 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID,
 544                 .exit_latency = 2,
 545                 .target_residency = 2,
 546                 .enter = &intel_idle },
 547         {
 548                 .name = "C6-AVN",
 549                 .desc = "MWAIT 0x51",
 550                 .flags = MWAIT2flg(0x51) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 551                 .exit_latency = 15,
 552                 .target_residency = 45,
 553                 .enter = &intel_idle },
 554         {
 555                 .enter = NULL }
 556 };
 557
 558 /**
 559  * intel_idle
 560  * @dev: cpuidle_device
 561  * @drv: cpuidle driver
 562  * @index: index of cpuidle state
 563  *
 564  * Must be called under local_irq_disable().
 565  */
 566 static int intel_idle(struct cpuidle_device *dev,
 567                 struct cpuidle_driver *drv, int index)
 568 {
 569         unsigned long ecx = 1; /* break on interrupt flag */
 570         struct cpuidle_state *state = &drv->states[index];
 571         unsigned long eax = flg2MWAIT(state->flags);
 572         unsigned int cstate;
 573         int cpu = smp_processor_id();
 574
 575         cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1;
 576
 577         /*
 578          * leave_mm() to avoid costly and often unnecessary wakeups
 579          * for flushing the user TLB's associated with the active mm.
 580          */
 581         if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED)
 582                 leave_mm(cpu);
 583
 584         if (!(lapic_timer_reliable_states & (1 << (cstate))))
 585                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
 586
 587         mwait_idle_with_hints(eax, ecx);
 588
 589         if (!(lapic_timer_reliable_states & (1 << (cstate))))
 590                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
 591
 592         return index;
 593 }
 594
 595 static void __setup_broadcast_timer(void *arg)
 596 {
 597         unsigned long reason = (unsigned long)arg;
 598         int cpu = smp_processor_id();
 599
 600         reason = reason ?
 601                 CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF;
 602
 603         clockevents_notify(reason, &cpu);
 604 }
 605
 606 static int cpu_hotplug_notify(struct notifier_block *n,
 607                               unsigned long action, void *hcpu)
 608 {
 609         int hotcpu = (unsigned long)hcpu;
 610         struct cpuidle_device *dev;
 611
 612         switch (action & ~CPU_TASKS_FROZEN) {
 613         case CPU_ONLINE:
 614
 615                 if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
 616                         smp_call_function_single(hotcpu, __setup_broadcast_timer,
 617                                                  (void *)true, 1);
 618
 619                 /*
 620                  * Some systems can hotplug a cpu at runtime after
 621                  * the kernel has booted, we have to initialize the
 622                  * driver in this case
 623                  */
 624                 dev = per_cpu_ptr(intel_idle_cpuidle_devices, hotcpu);
 625                 if (!dev->registered)
 626                         intel_idle_cpu_init(hotcpu);
 627
 628                 break;
 629         }
 630         return NOTIFY_OK;
 631 }
 632
 633 static struct notifier_block cpu_hotplug_notifier = {
 634         .notifier_call = cpu_hotplug_notify,
 635 };
 636
 637 static void auto_demotion_disable(void *dummy)
 638 {
 639         unsigned long long msr_bits;
 640
 641         rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
 642         msr_bits &= ~(icpu->auto_demotion_disable_flags);
 643         wrmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
 644 }
 645 static void c1e_promotion_disable(void *dummy)
 646 {
 647         unsigned long long msr_bits;
 648
 649         rdmsrl(MSR_IA32_POWER_CTL, msr_bits);
 650         msr_bits &= ~0x2;
 651         wrmsrl(MSR_IA32_POWER_CTL, msr_bits);
 652 }
 653
 654 static const struct idle_cpu idle_cpu_nehalem = {
 655         .state_table = nehalem_cstates,
 656         .auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
 657         .disable_promotion_to_c1e = true,
 658 };
 659
 660 static const struct idle_cpu idle_cpu_atom = {
 661         .state_table = atom_cstates,
 662 };
 663
 664 static const struct idle_cpu idle_cpu_lincroft = {
 665         .state_table = atom_cstates,
 666         .auto_demotion_disable_flags = ATM_LNC_C6_AUTO_DEMOTE,
 667 };
 668
 669 static const struct idle_cpu idle_cpu_snb = {
 670         .state_table = snb_cstates,
 671         .disable_promotion_to_c1e = true,
 672 };
 673
 674 static const struct idle_cpu idle_cpu_byt = {
 675         .state_table = byt_cstates,
 676         .disable_promotion_to_c1e = true,
 677         .byt_auto_demotion_disable_flag = true,
 678 };
 679
 680 static const struct idle_cpu idle_cpu_ivb = {
 681         .state_table = ivb_cstates,
 682         .disable_promotion_to_c1e = true,
 683 };
 684
 685 static const struct idle_cpu idle_cpu_ivt = {
 686         .state_table = ivt_cstates,
 687         .disable_promotion_to_c1e = true,
 688 };
 689
 690 static const struct idle_cpu idle_cpu_hsw = {
 691         .state_table = hsw_cstates,
 692         .disable_promotion_to_c1e = true,
 693 };
 694
 695 static const struct idle_cpu idle_cpu_bdw = {
 696         .state_table = bdw_cstates,
 697         .disable_promotion_to_c1e = true,
 698 };
 699
 700 static const struct idle_cpu idle_cpu_avn = {
 701         .state_table = avn_cstates,
 702         .disable_promotion_to_c1e = true,
 703 };
 704
 705 #define ICPU(model, cpu) \
 706         { X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu }
 707
 708 static const struct x86_cpu_id intel_idle_ids[] = {
 709         ICPU(0x1a, idle_cpu_nehalem),
 710         ICPU(0x1e, idle_cpu_nehalem),
 711         ICPU(0x1f, idle_cpu_nehalem),
 712         ICPU(0x25, idle_cpu_nehalem),
 713         ICPU(0x2c, idle_cpu_nehalem),
 714         ICPU(0x2e, idle_cpu_nehalem),
 715         ICPU(0x1c, idle_cpu_atom),
 716         ICPU(0x26, idle_cpu_lincroft),
 717         ICPU(0x2f, idle_cpu_nehalem),
 718         ICPU(0x2a, idle_cpu_snb),
 719         ICPU(0x2d, idle_cpu_snb),
 720         ICPU(0x36, idle_cpu_atom),
 721         ICPU(0x37, idle_cpu_byt),
 722         ICPU(0x3a, idle_cpu_ivb),
 723         ICPU(0x3e, idle_cpu_ivt),
 724         ICPU(0x3c, idle_cpu_hsw),
 725         ICPU(0x3f, idle_cpu_hsw),
 726         ICPU(0x45, idle_cpu_hsw),
 727         ICPU(0x46, idle_cpu_hsw),
 728         ICPU(0x4d, idle_cpu_avn),
 729         ICPU(0x3d, idle_cpu_bdw),
 730         ICPU(0x4f, idle_cpu_bdw),
 731         ICPU(0x56, idle_cpu_bdw),
 732         {}
 733 };
 734 MODULE_DEVICE_TABLE(x86cpu, intel_idle_ids);
 735
 736 /*
 737  * intel_idle_probe()
 738  */
 739 static int __init intel_idle_probe(void)
 740 {
 741         unsigned int eax, ebx, ecx;
 742         const struct x86_cpu_id *id;
 743
 744         if (max_cstate == 0) {
 745                 pr_debug(PREFIX "disabled\n");
 746                 return -EPERM;
 747         }
 748
 749         id = x86_match_cpu(intel_idle_ids);
 750         if (!id) {
 751                 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
 752                     boot_cpu_data.x86 == 6)
 753                         pr_debug(PREFIX "does not run on family %d model %d\n",
 754                                 boot_cpu_data.x86, boot_cpu_data.x86_model);
 755                 return -ENODEV;
 756         }
 757
 758         if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
 759                 return -ENODEV;
 760
 761         cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
 762
 763         if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
 764             !(ecx & CPUID5_ECX_INTERRUPT_BREAK) ||
 765             !mwait_substates)
 766                         return -ENODEV;
 767
 768         pr_debug(PREFIX "MWAIT substates: 0x%x\n", mwait_substates);
 769
 770         icpu = (const struct idle_cpu *)id->driver_data;
 771         cpuidle_state_table = icpu->state_table;
 772
 773         if (boot_cpu_has(X86_FEATURE_ARAT))     /* Always Reliable APIC Timer */
 774                 lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE;
 775         else
 776                 on_each_cpu(__setup_broadcast_timer, (void *)true, 1);
 777
 778         pr_debug(PREFIX "v" INTEL_IDLE_VERSION
 779                 " model 0x%X\n", boot_cpu_data.x86_model);
 780
 781         pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n",
 782                 lapic_timer_reliable_states);
 783         return 0;
 784 }
 785
 786 /*
 787  * intel_idle_cpuidle_devices_uninit()
 788  * unregister, free cpuidle_devices
 789  */
 790 static void intel_idle_cpuidle_devices_uninit(void)
 791 {
 792         int i;
 793         struct cpuidle_device *dev;
 794
 795         for_each_online_cpu(i) {
 796                 dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
 797                 cpuidle_unregister_device(dev);
 798         }
 799
 800         free_percpu(intel_idle_cpuidle_devices);
 801         return;
 802 }
 803
 804 /*
 805  * intel_idle_state_table_update()
 806  *
 807  * Update the default state_table for this CPU-id
 808  *
 809  * Currently used to access tuned IVT multi-socket targets
 810  * Assumption: num_sockets == (max_package_num + 1)
 811  */
 812 void intel_idle_state_table_update(void)
 813 {
 814         /* IVT uses a different table for 1-2, 3-4, and > 4 sockets */
 815         if (boot_cpu_data.x86_model == 0x3e) { /* IVT */
 816                 int cpu, package_num, num_sockets = 1;
 817
 818                 for_each_online_cpu(cpu) {
 819                         package_num = topology_physical_package_id(cpu);
 820                         if (package_num + 1 > num_sockets) {
 821                                 num_sockets = package_num + 1;
 822
 823                                 if (num_sockets > 4) {
 824                                         cpuidle_state_table = ivt_cstates_8s;
 825                                         return;
 826                                 }
 827                         }
 828                 }
 829
 830                 if (num_sockets > 2)
 831                         cpuidle_state_table = ivt_cstates_4s;
 832                 /* else, 1 and 2 socket systems use default ivt_cstates */
 833         }
 834         return;
 835 }
 836
 837 /*
 838  * intel_idle_cpuidle_driver_init()
 839  * allocate, initialize cpuidle_states
 840  */
 841 static int __init intel_idle_cpuidle_driver_init(void)
 842 {
 843         int cstate;
 844         struct cpuidle_driver *drv = &intel_idle_driver;
 845
 846         intel_idle_state_table_update();
 847
 848         drv->state_count = 1;
 849
 850         for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) {
 851                 int num_substates, mwait_hint, mwait_cstate;
 852
 853                 if (cpuidle_state_table[cstate].enter == NULL)
 854                         break;
 855
 856                 if (cstate + 1 > max_cstate) {
 857                         printk(PREFIX "max_cstate %d reached\n",
 858                                 max_cstate);
 859                         break;
 860                 }
 861
 862                 mwait_hint = flg2MWAIT(cpuidle_state_table[cstate].flags);
 863                 mwait_cstate = MWAIT_HINT2CSTATE(mwait_hint);
 864
 865                 /* number of sub-states for this state in CPUID.MWAIT */
 866                 num_substates = (mwait_substates >> ((mwait_cstate + 1) * 4))
 867                                         & MWAIT_SUBSTATE_MASK;
 868
 869                 /* if NO sub-states for this state in CPUID, skip it */
 870                 if (num_substates == 0)
 871                         continue;
 872
 873                 if (((mwait_cstate + 1) > 2) &&
 874                         !boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
 875                         mark_tsc_unstable("TSC halts in idle"
 876                                         " states deeper than C2");
 877
 878                 drv->states[drv->state_count] = /* structure copy */
 879                         cpuidle_state_table[cstate];
 880
 881                 drv->state_count += 1;
 882         }
 883
 884         if (icpu->auto_demotion_disable_flags)
 885                 on_each_cpu(auto_demotion_disable, NULL, 1);
 886
 887         if (icpu->byt_auto_demotion_disable_flag) {
 888                 wrmsrl(MSR_CC6_DEMOTION_POLICY_CONFIG, 0);
 889                 wrmsrl(MSR_MC6_DEMOTION_POLICY_CONFIG, 0);
 890         }
 891
 892         if (icpu->disable_promotion_to_c1e)     /* each-cpu is redundant */
 893                 on_each_cpu(c1e_promotion_disable, NULL, 1);
 894
 895         return 0;
 896 }
 897
 898
 899 /*
 900  * intel_idle_cpu_init()
 901  * allocate, initialize, register cpuidle_devices
 902  * @cpu: cpu/core to initialize
 903  */
 904 static int intel_idle_cpu_init(int cpu)
 905 {
 906         struct cpuidle_device *dev;
 907
 908         dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu);
 909
 910         dev->cpu = cpu;
 911
 912         if (cpuidle_register_device(dev)) {
 913                 pr_debug(PREFIX "cpuidle_register_device %d failed!\n", cpu);
 914                 intel_idle_cpuidle_devices_uninit();
 915                 return -EIO;
 916         }
 917
 918         if (icpu->auto_demotion_disable_flags)
 919                 smp_call_function_single(cpu, auto_demotion_disable, NULL, 1);
 920
 921         if (icpu->disable_promotion_to_c1e)
 922                 smp_call_function_single(cpu, c1e_promotion_disable, NULL, 1);
 923
 924         return 0;
 925 }
 926
 927 static int __init intel_idle_init(void)
 928 {
 929         int retval, i;
 930
 931         /* Do not load intel_idle at all for now if idle= is passed */
 932         if (boot_option_idle_override != IDLE_NO_OVERRIDE)
 933                 return -ENODEV;
 934
 935         retval = intel_idle_probe();
 936         if (retval)
 937                 return retval;
 938
 939         intel_idle_cpuidle_driver_init();
 940         retval = cpuidle_register_driver(&intel_idle_driver);
 941         if (retval) {
 942                 struct cpuidle_driver *drv = cpuidle_get_driver();
 943                 printk(KERN_DEBUG PREFIX "intel_idle yielding to %s",
 944                         drv ? drv->name : "none");
 945                 return retval;
 946         }
 947
 948         intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
 949         if (intel_idle_cpuidle_devices == NULL)
 950                 return -ENOMEM;
 951
 952         cpu_notifier_register_begin();
 953
 954         for_each_online_cpu(i) {
 955                 retval = intel_idle_cpu_init(i);
 956                 if (retval) {
 957                         cpu_notifier_register_done();
 958                         cpuidle_unregister_driver(&intel_idle_driver);
 959                         return retval;
 960                 }
 961         }
 962         __register_cpu_notifier(&cpu_hotplug_notifier);
 963
 964         cpu_notifier_register_done();
 965
 966         return 0;
 967 }
 968
 969 static void __exit intel_idle_exit(void)
 970 {
 971         intel_idle_cpuidle_devices_uninit();
 972         cpuidle_unregister_driver(&intel_idle_driver);
 973
 974         cpu_notifier_register_begin();
 975
 976         if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
 977                 on_each_cpu(__setup_broadcast_timer, (void *)false, 1);
 978         __unregister_cpu_notifier(&cpu_hotplug_notifier);
 979
 980         cpu_notifier_register_done();
 981
 982         return;
 983 }
 984
 985 module_init(intel_idle_init);
 986 module_exit(intel_idle_exit);
 987
 988 module_param(max_cstate, int, 0444);
 989
 990 MODULE_AUTHOR("Len Brown <len.brown@intel.com>");
 991 MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION);
 992 MODULE_LICENSE("GPL");