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iio: mma8452: add support for runtime power management
[mirror_ubuntu-bionic-kernel.git] / drivers / iio / accel / mma8452.c
1 /*
2 * mma8452.c - Support for following Freescale 3-axis accelerometers:
3 *
4 * MMA8451Q (14 bit)
5 * MMA8452Q (12 bit)
6 * MMA8453Q (10 bit)
7 * MMA8652FC (12 bit)
8 * MMA8653FC (10 bit)
9 *
10 * Copyright 2015 Martin Kepplinger <martin.kepplinger@theobroma-systems.com>
11 * Copyright 2014 Peter Meerwald <pmeerw@pmeerw.net>
12 *
13 * This file is subject to the terms and conditions of version 2 of
14 * the GNU General Public License. See the file COPYING in the main
15 * directory of this archive for more details.
16 *
17 * 7-bit I2C slave address 0x1c/0x1d (pin selectable)
18 *
19 * TODO: orientation events, autosleep
20 */
21
22 #include <linux/module.h>
23 #include <linux/i2c.h>
24 #include <linux/iio/iio.h>
25 #include <linux/iio/sysfs.h>
26 #include <linux/iio/buffer.h>
27 #include <linux/iio/trigger.h>
28 #include <linux/iio/trigger_consumer.h>
29 #include <linux/iio/triggered_buffer.h>
30 #include <linux/iio/events.h>
31 #include <linux/delay.h>
32 #include <linux/of_device.h>
33 #include <linux/of_irq.h>
34 #include <linux/pm_runtime.h>
35
36 #define MMA8452_STATUS 0x00
37 #define MMA8452_STATUS_DRDY (BIT(2) | BIT(1) | BIT(0))
38 #define MMA8452_OUT_X 0x01 /* MSB first */
39 #define MMA8452_OUT_Y 0x03
40 #define MMA8452_OUT_Z 0x05
41 #define MMA8452_INT_SRC 0x0c
42 #define MMA8452_WHO_AM_I 0x0d
43 #define MMA8452_DATA_CFG 0x0e
44 #define MMA8452_DATA_CFG_FS_MASK GENMASK(1, 0)
45 #define MMA8452_DATA_CFG_FS_2G 0
46 #define MMA8452_DATA_CFG_FS_4G 1
47 #define MMA8452_DATA_CFG_FS_8G 2
48 #define MMA8452_DATA_CFG_HPF_MASK BIT(4)
49 #define MMA8452_HP_FILTER_CUTOFF 0x0f
50 #define MMA8452_HP_FILTER_CUTOFF_SEL_MASK GENMASK(1, 0)
51 #define MMA8452_FF_MT_CFG 0x15
52 #define MMA8452_FF_MT_CFG_OAE BIT(6)
53 #define MMA8452_FF_MT_CFG_ELE BIT(7)
54 #define MMA8452_FF_MT_SRC 0x16
55 #define MMA8452_FF_MT_SRC_XHE BIT(1)
56 #define MMA8452_FF_MT_SRC_YHE BIT(3)
57 #define MMA8452_FF_MT_SRC_ZHE BIT(5)
58 #define MMA8452_FF_MT_THS 0x17
59 #define MMA8452_FF_MT_THS_MASK 0x7f
60 #define MMA8452_FF_MT_COUNT 0x18
61 #define MMA8452_TRANSIENT_CFG 0x1d
62 #define MMA8452_TRANSIENT_CFG_HPF_BYP BIT(0)
63 #define MMA8452_TRANSIENT_CFG_ELE BIT(4)
64 #define MMA8452_TRANSIENT_SRC 0x1e
65 #define MMA8452_TRANSIENT_SRC_XTRANSE BIT(1)
66 #define MMA8452_TRANSIENT_SRC_YTRANSE BIT(3)
67 #define MMA8452_TRANSIENT_SRC_ZTRANSE BIT(5)
68 #define MMA8452_TRANSIENT_THS 0x1f
69 #define MMA8452_TRANSIENT_THS_MASK GENMASK(6, 0)
70 #define MMA8452_TRANSIENT_COUNT 0x20
71 #define MMA8452_CTRL_REG1 0x2a
72 #define MMA8452_CTRL_ACTIVE BIT(0)
73 #define MMA8452_CTRL_DR_MASK GENMASK(5, 3)
74 #define MMA8452_CTRL_DR_SHIFT 3
75 #define MMA8452_CTRL_DR_DEFAULT 0x4 /* 50 Hz sample frequency */
76 #define MMA8452_CTRL_REG2 0x2b
77 #define MMA8452_CTRL_REG2_RST BIT(6)
78 #define MMA8452_CTRL_REG4 0x2d
79 #define MMA8452_CTRL_REG5 0x2e
80 #define MMA8452_OFF_X 0x2f
81 #define MMA8452_OFF_Y 0x30
82 #define MMA8452_OFF_Z 0x31
83
84 #define MMA8452_MAX_REG 0x31
85
86 #define MMA8452_INT_DRDY BIT(0)
87 #define MMA8452_INT_FF_MT BIT(2)
88 #define MMA8452_INT_TRANS BIT(5)
89
90 #define MMA8451_DEVICE_ID 0x1a
91 #define MMA8452_DEVICE_ID 0x2a
92 #define MMA8453_DEVICE_ID 0x3a
93 #define MMA8652_DEVICE_ID 0x4a
94 #define MMA8653_DEVICE_ID 0x5a
95
96 #define MMA8452_AUTO_SUSPEND_DELAY_MS 2000
97
98 struct mma8452_data {
99 struct i2c_client *client;
100 struct mutex lock;
101 u8 ctrl_reg1;
102 u8 data_cfg;
103 const struct mma_chip_info *chip_info;
104 };
105
106 /**
107 * struct mma_chip_info - chip specific data for Freescale's accelerometers
108 * @chip_id: WHO_AM_I register's value
109 * @channels: struct iio_chan_spec matching the device's
110 * capabilities
111 * @num_channels: number of channels
112 * @mma_scales: scale factors for converting register values
113 * to m/s^2; 3 modes: 2g, 4g, 8g; 2 integers
114 * per mode: m/s^2 and micro m/s^2
115 * @ev_cfg: event config register address
116 * @ev_cfg_ele: latch bit in event config register
117 * @ev_cfg_chan_shift: number of the bit to enable events in X
118 * direction; in event config register
119 * @ev_src: event source register address
120 * @ev_src_xe: bit in event source register that indicates
121 * an event in X direction
122 * @ev_src_ye: bit in event source register that indicates
123 * an event in Y direction
124 * @ev_src_ze: bit in event source register that indicates
125 * an event in Z direction
126 * @ev_ths: event threshold register address
127 * @ev_ths_mask: mask for the threshold value
128 * @ev_count: event count (period) register address
129 *
130 * Since not all chips supported by the driver support comparing high pass
131 * filtered data for events (interrupts), different interrupt sources are
132 * used for different chips and the relevant registers are included here.
133 */
134 struct mma_chip_info {
135 u8 chip_id;
136 const struct iio_chan_spec *channels;
137 int num_channels;
138 const int mma_scales[3][2];
139 u8 ev_cfg;
140 u8 ev_cfg_ele;
141 u8 ev_cfg_chan_shift;
142 u8 ev_src;
143 u8 ev_src_xe;
144 u8 ev_src_ye;
145 u8 ev_src_ze;
146 u8 ev_ths;
147 u8 ev_ths_mask;
148 u8 ev_count;
149 };
150
151 enum {
152 idx_x,
153 idx_y,
154 idx_z,
155 idx_ts,
156 };
157
158 static int mma8452_drdy(struct mma8452_data *data)
159 {
160 int tries = 150;
161
162 while (tries-- > 0) {
163 int ret = i2c_smbus_read_byte_data(data->client,
164 MMA8452_STATUS);
165 if (ret < 0)
166 return ret;
167 if ((ret & MMA8452_STATUS_DRDY) == MMA8452_STATUS_DRDY)
168 return 0;
169
170 msleep(20);
171 }
172
173 dev_err(&data->client->dev, "data not ready\n");
174
175 return -EIO;
176 }
177
178 static int mma8452_set_runtime_pm_state(struct i2c_client *client, bool on)
179 {
180 #ifdef CONFIG_PM
181 int ret;
182
183 if (on) {
184 ret = pm_runtime_get_sync(&client->dev);
185 } else {
186 pm_runtime_mark_last_busy(&client->dev);
187 ret = pm_runtime_put_autosuspend(&client->dev);
188 }
189
190 if (ret < 0) {
191 dev_err(&client->dev,
192 "failed to change power state to %d\n", on);
193 if (on)
194 pm_runtime_put_noidle(&client->dev);
195
196 return ret;
197 }
198 #endif
199
200 return 0;
201 }
202
203 static int mma8452_read(struct mma8452_data *data, __be16 buf[3])
204 {
205 int ret = mma8452_drdy(data);
206
207 if (ret < 0)
208 return ret;
209
210 ret = mma8452_set_runtime_pm_state(data->client, true);
211 if (ret)
212 return ret;
213
214 ret = i2c_smbus_read_i2c_block_data(data->client, MMA8452_OUT_X,
215 3 * sizeof(__be16), (u8 *)buf);
216
217 ret = mma8452_set_runtime_pm_state(data->client, false);
218
219 return ret;
220 }
221
222 static ssize_t mma8452_show_int_plus_micros(char *buf, const int (*vals)[2],
223 int n)
224 {
225 size_t len = 0;
226
227 while (n-- > 0)
228 len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06d ",
229 vals[n][0], vals[n][1]);
230
231 /* replace trailing space by newline */
232 buf[len - 1] = '\n';
233
234 return len;
235 }
236
237 static int mma8452_get_int_plus_micros_index(const int (*vals)[2], int n,
238 int val, int val2)
239 {
240 while (n-- > 0)
241 if (val == vals[n][0] && val2 == vals[n][1])
242 return n;
243
244 return -EINVAL;
245 }
246
247 static int mma8452_get_odr_index(struct mma8452_data *data)
248 {
249 return (data->ctrl_reg1 & MMA8452_CTRL_DR_MASK) >>
250 MMA8452_CTRL_DR_SHIFT;
251 }
252
253 static const int mma8452_samp_freq[8][2] = {
254 {800, 0}, {400, 0}, {200, 0}, {100, 0}, {50, 0}, {12, 500000},
255 {6, 250000}, {1, 560000}
256 };
257
258 /* Datasheet table 35 (step time vs sample frequency) */
259 static const int mma8452_transient_time_step_us[8] = {
260 1250,
261 2500,
262 5000,
263 10000,
264 20000,
265 20000,
266 20000,
267 20000
268 };
269
270 /* Datasheet table 18 (normal mode) */
271 static const int mma8452_hp_filter_cutoff[8][4][2] = {
272 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 800 Hz sample */
273 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 400 Hz sample */
274 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, /* 200 Hz sample */
275 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, /* 100 Hz sample */
276 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 50 Hz sample */
277 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 12.5 Hz sample */
278 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 6.25 Hz sample */
279 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} } /* 1.56 Hz sample */
280 };
281
282 static ssize_t mma8452_show_samp_freq_avail(struct device *dev,
283 struct device_attribute *attr,
284 char *buf)
285 {
286 return mma8452_show_int_plus_micros(buf, mma8452_samp_freq,
287 ARRAY_SIZE(mma8452_samp_freq));
288 }
289
290 static ssize_t mma8452_show_scale_avail(struct device *dev,
291 struct device_attribute *attr,
292 char *buf)
293 {
294 struct mma8452_data *data = iio_priv(i2c_get_clientdata(
295 to_i2c_client(dev)));
296
297 return mma8452_show_int_plus_micros(buf, data->chip_info->mma_scales,
298 ARRAY_SIZE(data->chip_info->mma_scales));
299 }
300
301 static ssize_t mma8452_show_hp_cutoff_avail(struct device *dev,
302 struct device_attribute *attr,
303 char *buf)
304 {
305 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
306 struct mma8452_data *data = iio_priv(indio_dev);
307 int i = mma8452_get_odr_index(data);
308
309 return mma8452_show_int_plus_micros(buf, mma8452_hp_filter_cutoff[i],
310 ARRAY_SIZE(mma8452_hp_filter_cutoff[0]));
311 }
312
313 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail);
314 static IIO_DEVICE_ATTR(in_accel_scale_available, S_IRUGO,
315 mma8452_show_scale_avail, NULL, 0);
316 static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available,
317 S_IRUGO, mma8452_show_hp_cutoff_avail, NULL, 0);
318
319 static int mma8452_get_samp_freq_index(struct mma8452_data *data,
320 int val, int val2)
321 {
322 return mma8452_get_int_plus_micros_index(mma8452_samp_freq,
323 ARRAY_SIZE(mma8452_samp_freq),
324 val, val2);
325 }
326
327 static int mma8452_get_scale_index(struct mma8452_data *data, int val, int val2)
328 {
329 return mma8452_get_int_plus_micros_index(data->chip_info->mma_scales,
330 ARRAY_SIZE(data->chip_info->mma_scales), val, val2);
331 }
332
333 static int mma8452_get_hp_filter_index(struct mma8452_data *data,
334 int val, int val2)
335 {
336 int i = mma8452_get_odr_index(data);
337
338 return mma8452_get_int_plus_micros_index(mma8452_hp_filter_cutoff[i],
339 ARRAY_SIZE(mma8452_hp_filter_cutoff[0]), val, val2);
340 }
341
342 static int mma8452_read_hp_filter(struct mma8452_data *data, int *hz, int *uHz)
343 {
344 int i, ret;
345
346 ret = i2c_smbus_read_byte_data(data->client, MMA8452_HP_FILTER_CUTOFF);
347 if (ret < 0)
348 return ret;
349
350 i = mma8452_get_odr_index(data);
351 ret &= MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
352 *hz = mma8452_hp_filter_cutoff[i][ret][0];
353 *uHz = mma8452_hp_filter_cutoff[i][ret][1];
354
355 return 0;
356 }
357
358 static int mma8452_read_raw(struct iio_dev *indio_dev,
359 struct iio_chan_spec const *chan,
360 int *val, int *val2, long mask)
361 {
362 struct mma8452_data *data = iio_priv(indio_dev);
363 __be16 buffer[3];
364 int i, ret;
365
366 switch (mask) {
367 case IIO_CHAN_INFO_RAW:
368 if (iio_buffer_enabled(indio_dev))
369 return -EBUSY;
370
371 mutex_lock(&data->lock);
372 ret = mma8452_read(data, buffer);
373 mutex_unlock(&data->lock);
374 if (ret < 0)
375 return ret;
376
377 *val = sign_extend32(be16_to_cpu(
378 buffer[chan->scan_index]) >> chan->scan_type.shift,
379 chan->scan_type.realbits - 1);
380
381 return IIO_VAL_INT;
382 case IIO_CHAN_INFO_SCALE:
383 i = data->data_cfg & MMA8452_DATA_CFG_FS_MASK;
384 *val = data->chip_info->mma_scales[i][0];
385 *val2 = data->chip_info->mma_scales[i][1];
386
387 return IIO_VAL_INT_PLUS_MICRO;
388 case IIO_CHAN_INFO_SAMP_FREQ:
389 i = mma8452_get_odr_index(data);
390 *val = mma8452_samp_freq[i][0];
391 *val2 = mma8452_samp_freq[i][1];
392
393 return IIO_VAL_INT_PLUS_MICRO;
394 case IIO_CHAN_INFO_CALIBBIAS:
395 ret = i2c_smbus_read_byte_data(data->client,
396 MMA8452_OFF_X +
397 chan->scan_index);
398 if (ret < 0)
399 return ret;
400
401 *val = sign_extend32(ret, 7);
402
403 return IIO_VAL_INT;
404 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
405 if (data->data_cfg & MMA8452_DATA_CFG_HPF_MASK) {
406 ret = mma8452_read_hp_filter(data, val, val2);
407 if (ret < 0)
408 return ret;
409 } else {
410 *val = 0;
411 *val2 = 0;
412 }
413
414 return IIO_VAL_INT_PLUS_MICRO;
415 }
416
417 return -EINVAL;
418 }
419
420 static int mma8452_standby(struct mma8452_data *data)
421 {
422 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
423 data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE);
424 }
425
426 static int mma8452_active(struct mma8452_data *data)
427 {
428 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
429 data->ctrl_reg1);
430 }
431
432 /* returns >0 if active, 0 if in standby and <0 on error */
433 static int mma8452_is_active(struct mma8452_data *data)
434 {
435 int reg;
436
437 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG1);
438 if (reg < 0)
439 return reg;
440
441 return reg & MMA8452_CTRL_ACTIVE;
442 }
443
444 static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val)
445 {
446 int ret;
447 int is_active;
448
449 mutex_lock(&data->lock);
450
451 is_active = mma8452_is_active(data);
452 if (is_active < 0) {
453 ret = is_active;
454 goto fail;
455 }
456
457 /* config can only be changed when in standby */
458 if (is_active > 0) {
459 ret = mma8452_standby(data);
460 if (ret < 0)
461 goto fail;
462 }
463
464 ret = i2c_smbus_write_byte_data(data->client, reg, val);
465 if (ret < 0)
466 goto fail;
467
468 if (is_active > 0) {
469 ret = mma8452_active(data);
470 if (ret < 0)
471 goto fail;
472 }
473
474 ret = 0;
475 fail:
476 mutex_unlock(&data->lock);
477
478 return ret;
479 }
480
481 /* returns >0 if in freefall mode, 0 if not or <0 if an error occurred */
482 static int mma8452_freefall_mode_enabled(struct mma8452_data *data)
483 {
484 int val;
485 const struct mma_chip_info *chip = data->chip_info;
486
487 val = i2c_smbus_read_byte_data(data->client, chip->ev_cfg);
488 if (val < 0)
489 return val;
490
491 return !(val & MMA8452_FF_MT_CFG_OAE);
492 }
493
494 static int mma8452_set_freefall_mode(struct mma8452_data *data, bool state)
495 {
496 int val;
497 const struct mma_chip_info *chip = data->chip_info;
498
499 if ((state && mma8452_freefall_mode_enabled(data)) ||
500 (!state && !(mma8452_freefall_mode_enabled(data))))
501 return 0;
502
503 val = i2c_smbus_read_byte_data(data->client, chip->ev_cfg);
504 if (val < 0)
505 return val;
506
507 if (state) {
508 val |= BIT(idx_x + chip->ev_cfg_chan_shift);
509 val |= BIT(idx_y + chip->ev_cfg_chan_shift);
510 val |= BIT(idx_z + chip->ev_cfg_chan_shift);
511 val &= ~MMA8452_FF_MT_CFG_OAE;
512 } else {
513 val &= ~BIT(idx_x + chip->ev_cfg_chan_shift);
514 val &= ~BIT(idx_y + chip->ev_cfg_chan_shift);
515 val &= ~BIT(idx_z + chip->ev_cfg_chan_shift);
516 val |= MMA8452_FF_MT_CFG_OAE;
517 }
518
519 val = mma8452_change_config(data, chip->ev_cfg, val);
520 if (val)
521 return val;
522
523 return 0;
524 }
525
526 static int mma8452_set_hp_filter_frequency(struct mma8452_data *data,
527 int val, int val2)
528 {
529 int i, reg;
530
531 i = mma8452_get_hp_filter_index(data, val, val2);
532 if (i < 0)
533 return i;
534
535 reg = i2c_smbus_read_byte_data(data->client,
536 MMA8452_HP_FILTER_CUTOFF);
537 if (reg < 0)
538 return reg;
539
540 reg &= ~MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
541 reg |= i;
542
543 return mma8452_change_config(data, MMA8452_HP_FILTER_CUTOFF, reg);
544 }
545
546 static int mma8452_write_raw(struct iio_dev *indio_dev,
547 struct iio_chan_spec const *chan,
548 int val, int val2, long mask)
549 {
550 struct mma8452_data *data = iio_priv(indio_dev);
551 int i, ret;
552
553 if (iio_buffer_enabled(indio_dev))
554 return -EBUSY;
555
556 switch (mask) {
557 case IIO_CHAN_INFO_SAMP_FREQ:
558 i = mma8452_get_samp_freq_index(data, val, val2);
559 if (i < 0)
560 return i;
561
562 data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK;
563 data->ctrl_reg1 |= i << MMA8452_CTRL_DR_SHIFT;
564
565 return mma8452_change_config(data, MMA8452_CTRL_REG1,
566 data->ctrl_reg1);
567 case IIO_CHAN_INFO_SCALE:
568 i = mma8452_get_scale_index(data, val, val2);
569 if (i < 0)
570 return i;
571
572 data->data_cfg &= ~MMA8452_DATA_CFG_FS_MASK;
573 data->data_cfg |= i;
574
575 return mma8452_change_config(data, MMA8452_DATA_CFG,
576 data->data_cfg);
577 case IIO_CHAN_INFO_CALIBBIAS:
578 if (val < -128 || val > 127)
579 return -EINVAL;
580
581 return mma8452_change_config(data,
582 MMA8452_OFF_X + chan->scan_index,
583 val);
584
585 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
586 if (val == 0 && val2 == 0) {
587 data->data_cfg &= ~MMA8452_DATA_CFG_HPF_MASK;
588 } else {
589 data->data_cfg |= MMA8452_DATA_CFG_HPF_MASK;
590 ret = mma8452_set_hp_filter_frequency(data, val, val2);
591 if (ret < 0)
592 return ret;
593 }
594
595 return mma8452_change_config(data, MMA8452_DATA_CFG,
596 data->data_cfg);
597
598 default:
599 return -EINVAL;
600 }
601 }
602
603 static int mma8452_read_thresh(struct iio_dev *indio_dev,
604 const struct iio_chan_spec *chan,
605 enum iio_event_type type,
606 enum iio_event_direction dir,
607 enum iio_event_info info,
608 int *val, int *val2)
609 {
610 struct mma8452_data *data = iio_priv(indio_dev);
611 int ret, us;
612
613 switch (info) {
614 case IIO_EV_INFO_VALUE:
615 ret = i2c_smbus_read_byte_data(data->client,
616 data->chip_info->ev_ths);
617 if (ret < 0)
618 return ret;
619
620 *val = ret & data->chip_info->ev_ths_mask;
621
622 return IIO_VAL_INT;
623
624 case IIO_EV_INFO_PERIOD:
625 ret = i2c_smbus_read_byte_data(data->client,
626 data->chip_info->ev_count);
627 if (ret < 0)
628 return ret;
629
630 us = ret * mma8452_transient_time_step_us[
631 mma8452_get_odr_index(data)];
632 *val = us / USEC_PER_SEC;
633 *val2 = us % USEC_PER_SEC;
634
635 return IIO_VAL_INT_PLUS_MICRO;
636
637 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
638 ret = i2c_smbus_read_byte_data(data->client,
639 MMA8452_TRANSIENT_CFG);
640 if (ret < 0)
641 return ret;
642
643 if (ret & MMA8452_TRANSIENT_CFG_HPF_BYP) {
644 *val = 0;
645 *val2 = 0;
646 } else {
647 ret = mma8452_read_hp_filter(data, val, val2);
648 if (ret < 0)
649 return ret;
650 }
651
652 return IIO_VAL_INT_PLUS_MICRO;
653
654 default:
655 return -EINVAL;
656 }
657 }
658
659 static int mma8452_write_thresh(struct iio_dev *indio_dev,
660 const struct iio_chan_spec *chan,
661 enum iio_event_type type,
662 enum iio_event_direction dir,
663 enum iio_event_info info,
664 int val, int val2)
665 {
666 struct mma8452_data *data = iio_priv(indio_dev);
667 int ret, reg, steps;
668
669 switch (info) {
670 case IIO_EV_INFO_VALUE:
671 if (val < 0 || val > MMA8452_TRANSIENT_THS_MASK)
672 return -EINVAL;
673
674 return mma8452_change_config(data, data->chip_info->ev_ths,
675 val);
676
677 case IIO_EV_INFO_PERIOD:
678 steps = (val * USEC_PER_SEC + val2) /
679 mma8452_transient_time_step_us[
680 mma8452_get_odr_index(data)];
681
682 if (steps < 0 || steps > 0xff)
683 return -EINVAL;
684
685 return mma8452_change_config(data, data->chip_info->ev_count,
686 steps);
687
688 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
689 reg = i2c_smbus_read_byte_data(data->client,
690 MMA8452_TRANSIENT_CFG);
691 if (reg < 0)
692 return reg;
693
694 if (val == 0 && val2 == 0) {
695 reg |= MMA8452_TRANSIENT_CFG_HPF_BYP;
696 } else {
697 reg &= ~MMA8452_TRANSIENT_CFG_HPF_BYP;
698 ret = mma8452_set_hp_filter_frequency(data, val, val2);
699 if (ret < 0)
700 return ret;
701 }
702
703 return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, reg);
704
705 default:
706 return -EINVAL;
707 }
708 }
709
710 static int mma8452_read_event_config(struct iio_dev *indio_dev,
711 const struct iio_chan_spec *chan,
712 enum iio_event_type type,
713 enum iio_event_direction dir)
714 {
715 struct mma8452_data *data = iio_priv(indio_dev);
716 const struct mma_chip_info *chip = data->chip_info;
717 int ret;
718
719 switch (dir) {
720 case IIO_EV_DIR_FALLING:
721 return mma8452_freefall_mode_enabled(data);
722 case IIO_EV_DIR_RISING:
723 if (mma8452_freefall_mode_enabled(data))
724 return 0;
725
726 ret = i2c_smbus_read_byte_data(data->client,
727 data->chip_info->ev_cfg);
728 if (ret < 0)
729 return ret;
730
731 return !!(ret & BIT(chan->scan_index +
732 chip->ev_cfg_chan_shift));
733 default:
734 return -EINVAL;
735 }
736 }
737
738 static int mma8452_write_event_config(struct iio_dev *indio_dev,
739 const struct iio_chan_spec *chan,
740 enum iio_event_type type,
741 enum iio_event_direction dir,
742 int state)
743 {
744 struct mma8452_data *data = iio_priv(indio_dev);
745 const struct mma_chip_info *chip = data->chip_info;
746 int val, ret;
747
748 ret = mma8452_set_runtime_pm_state(data->client, state);
749 if (ret)
750 return ret;
751
752 switch (dir) {
753 case IIO_EV_DIR_FALLING:
754 return mma8452_set_freefall_mode(data, state);
755 case IIO_EV_DIR_RISING:
756 val = i2c_smbus_read_byte_data(data->client, chip->ev_cfg);
757 if (val < 0)
758 return val;
759
760 if (state) {
761 if (mma8452_freefall_mode_enabled(data)) {
762 val &= ~BIT(idx_x + chip->ev_cfg_chan_shift);
763 val &= ~BIT(idx_y + chip->ev_cfg_chan_shift);
764 val &= ~BIT(idx_z + chip->ev_cfg_chan_shift);
765 val |= MMA8452_FF_MT_CFG_OAE;
766 }
767 val |= BIT(chan->scan_index + chip->ev_cfg_chan_shift);
768 } else {
769 if (mma8452_freefall_mode_enabled(data))
770 return 0;
771
772 val &= ~BIT(chan->scan_index + chip->ev_cfg_chan_shift);
773 }
774
775 val |= chip->ev_cfg_ele;
776
777 return mma8452_change_config(data, chip->ev_cfg, val);
778 default:
779 return -EINVAL;
780 }
781 }
782
783 static void mma8452_transient_interrupt(struct iio_dev *indio_dev)
784 {
785 struct mma8452_data *data = iio_priv(indio_dev);
786 s64 ts = iio_get_time_ns();
787 int src;
788
789 src = i2c_smbus_read_byte_data(data->client, data->chip_info->ev_src);
790 if (src < 0)
791 return;
792
793 if (mma8452_freefall_mode_enabled(data)) {
794 iio_push_event(indio_dev,
795 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0,
796 IIO_MOD_X_AND_Y_AND_Z,
797 IIO_EV_TYPE_MAG,
798 IIO_EV_DIR_FALLING),
799 ts);
800 return;
801 }
802
803 if (src & data->chip_info->ev_src_xe)
804 iio_push_event(indio_dev,
805 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X,
806 IIO_EV_TYPE_MAG,
807 IIO_EV_DIR_RISING),
808 ts);
809
810 if (src & data->chip_info->ev_src_ye)
811 iio_push_event(indio_dev,
812 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y,
813 IIO_EV_TYPE_MAG,
814 IIO_EV_DIR_RISING),
815 ts);
816
817 if (src & data->chip_info->ev_src_ze)
818 iio_push_event(indio_dev,
819 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z,
820 IIO_EV_TYPE_MAG,
821 IIO_EV_DIR_RISING),
822 ts);
823 }
824
825 static irqreturn_t mma8452_interrupt(int irq, void *p)
826 {
827 struct iio_dev *indio_dev = p;
828 struct mma8452_data *data = iio_priv(indio_dev);
829 const struct mma_chip_info *chip = data->chip_info;
830 int ret = IRQ_NONE;
831 int src;
832
833 src = i2c_smbus_read_byte_data(data->client, MMA8452_INT_SRC);
834 if (src < 0)
835 return IRQ_NONE;
836
837 if (src & MMA8452_INT_DRDY) {
838 iio_trigger_poll_chained(indio_dev->trig);
839 ret = IRQ_HANDLED;
840 }
841
842 if ((src & MMA8452_INT_TRANS &&
843 chip->ev_src == MMA8452_TRANSIENT_SRC) ||
844 (src & MMA8452_INT_FF_MT &&
845 chip->ev_src == MMA8452_FF_MT_SRC)) {
846 mma8452_transient_interrupt(indio_dev);
847 ret = IRQ_HANDLED;
848 }
849
850 return ret;
851 }
852
853 static irqreturn_t mma8452_trigger_handler(int irq, void *p)
854 {
855 struct iio_poll_func *pf = p;
856 struct iio_dev *indio_dev = pf->indio_dev;
857 struct mma8452_data *data = iio_priv(indio_dev);
858 u8 buffer[16]; /* 3 16-bit channels + padding + ts */
859 int ret;
860
861 ret = mma8452_read(data, (__be16 *)buffer);
862 if (ret < 0)
863 goto done;
864
865 iio_push_to_buffers_with_timestamp(indio_dev, buffer,
866 iio_get_time_ns());
867
868 done:
869 iio_trigger_notify_done(indio_dev->trig);
870
871 return IRQ_HANDLED;
872 }
873
874 static int mma8452_reg_access_dbg(struct iio_dev *indio_dev,
875 unsigned reg, unsigned writeval,
876 unsigned *readval)
877 {
878 int ret;
879 struct mma8452_data *data = iio_priv(indio_dev);
880
881 if (reg > MMA8452_MAX_REG)
882 return -EINVAL;
883
884 if (!readval)
885 return mma8452_change_config(data, reg, writeval);
886
887 ret = i2c_smbus_read_byte_data(data->client, reg);
888 if (ret < 0)
889 return ret;
890
891 *readval = ret;
892
893 return 0;
894 }
895
896 static const struct iio_event_spec mma8452_freefall_event[] = {
897 {
898 .type = IIO_EV_TYPE_MAG,
899 .dir = IIO_EV_DIR_FALLING,
900 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
901 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
902 BIT(IIO_EV_INFO_PERIOD) |
903 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
904 },
905 };
906
907 static const struct iio_event_spec mma8652_freefall_event[] = {
908 {
909 .type = IIO_EV_TYPE_MAG,
910 .dir = IIO_EV_DIR_FALLING,
911 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
912 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
913 BIT(IIO_EV_INFO_PERIOD)
914 },
915 };
916
917 static const struct iio_event_spec mma8452_transient_event[] = {
918 {
919 .type = IIO_EV_TYPE_MAG,
920 .dir = IIO_EV_DIR_RISING,
921 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
922 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
923 BIT(IIO_EV_INFO_PERIOD) |
924 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
925 },
926 };
927
928 static const struct iio_event_spec mma8452_motion_event[] = {
929 {
930 .type = IIO_EV_TYPE_MAG,
931 .dir = IIO_EV_DIR_RISING,
932 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
933 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
934 BIT(IIO_EV_INFO_PERIOD)
935 },
936 };
937
938 /*
939 * Threshold is configured in fixed 8G/127 steps regardless of
940 * currently selected scale for measurement.
941 */
942 static IIO_CONST_ATTR_NAMED(accel_transient_scale, in_accel_scale, "0.617742");
943
944 static struct attribute *mma8452_event_attributes[] = {
945 &iio_const_attr_accel_transient_scale.dev_attr.attr,
946 NULL,
947 };
948
949 static struct attribute_group mma8452_event_attribute_group = {
950 .attrs = mma8452_event_attributes,
951 };
952
953 #define MMA8452_FREEFALL_CHANNEL(modifier) { \
954 .type = IIO_ACCEL, \
955 .modified = 1, \
956 .channel2 = modifier, \
957 .scan_index = -1, \
958 .event_spec = mma8452_freefall_event, \
959 .num_event_specs = ARRAY_SIZE(mma8452_freefall_event), \
960 }
961
962 #define MMA8652_FREEFALL_CHANNEL(modifier) { \
963 .type = IIO_ACCEL, \
964 .modified = 1, \
965 .channel2 = modifier, \
966 .scan_index = -1, \
967 .event_spec = mma8652_freefall_event, \
968 .num_event_specs = ARRAY_SIZE(mma8652_freefall_event), \
969 }
970
971 #define MMA8452_CHANNEL(axis, idx, bits) { \
972 .type = IIO_ACCEL, \
973 .modified = 1, \
974 .channel2 = IIO_MOD_##axis, \
975 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
976 BIT(IIO_CHAN_INFO_CALIBBIAS), \
977 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
978 BIT(IIO_CHAN_INFO_SCALE) | \
979 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY), \
980 .scan_index = idx, \
981 .scan_type = { \
982 .sign = 's', \
983 .realbits = (bits), \
984 .storagebits = 16, \
985 .shift = 16 - (bits), \
986 .endianness = IIO_BE, \
987 }, \
988 .event_spec = mma8452_transient_event, \
989 .num_event_specs = ARRAY_SIZE(mma8452_transient_event), \
990 }
991
992 #define MMA8652_CHANNEL(axis, idx, bits) { \
993 .type = IIO_ACCEL, \
994 .modified = 1, \
995 .channel2 = IIO_MOD_##axis, \
996 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
997 BIT(IIO_CHAN_INFO_CALIBBIAS), \
998 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
999 BIT(IIO_CHAN_INFO_SCALE), \
1000 .scan_index = idx, \
1001 .scan_type = { \
1002 .sign = 's', \
1003 .realbits = (bits), \
1004 .storagebits = 16, \
1005 .shift = 16 - (bits), \
1006 .endianness = IIO_BE, \
1007 }, \
1008 .event_spec = mma8452_motion_event, \
1009 .num_event_specs = ARRAY_SIZE(mma8452_motion_event), \
1010 }
1011
1012 static const struct iio_chan_spec mma8451_channels[] = {
1013 MMA8452_CHANNEL(X, idx_x, 14),
1014 MMA8452_CHANNEL(Y, idx_y, 14),
1015 MMA8452_CHANNEL(Z, idx_z, 14),
1016 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1017 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1018 };
1019
1020 static const struct iio_chan_spec mma8452_channels[] = {
1021 MMA8452_CHANNEL(X, idx_x, 12),
1022 MMA8452_CHANNEL(Y, idx_y, 12),
1023 MMA8452_CHANNEL(Z, idx_z, 12),
1024 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1025 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1026 };
1027
1028 static const struct iio_chan_spec mma8453_channels[] = {
1029 MMA8452_CHANNEL(X, idx_x, 10),
1030 MMA8452_CHANNEL(Y, idx_y, 10),
1031 MMA8452_CHANNEL(Z, idx_z, 10),
1032 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1033 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1034 };
1035
1036 static const struct iio_chan_spec mma8652_channels[] = {
1037 MMA8652_CHANNEL(X, idx_x, 12),
1038 MMA8652_CHANNEL(Y, idx_y, 12),
1039 MMA8652_CHANNEL(Z, idx_z, 12),
1040 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1041 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1042 };
1043
1044 static const struct iio_chan_spec mma8653_channels[] = {
1045 MMA8652_CHANNEL(X, idx_x, 10),
1046 MMA8652_CHANNEL(Y, idx_y, 10),
1047 MMA8652_CHANNEL(Z, idx_z, 10),
1048 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1049 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1050 };
1051
1052 enum {
1053 mma8451,
1054 mma8452,
1055 mma8453,
1056 mma8652,
1057 mma8653,
1058 };
1059
1060 static const struct mma_chip_info mma_chip_info_table[] = {
1061 [mma8451] = {
1062 .chip_id = MMA8451_DEVICE_ID,
1063 .channels = mma8451_channels,
1064 .num_channels = ARRAY_SIZE(mma8451_channels),
1065 /*
1066 * Hardware has fullscale of -2G, -4G, -8G corresponding to
1067 * raw value -8192 for 14 bit, -2048 for 12 bit or -512 for 10
1068 * bit.
1069 * The userspace interface uses m/s^2 and we declare micro units
1070 * So scale factor for 12 bit here is given by:
1071 * g * N * 1000000 / 2048 for N = 2, 4, 8 and g=9.80665
1072 */
1073 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} },
1074 .ev_cfg = MMA8452_TRANSIENT_CFG,
1075 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
1076 .ev_cfg_chan_shift = 1,
1077 .ev_src = MMA8452_TRANSIENT_SRC,
1078 .ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE,
1079 .ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE,
1080 .ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE,
1081 .ev_ths = MMA8452_TRANSIENT_THS,
1082 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
1083 .ev_count = MMA8452_TRANSIENT_COUNT,
1084 },
1085 [mma8452] = {
1086 .chip_id = MMA8452_DEVICE_ID,
1087 .channels = mma8452_channels,
1088 .num_channels = ARRAY_SIZE(mma8452_channels),
1089 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
1090 .ev_cfg = MMA8452_TRANSIENT_CFG,
1091 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
1092 .ev_cfg_chan_shift = 1,
1093 .ev_src = MMA8452_TRANSIENT_SRC,
1094 .ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE,
1095 .ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE,
1096 .ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE,
1097 .ev_ths = MMA8452_TRANSIENT_THS,
1098 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
1099 .ev_count = MMA8452_TRANSIENT_COUNT,
1100 },
1101 [mma8453] = {
1102 .chip_id = MMA8453_DEVICE_ID,
1103 .channels = mma8453_channels,
1104 .num_channels = ARRAY_SIZE(mma8453_channels),
1105 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
1106 .ev_cfg = MMA8452_TRANSIENT_CFG,
1107 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
1108 .ev_cfg_chan_shift = 1,
1109 .ev_src = MMA8452_TRANSIENT_SRC,
1110 .ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE,
1111 .ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE,
1112 .ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE,
1113 .ev_ths = MMA8452_TRANSIENT_THS,
1114 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
1115 .ev_count = MMA8452_TRANSIENT_COUNT,
1116 },
1117 [mma8652] = {
1118 .chip_id = MMA8652_DEVICE_ID,
1119 .channels = mma8652_channels,
1120 .num_channels = ARRAY_SIZE(mma8652_channels),
1121 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
1122 .ev_cfg = MMA8452_FF_MT_CFG,
1123 .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE,
1124 .ev_cfg_chan_shift = 3,
1125 .ev_src = MMA8452_FF_MT_SRC,
1126 .ev_src_xe = MMA8452_FF_MT_SRC_XHE,
1127 .ev_src_ye = MMA8452_FF_MT_SRC_YHE,
1128 .ev_src_ze = MMA8452_FF_MT_SRC_ZHE,
1129 .ev_ths = MMA8452_FF_MT_THS,
1130 .ev_ths_mask = MMA8452_FF_MT_THS_MASK,
1131 .ev_count = MMA8452_FF_MT_COUNT,
1132 },
1133 [mma8653] = {
1134 .chip_id = MMA8653_DEVICE_ID,
1135 .channels = mma8653_channels,
1136 .num_channels = ARRAY_SIZE(mma8653_channels),
1137 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
1138 .ev_cfg = MMA8452_FF_MT_CFG,
1139 .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE,
1140 .ev_cfg_chan_shift = 3,
1141 .ev_src = MMA8452_FF_MT_SRC,
1142 .ev_src_xe = MMA8452_FF_MT_SRC_XHE,
1143 .ev_src_ye = MMA8452_FF_MT_SRC_YHE,
1144 .ev_src_ze = MMA8452_FF_MT_SRC_ZHE,
1145 .ev_ths = MMA8452_FF_MT_THS,
1146 .ev_ths_mask = MMA8452_FF_MT_THS_MASK,
1147 .ev_count = MMA8452_FF_MT_COUNT,
1148 },
1149 };
1150
1151 static struct attribute *mma8452_attributes[] = {
1152 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
1153 &iio_dev_attr_in_accel_scale_available.dev_attr.attr,
1154 &iio_dev_attr_in_accel_filter_high_pass_3db_frequency_available.dev_attr.attr,
1155 NULL
1156 };
1157
1158 static const struct attribute_group mma8452_group = {
1159 .attrs = mma8452_attributes,
1160 };
1161
1162 static const struct iio_info mma8452_info = {
1163 .attrs = &mma8452_group,
1164 .read_raw = &mma8452_read_raw,
1165 .write_raw = &mma8452_write_raw,
1166 .event_attrs = &mma8452_event_attribute_group,
1167 .read_event_value = &mma8452_read_thresh,
1168 .write_event_value = &mma8452_write_thresh,
1169 .read_event_config = &mma8452_read_event_config,
1170 .write_event_config = &mma8452_write_event_config,
1171 .debugfs_reg_access = &mma8452_reg_access_dbg,
1172 .driver_module = THIS_MODULE,
1173 };
1174
1175 static const unsigned long mma8452_scan_masks[] = {0x7, 0};
1176
1177 static int mma8452_data_rdy_trigger_set_state(struct iio_trigger *trig,
1178 bool state)
1179 {
1180 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
1181 struct mma8452_data *data = iio_priv(indio_dev);
1182 int reg, ret;
1183
1184 ret = mma8452_set_runtime_pm_state(data->client, state);
1185 if (ret)
1186 return ret;
1187
1188 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG4);
1189 if (reg < 0)
1190 return reg;
1191
1192 if (state)
1193 reg |= MMA8452_INT_DRDY;
1194 else
1195 reg &= ~MMA8452_INT_DRDY;
1196
1197 return mma8452_change_config(data, MMA8452_CTRL_REG4, reg);
1198 }
1199
1200 static int mma8452_validate_device(struct iio_trigger *trig,
1201 struct iio_dev *indio_dev)
1202 {
1203 struct iio_dev *indio = iio_trigger_get_drvdata(trig);
1204
1205 if (indio != indio_dev)
1206 return -EINVAL;
1207
1208 return 0;
1209 }
1210
1211 static const struct iio_trigger_ops mma8452_trigger_ops = {
1212 .set_trigger_state = mma8452_data_rdy_trigger_set_state,
1213 .validate_device = mma8452_validate_device,
1214 .owner = THIS_MODULE,
1215 };
1216
1217 static int mma8452_trigger_setup(struct iio_dev *indio_dev)
1218 {
1219 struct mma8452_data *data = iio_priv(indio_dev);
1220 struct iio_trigger *trig;
1221 int ret;
1222
1223 trig = devm_iio_trigger_alloc(&data->client->dev, "%s-dev%d",
1224 indio_dev->name,
1225 indio_dev->id);
1226 if (!trig)
1227 return -ENOMEM;
1228
1229 trig->dev.parent = &data->client->dev;
1230 trig->ops = &mma8452_trigger_ops;
1231 iio_trigger_set_drvdata(trig, indio_dev);
1232
1233 ret = iio_trigger_register(trig);
1234 if (ret)
1235 return ret;
1236
1237 indio_dev->trig = trig;
1238
1239 return 0;
1240 }
1241
1242 static void mma8452_trigger_cleanup(struct iio_dev *indio_dev)
1243 {
1244 if (indio_dev->trig)
1245 iio_trigger_unregister(indio_dev->trig);
1246 }
1247
1248 static int mma8452_reset(struct i2c_client *client)
1249 {
1250 int i;
1251 int ret;
1252
1253 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG2,
1254 MMA8452_CTRL_REG2_RST);
1255 if (ret < 0)
1256 return ret;
1257
1258 for (i = 0; i < 10; i++) {
1259 usleep_range(100, 200);
1260 ret = i2c_smbus_read_byte_data(client, MMA8452_CTRL_REG2);
1261 if (ret == -EIO)
1262 continue; /* I2C comm reset */
1263 if (ret < 0)
1264 return ret;
1265 if (!(ret & MMA8452_CTRL_REG2_RST))
1266 return 0;
1267 }
1268
1269 return -ETIMEDOUT;
1270 }
1271
1272 static const struct of_device_id mma8452_dt_ids[] = {
1273 { .compatible = "fsl,mma8451", .data = &mma_chip_info_table[mma8451] },
1274 { .compatible = "fsl,mma8452", .data = &mma_chip_info_table[mma8452] },
1275 { .compatible = "fsl,mma8453", .data = &mma_chip_info_table[mma8453] },
1276 { .compatible = "fsl,mma8652", .data = &mma_chip_info_table[mma8652] },
1277 { .compatible = "fsl,mma8653", .data = &mma_chip_info_table[mma8653] },
1278 { }
1279 };
1280 MODULE_DEVICE_TABLE(of, mma8452_dt_ids);
1281
1282 static int mma8452_probe(struct i2c_client *client,
1283 const struct i2c_device_id *id)
1284 {
1285 struct mma8452_data *data;
1286 struct iio_dev *indio_dev;
1287 int ret;
1288 const struct of_device_id *match;
1289
1290 match = of_match_device(mma8452_dt_ids, &client->dev);
1291 if (!match) {
1292 dev_err(&client->dev, "unknown device model\n");
1293 return -ENODEV;
1294 }
1295
1296 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
1297 if (!indio_dev)
1298 return -ENOMEM;
1299
1300 data = iio_priv(indio_dev);
1301 data->client = client;
1302 mutex_init(&data->lock);
1303 data->chip_info = match->data;
1304
1305 ret = i2c_smbus_read_byte_data(client, MMA8452_WHO_AM_I);
1306 if (ret < 0)
1307 return ret;
1308
1309 switch (ret) {
1310 case MMA8451_DEVICE_ID:
1311 case MMA8452_DEVICE_ID:
1312 case MMA8453_DEVICE_ID:
1313 case MMA8652_DEVICE_ID:
1314 case MMA8653_DEVICE_ID:
1315 if (ret == data->chip_info->chip_id)
1316 break;
1317 default:
1318 return -ENODEV;
1319 }
1320
1321 dev_info(&client->dev, "registering %s accelerometer; ID 0x%x\n",
1322 match->compatible, data->chip_info->chip_id);
1323
1324 i2c_set_clientdata(client, indio_dev);
1325 indio_dev->info = &mma8452_info;
1326 indio_dev->name = id->name;
1327 indio_dev->dev.parent = &client->dev;
1328 indio_dev->modes = INDIO_DIRECT_MODE;
1329 indio_dev->channels = data->chip_info->channels;
1330 indio_dev->num_channels = data->chip_info->num_channels;
1331 indio_dev->available_scan_masks = mma8452_scan_masks;
1332
1333 ret = mma8452_reset(client);
1334 if (ret < 0)
1335 return ret;
1336
1337 data->data_cfg = MMA8452_DATA_CFG_FS_2G;
1338 ret = i2c_smbus_write_byte_data(client, MMA8452_DATA_CFG,
1339 data->data_cfg);
1340 if (ret < 0)
1341 return ret;
1342
1343 /*
1344 * By default set transient threshold to max to avoid events if
1345 * enabling without configuring threshold.
1346 */
1347 ret = i2c_smbus_write_byte_data(client, MMA8452_TRANSIENT_THS,
1348 MMA8452_TRANSIENT_THS_MASK);
1349 if (ret < 0)
1350 return ret;
1351
1352 if (client->irq) {
1353 /*
1354 * Although we enable the interrupt sources once and for
1355 * all here the event detection itself is not enabled until
1356 * userspace asks for it by mma8452_write_event_config()
1357 */
1358 int supported_interrupts = MMA8452_INT_DRDY |
1359 MMA8452_INT_TRANS |
1360 MMA8452_INT_FF_MT;
1361 int enabled_interrupts = MMA8452_INT_TRANS |
1362 MMA8452_INT_FF_MT;
1363 int irq2;
1364
1365 irq2 = of_irq_get_byname(client->dev.of_node, "INT2");
1366
1367 if (irq2 == client->irq) {
1368 dev_dbg(&client->dev, "using interrupt line INT2\n");
1369 } else {
1370 ret = i2c_smbus_write_byte_data(client,
1371 MMA8452_CTRL_REG5,
1372 supported_interrupts);
1373 if (ret < 0)
1374 return ret;
1375
1376 dev_dbg(&client->dev, "using interrupt line INT1\n");
1377 }
1378
1379 ret = i2c_smbus_write_byte_data(client,
1380 MMA8452_CTRL_REG4,
1381 enabled_interrupts);
1382 if (ret < 0)
1383 return ret;
1384
1385 ret = mma8452_trigger_setup(indio_dev);
1386 if (ret < 0)
1387 return ret;
1388 }
1389
1390 data->ctrl_reg1 = MMA8452_CTRL_ACTIVE |
1391 (MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT);
1392 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG1,
1393 data->ctrl_reg1);
1394 if (ret < 0)
1395 goto trigger_cleanup;
1396
1397 ret = iio_triggered_buffer_setup(indio_dev, NULL,
1398 mma8452_trigger_handler, NULL);
1399 if (ret < 0)
1400 goto trigger_cleanup;
1401
1402 if (client->irq) {
1403 ret = devm_request_threaded_irq(&client->dev,
1404 client->irq,
1405 NULL, mma8452_interrupt,
1406 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1407 client->name, indio_dev);
1408 if (ret)
1409 goto buffer_cleanup;
1410 }
1411
1412 ret = pm_runtime_set_active(&client->dev);
1413 if (ret < 0)
1414 goto buffer_cleanup;
1415
1416 pm_runtime_enable(&client->dev);
1417 pm_runtime_set_autosuspend_delay(&client->dev,
1418 MMA8452_AUTO_SUSPEND_DELAY_MS);
1419 pm_runtime_use_autosuspend(&client->dev);
1420
1421 ret = iio_device_register(indio_dev);
1422 if (ret < 0)
1423 goto buffer_cleanup;
1424
1425 ret = mma8452_set_freefall_mode(data, false);
1426 if (ret)
1427 return ret;
1428
1429 return 0;
1430
1431 buffer_cleanup:
1432 iio_triggered_buffer_cleanup(indio_dev);
1433
1434 trigger_cleanup:
1435 mma8452_trigger_cleanup(indio_dev);
1436
1437 return ret;
1438 }
1439
1440 static int mma8452_remove(struct i2c_client *client)
1441 {
1442 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1443
1444 iio_device_unregister(indio_dev);
1445
1446 pm_runtime_disable(&client->dev);
1447 pm_runtime_set_suspended(&client->dev);
1448 pm_runtime_put_noidle(&client->dev);
1449
1450 iio_triggered_buffer_cleanup(indio_dev);
1451 mma8452_trigger_cleanup(indio_dev);
1452 mma8452_standby(iio_priv(indio_dev));
1453
1454 return 0;
1455 }
1456
1457 #ifdef CONFIG_PM
1458 static int mma8452_runtime_suspend(struct device *dev)
1459 {
1460 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1461 struct mma8452_data *data = iio_priv(indio_dev);
1462 int ret;
1463
1464 mutex_lock(&data->lock);
1465 ret = mma8452_standby(data);
1466 mutex_unlock(&data->lock);
1467 if (ret < 0) {
1468 dev_err(&data->client->dev, "powering off device failed\n");
1469 return -EAGAIN;
1470 }
1471
1472 return 0;
1473 }
1474
1475 static int mma8452_runtime_resume(struct device *dev)
1476 {
1477 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1478 struct mma8452_data *data = iio_priv(indio_dev);
1479 int ret, sleep_val;
1480
1481 ret = mma8452_active(data);
1482 if (ret < 0)
1483 return ret;
1484
1485 ret = mma8452_get_odr_index(data);
1486 sleep_val = 1000 / mma8452_samp_freq[ret][0];
1487 if (sleep_val < 20)
1488 usleep_range(sleep_val * 1000, 20000);
1489 else
1490 msleep_interruptible(sleep_val);
1491
1492 return 0;
1493 }
1494 #endif
1495
1496 #ifdef CONFIG_PM_SLEEP
1497 static int mma8452_suspend(struct device *dev)
1498 {
1499 return mma8452_standby(iio_priv(i2c_get_clientdata(
1500 to_i2c_client(dev))));
1501 }
1502
1503 static int mma8452_resume(struct device *dev)
1504 {
1505 return mma8452_active(iio_priv(i2c_get_clientdata(
1506 to_i2c_client(dev))));
1507 }
1508 #endif
1509
1510 static const struct dev_pm_ops mma8452_pm_ops = {
1511 SET_SYSTEM_SLEEP_PM_OPS(mma8452_suspend, mma8452_resume)
1512 SET_RUNTIME_PM_OPS(mma8452_runtime_suspend,
1513 mma8452_runtime_resume, NULL)
1514 };
1515
1516 static const struct i2c_device_id mma8452_id[] = {
1517 { "mma8452", mma8452 },
1518 { "mma8453", mma8453 },
1519 { "mma8652", mma8652 },
1520 { "mma8653", mma8653 },
1521 { }
1522 };
1523 MODULE_DEVICE_TABLE(i2c, mma8452_id);
1524
1525 static struct i2c_driver mma8452_driver = {
1526 .driver = {
1527 .name = "mma8452",
1528 .of_match_table = of_match_ptr(mma8452_dt_ids),
1529 .pm = &mma8452_pm_ops,
1530 },
1531 .probe = mma8452_probe,
1532 .remove = mma8452_remove,
1533 .id_table = mma8452_id,
1534 };
1535 module_i2c_driver(mma8452_driver);
1536
1537 MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>");
1538 MODULE_DESCRIPTION("Freescale MMA8452 accelerometer driver");
1539 MODULE_LICENSE("GPL");
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