2 * mma8452.c - Support for Freescale MMA8452Q 3-axis 12-bit accelerometer
4 * Copyright 2014 Peter Meerwald <pmeerw@pmeerw.net>
6 * This file is subject to the terms and conditions of version 2 of
7 * the GNU General Public License. See the file COPYING in the main
8 * directory of this archive for more details.
10 * 7-bit I2C slave address 0x1c/0x1d (pin selectable)
12 * TODO: orientation / freefall events, autosleep
15 #include <linux/module.h>
16 #include <linux/i2c.h>
17 #include <linux/iio/iio.h>
18 #include <linux/iio/sysfs.h>
19 #include <linux/iio/buffer.h>
20 #include <linux/iio/trigger.h>
21 #include <linux/iio/trigger_consumer.h>
22 #include <linux/iio/triggered_buffer.h>
23 #include <linux/iio/events.h>
24 #include <linux/delay.h>
26 #define MMA8452_STATUS 0x00
27 #define MMA8452_STATUS_DRDY (BIT(2) | BIT(1) | BIT(0))
28 #define MMA8452_OUT_X 0x01 /* MSB first, 12-bit */
29 #define MMA8452_OUT_Y 0x03
30 #define MMA8452_OUT_Z 0x05
31 #define MMA8452_INT_SRC 0x0c
32 #define MMA8452_WHO_AM_I 0x0d
33 #define MMA8452_DATA_CFG 0x0e
34 #define MMA8452_DATA_CFG_FS_MASK GENMASK(1, 0)
35 #define MMA8452_DATA_CFG_FS_2G 0
36 #define MMA8452_DATA_CFG_FS_4G 1
37 #define MMA8452_DATA_CFG_FS_8G 2
38 #define MMA8452_DATA_CFG_HPF_MASK BIT(4)
39 #define MMA8452_HP_FILTER_CUTOFF 0x0f
40 #define MMA8452_HP_FILTER_CUTOFF_SEL_MASK GENMASK(1, 0)
41 #define MMA8452_TRANSIENT_CFG 0x1d
42 #define MMA8452_TRANSIENT_CFG_HPF_BYP BIT(0)
43 #define MMA8452_TRANSIENT_CFG_CHAN(chan) BIT(chan + 1)
44 #define MMA8452_TRANSIENT_CFG_ELE BIT(4)
45 #define MMA8452_TRANSIENT_SRC 0x1e
46 #define MMA8452_TRANSIENT_SRC_XTRANSE BIT(1)
47 #define MMA8452_TRANSIENT_SRC_YTRANSE BIT(3)
48 #define MMA8452_TRANSIENT_SRC_ZTRANSE BIT(5)
49 #define MMA8452_TRANSIENT_THS 0x1f
50 #define MMA8452_TRANSIENT_THS_MASK GENMASK(6, 0)
51 #define MMA8452_TRANSIENT_COUNT 0x20
52 #define MMA8452_CTRL_REG1 0x2a
53 #define MMA8452_CTRL_ACTIVE BIT(0)
54 #define MMA8452_CTRL_DR_MASK GENMASK(5, 3)
55 #define MMA8452_CTRL_DR_SHIFT 3
56 #define MMA8452_CTRL_DR_DEFAULT 0x4 /* 50 Hz sample frequency */
57 #define MMA8452_CTRL_REG2 0x2b
58 #define MMA8452_CTRL_REG2_RST BIT(6)
59 #define MMA8452_CTRL_REG4 0x2d
60 #define MMA8452_CTRL_REG5 0x2e
61 #define MMA8452_OFF_X 0x2f
62 #define MMA8452_OFF_Y 0x30
63 #define MMA8452_OFF_Z 0x31
65 #define MMA8452_MAX_REG 0x31
67 #define MMA8452_INT_DRDY BIT(0)
68 #define MMA8452_INT_TRANS BIT(5)
70 #define MMA8452_DEVICE_ID 0x2a
73 struct i2c_client
*client
;
79 static int mma8452_drdy(struct mma8452_data
*data
)
84 int ret
= i2c_smbus_read_byte_data(data
->client
,
88 if ((ret
& MMA8452_STATUS_DRDY
) == MMA8452_STATUS_DRDY
)
94 dev_err(&data
->client
->dev
, "data not ready\n");
99 static int mma8452_read(struct mma8452_data
*data
, __be16 buf
[3])
101 int ret
= mma8452_drdy(data
);
106 return i2c_smbus_read_i2c_block_data(data
->client
, MMA8452_OUT_X
,
107 3 * sizeof(__be16
), (u8
*)buf
);
110 static ssize_t
mma8452_show_int_plus_micros(char *buf
, const int (*vals
)[2],
116 len
+= scnprintf(buf
+ len
, PAGE_SIZE
- len
, "%d.%06d ",
117 vals
[n
][0], vals
[n
][1]);
119 /* replace trailing space by newline */
125 static int mma8452_get_int_plus_micros_index(const int (*vals
)[2], int n
,
129 if (val
== vals
[n
][0] && val2
== vals
[n
][1])
135 static int mma8452_get_odr_index(struct mma8452_data
*data
)
137 return (data
->ctrl_reg1
& MMA8452_CTRL_DR_MASK
) >>
138 MMA8452_CTRL_DR_SHIFT
;
141 static const int mma8452_samp_freq
[8][2] = {
142 {800, 0}, {400, 0}, {200, 0}, {100, 0}, {50, 0}, {12, 500000},
143 {6, 250000}, {1, 560000}
147 * Hardware has fullscale of -2G, -4G, -8G corresponding to raw value -2048
148 * The userspace interface uses m/s^2 and we declare micro units
149 * So scale factor is given by:
150 * g * N * 1000000 / 2048 for N = 2, 4, 8 and g = 9.80665
152 static const int mma8452_scales
[3][2] = {
153 {0, 9577}, {0, 19154}, {0, 38307}
156 /* Datasheet table 35 (step time vs sample frequency) */
157 static const int mma8452_transient_time_step_us
[8] = {
168 /* Datasheet table 18 (normal mode) */
169 static const int mma8452_hp_filter_cutoff
[8][4][2] = {
170 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 800 Hz sample */
171 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 400 Hz sample */
172 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, /* 200 Hz sample */
173 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, /* 100 Hz sample */
174 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 50 Hz sample */
175 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 12.5 Hz sample */
176 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 6.25 Hz sample */
177 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} } /* 1.56 Hz sample */
180 static ssize_t
mma8452_show_samp_freq_avail(struct device
*dev
,
181 struct device_attribute
*attr
,
184 return mma8452_show_int_plus_micros(buf
, mma8452_samp_freq
,
185 ARRAY_SIZE(mma8452_samp_freq
));
188 static ssize_t
mma8452_show_scale_avail(struct device
*dev
,
189 struct device_attribute
*attr
,
192 return mma8452_show_int_plus_micros(buf
, mma8452_scales
,
193 ARRAY_SIZE(mma8452_scales
));
196 static ssize_t
mma8452_show_hp_cutoff_avail(struct device
*dev
,
197 struct device_attribute
*attr
,
200 struct iio_dev
*indio_dev
= dev_to_iio_dev(dev
);
201 struct mma8452_data
*data
= iio_priv(indio_dev
);
202 int i
= mma8452_get_odr_index(data
);
204 return mma8452_show_int_plus_micros(buf
, mma8452_hp_filter_cutoff
[i
],
205 ARRAY_SIZE(mma8452_hp_filter_cutoff
[0]));
208 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail
);
209 static IIO_DEVICE_ATTR(in_accel_scale_available
, S_IRUGO
,
210 mma8452_show_scale_avail
, NULL
, 0);
211 static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available
,
212 S_IRUGO
, mma8452_show_hp_cutoff_avail
, NULL
, 0);
214 static int mma8452_get_samp_freq_index(struct mma8452_data
*data
,
217 return mma8452_get_int_plus_micros_index(mma8452_samp_freq
,
218 ARRAY_SIZE(mma8452_samp_freq
),
222 static int mma8452_get_scale_index(struct mma8452_data
*data
, int val
, int val2
)
224 return mma8452_get_int_plus_micros_index(mma8452_scales
,
225 ARRAY_SIZE(mma8452_scales
),
229 static int mma8452_get_hp_filter_index(struct mma8452_data
*data
,
232 int i
= mma8452_get_odr_index(data
);
234 return mma8452_get_int_plus_micros_index(mma8452_hp_filter_cutoff
[i
],
235 ARRAY_SIZE(mma8452_hp_filter_cutoff
[0]), val
, val2
);
238 static int mma8452_read_hp_filter(struct mma8452_data
*data
, int *hz
, int *uHz
)
242 ret
= i2c_smbus_read_byte_data(data
->client
, MMA8452_HP_FILTER_CUTOFF
);
246 i
= mma8452_get_odr_index(data
);
247 ret
&= MMA8452_HP_FILTER_CUTOFF_SEL_MASK
;
248 *hz
= mma8452_hp_filter_cutoff
[i
][ret
][0];
249 *uHz
= mma8452_hp_filter_cutoff
[i
][ret
][1];
254 static int mma8452_read_raw(struct iio_dev
*indio_dev
,
255 struct iio_chan_spec
const *chan
,
256 int *val
, int *val2
, long mask
)
258 struct mma8452_data
*data
= iio_priv(indio_dev
);
263 case IIO_CHAN_INFO_RAW
:
264 if (iio_buffer_enabled(indio_dev
))
267 mutex_lock(&data
->lock
);
268 ret
= mma8452_read(data
, buffer
);
269 mutex_unlock(&data
->lock
);
273 *val
= sign_extend32(be16_to_cpu(buffer
[chan
->scan_index
]) >> 4,
277 case IIO_CHAN_INFO_SCALE
:
278 i
= data
->data_cfg
& MMA8452_DATA_CFG_FS_MASK
;
279 *val
= mma8452_scales
[i
][0];
280 *val2
= mma8452_scales
[i
][1];
282 return IIO_VAL_INT_PLUS_MICRO
;
283 case IIO_CHAN_INFO_SAMP_FREQ
:
284 i
= mma8452_get_odr_index(data
);
285 *val
= mma8452_samp_freq
[i
][0];
286 *val2
= mma8452_samp_freq
[i
][1];
288 return IIO_VAL_INT_PLUS_MICRO
;
289 case IIO_CHAN_INFO_CALIBBIAS
:
290 ret
= i2c_smbus_read_byte_data(data
->client
,
291 MMA8452_OFF_X
+ chan
->scan_index
);
295 *val
= sign_extend32(ret
, 7);
298 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY
:
299 if (data
->data_cfg
& MMA8452_DATA_CFG_HPF_MASK
) {
300 ret
= mma8452_read_hp_filter(data
, val
, val2
);
308 return IIO_VAL_INT_PLUS_MICRO
;
314 static int mma8452_standby(struct mma8452_data
*data
)
316 return i2c_smbus_write_byte_data(data
->client
, MMA8452_CTRL_REG1
,
317 data
->ctrl_reg1
& ~MMA8452_CTRL_ACTIVE
);
320 static int mma8452_active(struct mma8452_data
*data
)
322 return i2c_smbus_write_byte_data(data
->client
, MMA8452_CTRL_REG1
,
326 static int mma8452_change_config(struct mma8452_data
*data
, u8 reg
, u8 val
)
330 mutex_lock(&data
->lock
);
332 /* config can only be changed when in standby */
333 ret
= mma8452_standby(data
);
337 ret
= i2c_smbus_write_byte_data(data
->client
, reg
, val
);
341 ret
= mma8452_active(data
);
347 mutex_unlock(&data
->lock
);
352 static int mma8452_set_hp_filter_frequency(struct mma8452_data
*data
,
357 i
= mma8452_get_hp_filter_index(data
, val
, val2
);
361 reg
= i2c_smbus_read_byte_data(data
->client
,
362 MMA8452_HP_FILTER_CUTOFF
);
366 reg
&= ~MMA8452_HP_FILTER_CUTOFF_SEL_MASK
;
369 return mma8452_change_config(data
, MMA8452_HP_FILTER_CUTOFF
, reg
);
372 static int mma8452_write_raw(struct iio_dev
*indio_dev
,
373 struct iio_chan_spec
const *chan
,
374 int val
, int val2
, long mask
)
376 struct mma8452_data
*data
= iio_priv(indio_dev
);
379 if (iio_buffer_enabled(indio_dev
))
383 case IIO_CHAN_INFO_SAMP_FREQ
:
384 i
= mma8452_get_samp_freq_index(data
, val
, val2
);
388 data
->ctrl_reg1
&= ~MMA8452_CTRL_DR_MASK
;
389 data
->ctrl_reg1
|= i
<< MMA8452_CTRL_DR_SHIFT
;
391 return mma8452_change_config(data
, MMA8452_CTRL_REG1
,
393 case IIO_CHAN_INFO_SCALE
:
394 i
= mma8452_get_scale_index(data
, val
, val2
);
398 data
->data_cfg
&= ~MMA8452_DATA_CFG_FS_MASK
;
401 return mma8452_change_config(data
, MMA8452_DATA_CFG
,
403 case IIO_CHAN_INFO_CALIBBIAS
:
404 if (val
< -128 || val
> 127)
407 return mma8452_change_config(data
,
408 MMA8452_OFF_X
+ chan
->scan_index
,
411 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY
:
412 if (val
== 0 && val2
== 0) {
413 data
->data_cfg
&= ~MMA8452_DATA_CFG_HPF_MASK
;
415 data
->data_cfg
|= MMA8452_DATA_CFG_HPF_MASK
;
416 ret
= mma8452_set_hp_filter_frequency(data
, val
, val2
);
421 return mma8452_change_config(data
, MMA8452_DATA_CFG
,
429 static int mma8452_read_thresh(struct iio_dev
*indio_dev
,
430 const struct iio_chan_spec
*chan
,
431 enum iio_event_type type
,
432 enum iio_event_direction dir
,
433 enum iio_event_info info
,
436 struct mma8452_data
*data
= iio_priv(indio_dev
);
440 case IIO_EV_INFO_VALUE
:
441 ret
= i2c_smbus_read_byte_data(data
->client
,
442 MMA8452_TRANSIENT_THS
);
446 *val
= ret
& MMA8452_TRANSIENT_THS_MASK
;
450 case IIO_EV_INFO_PERIOD
:
451 ret
= i2c_smbus_read_byte_data(data
->client
,
452 MMA8452_TRANSIENT_COUNT
);
456 us
= ret
* mma8452_transient_time_step_us
[
457 mma8452_get_odr_index(data
)];
458 *val
= us
/ USEC_PER_SEC
;
459 *val2
= us
% USEC_PER_SEC
;
461 return IIO_VAL_INT_PLUS_MICRO
;
463 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB
:
464 ret
= i2c_smbus_read_byte_data(data
->client
,
465 MMA8452_TRANSIENT_CFG
);
469 if (ret
& MMA8452_TRANSIENT_CFG_HPF_BYP
) {
473 ret
= mma8452_read_hp_filter(data
, val
, val2
);
478 return IIO_VAL_INT_PLUS_MICRO
;
485 static int mma8452_write_thresh(struct iio_dev
*indio_dev
,
486 const struct iio_chan_spec
*chan
,
487 enum iio_event_type type
,
488 enum iio_event_direction dir
,
489 enum iio_event_info info
,
492 struct mma8452_data
*data
= iio_priv(indio_dev
);
496 case IIO_EV_INFO_VALUE
:
497 if (val
< 0 || val
> MMA8452_TRANSIENT_THS_MASK
)
500 return mma8452_change_config(data
, MMA8452_TRANSIENT_THS
, val
);
502 case IIO_EV_INFO_PERIOD
:
503 steps
= (val
* USEC_PER_SEC
+ val2
) /
504 mma8452_transient_time_step_us
[
505 mma8452_get_odr_index(data
)];
507 if (steps
< 0 || steps
> 0xff)
510 return mma8452_change_config(data
, MMA8452_TRANSIENT_COUNT
,
513 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB
:
514 reg
= i2c_smbus_read_byte_data(data
->client
,
515 MMA8452_TRANSIENT_CFG
);
519 if (val
== 0 && val2
== 0) {
520 reg
|= MMA8452_TRANSIENT_CFG_HPF_BYP
;
522 reg
&= ~MMA8452_TRANSIENT_CFG_HPF_BYP
;
523 ret
= mma8452_set_hp_filter_frequency(data
, val
, val2
);
528 return mma8452_change_config(data
, MMA8452_TRANSIENT_CFG
, reg
);
535 static int mma8452_read_event_config(struct iio_dev
*indio_dev
,
536 const struct iio_chan_spec
*chan
,
537 enum iio_event_type type
,
538 enum iio_event_direction dir
)
540 struct mma8452_data
*data
= iio_priv(indio_dev
);
543 ret
= i2c_smbus_read_byte_data(data
->client
, MMA8452_TRANSIENT_CFG
);
547 return ret
& MMA8452_TRANSIENT_CFG_CHAN(chan
->scan_index
) ? 1 : 0;
550 static int mma8452_write_event_config(struct iio_dev
*indio_dev
,
551 const struct iio_chan_spec
*chan
,
552 enum iio_event_type type
,
553 enum iio_event_direction dir
,
556 struct mma8452_data
*data
= iio_priv(indio_dev
);
559 val
= i2c_smbus_read_byte_data(data
->client
, MMA8452_TRANSIENT_CFG
);
564 val
|= MMA8452_TRANSIENT_CFG_CHAN(chan
->scan_index
);
566 val
&= ~MMA8452_TRANSIENT_CFG_CHAN(chan
->scan_index
);
568 val
|= MMA8452_TRANSIENT_CFG_ELE
;
570 return mma8452_change_config(data
, MMA8452_TRANSIENT_CFG
, val
);
573 static void mma8452_transient_interrupt(struct iio_dev
*indio_dev
)
575 struct mma8452_data
*data
= iio_priv(indio_dev
);
576 s64 ts
= iio_get_time_ns();
579 src
= i2c_smbus_read_byte_data(data
->client
, MMA8452_TRANSIENT_SRC
);
583 if (src
& MMA8452_TRANSIENT_SRC_XTRANSE
)
584 iio_push_event(indio_dev
,
585 IIO_MOD_EVENT_CODE(IIO_ACCEL
, 0, IIO_MOD_X
,
590 if (src
& MMA8452_TRANSIENT_SRC_YTRANSE
)
591 iio_push_event(indio_dev
,
592 IIO_MOD_EVENT_CODE(IIO_ACCEL
, 0, IIO_MOD_Y
,
597 if (src
& MMA8452_TRANSIENT_SRC_ZTRANSE
)
598 iio_push_event(indio_dev
,
599 IIO_MOD_EVENT_CODE(IIO_ACCEL
, 0, IIO_MOD_Z
,
605 static irqreturn_t
mma8452_interrupt(int irq
, void *p
)
607 struct iio_dev
*indio_dev
= p
;
608 struct mma8452_data
*data
= iio_priv(indio_dev
);
612 src
= i2c_smbus_read_byte_data(data
->client
, MMA8452_INT_SRC
);
616 if (src
& MMA8452_INT_DRDY
) {
617 iio_trigger_poll_chained(indio_dev
->trig
);
621 if (src
& MMA8452_INT_TRANS
) {
622 mma8452_transient_interrupt(indio_dev
);
629 static irqreturn_t
mma8452_trigger_handler(int irq
, void *p
)
631 struct iio_poll_func
*pf
= p
;
632 struct iio_dev
*indio_dev
= pf
->indio_dev
;
633 struct mma8452_data
*data
= iio_priv(indio_dev
);
634 u8 buffer
[16]; /* 3 16-bit channels + padding + ts */
637 ret
= mma8452_read(data
, (__be16
*)buffer
);
641 iio_push_to_buffers_with_timestamp(indio_dev
, buffer
,
645 iio_trigger_notify_done(indio_dev
->trig
);
650 static int mma8452_reg_access_dbg(struct iio_dev
*indio_dev
,
651 unsigned reg
, unsigned writeval
,
655 struct mma8452_data
*data
= iio_priv(indio_dev
);
657 if (reg
> MMA8452_MAX_REG
)
661 return mma8452_change_config(data
, reg
, writeval
);
663 ret
= i2c_smbus_read_byte_data(data
->client
, reg
);
672 static const struct iio_event_spec mma8452_transient_event
[] = {
674 .type
= IIO_EV_TYPE_MAG
,
675 .dir
= IIO_EV_DIR_RISING
,
676 .mask_separate
= BIT(IIO_EV_INFO_ENABLE
),
677 .mask_shared_by_type
= BIT(IIO_EV_INFO_VALUE
) |
678 BIT(IIO_EV_INFO_PERIOD
) |
679 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB
)
684 * Threshold is configured in fixed 8G/127 steps regardless of
685 * currently selected scale for measurement.
687 static IIO_CONST_ATTR_NAMED(accel_transient_scale
, in_accel_scale
, "0.617742");
689 static struct attribute
*mma8452_event_attributes
[] = {
690 &iio_const_attr_accel_transient_scale
.dev_attr
.attr
,
694 static struct attribute_group mma8452_event_attribute_group
= {
695 .attrs
= mma8452_event_attributes
,
699 #define MMA8452_CHANNEL(axis, idx) { \
702 .channel2 = IIO_MOD_##axis, \
703 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
704 BIT(IIO_CHAN_INFO_CALIBBIAS), \
705 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
706 BIT(IIO_CHAN_INFO_SCALE) | \
707 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY), \
714 .endianness = IIO_BE, \
716 .event_spec = mma8452_transient_event, \
717 .num_event_specs = ARRAY_SIZE(mma8452_transient_event), \
720 static const struct iio_chan_spec mma8452_channels
[] = {
721 MMA8452_CHANNEL(X
, 0),
722 MMA8452_CHANNEL(Y
, 1),
723 MMA8452_CHANNEL(Z
, 2),
724 IIO_CHAN_SOFT_TIMESTAMP(3),
727 static struct attribute
*mma8452_attributes
[] = {
728 &iio_dev_attr_sampling_frequency_available
.dev_attr
.attr
,
729 &iio_dev_attr_in_accel_scale_available
.dev_attr
.attr
,
730 &iio_dev_attr_in_accel_filter_high_pass_3db_frequency_available
.dev_attr
.attr
,
734 static const struct attribute_group mma8452_group
= {
735 .attrs
= mma8452_attributes
,
738 static const struct iio_info mma8452_info
= {
739 .attrs
= &mma8452_group
,
740 .read_raw
= &mma8452_read_raw
,
741 .write_raw
= &mma8452_write_raw
,
742 .event_attrs
= &mma8452_event_attribute_group
,
743 .read_event_value
= &mma8452_read_thresh
,
744 .write_event_value
= &mma8452_write_thresh
,
745 .read_event_config
= &mma8452_read_event_config
,
746 .write_event_config
= &mma8452_write_event_config
,
747 .debugfs_reg_access
= &mma8452_reg_access_dbg
,
748 .driver_module
= THIS_MODULE
,
751 static const unsigned long mma8452_scan_masks
[] = {0x7, 0};
753 static int mma8452_data_rdy_trigger_set_state(struct iio_trigger
*trig
,
756 struct iio_dev
*indio_dev
= iio_trigger_get_drvdata(trig
);
757 struct mma8452_data
*data
= iio_priv(indio_dev
);
760 reg
= i2c_smbus_read_byte_data(data
->client
, MMA8452_CTRL_REG4
);
765 reg
|= MMA8452_INT_DRDY
;
767 reg
&= ~MMA8452_INT_DRDY
;
769 return mma8452_change_config(data
, MMA8452_CTRL_REG4
, reg
);
772 static int mma8452_validate_device(struct iio_trigger
*trig
,
773 struct iio_dev
*indio_dev
)
775 struct iio_dev
*indio
= iio_trigger_get_drvdata(trig
);
777 if (indio
!= indio_dev
)
783 static const struct iio_trigger_ops mma8452_trigger_ops
= {
784 .set_trigger_state
= mma8452_data_rdy_trigger_set_state
,
785 .validate_device
= mma8452_validate_device
,
786 .owner
= THIS_MODULE
,
789 static int mma8452_trigger_setup(struct iio_dev
*indio_dev
)
791 struct mma8452_data
*data
= iio_priv(indio_dev
);
792 struct iio_trigger
*trig
;
795 trig
= devm_iio_trigger_alloc(&data
->client
->dev
, "%s-dev%d",
801 trig
->dev
.parent
= &data
->client
->dev
;
802 trig
->ops
= &mma8452_trigger_ops
;
803 iio_trigger_set_drvdata(trig
, indio_dev
);
805 ret
= iio_trigger_register(trig
);
809 indio_dev
->trig
= trig
;
814 static void mma8452_trigger_cleanup(struct iio_dev
*indio_dev
)
817 iio_trigger_unregister(indio_dev
->trig
);
820 static int mma8452_reset(struct i2c_client
*client
)
825 ret
= i2c_smbus_write_byte_data(client
, MMA8452_CTRL_REG2
,
826 MMA8452_CTRL_REG2_RST
);
830 for (i
= 0; i
< 10; i
++) {
831 usleep_range(100, 200);
832 ret
= i2c_smbus_read_byte_data(client
, MMA8452_CTRL_REG2
);
834 continue; /* I2C comm reset */
837 if (!(ret
& MMA8452_CTRL_REG2_RST
))
844 static int mma8452_probe(struct i2c_client
*client
,
845 const struct i2c_device_id
*id
)
847 struct mma8452_data
*data
;
848 struct iio_dev
*indio_dev
;
851 ret
= i2c_smbus_read_byte_data(client
, MMA8452_WHO_AM_I
);
854 if (ret
!= MMA8452_DEVICE_ID
)
857 indio_dev
= devm_iio_device_alloc(&client
->dev
, sizeof(*data
));
861 data
= iio_priv(indio_dev
);
862 data
->client
= client
;
863 mutex_init(&data
->lock
);
865 i2c_set_clientdata(client
, indio_dev
);
866 indio_dev
->info
= &mma8452_info
;
867 indio_dev
->name
= id
->name
;
868 indio_dev
->dev
.parent
= &client
->dev
;
869 indio_dev
->modes
= INDIO_DIRECT_MODE
;
870 indio_dev
->channels
= mma8452_channels
;
871 indio_dev
->num_channels
= ARRAY_SIZE(mma8452_channels
);
872 indio_dev
->available_scan_masks
= mma8452_scan_masks
;
874 ret
= mma8452_reset(client
);
878 data
->data_cfg
= MMA8452_DATA_CFG_FS_2G
;
879 ret
= i2c_smbus_write_byte_data(client
, MMA8452_DATA_CFG
,
885 * By default set transient threshold to max to avoid events if
886 * enabling without configuring threshold.
888 ret
= i2c_smbus_write_byte_data(client
, MMA8452_TRANSIENT_THS
,
889 MMA8452_TRANSIENT_THS_MASK
);
895 * Although we enable the transient interrupt source once and
896 * for all here the transient event detection itself is not
897 * enabled until userspace asks for it by
898 * mma8452_write_event_config()
900 int supported_interrupts
= MMA8452_INT_DRDY
| MMA8452_INT_TRANS
;
901 int enabled_interrupts
= MMA8452_INT_TRANS
;
903 /* Assume wired to INT1 pin */
904 ret
= i2c_smbus_write_byte_data(client
,
906 supported_interrupts
);
910 ret
= i2c_smbus_write_byte_data(client
,
916 ret
= mma8452_trigger_setup(indio_dev
);
921 data
->ctrl_reg1
= MMA8452_CTRL_ACTIVE
|
922 (MMA8452_CTRL_DR_DEFAULT
<< MMA8452_CTRL_DR_SHIFT
);
923 ret
= i2c_smbus_write_byte_data(client
, MMA8452_CTRL_REG1
,
926 goto trigger_cleanup
;
928 ret
= iio_triggered_buffer_setup(indio_dev
, NULL
,
929 mma8452_trigger_handler
, NULL
);
931 goto trigger_cleanup
;
934 ret
= devm_request_threaded_irq(&client
->dev
,
936 NULL
, mma8452_interrupt
,
937 IRQF_TRIGGER_LOW
| IRQF_ONESHOT
,
938 client
->name
, indio_dev
);
943 ret
= iio_device_register(indio_dev
);
950 iio_triggered_buffer_cleanup(indio_dev
);
953 mma8452_trigger_cleanup(indio_dev
);
958 static int mma8452_remove(struct i2c_client
*client
)
960 struct iio_dev
*indio_dev
= i2c_get_clientdata(client
);
962 iio_device_unregister(indio_dev
);
963 iio_triggered_buffer_cleanup(indio_dev
);
964 mma8452_trigger_cleanup(indio_dev
);
965 mma8452_standby(iio_priv(indio_dev
));
970 #ifdef CONFIG_PM_SLEEP
971 static int mma8452_suspend(struct device
*dev
)
973 return mma8452_standby(iio_priv(i2c_get_clientdata(
974 to_i2c_client(dev
))));
977 static int mma8452_resume(struct device
*dev
)
979 return mma8452_active(iio_priv(i2c_get_clientdata(
980 to_i2c_client(dev
))));
983 static SIMPLE_DEV_PM_OPS(mma8452_pm_ops
, mma8452_suspend
, mma8452_resume
);
984 #define MMA8452_PM_OPS (&mma8452_pm_ops)
986 #define MMA8452_PM_OPS NULL
989 static const struct i2c_device_id mma8452_id
[] = {
993 MODULE_DEVICE_TABLE(i2c
, mma8452_id
);
995 static const struct of_device_id mma8452_dt_ids
[] = {
996 { .compatible
= "fsl,mma8452" },
999 MODULE_DEVICE_TABLE(of
, mma8452_dt_ids
);
1001 static struct i2c_driver mma8452_driver
= {
1004 .of_match_table
= of_match_ptr(mma8452_dt_ids
),
1005 .pm
= MMA8452_PM_OPS
,
1007 .probe
= mma8452_probe
,
1008 .remove
= mma8452_remove
,
1009 .id_table
= mma8452_id
,
1011 module_i2c_driver(mma8452_driver
);
1013 MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>");
1014 MODULE_DESCRIPTION("Freescale MMA8452 accelerometer driver");
1015 MODULE_LICENSE("GPL");