2 * mma8452.c - Support for following Freescale / NXP 3-axis accelerometers:
4 * device name digital output 7-bit I2C slave address (pin selectable)
5 * ---------------------------------------------------------------------
6 * MMA8451Q 14 bit 0x1c / 0x1d
7 * MMA8452Q 12 bit 0x1c / 0x1d
8 * MMA8453Q 10 bit 0x1c / 0x1d
9 * MMA8652FC 12 bit 0x1d
10 * MMA8653FC 10 bit 0x1d
11 * FXLS8471Q 14 bit 0x1e / 0x1d / 0x1c / 0x1f
13 * Copyright 2015 Martin Kepplinger <martink@posteo.de>
14 * Copyright 2014 Peter Meerwald <pmeerw@pmeerw.net>
16 * This file is subject to the terms and conditions of version 2 of
17 * the GNU General Public License. See the file COPYING in the main
18 * directory of this archive for more details.
20 * TODO: orientation events
23 #include <linux/module.h>
24 #include <linux/i2c.h>
25 #include <linux/iio/iio.h>
26 #include <linux/iio/sysfs.h>
27 #include <linux/iio/buffer.h>
28 #include <linux/iio/trigger.h>
29 #include <linux/iio/trigger_consumer.h>
30 #include <linux/iio/triggered_buffer.h>
31 #include <linux/iio/events.h>
32 #include <linux/delay.h>
33 #include <linux/of_device.h>
34 #include <linux/of_irq.h>
35 #include <linux/pm_runtime.h>
37 #define MMA8452_STATUS 0x00
38 #define MMA8452_STATUS_DRDY (BIT(2) | BIT(1) | BIT(0))
39 #define MMA8452_OUT_X 0x01 /* MSB first */
40 #define MMA8452_OUT_Y 0x03
41 #define MMA8452_OUT_Z 0x05
42 #define MMA8452_INT_SRC 0x0c
43 #define MMA8452_WHO_AM_I 0x0d
44 #define MMA8452_DATA_CFG 0x0e
45 #define MMA8452_DATA_CFG_FS_MASK GENMASK(1, 0)
46 #define MMA8452_DATA_CFG_FS_2G 0
47 #define MMA8452_DATA_CFG_FS_4G 1
48 #define MMA8452_DATA_CFG_FS_8G 2
49 #define MMA8452_DATA_CFG_HPF_MASK BIT(4)
50 #define MMA8452_HP_FILTER_CUTOFF 0x0f
51 #define MMA8452_HP_FILTER_CUTOFF_SEL_MASK GENMASK(1, 0)
52 #define MMA8452_FF_MT_CFG 0x15
53 #define MMA8452_FF_MT_CFG_OAE BIT(6)
54 #define MMA8452_FF_MT_CFG_ELE BIT(7)
55 #define MMA8452_FF_MT_SRC 0x16
56 #define MMA8452_FF_MT_SRC_XHE BIT(1)
57 #define MMA8452_FF_MT_SRC_YHE BIT(3)
58 #define MMA8452_FF_MT_SRC_ZHE BIT(5)
59 #define MMA8452_FF_MT_THS 0x17
60 #define MMA8452_FF_MT_THS_MASK 0x7f
61 #define MMA8452_FF_MT_COUNT 0x18
62 #define MMA8452_FF_MT_CHAN_SHIFT 3
63 #define MMA8452_TRANSIENT_CFG 0x1d
64 #define MMA8452_TRANSIENT_CFG_CHAN(chan) BIT(chan + 1)
65 #define MMA8452_TRANSIENT_CFG_HPF_BYP BIT(0)
66 #define MMA8452_TRANSIENT_CFG_ELE BIT(4)
67 #define MMA8452_TRANSIENT_SRC 0x1e
68 #define MMA8452_TRANSIENT_SRC_XTRANSE BIT(1)
69 #define MMA8452_TRANSIENT_SRC_YTRANSE BIT(3)
70 #define MMA8452_TRANSIENT_SRC_ZTRANSE BIT(5)
71 #define MMA8452_TRANSIENT_THS 0x1f
72 #define MMA8452_TRANSIENT_THS_MASK GENMASK(6, 0)
73 #define MMA8452_TRANSIENT_COUNT 0x20
74 #define MMA8452_TRANSIENT_CHAN_SHIFT 1
75 #define MMA8452_CTRL_REG1 0x2a
76 #define MMA8452_CTRL_ACTIVE BIT(0)
77 #define MMA8452_CTRL_DR_MASK GENMASK(5, 3)
78 #define MMA8452_CTRL_DR_SHIFT 3
79 #define MMA8452_CTRL_DR_DEFAULT 0x4 /* 50 Hz sample frequency */
80 #define MMA8452_CTRL_REG2 0x2b
81 #define MMA8452_CTRL_REG2_RST BIT(6)
82 #define MMA8452_CTRL_REG2_MODS_SHIFT 3
83 #define MMA8452_CTRL_REG2_MODS_MASK 0x1b
84 #define MMA8452_CTRL_REG4 0x2d
85 #define MMA8452_CTRL_REG5 0x2e
86 #define MMA8452_OFF_X 0x2f
87 #define MMA8452_OFF_Y 0x30
88 #define MMA8452_OFF_Z 0x31
90 #define MMA8452_MAX_REG 0x31
92 #define MMA8452_INT_DRDY BIT(0)
93 #define MMA8452_INT_FF_MT BIT(2)
94 #define MMA8452_INT_TRANS BIT(5)
96 #define MMA8451_DEVICE_ID 0x1a
97 #define MMA8452_DEVICE_ID 0x2a
98 #define MMA8453_DEVICE_ID 0x3a
99 #define MMA8652_DEVICE_ID 0x4a
100 #define MMA8653_DEVICE_ID 0x5a
101 #define FXLS8471_DEVICE_ID 0x6a
103 #define MMA8452_AUTO_SUSPEND_DELAY_MS 2000
105 struct mma8452_data
{
106 struct i2c_client
*client
;
110 const struct mma_chip_info
*chip_info
;
114 * struct mma8452_event_regs - chip specific data related to events
115 * @ev_cfg: event config register address
116 * @ev_cfg_ele: latch bit in event config register
117 * @ev_cfg_chan_shift: number of the bit to enable events in X
118 * direction; in event config register
119 * @ev_src: event source register address
120 * @ev_ths: event threshold register address
121 * @ev_ths_mask: mask for the threshold value
122 * @ev_count: event count (period) register address
124 * Since not all chips supported by the driver support comparing high pass
125 * filtered data for events (interrupts), different interrupt sources are
126 * used for different chips and the relevant registers are included here.
128 struct mma8452_event_regs
{
131 u8 ev_cfg_chan_shift
;
138 static const struct mma8452_event_regs ev_regs_accel_falling
= {
139 .ev_cfg
= MMA8452_FF_MT_CFG
,
140 .ev_cfg_ele
= MMA8452_FF_MT_CFG_ELE
,
141 .ev_cfg_chan_shift
= MMA8452_FF_MT_CHAN_SHIFT
,
142 .ev_src
= MMA8452_FF_MT_SRC
,
143 .ev_ths
= MMA8452_FF_MT_THS
,
144 .ev_ths_mask
= MMA8452_FF_MT_THS_MASK
,
145 .ev_count
= MMA8452_FF_MT_COUNT
148 static const struct mma8452_event_regs ev_regs_accel_rising
= {
149 .ev_cfg
= MMA8452_TRANSIENT_CFG
,
150 .ev_cfg_ele
= MMA8452_TRANSIENT_CFG_ELE
,
151 .ev_cfg_chan_shift
= MMA8452_TRANSIENT_CHAN_SHIFT
,
152 .ev_src
= MMA8452_TRANSIENT_SRC
,
153 .ev_ths
= MMA8452_TRANSIENT_THS
,
154 .ev_ths_mask
= MMA8452_TRANSIENT_THS_MASK
,
155 .ev_count
= MMA8452_TRANSIENT_COUNT
,
159 * struct mma_chip_info - chip specific data
160 * @chip_id: WHO_AM_I register's value
161 * @channels: struct iio_chan_spec matching the device's
163 * @num_channels: number of channels
164 * @mma_scales: scale factors for converting register values
165 * to m/s^2; 3 modes: 2g, 4g, 8g; 2 integers
166 * per mode: m/s^2 and micro m/s^2
167 * @all_events: all events supported by this chip
168 * @enabled_events: event flags enabled and handled by this driver
170 struct mma_chip_info
{
172 const struct iio_chan_spec
*channels
;
174 const int mma_scales
[3][2];
186 static int mma8452_drdy(struct mma8452_data
*data
)
190 while (tries
-- > 0) {
191 int ret
= i2c_smbus_read_byte_data(data
->client
,
195 if ((ret
& MMA8452_STATUS_DRDY
) == MMA8452_STATUS_DRDY
)
201 dev_err(&data
->client
->dev
, "data not ready\n");
206 static int mma8452_set_runtime_pm_state(struct i2c_client
*client
, bool on
)
212 ret
= pm_runtime_get_sync(&client
->dev
);
214 pm_runtime_mark_last_busy(&client
->dev
);
215 ret
= pm_runtime_put_autosuspend(&client
->dev
);
219 dev_err(&client
->dev
,
220 "failed to change power state to %d\n", on
);
222 pm_runtime_put_noidle(&client
->dev
);
231 static int mma8452_read(struct mma8452_data
*data
, __be16 buf
[3])
233 int ret
= mma8452_drdy(data
);
238 ret
= mma8452_set_runtime_pm_state(data
->client
, true);
242 ret
= i2c_smbus_read_i2c_block_data(data
->client
, MMA8452_OUT_X
,
243 3 * sizeof(__be16
), (u8
*)buf
);
245 ret
= mma8452_set_runtime_pm_state(data
->client
, false);
250 static ssize_t
mma8452_show_int_plus_micros(char *buf
, const int (*vals
)[2],
256 len
+= scnprintf(buf
+ len
, PAGE_SIZE
- len
, "%d.%06d ",
257 vals
[n
][0], vals
[n
][1]);
259 /* replace trailing space by newline */
265 static int mma8452_get_int_plus_micros_index(const int (*vals
)[2], int n
,
269 if (val
== vals
[n
][0] && val2
== vals
[n
][1])
275 static unsigned int mma8452_get_odr_index(struct mma8452_data
*data
)
277 return (data
->ctrl_reg1
& MMA8452_CTRL_DR_MASK
) >>
278 MMA8452_CTRL_DR_SHIFT
;
281 static const int mma8452_samp_freq
[8][2] = {
282 {800, 0}, {400, 0}, {200, 0}, {100, 0}, {50, 0}, {12, 500000},
283 {6, 250000}, {1, 560000}
286 /* Datasheet table: step time "Relationship with the ODR" (sample frequency) */
287 static const unsigned int mma8452_transient_time_step_us
[4][8] = {
288 { 1250, 2500, 5000, 10000, 20000, 20000, 20000, 20000 }, /* normal */
289 { 1250, 2500, 5000, 10000, 20000, 80000, 80000, 80000 }, /* l p l n */
290 { 1250, 2500, 2500, 2500, 2500, 2500, 2500, 2500 }, /* high res*/
291 { 1250, 2500, 5000, 10000, 20000, 80000, 160000, 160000 } /* l p */
294 /* Datasheet table "High-Pass Filter Cutoff Options" */
295 static const int mma8452_hp_filter_cutoff
[4][8][4][2] = {
297 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 800 Hz sample */
298 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 400 Hz sample */
299 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, /* 200 Hz sample */
300 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, /* 100 Hz sample */
301 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 50 Hz sample */
302 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 12.5 Hz sample */
303 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 6.25 Hz sample */
304 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} } /* 1.56 Hz sample */
306 { /* low noise low power */
307 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
308 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
309 { {8, 0}, {4, 0}, {2, 0}, {1, 0} },
310 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} },
311 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },
312 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} },
313 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} },
314 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} }
316 { /* high resolution */
317 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
318 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
319 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
320 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
321 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
322 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
323 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
324 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }
327 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
328 { {8, 0}, {4, 0}, {2, 0}, {1, 0} },
329 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} },
330 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },
331 { {1, 0}, {0, 500000}, {0, 250000}, {0, 125000} },
332 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} },
333 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} },
334 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} }
338 /* Datasheet table "MODS Oversampling modes averaging values at each ODR" */
339 static const u16 mma8452_os_ratio
[4][8] = {
340 /* 800 Hz, 400 Hz, ... , 1.56 Hz */
341 { 2, 4, 4, 4, 4, 16, 32, 128 }, /* normal */
342 { 2, 4, 4, 4, 4, 4, 8, 32 }, /* low power low noise */
343 { 2, 4, 8, 16, 32, 128, 256, 1024 }, /* high resolution */
344 { 2, 2, 2, 2, 2, 2, 4, 16 } /* low power */
347 static int mma8452_get_power_mode(struct mma8452_data
*data
)
351 reg
= i2c_smbus_read_byte_data(data
->client
,
356 return ((reg
& MMA8452_CTRL_REG2_MODS_MASK
) >>
357 MMA8452_CTRL_REG2_MODS_SHIFT
);
360 static ssize_t
mma8452_show_samp_freq_avail(struct device
*dev
,
361 struct device_attribute
*attr
,
364 return mma8452_show_int_plus_micros(buf
, mma8452_samp_freq
,
365 ARRAY_SIZE(mma8452_samp_freq
));
368 static ssize_t
mma8452_show_scale_avail(struct device
*dev
,
369 struct device_attribute
*attr
,
372 struct mma8452_data
*data
= iio_priv(i2c_get_clientdata(
373 to_i2c_client(dev
)));
375 return mma8452_show_int_plus_micros(buf
, data
->chip_info
->mma_scales
,
376 ARRAY_SIZE(data
->chip_info
->mma_scales
));
379 static ssize_t
mma8452_show_hp_cutoff_avail(struct device
*dev
,
380 struct device_attribute
*attr
,
383 struct iio_dev
*indio_dev
= dev_to_iio_dev(dev
);
384 struct mma8452_data
*data
= iio_priv(indio_dev
);
387 i
= mma8452_get_odr_index(data
);
388 j
= mma8452_get_power_mode(data
);
392 return mma8452_show_int_plus_micros(buf
, mma8452_hp_filter_cutoff
[j
][i
],
393 ARRAY_SIZE(mma8452_hp_filter_cutoff
[0][0]));
396 static ssize_t
mma8452_show_os_ratio_avail(struct device
*dev
,
397 struct device_attribute
*attr
,
400 struct iio_dev
*indio_dev
= dev_to_iio_dev(dev
);
401 struct mma8452_data
*data
= iio_priv(indio_dev
);
402 int i
= mma8452_get_odr_index(data
);
407 for (j
= 0; j
< ARRAY_SIZE(mma8452_os_ratio
); j
++) {
408 if (val
== mma8452_os_ratio
[j
][i
])
411 val
= mma8452_os_ratio
[j
][i
];
413 len
+= scnprintf(buf
+ len
, PAGE_SIZE
- len
, "%d ", val
);
420 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail
);
421 static IIO_DEVICE_ATTR(in_accel_scale_available
, 0444,
422 mma8452_show_scale_avail
, NULL
, 0);
423 static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available
,
424 0444, mma8452_show_hp_cutoff_avail
, NULL
, 0);
425 static IIO_DEVICE_ATTR(in_accel_oversampling_ratio_available
, 0444,
426 mma8452_show_os_ratio_avail
, NULL
, 0);
428 static int mma8452_get_samp_freq_index(struct mma8452_data
*data
,
431 return mma8452_get_int_plus_micros_index(mma8452_samp_freq
,
432 ARRAY_SIZE(mma8452_samp_freq
),
436 static int mma8452_get_scale_index(struct mma8452_data
*data
, int val
, int val2
)
438 return mma8452_get_int_plus_micros_index(data
->chip_info
->mma_scales
,
439 ARRAY_SIZE(data
->chip_info
->mma_scales
), val
, val2
);
442 static int mma8452_get_hp_filter_index(struct mma8452_data
*data
,
447 i
= mma8452_get_odr_index(data
);
448 j
= mma8452_get_power_mode(data
);
452 return mma8452_get_int_plus_micros_index(mma8452_hp_filter_cutoff
[j
][i
],
453 ARRAY_SIZE(mma8452_hp_filter_cutoff
[0][0]), val
, val2
);
456 static int mma8452_read_hp_filter(struct mma8452_data
*data
, int *hz
, int *uHz
)
460 ret
= i2c_smbus_read_byte_data(data
->client
, MMA8452_HP_FILTER_CUTOFF
);
464 i
= mma8452_get_odr_index(data
);
465 j
= mma8452_get_power_mode(data
);
469 ret
&= MMA8452_HP_FILTER_CUTOFF_SEL_MASK
;
470 *hz
= mma8452_hp_filter_cutoff
[j
][i
][ret
][0];
471 *uHz
= mma8452_hp_filter_cutoff
[j
][i
][ret
][1];
476 static int mma8452_read_raw(struct iio_dev
*indio_dev
,
477 struct iio_chan_spec
const *chan
,
478 int *val
, int *val2
, long mask
)
480 struct mma8452_data
*data
= iio_priv(indio_dev
);
485 case IIO_CHAN_INFO_RAW
:
486 ret
= iio_device_claim_direct_mode(indio_dev
);
490 mutex_lock(&data
->lock
);
491 ret
= mma8452_read(data
, buffer
);
492 mutex_unlock(&data
->lock
);
493 iio_device_release_direct_mode(indio_dev
);
497 *val
= sign_extend32(be16_to_cpu(
498 buffer
[chan
->scan_index
]) >> chan
->scan_type
.shift
,
499 chan
->scan_type
.realbits
- 1);
502 case IIO_CHAN_INFO_SCALE
:
503 i
= data
->data_cfg
& MMA8452_DATA_CFG_FS_MASK
;
504 *val
= data
->chip_info
->mma_scales
[i
][0];
505 *val2
= data
->chip_info
->mma_scales
[i
][1];
507 return IIO_VAL_INT_PLUS_MICRO
;
508 case IIO_CHAN_INFO_SAMP_FREQ
:
509 i
= mma8452_get_odr_index(data
);
510 *val
= mma8452_samp_freq
[i
][0];
511 *val2
= mma8452_samp_freq
[i
][1];
513 return IIO_VAL_INT_PLUS_MICRO
;
514 case IIO_CHAN_INFO_CALIBBIAS
:
515 ret
= i2c_smbus_read_byte_data(data
->client
,
521 *val
= sign_extend32(ret
, 7);
524 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY
:
525 if (data
->data_cfg
& MMA8452_DATA_CFG_HPF_MASK
) {
526 ret
= mma8452_read_hp_filter(data
, val
, val2
);
534 return IIO_VAL_INT_PLUS_MICRO
;
535 case IIO_CHAN_INFO_OVERSAMPLING_RATIO
:
536 ret
= mma8452_get_power_mode(data
);
540 i
= mma8452_get_odr_index(data
);
542 *val
= mma8452_os_ratio
[ret
][i
];
549 static int mma8452_standby(struct mma8452_data
*data
)
551 return i2c_smbus_write_byte_data(data
->client
, MMA8452_CTRL_REG1
,
552 data
->ctrl_reg1
& ~MMA8452_CTRL_ACTIVE
);
555 static int mma8452_active(struct mma8452_data
*data
)
557 return i2c_smbus_write_byte_data(data
->client
, MMA8452_CTRL_REG1
,
561 /* returns >0 if active, 0 if in standby and <0 on error */
562 static int mma8452_is_active(struct mma8452_data
*data
)
566 reg
= i2c_smbus_read_byte_data(data
->client
, MMA8452_CTRL_REG1
);
570 return reg
& MMA8452_CTRL_ACTIVE
;
573 static int mma8452_change_config(struct mma8452_data
*data
, u8 reg
, u8 val
)
578 mutex_lock(&data
->lock
);
580 is_active
= mma8452_is_active(data
);
586 /* config can only be changed when in standby */
588 ret
= mma8452_standby(data
);
593 ret
= i2c_smbus_write_byte_data(data
->client
, reg
, val
);
598 ret
= mma8452_active(data
);
605 mutex_unlock(&data
->lock
);
610 static int mma8452_set_power_mode(struct mma8452_data
*data
, u8 mode
)
614 reg
= i2c_smbus_read_byte_data(data
->client
,
619 reg
&= ~MMA8452_CTRL_REG2_MODS_MASK
;
620 reg
|= mode
<< MMA8452_CTRL_REG2_MODS_SHIFT
;
622 return mma8452_change_config(data
, MMA8452_CTRL_REG2
, reg
);
625 /* returns >0 if in freefall mode, 0 if not or <0 if an error occurred */
626 static int mma8452_freefall_mode_enabled(struct mma8452_data
*data
)
630 val
= i2c_smbus_read_byte_data(data
->client
, MMA8452_FF_MT_CFG
);
634 return !(val
& MMA8452_FF_MT_CFG_OAE
);
637 static int mma8452_set_freefall_mode(struct mma8452_data
*data
, bool state
)
641 if ((state
&& mma8452_freefall_mode_enabled(data
)) ||
642 (!state
&& !(mma8452_freefall_mode_enabled(data
))))
645 val
= i2c_smbus_read_byte_data(data
->client
, MMA8452_FF_MT_CFG
);
650 val
|= BIT(idx_x
+ MMA8452_FF_MT_CHAN_SHIFT
);
651 val
|= BIT(idx_y
+ MMA8452_FF_MT_CHAN_SHIFT
);
652 val
|= BIT(idx_z
+ MMA8452_FF_MT_CHAN_SHIFT
);
653 val
&= ~MMA8452_FF_MT_CFG_OAE
;
655 val
&= ~BIT(idx_x
+ MMA8452_FF_MT_CHAN_SHIFT
);
656 val
&= ~BIT(idx_y
+ MMA8452_FF_MT_CHAN_SHIFT
);
657 val
&= ~BIT(idx_z
+ MMA8452_FF_MT_CHAN_SHIFT
);
658 val
|= MMA8452_FF_MT_CFG_OAE
;
661 return mma8452_change_config(data
, MMA8452_FF_MT_CFG
, val
);
664 static int mma8452_set_hp_filter_frequency(struct mma8452_data
*data
,
669 i
= mma8452_get_hp_filter_index(data
, val
, val2
);
673 reg
= i2c_smbus_read_byte_data(data
->client
,
674 MMA8452_HP_FILTER_CUTOFF
);
678 reg
&= ~MMA8452_HP_FILTER_CUTOFF_SEL_MASK
;
681 return mma8452_change_config(data
, MMA8452_HP_FILTER_CUTOFF
, reg
);
684 static int mma8452_write_raw(struct iio_dev
*indio_dev
,
685 struct iio_chan_spec
const *chan
,
686 int val
, int val2
, long mask
)
688 struct mma8452_data
*data
= iio_priv(indio_dev
);
691 ret
= iio_device_claim_direct_mode(indio_dev
);
696 case IIO_CHAN_INFO_SAMP_FREQ
:
697 i
= mma8452_get_samp_freq_index(data
, val
, val2
);
702 data
->ctrl_reg1
&= ~MMA8452_CTRL_DR_MASK
;
703 data
->ctrl_reg1
|= i
<< MMA8452_CTRL_DR_SHIFT
;
705 ret
= mma8452_change_config(data
, MMA8452_CTRL_REG1
,
708 case IIO_CHAN_INFO_SCALE
:
709 i
= mma8452_get_scale_index(data
, val
, val2
);
715 data
->data_cfg
&= ~MMA8452_DATA_CFG_FS_MASK
;
718 ret
= mma8452_change_config(data
, MMA8452_DATA_CFG
,
721 case IIO_CHAN_INFO_CALIBBIAS
:
722 if (val
< -128 || val
> 127) {
727 ret
= mma8452_change_config(data
,
728 MMA8452_OFF_X
+ chan
->scan_index
,
732 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY
:
733 if (val
== 0 && val2
== 0) {
734 data
->data_cfg
&= ~MMA8452_DATA_CFG_HPF_MASK
;
736 data
->data_cfg
|= MMA8452_DATA_CFG_HPF_MASK
;
737 ret
= mma8452_set_hp_filter_frequency(data
, val
, val2
);
742 ret
= mma8452_change_config(data
, MMA8452_DATA_CFG
,
746 case IIO_CHAN_INFO_OVERSAMPLING_RATIO
:
747 ret
= mma8452_get_odr_index(data
);
749 for (i
= 0; i
< ARRAY_SIZE(mma8452_os_ratio
); i
++) {
750 if (mma8452_os_ratio
[i
][ret
] == val
) {
751 ret
= mma8452_set_power_mode(data
, i
);
761 iio_device_release_direct_mode(indio_dev
);
765 static int mma8452_get_event_regs(struct mma8452_data
*data
,
766 const struct iio_chan_spec
*chan
, enum iio_event_direction dir
,
767 const struct mma8452_event_regs
**ev_reg
)
772 switch (chan
->type
) {
775 case IIO_EV_DIR_RISING
:
776 if ((data
->chip_info
->all_events
777 & MMA8452_INT_TRANS
) &&
778 (data
->chip_info
->enabled_events
779 & MMA8452_INT_TRANS
))
780 *ev_reg
= &ev_regs_accel_rising
;
782 *ev_reg
= &ev_regs_accel_falling
;
784 case IIO_EV_DIR_FALLING
:
785 *ev_reg
= &ev_regs_accel_falling
;
795 static int mma8452_read_event_value(struct iio_dev
*indio_dev
,
796 const struct iio_chan_spec
*chan
,
797 enum iio_event_type type
,
798 enum iio_event_direction dir
,
799 enum iio_event_info info
,
802 struct mma8452_data
*data
= iio_priv(indio_dev
);
803 int ret
, us
, power_mode
;
804 const struct mma8452_event_regs
*ev_regs
;
806 ret
= mma8452_get_event_regs(data
, chan
, dir
, &ev_regs
);
811 case IIO_EV_INFO_VALUE
:
812 ret
= i2c_smbus_read_byte_data(data
->client
, ev_regs
->ev_ths
);
816 *val
= ret
& ev_regs
->ev_ths_mask
;
820 case IIO_EV_INFO_PERIOD
:
821 ret
= i2c_smbus_read_byte_data(data
->client
, ev_regs
->ev_count
);
825 power_mode
= mma8452_get_power_mode(data
);
829 us
= ret
* mma8452_transient_time_step_us
[power_mode
][
830 mma8452_get_odr_index(data
)];
831 *val
= us
/ USEC_PER_SEC
;
832 *val2
= us
% USEC_PER_SEC
;
834 return IIO_VAL_INT_PLUS_MICRO
;
836 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB
:
837 ret
= i2c_smbus_read_byte_data(data
->client
,
838 MMA8452_TRANSIENT_CFG
);
842 if (ret
& MMA8452_TRANSIENT_CFG_HPF_BYP
) {
846 ret
= mma8452_read_hp_filter(data
, val
, val2
);
851 return IIO_VAL_INT_PLUS_MICRO
;
858 static int mma8452_write_event_value(struct iio_dev
*indio_dev
,
859 const struct iio_chan_spec
*chan
,
860 enum iio_event_type type
,
861 enum iio_event_direction dir
,
862 enum iio_event_info info
,
865 struct mma8452_data
*data
= iio_priv(indio_dev
);
867 const struct mma8452_event_regs
*ev_regs
;
869 ret
= mma8452_get_event_regs(data
, chan
, dir
, &ev_regs
);
874 case IIO_EV_INFO_VALUE
:
875 if (val
< 0 || val
> ev_regs
->ev_ths_mask
)
878 return mma8452_change_config(data
, ev_regs
->ev_ths
, val
);
880 case IIO_EV_INFO_PERIOD
:
881 ret
= mma8452_get_power_mode(data
);
885 steps
= (val
* USEC_PER_SEC
+ val2
) /
886 mma8452_transient_time_step_us
[ret
][
887 mma8452_get_odr_index(data
)];
889 if (steps
< 0 || steps
> 0xff)
892 return mma8452_change_config(data
, ev_regs
->ev_count
, steps
);
894 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB
:
895 reg
= i2c_smbus_read_byte_data(data
->client
,
896 MMA8452_TRANSIENT_CFG
);
900 if (val
== 0 && val2
== 0) {
901 reg
|= MMA8452_TRANSIENT_CFG_HPF_BYP
;
903 reg
&= ~MMA8452_TRANSIENT_CFG_HPF_BYP
;
904 ret
= mma8452_set_hp_filter_frequency(data
, val
, val2
);
909 return mma8452_change_config(data
, MMA8452_TRANSIENT_CFG
, reg
);
916 static int mma8452_read_event_config(struct iio_dev
*indio_dev
,
917 const struct iio_chan_spec
*chan
,
918 enum iio_event_type type
,
919 enum iio_event_direction dir
)
921 struct mma8452_data
*data
= iio_priv(indio_dev
);
923 const struct mma8452_event_regs
*ev_regs
;
925 ret
= mma8452_get_event_regs(data
, chan
, dir
, &ev_regs
);
930 case IIO_EV_DIR_FALLING
:
931 return mma8452_freefall_mode_enabled(data
);
932 case IIO_EV_DIR_RISING
:
933 ret
= i2c_smbus_read_byte_data(data
->client
,
938 return !!(ret
& BIT(chan
->scan_index
+
939 ev_regs
->ev_cfg_chan_shift
));
945 static int mma8452_write_event_config(struct iio_dev
*indio_dev
,
946 const struct iio_chan_spec
*chan
,
947 enum iio_event_type type
,
948 enum iio_event_direction dir
,
951 struct mma8452_data
*data
= iio_priv(indio_dev
);
953 const struct mma8452_event_regs
*ev_regs
;
955 ret
= mma8452_get_event_regs(data
, chan
, dir
, &ev_regs
);
959 ret
= mma8452_set_runtime_pm_state(data
->client
, state
);
964 case IIO_EV_DIR_FALLING
:
965 return mma8452_set_freefall_mode(data
, state
);
966 case IIO_EV_DIR_RISING
:
967 val
= i2c_smbus_read_byte_data(data
->client
, ev_regs
->ev_cfg
);
972 if (mma8452_freefall_mode_enabled(data
)) {
973 val
&= ~BIT(idx_x
+ ev_regs
->ev_cfg_chan_shift
);
974 val
&= ~BIT(idx_y
+ ev_regs
->ev_cfg_chan_shift
);
975 val
&= ~BIT(idx_z
+ ev_regs
->ev_cfg_chan_shift
);
976 val
|= MMA8452_FF_MT_CFG_OAE
;
978 val
|= BIT(chan
->scan_index
+
979 ev_regs
->ev_cfg_chan_shift
);
981 if (mma8452_freefall_mode_enabled(data
))
984 val
&= ~BIT(chan
->scan_index
+
985 ev_regs
->ev_cfg_chan_shift
);
988 val
|= ev_regs
->ev_cfg_ele
;
990 return mma8452_change_config(data
, ev_regs
->ev_cfg
, val
);
996 static void mma8452_transient_interrupt(struct iio_dev
*indio_dev
)
998 struct mma8452_data
*data
= iio_priv(indio_dev
);
999 s64 ts
= iio_get_time_ns(indio_dev
);
1002 src
= i2c_smbus_read_byte_data(data
->client
, MMA8452_TRANSIENT_SRC
);
1006 if (src
& MMA8452_TRANSIENT_SRC_XTRANSE
)
1007 iio_push_event(indio_dev
,
1008 IIO_MOD_EVENT_CODE(IIO_ACCEL
, 0, IIO_MOD_X
,
1013 if (src
& MMA8452_TRANSIENT_SRC_YTRANSE
)
1014 iio_push_event(indio_dev
,
1015 IIO_MOD_EVENT_CODE(IIO_ACCEL
, 0, IIO_MOD_Y
,
1020 if (src
& MMA8452_TRANSIENT_SRC_ZTRANSE
)
1021 iio_push_event(indio_dev
,
1022 IIO_MOD_EVENT_CODE(IIO_ACCEL
, 0, IIO_MOD_Z
,
1028 static irqreturn_t
mma8452_interrupt(int irq
, void *p
)
1030 struct iio_dev
*indio_dev
= p
;
1031 struct mma8452_data
*data
= iio_priv(indio_dev
);
1035 src
= i2c_smbus_read_byte_data(data
->client
, MMA8452_INT_SRC
);
1039 if (!(src
& data
->chip_info
->enabled_events
))
1042 if (src
& MMA8452_INT_DRDY
) {
1043 iio_trigger_poll_chained(indio_dev
->trig
);
1047 if (src
& MMA8452_INT_FF_MT
) {
1048 if (mma8452_freefall_mode_enabled(data
)) {
1049 s64 ts
= iio_get_time_ns(indio_dev
);
1051 iio_push_event(indio_dev
,
1052 IIO_MOD_EVENT_CODE(IIO_ACCEL
, 0,
1053 IIO_MOD_X_AND_Y_AND_Z
,
1055 IIO_EV_DIR_FALLING
),
1061 if (src
& MMA8452_INT_TRANS
) {
1062 mma8452_transient_interrupt(indio_dev
);
1069 static irqreturn_t
mma8452_trigger_handler(int irq
, void *p
)
1071 struct iio_poll_func
*pf
= p
;
1072 struct iio_dev
*indio_dev
= pf
->indio_dev
;
1073 struct mma8452_data
*data
= iio_priv(indio_dev
);
1074 u8 buffer
[16]; /* 3 16-bit channels + padding + ts */
1077 ret
= mma8452_read(data
, (__be16
*)buffer
);
1081 iio_push_to_buffers_with_timestamp(indio_dev
, buffer
,
1082 iio_get_time_ns(indio_dev
));
1085 iio_trigger_notify_done(indio_dev
->trig
);
1090 static int mma8452_reg_access_dbg(struct iio_dev
*indio_dev
,
1091 unsigned int reg
, unsigned int writeval
,
1092 unsigned int *readval
)
1095 struct mma8452_data
*data
= iio_priv(indio_dev
);
1097 if (reg
> MMA8452_MAX_REG
)
1101 return mma8452_change_config(data
, reg
, writeval
);
1103 ret
= i2c_smbus_read_byte_data(data
->client
, reg
);
1112 static const struct iio_event_spec mma8452_freefall_event
[] = {
1114 .type
= IIO_EV_TYPE_MAG
,
1115 .dir
= IIO_EV_DIR_FALLING
,
1116 .mask_separate
= BIT(IIO_EV_INFO_ENABLE
),
1117 .mask_shared_by_type
= BIT(IIO_EV_INFO_VALUE
) |
1118 BIT(IIO_EV_INFO_PERIOD
) |
1119 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB
)
1123 static const struct iio_event_spec mma8652_freefall_event
[] = {
1125 .type
= IIO_EV_TYPE_MAG
,
1126 .dir
= IIO_EV_DIR_FALLING
,
1127 .mask_separate
= BIT(IIO_EV_INFO_ENABLE
),
1128 .mask_shared_by_type
= BIT(IIO_EV_INFO_VALUE
) |
1129 BIT(IIO_EV_INFO_PERIOD
)
1133 static const struct iio_event_spec mma8452_transient_event
[] = {
1135 .type
= IIO_EV_TYPE_MAG
,
1136 .dir
= IIO_EV_DIR_RISING
,
1137 .mask_separate
= BIT(IIO_EV_INFO_ENABLE
),
1138 .mask_shared_by_type
= BIT(IIO_EV_INFO_VALUE
) |
1139 BIT(IIO_EV_INFO_PERIOD
) |
1140 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB
)
1144 static const struct iio_event_spec mma8452_motion_event
[] = {
1146 .type
= IIO_EV_TYPE_MAG
,
1147 .dir
= IIO_EV_DIR_RISING
,
1148 .mask_separate
= BIT(IIO_EV_INFO_ENABLE
),
1149 .mask_shared_by_type
= BIT(IIO_EV_INFO_VALUE
) |
1150 BIT(IIO_EV_INFO_PERIOD
)
1155 * Threshold is configured in fixed 8G/127 steps regardless of
1156 * currently selected scale for measurement.
1158 static IIO_CONST_ATTR_NAMED(accel_transient_scale
, in_accel_scale
, "0.617742");
1160 static struct attribute
*mma8452_event_attributes
[] = {
1161 &iio_const_attr_accel_transient_scale
.dev_attr
.attr
,
1165 static struct attribute_group mma8452_event_attribute_group
= {
1166 .attrs
= mma8452_event_attributes
,
1169 #define MMA8452_FREEFALL_CHANNEL(modifier) { \
1170 .type = IIO_ACCEL, \
1172 .channel2 = modifier, \
1174 .event_spec = mma8452_freefall_event, \
1175 .num_event_specs = ARRAY_SIZE(mma8452_freefall_event), \
1178 #define MMA8652_FREEFALL_CHANNEL(modifier) { \
1179 .type = IIO_ACCEL, \
1181 .channel2 = modifier, \
1183 .event_spec = mma8652_freefall_event, \
1184 .num_event_specs = ARRAY_SIZE(mma8652_freefall_event), \
1187 #define MMA8452_CHANNEL(axis, idx, bits) { \
1188 .type = IIO_ACCEL, \
1190 .channel2 = IIO_MOD_##axis, \
1191 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1192 BIT(IIO_CHAN_INFO_CALIBBIAS), \
1193 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
1194 BIT(IIO_CHAN_INFO_SCALE) | \
1195 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY) | \
1196 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
1197 .scan_index = idx, \
1200 .realbits = (bits), \
1201 .storagebits = 16, \
1202 .shift = 16 - (bits), \
1203 .endianness = IIO_BE, \
1205 .event_spec = mma8452_transient_event, \
1206 .num_event_specs = ARRAY_SIZE(mma8452_transient_event), \
1209 #define MMA8652_CHANNEL(axis, idx, bits) { \
1210 .type = IIO_ACCEL, \
1212 .channel2 = IIO_MOD_##axis, \
1213 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1214 BIT(IIO_CHAN_INFO_CALIBBIAS), \
1215 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
1216 BIT(IIO_CHAN_INFO_SCALE) | \
1217 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
1218 .scan_index = idx, \
1221 .realbits = (bits), \
1222 .storagebits = 16, \
1223 .shift = 16 - (bits), \
1224 .endianness = IIO_BE, \
1226 .event_spec = mma8452_motion_event, \
1227 .num_event_specs = ARRAY_SIZE(mma8452_motion_event), \
1230 static const struct iio_chan_spec mma8451_channels
[] = {
1231 MMA8452_CHANNEL(X
, idx_x
, 14),
1232 MMA8452_CHANNEL(Y
, idx_y
, 14),
1233 MMA8452_CHANNEL(Z
, idx_z
, 14),
1234 IIO_CHAN_SOFT_TIMESTAMP(idx_ts
),
1235 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z
),
1238 static const struct iio_chan_spec mma8452_channels
[] = {
1239 MMA8452_CHANNEL(X
, idx_x
, 12),
1240 MMA8452_CHANNEL(Y
, idx_y
, 12),
1241 MMA8452_CHANNEL(Z
, idx_z
, 12),
1242 IIO_CHAN_SOFT_TIMESTAMP(idx_ts
),
1243 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z
),
1246 static const struct iio_chan_spec mma8453_channels
[] = {
1247 MMA8452_CHANNEL(X
, idx_x
, 10),
1248 MMA8452_CHANNEL(Y
, idx_y
, 10),
1249 MMA8452_CHANNEL(Z
, idx_z
, 10),
1250 IIO_CHAN_SOFT_TIMESTAMP(idx_ts
),
1251 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z
),
1254 static const struct iio_chan_spec mma8652_channels
[] = {
1255 MMA8652_CHANNEL(X
, idx_x
, 12),
1256 MMA8652_CHANNEL(Y
, idx_y
, 12),
1257 MMA8652_CHANNEL(Z
, idx_z
, 12),
1258 IIO_CHAN_SOFT_TIMESTAMP(idx_ts
),
1259 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z
),
1262 static const struct iio_chan_spec mma8653_channels
[] = {
1263 MMA8652_CHANNEL(X
, idx_x
, 10),
1264 MMA8652_CHANNEL(Y
, idx_y
, 10),
1265 MMA8652_CHANNEL(Z
, idx_z
, 10),
1266 IIO_CHAN_SOFT_TIMESTAMP(idx_ts
),
1267 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z
),
1279 static const struct mma_chip_info mma_chip_info_table
[] = {
1281 .chip_id
= MMA8451_DEVICE_ID
,
1282 .channels
= mma8451_channels
,
1283 .num_channels
= ARRAY_SIZE(mma8451_channels
),
1285 * Hardware has fullscale of -2G, -4G, -8G corresponding to
1286 * raw value -8192 for 14 bit, -2048 for 12 bit or -512 for 10
1288 * The userspace interface uses m/s^2 and we declare micro units
1289 * So scale factor for 12 bit here is given by:
1290 * g * N * 1000000 / 2048 for N = 2, 4, 8 and g=9.80665
1292 .mma_scales
= { {0, 2394}, {0, 4788}, {0, 9577} },
1294 * Although we enable the interrupt sources once and for
1295 * all here the event detection itself is not enabled until
1296 * userspace asks for it by mma8452_write_event_config()
1298 .all_events
= MMA8452_INT_DRDY
|
1301 .enabled_events
= MMA8452_INT_TRANS
|
1305 .chip_id
= MMA8452_DEVICE_ID
,
1306 .channels
= mma8452_channels
,
1307 .num_channels
= ARRAY_SIZE(mma8452_channels
),
1308 .mma_scales
= { {0, 9577}, {0, 19154}, {0, 38307} },
1310 * Although we enable the interrupt sources once and for
1311 * all here the event detection itself is not enabled until
1312 * userspace asks for it by mma8452_write_event_config()
1314 .all_events
= MMA8452_INT_DRDY
|
1317 .enabled_events
= MMA8452_INT_TRANS
|
1321 .chip_id
= MMA8453_DEVICE_ID
,
1322 .channels
= mma8453_channels
,
1323 .num_channels
= ARRAY_SIZE(mma8453_channels
),
1324 .mma_scales
= { {0, 38307}, {0, 76614}, {0, 153228} },
1326 * Although we enable the interrupt sources once and for
1327 * all here the event detection itself is not enabled until
1328 * userspace asks for it by mma8452_write_event_config()
1330 .all_events
= MMA8452_INT_DRDY
|
1333 .enabled_events
= MMA8452_INT_TRANS
|
1337 .chip_id
= MMA8652_DEVICE_ID
,
1338 .channels
= mma8652_channels
,
1339 .num_channels
= ARRAY_SIZE(mma8652_channels
),
1340 .mma_scales
= { {0, 9577}, {0, 19154}, {0, 38307} },
1341 .all_events
= MMA8452_INT_DRDY
|
1343 .enabled_events
= MMA8452_INT_FF_MT
,
1346 .chip_id
= MMA8653_DEVICE_ID
,
1347 .channels
= mma8653_channels
,
1348 .num_channels
= ARRAY_SIZE(mma8653_channels
),
1349 .mma_scales
= { {0, 38307}, {0, 76614}, {0, 153228} },
1351 * Although we enable the interrupt sources once and for
1352 * all here the event detection itself is not enabled until
1353 * userspace asks for it by mma8452_write_event_config()
1355 .all_events
= MMA8452_INT_DRDY
|
1357 .enabled_events
= MMA8452_INT_FF_MT
,
1360 .chip_id
= FXLS8471_DEVICE_ID
,
1361 .channels
= mma8451_channels
,
1362 .num_channels
= ARRAY_SIZE(mma8451_channels
),
1363 .mma_scales
= { {0, 2394}, {0, 4788}, {0, 9577} },
1365 * Although we enable the interrupt sources once and for
1366 * all here the event detection itself is not enabled until
1367 * userspace asks for it by mma8452_write_event_config()
1369 .all_events
= MMA8452_INT_DRDY
|
1372 .enabled_events
= MMA8452_INT_TRANS
|
1377 static struct attribute
*mma8452_attributes
[] = {
1378 &iio_dev_attr_sampling_frequency_available
.dev_attr
.attr
,
1379 &iio_dev_attr_in_accel_scale_available
.dev_attr
.attr
,
1380 &iio_dev_attr_in_accel_filter_high_pass_3db_frequency_available
.dev_attr
.attr
,
1381 &iio_dev_attr_in_accel_oversampling_ratio_available
.dev_attr
.attr
,
1385 static const struct attribute_group mma8452_group
= {
1386 .attrs
= mma8452_attributes
,
1389 static const struct iio_info mma8452_info
= {
1390 .attrs
= &mma8452_group
,
1391 .read_raw
= &mma8452_read_raw
,
1392 .write_raw
= &mma8452_write_raw
,
1393 .event_attrs
= &mma8452_event_attribute_group
,
1394 .read_event_value
= &mma8452_read_event_value
,
1395 .write_event_value
= &mma8452_write_event_value
,
1396 .read_event_config
= &mma8452_read_event_config
,
1397 .write_event_config
= &mma8452_write_event_config
,
1398 .debugfs_reg_access
= &mma8452_reg_access_dbg
,
1401 static const unsigned long mma8452_scan_masks
[] = {0x7, 0};
1403 static int mma8452_data_rdy_trigger_set_state(struct iio_trigger
*trig
,
1406 struct iio_dev
*indio_dev
= iio_trigger_get_drvdata(trig
);
1407 struct mma8452_data
*data
= iio_priv(indio_dev
);
1410 ret
= mma8452_set_runtime_pm_state(data
->client
, state
);
1414 reg
= i2c_smbus_read_byte_data(data
->client
, MMA8452_CTRL_REG4
);
1419 reg
|= MMA8452_INT_DRDY
;
1421 reg
&= ~MMA8452_INT_DRDY
;
1423 return mma8452_change_config(data
, MMA8452_CTRL_REG4
, reg
);
1426 static const struct iio_trigger_ops mma8452_trigger_ops
= {
1427 .set_trigger_state
= mma8452_data_rdy_trigger_set_state
,
1428 .validate_device
= iio_trigger_validate_own_device
,
1431 static int mma8452_trigger_setup(struct iio_dev
*indio_dev
)
1433 struct mma8452_data
*data
= iio_priv(indio_dev
);
1434 struct iio_trigger
*trig
;
1437 trig
= devm_iio_trigger_alloc(&data
->client
->dev
, "%s-dev%d",
1443 trig
->dev
.parent
= &data
->client
->dev
;
1444 trig
->ops
= &mma8452_trigger_ops
;
1445 iio_trigger_set_drvdata(trig
, indio_dev
);
1447 ret
= iio_trigger_register(trig
);
1451 indio_dev
->trig
= trig
;
1456 static void mma8452_trigger_cleanup(struct iio_dev
*indio_dev
)
1458 if (indio_dev
->trig
)
1459 iio_trigger_unregister(indio_dev
->trig
);
1462 static int mma8452_reset(struct i2c_client
*client
)
1467 ret
= i2c_smbus_write_byte_data(client
, MMA8452_CTRL_REG2
,
1468 MMA8452_CTRL_REG2_RST
);
1472 for (i
= 0; i
< 10; i
++) {
1473 usleep_range(100, 200);
1474 ret
= i2c_smbus_read_byte_data(client
, MMA8452_CTRL_REG2
);
1476 continue; /* I2C comm reset */
1479 if (!(ret
& MMA8452_CTRL_REG2_RST
))
1486 static const struct of_device_id mma8452_dt_ids
[] = {
1487 { .compatible
= "fsl,mma8451", .data
= &mma_chip_info_table
[mma8451
] },
1488 { .compatible
= "fsl,mma8452", .data
= &mma_chip_info_table
[mma8452
] },
1489 { .compatible
= "fsl,mma8453", .data
= &mma_chip_info_table
[mma8453
] },
1490 { .compatible
= "fsl,mma8652", .data
= &mma_chip_info_table
[mma8652
] },
1491 { .compatible
= "fsl,mma8653", .data
= &mma_chip_info_table
[mma8653
] },
1492 { .compatible
= "fsl,fxls8471", .data
= &mma_chip_info_table
[fxls8471
] },
1495 MODULE_DEVICE_TABLE(of
, mma8452_dt_ids
);
1497 static int mma8452_probe(struct i2c_client
*client
,
1498 const struct i2c_device_id
*id
)
1500 struct mma8452_data
*data
;
1501 struct iio_dev
*indio_dev
;
1503 const struct of_device_id
*match
;
1505 match
= of_match_device(mma8452_dt_ids
, &client
->dev
);
1507 dev_err(&client
->dev
, "unknown device model\n");
1511 indio_dev
= devm_iio_device_alloc(&client
->dev
, sizeof(*data
));
1515 data
= iio_priv(indio_dev
);
1516 data
->client
= client
;
1517 mutex_init(&data
->lock
);
1518 data
->chip_info
= match
->data
;
1520 ret
= i2c_smbus_read_byte_data(client
, MMA8452_WHO_AM_I
);
1525 case MMA8451_DEVICE_ID
:
1526 case MMA8452_DEVICE_ID
:
1527 case MMA8453_DEVICE_ID
:
1528 case MMA8652_DEVICE_ID
:
1529 case MMA8653_DEVICE_ID
:
1530 case FXLS8471_DEVICE_ID
:
1531 if (ret
== data
->chip_info
->chip_id
)
1537 dev_info(&client
->dev
, "registering %s accelerometer; ID 0x%x\n",
1538 match
->compatible
, data
->chip_info
->chip_id
);
1540 i2c_set_clientdata(client
, indio_dev
);
1541 indio_dev
->info
= &mma8452_info
;
1542 indio_dev
->name
= id
->name
;
1543 indio_dev
->dev
.parent
= &client
->dev
;
1544 indio_dev
->modes
= INDIO_DIRECT_MODE
;
1545 indio_dev
->channels
= data
->chip_info
->channels
;
1546 indio_dev
->num_channels
= data
->chip_info
->num_channels
;
1547 indio_dev
->available_scan_masks
= mma8452_scan_masks
;
1549 ret
= mma8452_reset(client
);
1553 data
->data_cfg
= MMA8452_DATA_CFG_FS_2G
;
1554 ret
= i2c_smbus_write_byte_data(client
, MMA8452_DATA_CFG
,
1560 * By default set transient threshold to max to avoid events if
1561 * enabling without configuring threshold.
1563 ret
= i2c_smbus_write_byte_data(client
, MMA8452_TRANSIENT_THS
,
1564 MMA8452_TRANSIENT_THS_MASK
);
1571 irq2
= of_irq_get_byname(client
->dev
.of_node
, "INT2");
1573 if (irq2
== client
->irq
) {
1574 dev_dbg(&client
->dev
, "using interrupt line INT2\n");
1576 ret
= i2c_smbus_write_byte_data(client
,
1578 data
->chip_info
->all_events
);
1582 dev_dbg(&client
->dev
, "using interrupt line INT1\n");
1585 ret
= i2c_smbus_write_byte_data(client
,
1587 data
->chip_info
->enabled_events
);
1591 ret
= mma8452_trigger_setup(indio_dev
);
1596 data
->ctrl_reg1
= MMA8452_CTRL_ACTIVE
|
1597 (MMA8452_CTRL_DR_DEFAULT
<< MMA8452_CTRL_DR_SHIFT
);
1598 ret
= i2c_smbus_write_byte_data(client
, MMA8452_CTRL_REG1
,
1601 goto trigger_cleanup
;
1603 ret
= iio_triggered_buffer_setup(indio_dev
, NULL
,
1604 mma8452_trigger_handler
, NULL
);
1606 goto trigger_cleanup
;
1609 ret
= devm_request_threaded_irq(&client
->dev
,
1611 NULL
, mma8452_interrupt
,
1612 IRQF_TRIGGER_LOW
| IRQF_ONESHOT
,
1613 client
->name
, indio_dev
);
1615 goto buffer_cleanup
;
1618 ret
= pm_runtime_set_active(&client
->dev
);
1620 goto buffer_cleanup
;
1622 pm_runtime_enable(&client
->dev
);
1623 pm_runtime_set_autosuspend_delay(&client
->dev
,
1624 MMA8452_AUTO_SUSPEND_DELAY_MS
);
1625 pm_runtime_use_autosuspend(&client
->dev
);
1627 ret
= iio_device_register(indio_dev
);
1629 goto buffer_cleanup
;
1631 ret
= mma8452_set_freefall_mode(data
, false);
1633 goto buffer_cleanup
;
1638 iio_triggered_buffer_cleanup(indio_dev
);
1641 mma8452_trigger_cleanup(indio_dev
);
1646 static int mma8452_remove(struct i2c_client
*client
)
1648 struct iio_dev
*indio_dev
= i2c_get_clientdata(client
);
1650 iio_device_unregister(indio_dev
);
1652 pm_runtime_disable(&client
->dev
);
1653 pm_runtime_set_suspended(&client
->dev
);
1654 pm_runtime_put_noidle(&client
->dev
);
1656 iio_triggered_buffer_cleanup(indio_dev
);
1657 mma8452_trigger_cleanup(indio_dev
);
1658 mma8452_standby(iio_priv(indio_dev
));
1664 static int mma8452_runtime_suspend(struct device
*dev
)
1666 struct iio_dev
*indio_dev
= i2c_get_clientdata(to_i2c_client(dev
));
1667 struct mma8452_data
*data
= iio_priv(indio_dev
);
1670 mutex_lock(&data
->lock
);
1671 ret
= mma8452_standby(data
);
1672 mutex_unlock(&data
->lock
);
1674 dev_err(&data
->client
->dev
, "powering off device failed\n");
1681 static int mma8452_runtime_resume(struct device
*dev
)
1683 struct iio_dev
*indio_dev
= i2c_get_clientdata(to_i2c_client(dev
));
1684 struct mma8452_data
*data
= iio_priv(indio_dev
);
1687 ret
= mma8452_active(data
);
1691 ret
= mma8452_get_odr_index(data
);
1692 sleep_val
= 1000 / mma8452_samp_freq
[ret
][0];
1694 usleep_range(sleep_val
* 1000, 20000);
1696 msleep_interruptible(sleep_val
);
1702 #ifdef CONFIG_PM_SLEEP
1703 static int mma8452_suspend(struct device
*dev
)
1705 return mma8452_standby(iio_priv(i2c_get_clientdata(
1706 to_i2c_client(dev
))));
1709 static int mma8452_resume(struct device
*dev
)
1711 return mma8452_active(iio_priv(i2c_get_clientdata(
1712 to_i2c_client(dev
))));
1716 static const struct dev_pm_ops mma8452_pm_ops
= {
1717 SET_SYSTEM_SLEEP_PM_OPS(mma8452_suspend
, mma8452_resume
)
1718 SET_RUNTIME_PM_OPS(mma8452_runtime_suspend
,
1719 mma8452_runtime_resume
, NULL
)
1722 static const struct i2c_device_id mma8452_id
[] = {
1723 { "mma8451", mma8451
},
1724 { "mma8452", mma8452
},
1725 { "mma8453", mma8453
},
1726 { "mma8652", mma8652
},
1727 { "mma8653", mma8653
},
1728 { "fxls8471", fxls8471
},
1731 MODULE_DEVICE_TABLE(i2c
, mma8452_id
);
1733 static struct i2c_driver mma8452_driver
= {
1736 .of_match_table
= of_match_ptr(mma8452_dt_ids
),
1737 .pm
= &mma8452_pm_ops
,
1739 .probe
= mma8452_probe
,
1740 .remove
= mma8452_remove
,
1741 .id_table
= mma8452_id
,
1743 module_i2c_driver(mma8452_driver
);
1745 MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>");
1746 MODULE_DESCRIPTION("Freescale / NXP MMA8452 accelerometer driver");
1747 MODULE_LICENSE("GPL");