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Merge branch 'x86-pti-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[mirror_ubuntu-bionic-kernel.git] / drivers / iio / accel / sca3000.c
1 /*
2 * sca3000_core.c -- support VTI sca3000 series accelerometers via SPI
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License version 2 as published by
6 * the Free Software Foundation.
7 *
8 * Copyright (c) 2009 Jonathan Cameron <jic23@kernel.org>
9 *
10 * See industrialio/accels/sca3000.h for comments.
11 */
12
13 #include <linux/interrupt.h>
14 #include <linux/fs.h>
15 #include <linux/device.h>
16 #include <linux/slab.h>
17 #include <linux/kernel.h>
18 #include <linux/spi/spi.h>
19 #include <linux/sysfs.h>
20 #include <linux/module.h>
21 #include <linux/uaccess.h>
22 #include <linux/iio/iio.h>
23 #include <linux/iio/sysfs.h>
24 #include <linux/iio/events.h>
25 #include <linux/iio/buffer.h>
26 #include <linux/iio/kfifo_buf.h>
27
28 #define SCA3000_WRITE_REG(a) (((a) << 2) | 0x02)
29 #define SCA3000_READ_REG(a) ((a) << 2)
30
31 #define SCA3000_REG_REVID_ADDR 0x00
32 #define SCA3000_REG_REVID_MAJOR_MASK GENMASK(8, 4)
33 #define SCA3000_REG_REVID_MINOR_MASK GENMASK(3, 0)
34
35 #define SCA3000_REG_STATUS_ADDR 0x02
36 #define SCA3000_LOCKED BIT(5)
37 #define SCA3000_EEPROM_CS_ERROR BIT(1)
38 #define SCA3000_SPI_FRAME_ERROR BIT(0)
39
40 /* All reads done using register decrement so no need to directly access LSBs */
41 #define SCA3000_REG_X_MSB_ADDR 0x05
42 #define SCA3000_REG_Y_MSB_ADDR 0x07
43 #define SCA3000_REG_Z_MSB_ADDR 0x09
44
45 #define SCA3000_REG_RING_OUT_ADDR 0x0f
46
47 /* Temp read untested - the e05 doesn't have the sensor */
48 #define SCA3000_REG_TEMP_MSB_ADDR 0x13
49
50 #define SCA3000_REG_MODE_ADDR 0x14
51 #define SCA3000_MODE_PROT_MASK 0x28
52 #define SCA3000_REG_MODE_RING_BUF_ENABLE BIT(7)
53 #define SCA3000_REG_MODE_RING_BUF_8BIT BIT(6)
54
55 /*
56 * Free fall detection triggers an interrupt if the acceleration
57 * is below a threshold for equivalent of 25cm drop
58 */
59 #define SCA3000_REG_MODE_FREE_FALL_DETECT BIT(4)
60 #define SCA3000_REG_MODE_MEAS_MODE_NORMAL 0x00
61 #define SCA3000_REG_MODE_MEAS_MODE_OP_1 0x01
62 #define SCA3000_REG_MODE_MEAS_MODE_OP_2 0x02
63
64 /*
65 * In motion detection mode the accelerations are band pass filtered
66 * (approx 1 - 25Hz) and then a programmable threshold used to trigger
67 * and interrupt.
68 */
69 #define SCA3000_REG_MODE_MEAS_MODE_MOT_DET 0x03
70 #define SCA3000_REG_MODE_MODE_MASK 0x03
71
72 #define SCA3000_REG_BUF_COUNT_ADDR 0x15
73
74 #define SCA3000_REG_INT_STATUS_ADDR 0x16
75 #define SCA3000_REG_INT_STATUS_THREE_QUARTERS BIT(7)
76 #define SCA3000_REG_INT_STATUS_HALF BIT(6)
77
78 #define SCA3000_INT_STATUS_FREE_FALL BIT(3)
79 #define SCA3000_INT_STATUS_Y_TRIGGER BIT(2)
80 #define SCA3000_INT_STATUS_X_TRIGGER BIT(1)
81 #define SCA3000_INT_STATUS_Z_TRIGGER BIT(0)
82
83 /* Used to allow access to multiplexed registers */
84 #define SCA3000_REG_CTRL_SEL_ADDR 0x18
85 /* Only available for SCA3000-D03 and SCA3000-D01 */
86 #define SCA3000_REG_CTRL_SEL_I2C_DISABLE 0x01
87 #define SCA3000_REG_CTRL_SEL_MD_CTRL 0x02
88 #define SCA3000_REG_CTRL_SEL_MD_Y_TH 0x03
89 #define SCA3000_REG_CTRL_SEL_MD_X_TH 0x04
90 #define SCA3000_REG_CTRL_SEL_MD_Z_TH 0x05
91 /*
92 * BE VERY CAREFUL WITH THIS, IF 3 BITS ARE NOT SET the device
93 * will not function
94 */
95 #define SCA3000_REG_CTRL_SEL_OUT_CTRL 0x0B
96
97 #define SCA3000_REG_OUT_CTRL_PROT_MASK 0xE0
98 #define SCA3000_REG_OUT_CTRL_BUF_X_EN 0x10
99 #define SCA3000_REG_OUT_CTRL_BUF_Y_EN 0x08
100 #define SCA3000_REG_OUT_CTRL_BUF_Z_EN 0x04
101 #define SCA3000_REG_OUT_CTRL_BUF_DIV_MASK 0x03
102 #define SCA3000_REG_OUT_CTRL_BUF_DIV_4 0x02
103 #define SCA3000_REG_OUT_CTRL_BUF_DIV_2 0x01
104
105
106 /*
107 * Control which motion detector interrupts are on.
108 * For now only OR combinations are supported.
109 */
110 #define SCA3000_MD_CTRL_PROT_MASK 0xC0
111 #define SCA3000_MD_CTRL_OR_Y BIT(0)
112 #define SCA3000_MD_CTRL_OR_X BIT(1)
113 #define SCA3000_MD_CTRL_OR_Z BIT(2)
114 /* Currently unsupported */
115 #define SCA3000_MD_CTRL_AND_Y BIT(3)
116 #define SCA3000_MD_CTRL_AND_X BIT(4)
117 #define SAC3000_MD_CTRL_AND_Z BIT(5)
118
119 /*
120 * Some control registers of complex access methods requiring this register to
121 * be used to remove a lock.
122 */
123 #define SCA3000_REG_UNLOCK_ADDR 0x1e
124
125 #define SCA3000_REG_INT_MASK_ADDR 0x21
126 #define SCA3000_REG_INT_MASK_PROT_MASK 0x1C
127
128 #define SCA3000_REG_INT_MASK_RING_THREE_QUARTER BIT(7)
129 #define SCA3000_REG_INT_MASK_RING_HALF BIT(6)
130
131 #define SCA3000_REG_INT_MASK_ALL_INTS 0x02
132 #define SCA3000_REG_INT_MASK_ACTIVE_HIGH 0x01
133 #define SCA3000_REG_INT_MASK_ACTIVE_LOW 0x00
134 /* Values of multiplexed registers (write to ctrl_data after select) */
135 #define SCA3000_REG_CTRL_DATA_ADDR 0x22
136
137 /*
138 * Measurement modes available on some sca3000 series chips. Code assumes others
139 * may become available in the future.
140 *
141 * Bypass - Bypass the low-pass filter in the signal channel so as to increase
142 * signal bandwidth.
143 *
144 * Narrow - Narrow low-pass filtering of the signal channel and half output
145 * data rate by decimation.
146 *
147 * Wide - Widen low-pass filtering of signal channel to increase bandwidth
148 */
149 #define SCA3000_OP_MODE_BYPASS 0x01
150 #define SCA3000_OP_MODE_NARROW 0x02
151 #define SCA3000_OP_MODE_WIDE 0x04
152 #define SCA3000_MAX_TX 6
153 #define SCA3000_MAX_RX 2
154
155 /**
156 * struct sca3000_state - device instance state information
157 * @us: the associated spi device
158 * @info: chip variant information
159 * @last_timestamp: the timestamp of the last event
160 * @mo_det_use_count: reference counter for the motion detection unit
161 * @lock: lock used to protect elements of sca3000_state
162 * and the underlying device state.
163 * @tx: dma-able transmit buffer
164 * @rx: dma-able receive buffer
165 **/
166 struct sca3000_state {
167 struct spi_device *us;
168 const struct sca3000_chip_info *info;
169 s64 last_timestamp;
170 int mo_det_use_count;
171 struct mutex lock;
172 /* Can these share a cacheline ? */
173 u8 rx[384] ____cacheline_aligned;
174 u8 tx[6] ____cacheline_aligned;
175 };
176
177 /**
178 * struct sca3000_chip_info - model dependent parameters
179 * @scale: scale * 10^-6
180 * @temp_output: some devices have temperature sensors.
181 * @measurement_mode_freq: normal mode sampling frequency
182 * @measurement_mode_3db_freq: 3db cutoff frequency of the low pass filter for
183 * the normal measurement mode.
184 * @option_mode_1: first optional mode. Not all models have one
185 * @option_mode_1_freq: option mode 1 sampling frequency
186 * @option_mode_1_3db_freq: 3db cutoff frequency of the low pass filter for
187 * the first option mode.
188 * @option_mode_2: second optional mode. Not all chips have one
189 * @option_mode_2_freq: option mode 2 sampling frequency
190 * @option_mode_2_3db_freq: 3db cutoff frequency of the low pass filter for
191 * the second option mode.
192 * @mod_det_mult_xz: Bit wise multipliers to calculate the threshold
193 * for motion detection in the x and z axis.
194 * @mod_det_mult_y: Bit wise multipliers to calculate the threshold
195 * for motion detection in the y axis.
196 *
197 * This structure is used to hold information about the functionality of a given
198 * sca3000 variant.
199 **/
200 struct sca3000_chip_info {
201 unsigned int scale;
202 bool temp_output;
203 int measurement_mode_freq;
204 int measurement_mode_3db_freq;
205 int option_mode_1;
206 int option_mode_1_freq;
207 int option_mode_1_3db_freq;
208 int option_mode_2;
209 int option_mode_2_freq;
210 int option_mode_2_3db_freq;
211 int mot_det_mult_xz[6];
212 int mot_det_mult_y[7];
213 };
214
215 enum sca3000_variant {
216 d01,
217 e02,
218 e04,
219 e05,
220 };
221
222 /*
223 * Note where option modes are not defined, the chip simply does not
224 * support any.
225 * Other chips in the sca3000 series use i2c and are not included here.
226 *
227 * Some of these devices are only listed in the family data sheet and
228 * do not actually appear to be available.
229 */
230 static const struct sca3000_chip_info sca3000_spi_chip_info_tbl[] = {
231 [d01] = {
232 .scale = 7357,
233 .temp_output = true,
234 .measurement_mode_freq = 250,
235 .measurement_mode_3db_freq = 45,
236 .option_mode_1 = SCA3000_OP_MODE_BYPASS,
237 .option_mode_1_freq = 250,
238 .option_mode_1_3db_freq = 70,
239 .mot_det_mult_xz = {50, 100, 200, 350, 650, 1300},
240 .mot_det_mult_y = {50, 100, 150, 250, 450, 850, 1750},
241 },
242 [e02] = {
243 .scale = 9810,
244 .measurement_mode_freq = 125,
245 .measurement_mode_3db_freq = 40,
246 .option_mode_1 = SCA3000_OP_MODE_NARROW,
247 .option_mode_1_freq = 63,
248 .option_mode_1_3db_freq = 11,
249 .mot_det_mult_xz = {100, 150, 300, 550, 1050, 2050},
250 .mot_det_mult_y = {50, 100, 200, 350, 700, 1350, 2700},
251 },
252 [e04] = {
253 .scale = 19620,
254 .measurement_mode_freq = 100,
255 .measurement_mode_3db_freq = 38,
256 .option_mode_1 = SCA3000_OP_MODE_NARROW,
257 .option_mode_1_freq = 50,
258 .option_mode_1_3db_freq = 9,
259 .option_mode_2 = SCA3000_OP_MODE_WIDE,
260 .option_mode_2_freq = 400,
261 .option_mode_2_3db_freq = 70,
262 .mot_det_mult_xz = {200, 300, 600, 1100, 2100, 4100},
263 .mot_det_mult_y = {100, 200, 400, 7000, 1400, 2700, 54000},
264 },
265 [e05] = {
266 .scale = 61313,
267 .measurement_mode_freq = 200,
268 .measurement_mode_3db_freq = 60,
269 .option_mode_1 = SCA3000_OP_MODE_NARROW,
270 .option_mode_1_freq = 50,
271 .option_mode_1_3db_freq = 9,
272 .option_mode_2 = SCA3000_OP_MODE_WIDE,
273 .option_mode_2_freq = 400,
274 .option_mode_2_3db_freq = 75,
275 .mot_det_mult_xz = {600, 900, 1700, 3200, 6100, 11900},
276 .mot_det_mult_y = {300, 600, 1200, 2000, 4100, 7800, 15600},
277 },
278 };
279
280 static int sca3000_write_reg(struct sca3000_state *st, u8 address, u8 val)
281 {
282 st->tx[0] = SCA3000_WRITE_REG(address);
283 st->tx[1] = val;
284 return spi_write(st->us, st->tx, 2);
285 }
286
287 static int sca3000_read_data_short(struct sca3000_state *st,
288 u8 reg_address_high,
289 int len)
290 {
291 struct spi_transfer xfer[2] = {
292 {
293 .len = 1,
294 .tx_buf = st->tx,
295 }, {
296 .len = len,
297 .rx_buf = st->rx,
298 }
299 };
300 st->tx[0] = SCA3000_READ_REG(reg_address_high);
301
302 return spi_sync_transfer(st->us, xfer, ARRAY_SIZE(xfer));
303 }
304
305 /**
306 * sca3000_reg_lock_on() - test if the ctrl register lock is on
307 * @st: Driver specific device instance data.
308 *
309 * Lock must be held.
310 **/
311 static int sca3000_reg_lock_on(struct sca3000_state *st)
312 {
313 int ret;
314
315 ret = sca3000_read_data_short(st, SCA3000_REG_STATUS_ADDR, 1);
316 if (ret < 0)
317 return ret;
318
319 return !(st->rx[0] & SCA3000_LOCKED);
320 }
321
322 /**
323 * __sca3000_unlock_reg_lock() - unlock the control registers
324 * @st: Driver specific device instance data.
325 *
326 * Note the device does not appear to support doing this in a single transfer.
327 * This should only ever be used as part of ctrl reg read.
328 * Lock must be held before calling this
329 */
330 static int __sca3000_unlock_reg_lock(struct sca3000_state *st)
331 {
332 struct spi_transfer xfer[3] = {
333 {
334 .len = 2,
335 .cs_change = 1,
336 .tx_buf = st->tx,
337 }, {
338 .len = 2,
339 .cs_change = 1,
340 .tx_buf = st->tx + 2,
341 }, {
342 .len = 2,
343 .tx_buf = st->tx + 4,
344 },
345 };
346 st->tx[0] = SCA3000_WRITE_REG(SCA3000_REG_UNLOCK_ADDR);
347 st->tx[1] = 0x00;
348 st->tx[2] = SCA3000_WRITE_REG(SCA3000_REG_UNLOCK_ADDR);
349 st->tx[3] = 0x50;
350 st->tx[4] = SCA3000_WRITE_REG(SCA3000_REG_UNLOCK_ADDR);
351 st->tx[5] = 0xA0;
352
353 return spi_sync_transfer(st->us, xfer, ARRAY_SIZE(xfer));
354 }
355
356 /**
357 * sca3000_write_ctrl_reg() write to a lock protect ctrl register
358 * @st: Driver specific device instance data.
359 * @sel: selects which registers we wish to write to
360 * @val: the value to be written
361 *
362 * Certain control registers are protected against overwriting by the lock
363 * register and use a shared write address. This function allows writing of
364 * these registers.
365 * Lock must be held.
366 */
367 static int sca3000_write_ctrl_reg(struct sca3000_state *st,
368 u8 sel,
369 uint8_t val)
370 {
371 int ret;
372
373 ret = sca3000_reg_lock_on(st);
374 if (ret < 0)
375 goto error_ret;
376 if (ret) {
377 ret = __sca3000_unlock_reg_lock(st);
378 if (ret)
379 goto error_ret;
380 }
381
382 /* Set the control select register */
383 ret = sca3000_write_reg(st, SCA3000_REG_CTRL_SEL_ADDR, sel);
384 if (ret)
385 goto error_ret;
386
387 /* Write the actual value into the register */
388 ret = sca3000_write_reg(st, SCA3000_REG_CTRL_DATA_ADDR, val);
389
390 error_ret:
391 return ret;
392 }
393
394 /**
395 * sca3000_read_ctrl_reg() read from lock protected control register.
396 * @st: Driver specific device instance data.
397 * @ctrl_reg: Which ctrl register do we want to read.
398 *
399 * Lock must be held.
400 */
401 static int sca3000_read_ctrl_reg(struct sca3000_state *st,
402 u8 ctrl_reg)
403 {
404 int ret;
405
406 ret = sca3000_reg_lock_on(st);
407 if (ret < 0)
408 goto error_ret;
409 if (ret) {
410 ret = __sca3000_unlock_reg_lock(st);
411 if (ret)
412 goto error_ret;
413 }
414 /* Set the control select register */
415 ret = sca3000_write_reg(st, SCA3000_REG_CTRL_SEL_ADDR, ctrl_reg);
416 if (ret)
417 goto error_ret;
418 ret = sca3000_read_data_short(st, SCA3000_REG_CTRL_DATA_ADDR, 1);
419 if (ret)
420 goto error_ret;
421 return st->rx[0];
422 error_ret:
423 return ret;
424 }
425
426 /**
427 * sca3000_show_rev() - sysfs interface to read the chip revision number
428 * @indio_dev: Device instance specific generic IIO data.
429 * Driver specific device instance data can be obtained via
430 * via iio_priv(indio_dev)
431 */
432 static int sca3000_print_rev(struct iio_dev *indio_dev)
433 {
434 int ret;
435 struct sca3000_state *st = iio_priv(indio_dev);
436
437 mutex_lock(&st->lock);
438 ret = sca3000_read_data_short(st, SCA3000_REG_REVID_ADDR, 1);
439 if (ret < 0)
440 goto error_ret;
441 dev_info(&indio_dev->dev,
442 "sca3000 revision major=%lu, minor=%lu\n",
443 st->rx[0] & SCA3000_REG_REVID_MAJOR_MASK,
444 st->rx[0] & SCA3000_REG_REVID_MINOR_MASK);
445 error_ret:
446 mutex_unlock(&st->lock);
447
448 return ret;
449 }
450
451 static ssize_t
452 sca3000_show_available_3db_freqs(struct device *dev,
453 struct device_attribute *attr,
454 char *buf)
455 {
456 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
457 struct sca3000_state *st = iio_priv(indio_dev);
458 int len;
459
460 len = sprintf(buf, "%d", st->info->measurement_mode_3db_freq);
461 if (st->info->option_mode_1)
462 len += sprintf(buf + len, " %d",
463 st->info->option_mode_1_3db_freq);
464 if (st->info->option_mode_2)
465 len += sprintf(buf + len, " %d",
466 st->info->option_mode_2_3db_freq);
467 len += sprintf(buf + len, "\n");
468
469 return len;
470 }
471
472 static IIO_DEVICE_ATTR(in_accel_filter_low_pass_3db_frequency_available,
473 S_IRUGO, sca3000_show_available_3db_freqs,
474 NULL, 0);
475
476 static const struct iio_event_spec sca3000_event = {
477 .type = IIO_EV_TYPE_MAG,
478 .dir = IIO_EV_DIR_RISING,
479 .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT(IIO_EV_INFO_ENABLE),
480 };
481
482 /*
483 * Note the hack in the number of bits to pretend we have 2 more than
484 * we do in the fifo.
485 */
486 #define SCA3000_CHAN(index, mod) \
487 { \
488 .type = IIO_ACCEL, \
489 .modified = 1, \
490 .channel2 = mod, \
491 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
492 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |\
493 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),\
494 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
495 .address = index, \
496 .scan_index = index, \
497 .scan_type = { \
498 .sign = 's', \
499 .realbits = 13, \
500 .storagebits = 16, \
501 .shift = 3, \
502 .endianness = IIO_BE, \
503 }, \
504 .event_spec = &sca3000_event, \
505 .num_event_specs = 1, \
506 }
507
508 static const struct iio_event_spec sca3000_freefall_event_spec = {
509 .type = IIO_EV_TYPE_MAG,
510 .dir = IIO_EV_DIR_FALLING,
511 .mask_separate = BIT(IIO_EV_INFO_ENABLE) |
512 BIT(IIO_EV_INFO_PERIOD),
513 };
514
515 static const struct iio_chan_spec sca3000_channels[] = {
516 SCA3000_CHAN(0, IIO_MOD_X),
517 SCA3000_CHAN(1, IIO_MOD_Y),
518 SCA3000_CHAN(2, IIO_MOD_Z),
519 {
520 .type = IIO_ACCEL,
521 .modified = 1,
522 .channel2 = IIO_MOD_X_AND_Y_AND_Z,
523 .scan_index = -1, /* Fake channel */
524 .event_spec = &sca3000_freefall_event_spec,
525 .num_event_specs = 1,
526 },
527 };
528
529 static const struct iio_chan_spec sca3000_channels_with_temp[] = {
530 SCA3000_CHAN(0, IIO_MOD_X),
531 SCA3000_CHAN(1, IIO_MOD_Y),
532 SCA3000_CHAN(2, IIO_MOD_Z),
533 {
534 .type = IIO_TEMP,
535 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
536 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |
537 BIT(IIO_CHAN_INFO_OFFSET),
538 /* No buffer support */
539 .scan_index = -1,
540 },
541 {
542 .type = IIO_ACCEL,
543 .modified = 1,
544 .channel2 = IIO_MOD_X_AND_Y_AND_Z,
545 .scan_index = -1, /* Fake channel */
546 .event_spec = &sca3000_freefall_event_spec,
547 .num_event_specs = 1,
548 },
549 };
550
551 static u8 sca3000_addresses[3][3] = {
552 [0] = {SCA3000_REG_X_MSB_ADDR, SCA3000_REG_CTRL_SEL_MD_X_TH,
553 SCA3000_MD_CTRL_OR_X},
554 [1] = {SCA3000_REG_Y_MSB_ADDR, SCA3000_REG_CTRL_SEL_MD_Y_TH,
555 SCA3000_MD_CTRL_OR_Y},
556 [2] = {SCA3000_REG_Z_MSB_ADDR, SCA3000_REG_CTRL_SEL_MD_Z_TH,
557 SCA3000_MD_CTRL_OR_Z},
558 };
559
560 /**
561 * __sca3000_get_base_freq() - obtain mode specific base frequency
562 * @st: Private driver specific device instance specific state.
563 * @info: chip type specific information.
564 * @base_freq: Base frequency for the current measurement mode.
565 *
566 * lock must be held
567 */
568 static inline int __sca3000_get_base_freq(struct sca3000_state *st,
569 const struct sca3000_chip_info *info,
570 int *base_freq)
571 {
572 int ret;
573
574 ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
575 if (ret)
576 goto error_ret;
577 switch (SCA3000_REG_MODE_MODE_MASK & st->rx[0]) {
578 case SCA3000_REG_MODE_MEAS_MODE_NORMAL:
579 *base_freq = info->measurement_mode_freq;
580 break;
581 case SCA3000_REG_MODE_MEAS_MODE_OP_1:
582 *base_freq = info->option_mode_1_freq;
583 break;
584 case SCA3000_REG_MODE_MEAS_MODE_OP_2:
585 *base_freq = info->option_mode_2_freq;
586 break;
587 default:
588 ret = -EINVAL;
589 }
590 error_ret:
591 return ret;
592 }
593
594 /**
595 * sca3000_read_raw_samp_freq() - read_raw handler for IIO_CHAN_INFO_SAMP_FREQ
596 * @st: Private driver specific device instance specific state.
597 * @val: The frequency read back.
598 *
599 * lock must be held
600 **/
601 static int sca3000_read_raw_samp_freq(struct sca3000_state *st, int *val)
602 {
603 int ret;
604
605 ret = __sca3000_get_base_freq(st, st->info, val);
606 if (ret)
607 return ret;
608
609 ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL);
610 if (ret < 0)
611 return ret;
612
613 if (*val > 0) {
614 ret &= SCA3000_REG_OUT_CTRL_BUF_DIV_MASK;
615 switch (ret) {
616 case SCA3000_REG_OUT_CTRL_BUF_DIV_2:
617 *val /= 2;
618 break;
619 case SCA3000_REG_OUT_CTRL_BUF_DIV_4:
620 *val /= 4;
621 break;
622 }
623 }
624
625 return 0;
626 }
627
628 /**
629 * sca3000_write_raw_samp_freq() - write_raw handler for IIO_CHAN_INFO_SAMP_FREQ
630 * @st: Private driver specific device instance specific state.
631 * @val: The frequency desired.
632 *
633 * lock must be held
634 */
635 static int sca3000_write_raw_samp_freq(struct sca3000_state *st, int val)
636 {
637 int ret, base_freq, ctrlval;
638
639 ret = __sca3000_get_base_freq(st, st->info, &base_freq);
640 if (ret)
641 return ret;
642
643 ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL);
644 if (ret < 0)
645 return ret;
646
647 ctrlval = ret & ~SCA3000_REG_OUT_CTRL_BUF_DIV_MASK;
648
649 if (val == base_freq / 2)
650 ctrlval |= SCA3000_REG_OUT_CTRL_BUF_DIV_2;
651 if (val == base_freq / 4)
652 ctrlval |= SCA3000_REG_OUT_CTRL_BUF_DIV_4;
653 else if (val != base_freq)
654 return -EINVAL;
655
656 return sca3000_write_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL,
657 ctrlval);
658 }
659
660 static int sca3000_read_3db_freq(struct sca3000_state *st, int *val)
661 {
662 int ret;
663
664 ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
665 if (ret)
666 return ret;
667
668 /* mask bottom 2 bits - only ones that are relevant */
669 st->rx[0] &= SCA3000_REG_MODE_MODE_MASK;
670 switch (st->rx[0]) {
671 case SCA3000_REG_MODE_MEAS_MODE_NORMAL:
672 *val = st->info->measurement_mode_3db_freq;
673 return IIO_VAL_INT;
674 case SCA3000_REG_MODE_MEAS_MODE_MOT_DET:
675 return -EBUSY;
676 case SCA3000_REG_MODE_MEAS_MODE_OP_1:
677 *val = st->info->option_mode_1_3db_freq;
678 return IIO_VAL_INT;
679 case SCA3000_REG_MODE_MEAS_MODE_OP_2:
680 *val = st->info->option_mode_2_3db_freq;
681 return IIO_VAL_INT;
682 default:
683 return -EINVAL;
684 }
685 }
686
687 static int sca3000_write_3db_freq(struct sca3000_state *st, int val)
688 {
689 int ret;
690 int mode;
691
692 if (val == st->info->measurement_mode_3db_freq)
693 mode = SCA3000_REG_MODE_MEAS_MODE_NORMAL;
694 else if (st->info->option_mode_1 &&
695 (val == st->info->option_mode_1_3db_freq))
696 mode = SCA3000_REG_MODE_MEAS_MODE_OP_1;
697 else if (st->info->option_mode_2 &&
698 (val == st->info->option_mode_2_3db_freq))
699 mode = SCA3000_REG_MODE_MEAS_MODE_OP_2;
700 else
701 return -EINVAL;
702 ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
703 if (ret)
704 return ret;
705
706 st->rx[0] &= ~SCA3000_REG_MODE_MODE_MASK;
707 st->rx[0] |= (mode & SCA3000_REG_MODE_MODE_MASK);
708
709 return sca3000_write_reg(st, SCA3000_REG_MODE_ADDR, st->rx[0]);
710 }
711
712 static int sca3000_read_raw(struct iio_dev *indio_dev,
713 struct iio_chan_spec const *chan,
714 int *val,
715 int *val2,
716 long mask)
717 {
718 struct sca3000_state *st = iio_priv(indio_dev);
719 int ret;
720 u8 address;
721
722 switch (mask) {
723 case IIO_CHAN_INFO_RAW:
724 mutex_lock(&st->lock);
725 if (chan->type == IIO_ACCEL) {
726 if (st->mo_det_use_count) {
727 mutex_unlock(&st->lock);
728 return -EBUSY;
729 }
730 address = sca3000_addresses[chan->address][0];
731 ret = sca3000_read_data_short(st, address, 2);
732 if (ret < 0) {
733 mutex_unlock(&st->lock);
734 return ret;
735 }
736 *val = (be16_to_cpup((__be16 *)st->rx) >> 3) & 0x1FFF;
737 *val = ((*val) << (sizeof(*val) * 8 - 13)) >>
738 (sizeof(*val) * 8 - 13);
739 } else {
740 /* get the temperature when available */
741 ret = sca3000_read_data_short(st,
742 SCA3000_REG_TEMP_MSB_ADDR,
743 2);
744 if (ret < 0) {
745 mutex_unlock(&st->lock);
746 return ret;
747 }
748 *val = ((st->rx[0] & 0x3F) << 3) |
749 ((st->rx[1] & 0xE0) >> 5);
750 }
751 mutex_unlock(&st->lock);
752 return IIO_VAL_INT;
753 case IIO_CHAN_INFO_SCALE:
754 *val = 0;
755 if (chan->type == IIO_ACCEL)
756 *val2 = st->info->scale;
757 else /* temperature */
758 *val2 = 555556;
759 return IIO_VAL_INT_PLUS_MICRO;
760 case IIO_CHAN_INFO_OFFSET:
761 *val = -214;
762 *val2 = 600000;
763 return IIO_VAL_INT_PLUS_MICRO;
764 case IIO_CHAN_INFO_SAMP_FREQ:
765 mutex_lock(&st->lock);
766 ret = sca3000_read_raw_samp_freq(st, val);
767 mutex_unlock(&st->lock);
768 return ret ? ret : IIO_VAL_INT;
769 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
770 mutex_lock(&st->lock);
771 ret = sca3000_read_3db_freq(st, val);
772 mutex_unlock(&st->lock);
773 return ret;
774 default:
775 return -EINVAL;
776 }
777 }
778
779 static int sca3000_write_raw(struct iio_dev *indio_dev,
780 struct iio_chan_spec const *chan,
781 int val, int val2, long mask)
782 {
783 struct sca3000_state *st = iio_priv(indio_dev);
784 int ret;
785
786 switch (mask) {
787 case IIO_CHAN_INFO_SAMP_FREQ:
788 if (val2)
789 return -EINVAL;
790 mutex_lock(&st->lock);
791 ret = sca3000_write_raw_samp_freq(st, val);
792 mutex_unlock(&st->lock);
793 return ret;
794 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
795 if (val2)
796 return -EINVAL;
797 mutex_lock(&st->lock);
798 ret = sca3000_write_3db_freq(st, val);
799 mutex_unlock(&st->lock);
800 default:
801 return -EINVAL;
802 }
803
804 return ret;
805 }
806
807 /**
808 * sca3000_read_av_freq() - sysfs function to get available frequencies
809 * @dev: Device structure for this device.
810 * @attr: Description of the attribute.
811 * @buf: Incoming string
812 *
813 * The later modes are only relevant to the ring buffer - and depend on current
814 * mode. Note that data sheet gives rather wide tolerances for these so integer
815 * division will give good enough answer and not all chips have them specified
816 * at all.
817 **/
818 static ssize_t sca3000_read_av_freq(struct device *dev,
819 struct device_attribute *attr,
820 char *buf)
821 {
822 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
823 struct sca3000_state *st = iio_priv(indio_dev);
824 int len = 0, ret, val;
825
826 mutex_lock(&st->lock);
827 ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
828 val = st->rx[0];
829 mutex_unlock(&st->lock);
830 if (ret)
831 goto error_ret;
832
833 switch (val & SCA3000_REG_MODE_MODE_MASK) {
834 case SCA3000_REG_MODE_MEAS_MODE_NORMAL:
835 len += sprintf(buf + len, "%d %d %d\n",
836 st->info->measurement_mode_freq,
837 st->info->measurement_mode_freq / 2,
838 st->info->measurement_mode_freq / 4);
839 break;
840 case SCA3000_REG_MODE_MEAS_MODE_OP_1:
841 len += sprintf(buf + len, "%d %d %d\n",
842 st->info->option_mode_1_freq,
843 st->info->option_mode_1_freq / 2,
844 st->info->option_mode_1_freq / 4);
845 break;
846 case SCA3000_REG_MODE_MEAS_MODE_OP_2:
847 len += sprintf(buf + len, "%d %d %d\n",
848 st->info->option_mode_2_freq,
849 st->info->option_mode_2_freq / 2,
850 st->info->option_mode_2_freq / 4);
851 break;
852 }
853 return len;
854 error_ret:
855 return ret;
856 }
857
858 /*
859 * Should only really be registered if ring buffer support is compiled in.
860 * Does no harm however and doing it right would add a fair bit of complexity
861 */
862 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(sca3000_read_av_freq);
863
864 /**
865 * sca3000_read_event_value() - query of a threshold or period
866 **/
867 static int sca3000_read_event_value(struct iio_dev *indio_dev,
868 const struct iio_chan_spec *chan,
869 enum iio_event_type type,
870 enum iio_event_direction dir,
871 enum iio_event_info info,
872 int *val, int *val2)
873 {
874 int ret, i;
875 struct sca3000_state *st = iio_priv(indio_dev);
876
877 switch (info) {
878 case IIO_EV_INFO_VALUE:
879 mutex_lock(&st->lock);
880 ret = sca3000_read_ctrl_reg(st,
881 sca3000_addresses[chan->address][1]);
882 mutex_unlock(&st->lock);
883 if (ret < 0)
884 return ret;
885 *val = 0;
886 if (chan->channel2 == IIO_MOD_Y)
887 for_each_set_bit(i, (unsigned long *)&ret,
888 ARRAY_SIZE(st->info->mot_det_mult_y))
889 *val += st->info->mot_det_mult_y[i];
890 else
891 for_each_set_bit(i, (unsigned long *)&ret,
892 ARRAY_SIZE(st->info->mot_det_mult_xz))
893 *val += st->info->mot_det_mult_xz[i];
894
895 return IIO_VAL_INT;
896 case IIO_EV_INFO_PERIOD:
897 *val = 0;
898 *val2 = 226000;
899 return IIO_VAL_INT_PLUS_MICRO;
900 default:
901 return -EINVAL;
902 }
903 }
904
905 /**
906 * sca3000_write_value() - control of threshold and period
907 * @indio_dev: Device instance specific IIO information.
908 * @chan: Description of the channel for which the event is being
909 * configured.
910 * @type: The type of event being configured, here magnitude rising
911 * as everything else is read only.
912 * @dir: Direction of the event (here rising)
913 * @info: What information about the event are we configuring.
914 * Here the threshold only.
915 * @val: Integer part of the value being written..
916 * @val2: Non integer part of the value being written. Here always 0.
917 */
918 static int sca3000_write_event_value(struct iio_dev *indio_dev,
919 const struct iio_chan_spec *chan,
920 enum iio_event_type type,
921 enum iio_event_direction dir,
922 enum iio_event_info info,
923 int val, int val2)
924 {
925 struct sca3000_state *st = iio_priv(indio_dev);
926 int ret;
927 int i;
928 u8 nonlinear = 0;
929
930 if (chan->channel2 == IIO_MOD_Y) {
931 i = ARRAY_SIZE(st->info->mot_det_mult_y);
932 while (i > 0)
933 if (val >= st->info->mot_det_mult_y[--i]) {
934 nonlinear |= (1 << i);
935 val -= st->info->mot_det_mult_y[i];
936 }
937 } else {
938 i = ARRAY_SIZE(st->info->mot_det_mult_xz);
939 while (i > 0)
940 if (val >= st->info->mot_det_mult_xz[--i]) {
941 nonlinear |= (1 << i);
942 val -= st->info->mot_det_mult_xz[i];
943 }
944 }
945
946 mutex_lock(&st->lock);
947 ret = sca3000_write_ctrl_reg(st,
948 sca3000_addresses[chan->address][1],
949 nonlinear);
950 mutex_unlock(&st->lock);
951
952 return ret;
953 }
954
955 static struct attribute *sca3000_attributes[] = {
956 &iio_dev_attr_in_accel_filter_low_pass_3db_frequency_available.dev_attr.attr,
957 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
958 NULL,
959 };
960
961 static const struct attribute_group sca3000_attribute_group = {
962 .attrs = sca3000_attributes,
963 };
964
965 static int sca3000_read_data(struct sca3000_state *st,
966 u8 reg_address_high,
967 u8 *rx,
968 int len)
969 {
970 int ret;
971 struct spi_transfer xfer[2] = {
972 {
973 .len = 1,
974 .tx_buf = st->tx,
975 }, {
976 .len = len,
977 .rx_buf = rx,
978 }
979 };
980
981 st->tx[0] = SCA3000_READ_REG(reg_address_high);
982 ret = spi_sync_transfer(st->us, xfer, ARRAY_SIZE(xfer));
983 if (ret) {
984 dev_err(get_device(&st->us->dev), "problem reading register");
985 return ret;
986 }
987
988 return 0;
989 }
990
991 /**
992 * sca3000_ring_int_process() - ring specific interrupt handling.
993 * @val: Value of the interrupt status register.
994 * @indio_dev: Device instance specific IIO device structure.
995 */
996 static void sca3000_ring_int_process(u8 val, struct iio_dev *indio_dev)
997 {
998 struct sca3000_state *st = iio_priv(indio_dev);
999 int ret, i, num_available;
1000
1001 mutex_lock(&st->lock);
1002
1003 if (val & SCA3000_REG_INT_STATUS_HALF) {
1004 ret = sca3000_read_data_short(st, SCA3000_REG_BUF_COUNT_ADDR,
1005 1);
1006 if (ret)
1007 goto error_ret;
1008 num_available = st->rx[0];
1009 /*
1010 * num_available is the total number of samples available
1011 * i.e. number of time points * number of channels.
1012 */
1013 ret = sca3000_read_data(st, SCA3000_REG_RING_OUT_ADDR, st->rx,
1014 num_available * 2);
1015 if (ret)
1016 goto error_ret;
1017 for (i = 0; i < num_available / 3; i++) {
1018 /*
1019 * Dirty hack to cover for 11 bit in fifo, 13 bit
1020 * direct reading.
1021 *
1022 * In theory the bottom two bits are undefined.
1023 * In reality they appear to always be 0.
1024 */
1025 iio_push_to_buffers(indio_dev, st->rx + i * 3 * 2);
1026 }
1027 }
1028 error_ret:
1029 mutex_unlock(&st->lock);
1030 }
1031
1032 /**
1033 * sca3000_event_handler() - handling ring and non ring events
1034 * @irq: The irq being handled.
1035 * @private: struct iio_device pointer for the device.
1036 *
1037 * Ring related interrupt handler. Depending on event, push to
1038 * the ring buffer event chrdev or the event one.
1039 *
1040 * This function is complicated by the fact that the devices can signify ring
1041 * and non ring events via the same interrupt line and they can only
1042 * be distinguished via a read of the relevant status register.
1043 */
1044 static irqreturn_t sca3000_event_handler(int irq, void *private)
1045 {
1046 struct iio_dev *indio_dev = private;
1047 struct sca3000_state *st = iio_priv(indio_dev);
1048 int ret, val;
1049 s64 last_timestamp = iio_get_time_ns(indio_dev);
1050
1051 /*
1052 * Could lead if badly timed to an extra read of status reg,
1053 * but ensures no interrupt is missed.
1054 */
1055 mutex_lock(&st->lock);
1056 ret = sca3000_read_data_short(st, SCA3000_REG_INT_STATUS_ADDR, 1);
1057 val = st->rx[0];
1058 mutex_unlock(&st->lock);
1059 if (ret)
1060 goto done;
1061
1062 sca3000_ring_int_process(val, indio_dev);
1063
1064 if (val & SCA3000_INT_STATUS_FREE_FALL)
1065 iio_push_event(indio_dev,
1066 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1067 0,
1068 IIO_MOD_X_AND_Y_AND_Z,
1069 IIO_EV_TYPE_MAG,
1070 IIO_EV_DIR_FALLING),
1071 last_timestamp);
1072
1073 if (val & SCA3000_INT_STATUS_Y_TRIGGER)
1074 iio_push_event(indio_dev,
1075 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1076 0,
1077 IIO_MOD_Y,
1078 IIO_EV_TYPE_MAG,
1079 IIO_EV_DIR_RISING),
1080 last_timestamp);
1081
1082 if (val & SCA3000_INT_STATUS_X_TRIGGER)
1083 iio_push_event(indio_dev,
1084 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1085 0,
1086 IIO_MOD_X,
1087 IIO_EV_TYPE_MAG,
1088 IIO_EV_DIR_RISING),
1089 last_timestamp);
1090
1091 if (val & SCA3000_INT_STATUS_Z_TRIGGER)
1092 iio_push_event(indio_dev,
1093 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1094 0,
1095 IIO_MOD_Z,
1096 IIO_EV_TYPE_MAG,
1097 IIO_EV_DIR_RISING),
1098 last_timestamp);
1099
1100 done:
1101 return IRQ_HANDLED;
1102 }
1103
1104 /**
1105 * sca3000_read_event_config() what events are enabled
1106 **/
1107 static int sca3000_read_event_config(struct iio_dev *indio_dev,
1108 const struct iio_chan_spec *chan,
1109 enum iio_event_type type,
1110 enum iio_event_direction dir)
1111 {
1112 struct sca3000_state *st = iio_priv(indio_dev);
1113 int ret;
1114 /* read current value of mode register */
1115 mutex_lock(&st->lock);
1116
1117 ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
1118 if (ret)
1119 goto error_ret;
1120
1121 switch (chan->channel2) {
1122 case IIO_MOD_X_AND_Y_AND_Z:
1123 ret = !!(st->rx[0] & SCA3000_REG_MODE_FREE_FALL_DETECT);
1124 break;
1125 case IIO_MOD_X:
1126 case IIO_MOD_Y:
1127 case IIO_MOD_Z:
1128 /*
1129 * Motion detection mode cannot run at the same time as
1130 * acceleration data being read.
1131 */
1132 if ((st->rx[0] & SCA3000_REG_MODE_MODE_MASK)
1133 != SCA3000_REG_MODE_MEAS_MODE_MOT_DET) {
1134 ret = 0;
1135 } else {
1136 ret = sca3000_read_ctrl_reg(st,
1137 SCA3000_REG_CTRL_SEL_MD_CTRL);
1138 if (ret < 0)
1139 goto error_ret;
1140 /* only supporting logical or's for now */
1141 ret = !!(ret & sca3000_addresses[chan->address][2]);
1142 }
1143 break;
1144 default:
1145 ret = -EINVAL;
1146 }
1147
1148 error_ret:
1149 mutex_unlock(&st->lock);
1150
1151 return ret;
1152 }
1153
1154 static int sca3000_freefall_set_state(struct iio_dev *indio_dev, int state)
1155 {
1156 struct sca3000_state *st = iio_priv(indio_dev);
1157 int ret;
1158
1159 /* read current value of mode register */
1160 ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
1161 if (ret)
1162 return ret;
1163
1164 /* if off and should be on */
1165 if (state && !(st->rx[0] & SCA3000_REG_MODE_FREE_FALL_DETECT))
1166 return sca3000_write_reg(st, SCA3000_REG_MODE_ADDR,
1167 st->rx[0] | SCA3000_REG_MODE_FREE_FALL_DETECT);
1168 /* if on and should be off */
1169 else if (!state && (st->rx[0] & SCA3000_REG_MODE_FREE_FALL_DETECT))
1170 return sca3000_write_reg(st, SCA3000_REG_MODE_ADDR,
1171 st->rx[0] & ~SCA3000_REG_MODE_FREE_FALL_DETECT);
1172 else
1173 return 0;
1174 }
1175
1176 static int sca3000_motion_detect_set_state(struct iio_dev *indio_dev, int axis,
1177 int state)
1178 {
1179 struct sca3000_state *st = iio_priv(indio_dev);
1180 int ret, ctrlval;
1181
1182 /*
1183 * First read the motion detector config to find out if
1184 * this axis is on
1185 */
1186 ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_MD_CTRL);
1187 if (ret < 0)
1188 return ret;
1189 ctrlval = ret;
1190 /* if off and should be on */
1191 if (state && !(ctrlval & sca3000_addresses[axis][2])) {
1192 ret = sca3000_write_ctrl_reg(st,
1193 SCA3000_REG_CTRL_SEL_MD_CTRL,
1194 ctrlval |
1195 sca3000_addresses[axis][2]);
1196 if (ret)
1197 return ret;
1198 st->mo_det_use_count++;
1199 } else if (!state && (ctrlval & sca3000_addresses[axis][2])) {
1200 ret = sca3000_write_ctrl_reg(st,
1201 SCA3000_REG_CTRL_SEL_MD_CTRL,
1202 ctrlval &
1203 ~(sca3000_addresses[axis][2]));
1204 if (ret)
1205 return ret;
1206 st->mo_det_use_count--;
1207 }
1208
1209 /* read current value of mode register */
1210 ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
1211 if (ret)
1212 return ret;
1213 /* if off and should be on */
1214 if ((st->mo_det_use_count) &&
1215 ((st->rx[0] & SCA3000_REG_MODE_MODE_MASK)
1216 != SCA3000_REG_MODE_MEAS_MODE_MOT_DET))
1217 return sca3000_write_reg(st, SCA3000_REG_MODE_ADDR,
1218 (st->rx[0] & ~SCA3000_REG_MODE_MODE_MASK)
1219 | SCA3000_REG_MODE_MEAS_MODE_MOT_DET);
1220 /* if on and should be off */
1221 else if (!(st->mo_det_use_count) &&
1222 ((st->rx[0] & SCA3000_REG_MODE_MODE_MASK)
1223 == SCA3000_REG_MODE_MEAS_MODE_MOT_DET))
1224 return sca3000_write_reg(st, SCA3000_REG_MODE_ADDR,
1225 st->rx[0] & SCA3000_REG_MODE_MODE_MASK);
1226 else
1227 return 0;
1228 }
1229
1230 /**
1231 * sca3000_write_event_config() - simple on off control for motion detector
1232 * @indio_dev: IIO device instance specific structure. Data specific to this
1233 * particular driver may be accessed via iio_priv(indio_dev).
1234 * @chan: Description of the channel whose event we are configuring.
1235 * @type: The type of event.
1236 * @dir: The direction of the event.
1237 * @state: Desired state of event being configured.
1238 *
1239 * This is a per axis control, but enabling any will result in the
1240 * motion detector unit being enabled.
1241 * N.B. enabling motion detector stops normal data acquisition.
1242 * There is a complexity in knowing which mode to return to when
1243 * this mode is disabled. Currently normal mode is assumed.
1244 **/
1245 static int sca3000_write_event_config(struct iio_dev *indio_dev,
1246 const struct iio_chan_spec *chan,
1247 enum iio_event_type type,
1248 enum iio_event_direction dir,
1249 int state)
1250 {
1251 struct sca3000_state *st = iio_priv(indio_dev);
1252 int ret;
1253
1254 mutex_lock(&st->lock);
1255 switch (chan->channel2) {
1256 case IIO_MOD_X_AND_Y_AND_Z:
1257 ret = sca3000_freefall_set_state(indio_dev, state);
1258 break;
1259
1260 case IIO_MOD_X:
1261 case IIO_MOD_Y:
1262 case IIO_MOD_Z:
1263 ret = sca3000_motion_detect_set_state(indio_dev,
1264 chan->address,
1265 state);
1266 break;
1267 default:
1268 ret = -EINVAL;
1269 break;
1270 }
1271 mutex_unlock(&st->lock);
1272
1273 return ret;
1274 }
1275
1276 static int sca3000_configure_ring(struct iio_dev *indio_dev)
1277 {
1278 struct iio_buffer *buffer;
1279
1280 buffer = iio_kfifo_allocate();
1281 if (!buffer)
1282 return -ENOMEM;
1283
1284 iio_device_attach_buffer(indio_dev, buffer);
1285 indio_dev->modes |= INDIO_BUFFER_SOFTWARE;
1286
1287 return 0;
1288 }
1289
1290 static void sca3000_unconfigure_ring(struct iio_dev *indio_dev)
1291 {
1292 iio_kfifo_free(indio_dev->buffer);
1293 }
1294
1295 static inline
1296 int __sca3000_hw_ring_state_set(struct iio_dev *indio_dev, bool state)
1297 {
1298 struct sca3000_state *st = iio_priv(indio_dev);
1299 int ret;
1300
1301 mutex_lock(&st->lock);
1302 ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
1303 if (ret)
1304 goto error_ret;
1305 if (state) {
1306 dev_info(&indio_dev->dev, "supposedly enabling ring buffer\n");
1307 ret = sca3000_write_reg(st,
1308 SCA3000_REG_MODE_ADDR,
1309 (st->rx[0] | SCA3000_REG_MODE_RING_BUF_ENABLE));
1310 } else
1311 ret = sca3000_write_reg(st,
1312 SCA3000_REG_MODE_ADDR,
1313 (st->rx[0] & ~SCA3000_REG_MODE_RING_BUF_ENABLE));
1314 error_ret:
1315 mutex_unlock(&st->lock);
1316
1317 return ret;
1318 }
1319
1320 /**
1321 * sca3000_hw_ring_preenable() - hw ring buffer preenable function
1322 * @indio_dev: structure representing the IIO device. Device instance
1323 * specific state can be accessed via iio_priv(indio_dev).
1324 *
1325 * Very simple enable function as the chip will allows normal reads
1326 * during ring buffer operation so as long as it is indeed running
1327 * before we notify the core, the precise ordering does not matter.
1328 */
1329 static int sca3000_hw_ring_preenable(struct iio_dev *indio_dev)
1330 {
1331 int ret;
1332 struct sca3000_state *st = iio_priv(indio_dev);
1333
1334 mutex_lock(&st->lock);
1335
1336 /* Enable the 50% full interrupt */
1337 ret = sca3000_read_data_short(st, SCA3000_REG_INT_MASK_ADDR, 1);
1338 if (ret)
1339 goto error_unlock;
1340 ret = sca3000_write_reg(st,
1341 SCA3000_REG_INT_MASK_ADDR,
1342 st->rx[0] | SCA3000_REG_INT_MASK_RING_HALF);
1343 if (ret)
1344 goto error_unlock;
1345
1346 mutex_unlock(&st->lock);
1347
1348 return __sca3000_hw_ring_state_set(indio_dev, 1);
1349
1350 error_unlock:
1351 mutex_unlock(&st->lock);
1352
1353 return ret;
1354 }
1355
1356 static int sca3000_hw_ring_postdisable(struct iio_dev *indio_dev)
1357 {
1358 int ret;
1359 struct sca3000_state *st = iio_priv(indio_dev);
1360
1361 ret = __sca3000_hw_ring_state_set(indio_dev, 0);
1362 if (ret)
1363 return ret;
1364
1365 /* Disable the 50% full interrupt */
1366 mutex_lock(&st->lock);
1367
1368 ret = sca3000_read_data_short(st, SCA3000_REG_INT_MASK_ADDR, 1);
1369 if (ret)
1370 goto unlock;
1371 ret = sca3000_write_reg(st,
1372 SCA3000_REG_INT_MASK_ADDR,
1373 st->rx[0] & ~SCA3000_REG_INT_MASK_RING_HALF);
1374 unlock:
1375 mutex_unlock(&st->lock);
1376 return ret;
1377 }
1378
1379 static const struct iio_buffer_setup_ops sca3000_ring_setup_ops = {
1380 .preenable = &sca3000_hw_ring_preenable,
1381 .postdisable = &sca3000_hw_ring_postdisable,
1382 };
1383
1384 /**
1385 * sca3000_clean_setup() - get the device into a predictable state
1386 * @st: Device instance specific private data structure
1387 *
1388 * Devices use flash memory to store many of the register values
1389 * and hence can come up in somewhat unpredictable states.
1390 * Hence reset everything on driver load.
1391 */
1392 static int sca3000_clean_setup(struct sca3000_state *st)
1393 {
1394 int ret;
1395
1396 mutex_lock(&st->lock);
1397 /* Ensure all interrupts have been acknowledged */
1398 ret = sca3000_read_data_short(st, SCA3000_REG_INT_STATUS_ADDR, 1);
1399 if (ret)
1400 goto error_ret;
1401
1402 /* Turn off all motion detection channels */
1403 ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_MD_CTRL);
1404 if (ret < 0)
1405 goto error_ret;
1406 ret = sca3000_write_ctrl_reg(st, SCA3000_REG_CTRL_SEL_MD_CTRL,
1407 ret & SCA3000_MD_CTRL_PROT_MASK);
1408 if (ret)
1409 goto error_ret;
1410
1411 /* Disable ring buffer */
1412 ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL);
1413 if (ret < 0)
1414 goto error_ret;
1415 ret = sca3000_write_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL,
1416 (ret & SCA3000_REG_OUT_CTRL_PROT_MASK)
1417 | SCA3000_REG_OUT_CTRL_BUF_X_EN
1418 | SCA3000_REG_OUT_CTRL_BUF_Y_EN
1419 | SCA3000_REG_OUT_CTRL_BUF_Z_EN
1420 | SCA3000_REG_OUT_CTRL_BUF_DIV_4);
1421 if (ret)
1422 goto error_ret;
1423 /* Enable interrupts, relevant to mode and set up as active low */
1424 ret = sca3000_read_data_short(st, SCA3000_REG_INT_MASK_ADDR, 1);
1425 if (ret)
1426 goto error_ret;
1427 ret = sca3000_write_reg(st,
1428 SCA3000_REG_INT_MASK_ADDR,
1429 (ret & SCA3000_REG_INT_MASK_PROT_MASK)
1430 | SCA3000_REG_INT_MASK_ACTIVE_LOW);
1431 if (ret)
1432 goto error_ret;
1433 /*
1434 * Select normal measurement mode, free fall off, ring off
1435 * Ring in 12 bit mode - it is fine to overwrite reserved bits 3,5
1436 * as that occurs in one of the example on the datasheet
1437 */
1438 ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
1439 if (ret)
1440 goto error_ret;
1441 ret = sca3000_write_reg(st, SCA3000_REG_MODE_ADDR,
1442 (st->rx[0] & SCA3000_MODE_PROT_MASK));
1443
1444 error_ret:
1445 mutex_unlock(&st->lock);
1446 return ret;
1447 }
1448
1449 static const struct iio_info sca3000_info = {
1450 .attrs = &sca3000_attribute_group,
1451 .read_raw = &sca3000_read_raw,
1452 .write_raw = &sca3000_write_raw,
1453 .read_event_value = &sca3000_read_event_value,
1454 .write_event_value = &sca3000_write_event_value,
1455 .read_event_config = &sca3000_read_event_config,
1456 .write_event_config = &sca3000_write_event_config,
1457 };
1458
1459 static int sca3000_probe(struct spi_device *spi)
1460 {
1461 int ret;
1462 struct sca3000_state *st;
1463 struct iio_dev *indio_dev;
1464
1465 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
1466 if (!indio_dev)
1467 return -ENOMEM;
1468
1469 st = iio_priv(indio_dev);
1470 spi_set_drvdata(spi, indio_dev);
1471 st->us = spi;
1472 mutex_init(&st->lock);
1473 st->info = &sca3000_spi_chip_info_tbl[spi_get_device_id(spi)
1474 ->driver_data];
1475
1476 indio_dev->dev.parent = &spi->dev;
1477 indio_dev->name = spi_get_device_id(spi)->name;
1478 indio_dev->info = &sca3000_info;
1479 if (st->info->temp_output) {
1480 indio_dev->channels = sca3000_channels_with_temp;
1481 indio_dev->num_channels =
1482 ARRAY_SIZE(sca3000_channels_with_temp);
1483 } else {
1484 indio_dev->channels = sca3000_channels;
1485 indio_dev->num_channels = ARRAY_SIZE(sca3000_channels);
1486 }
1487 indio_dev->modes = INDIO_DIRECT_MODE;
1488
1489 sca3000_configure_ring(indio_dev);
1490
1491 if (spi->irq) {
1492 ret = request_threaded_irq(spi->irq,
1493 NULL,
1494 &sca3000_event_handler,
1495 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1496 "sca3000",
1497 indio_dev);
1498 if (ret)
1499 return ret;
1500 }
1501 indio_dev->setup_ops = &sca3000_ring_setup_ops;
1502 ret = sca3000_clean_setup(st);
1503 if (ret)
1504 goto error_free_irq;
1505
1506 ret = sca3000_print_rev(indio_dev);
1507 if (ret)
1508 goto error_free_irq;
1509
1510 return iio_device_register(indio_dev);
1511
1512 error_free_irq:
1513 if (spi->irq)
1514 free_irq(spi->irq, indio_dev);
1515
1516 return ret;
1517 }
1518
1519 static int sca3000_stop_all_interrupts(struct sca3000_state *st)
1520 {
1521 int ret;
1522
1523 mutex_lock(&st->lock);
1524 ret = sca3000_read_data_short(st, SCA3000_REG_INT_MASK_ADDR, 1);
1525 if (ret)
1526 goto error_ret;
1527 ret = sca3000_write_reg(st, SCA3000_REG_INT_MASK_ADDR,
1528 (st->rx[0] &
1529 ~(SCA3000_REG_INT_MASK_RING_THREE_QUARTER |
1530 SCA3000_REG_INT_MASK_RING_HALF |
1531 SCA3000_REG_INT_MASK_ALL_INTS)));
1532 error_ret:
1533 mutex_unlock(&st->lock);
1534 return ret;
1535 }
1536
1537 static int sca3000_remove(struct spi_device *spi)
1538 {
1539 struct iio_dev *indio_dev = spi_get_drvdata(spi);
1540 struct sca3000_state *st = iio_priv(indio_dev);
1541
1542 iio_device_unregister(indio_dev);
1543
1544 /* Must ensure no interrupts can be generated after this! */
1545 sca3000_stop_all_interrupts(st);
1546 if (spi->irq)
1547 free_irq(spi->irq, indio_dev);
1548
1549 sca3000_unconfigure_ring(indio_dev);
1550
1551 return 0;
1552 }
1553
1554 static const struct spi_device_id sca3000_id[] = {
1555 {"sca3000_d01", d01},
1556 {"sca3000_e02", e02},
1557 {"sca3000_e04", e04},
1558 {"sca3000_e05", e05},
1559 {}
1560 };
1561 MODULE_DEVICE_TABLE(spi, sca3000_id);
1562
1563 static struct spi_driver sca3000_driver = {
1564 .driver = {
1565 .name = "sca3000",
1566 },
1567 .probe = sca3000_probe,
1568 .remove = sca3000_remove,
1569 .id_table = sca3000_id,
1570 };
1571 module_spi_driver(sca3000_driver);
1572
1573 MODULE_AUTHOR("Jonathan Cameron <jic23@kernel.org>");
1574 MODULE_DESCRIPTION("VTI SCA3000 Series Accelerometers SPI driver");
1575 MODULE_LICENSE("GPL v2");
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