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[mirror_ubuntu-artful-kernel.git] / drivers / iio / accel / st_accel_core.c
1 /*
2 * STMicroelectronics accelerometers driver
3 *
4 * Copyright 2012-2013 STMicroelectronics Inc.
5 *
6 * Denis Ciocca <denis.ciocca@st.com>
7 *
8 * Licensed under the GPL-2.
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/slab.h>
14 #include <linux/errno.h>
15 #include <linux/types.h>
16 #include <linux/mutex.h>
17 #include <linux/interrupt.h>
18 #include <linux/i2c.h>
19 #include <linux/gpio.h>
20 #include <linux/irq.h>
21 #include <linux/iio/iio.h>
22 #include <linux/iio/sysfs.h>
23 #include <linux/iio/trigger.h>
24 #include <linux/iio/buffer.h>
25
26 #include <linux/iio/common/st_sensors.h>
27 #include "st_accel.h"
28
29 #define ST_ACCEL_NUMBER_DATA_CHANNELS 3
30
31 /* DEFAULT VALUE FOR SENSORS */
32 #define ST_ACCEL_DEFAULT_OUT_X_L_ADDR 0x28
33 #define ST_ACCEL_DEFAULT_OUT_Y_L_ADDR 0x2a
34 #define ST_ACCEL_DEFAULT_OUT_Z_L_ADDR 0x2c
35
36 /* FULLSCALE */
37 #define ST_ACCEL_FS_AVL_2G 2
38 #define ST_ACCEL_FS_AVL_4G 4
39 #define ST_ACCEL_FS_AVL_6G 6
40 #define ST_ACCEL_FS_AVL_8G 8
41 #define ST_ACCEL_FS_AVL_16G 16
42
43 /* CUSTOM VALUES FOR SENSOR 1 */
44 #define ST_ACCEL_1_WAI_EXP 0x33
45 #define ST_ACCEL_1_ODR_ADDR 0x20
46 #define ST_ACCEL_1_ODR_MASK 0xf0
47 #define ST_ACCEL_1_ODR_AVL_1HZ_VAL 0x01
48 #define ST_ACCEL_1_ODR_AVL_10HZ_VAL 0x02
49 #define ST_ACCEL_1_ODR_AVL_25HZ_VAL 0x03
50 #define ST_ACCEL_1_ODR_AVL_50HZ_VAL 0x04
51 #define ST_ACCEL_1_ODR_AVL_100HZ_VAL 0x05
52 #define ST_ACCEL_1_ODR_AVL_200HZ_VAL 0x06
53 #define ST_ACCEL_1_ODR_AVL_400HZ_VAL 0x07
54 #define ST_ACCEL_1_ODR_AVL_1600HZ_VAL 0x08
55 #define ST_ACCEL_1_FS_ADDR 0x23
56 #define ST_ACCEL_1_FS_MASK 0x30
57 #define ST_ACCEL_1_FS_AVL_2_VAL 0x00
58 #define ST_ACCEL_1_FS_AVL_4_VAL 0x01
59 #define ST_ACCEL_1_FS_AVL_8_VAL 0x02
60 #define ST_ACCEL_1_FS_AVL_16_VAL 0x03
61 #define ST_ACCEL_1_FS_AVL_2_GAIN IIO_G_TO_M_S_2(1000)
62 #define ST_ACCEL_1_FS_AVL_4_GAIN IIO_G_TO_M_S_2(2000)
63 #define ST_ACCEL_1_FS_AVL_8_GAIN IIO_G_TO_M_S_2(4000)
64 #define ST_ACCEL_1_FS_AVL_16_GAIN IIO_G_TO_M_S_2(12000)
65 #define ST_ACCEL_1_BDU_ADDR 0x23
66 #define ST_ACCEL_1_BDU_MASK 0x80
67 #define ST_ACCEL_1_DRDY_IRQ_ADDR 0x22
68 #define ST_ACCEL_1_DRDY_IRQ_INT1_MASK 0x10
69 #define ST_ACCEL_1_DRDY_IRQ_INT2_MASK 0x08
70 #define ST_ACCEL_1_MULTIREAD_BIT true
71
72 /* CUSTOM VALUES FOR SENSOR 2 */
73 #define ST_ACCEL_2_WAI_EXP 0x32
74 #define ST_ACCEL_2_ODR_ADDR 0x20
75 #define ST_ACCEL_2_ODR_MASK 0x18
76 #define ST_ACCEL_2_ODR_AVL_50HZ_VAL 0x00
77 #define ST_ACCEL_2_ODR_AVL_100HZ_VAL 0x01
78 #define ST_ACCEL_2_ODR_AVL_400HZ_VAL 0x02
79 #define ST_ACCEL_2_ODR_AVL_1000HZ_VAL 0x03
80 #define ST_ACCEL_2_PW_ADDR 0x20
81 #define ST_ACCEL_2_PW_MASK 0xe0
82 #define ST_ACCEL_2_FS_ADDR 0x23
83 #define ST_ACCEL_2_FS_MASK 0x30
84 #define ST_ACCEL_2_FS_AVL_2_VAL 0X00
85 #define ST_ACCEL_2_FS_AVL_4_VAL 0X01
86 #define ST_ACCEL_2_FS_AVL_8_VAL 0x03
87 #define ST_ACCEL_2_FS_AVL_2_GAIN IIO_G_TO_M_S_2(1000)
88 #define ST_ACCEL_2_FS_AVL_4_GAIN IIO_G_TO_M_S_2(2000)
89 #define ST_ACCEL_2_FS_AVL_8_GAIN IIO_G_TO_M_S_2(3900)
90 #define ST_ACCEL_2_BDU_ADDR 0x23
91 #define ST_ACCEL_2_BDU_MASK 0x80
92 #define ST_ACCEL_2_DRDY_IRQ_ADDR 0x22
93 #define ST_ACCEL_2_DRDY_IRQ_INT1_MASK 0x02
94 #define ST_ACCEL_2_DRDY_IRQ_INT2_MASK 0x10
95 #define ST_ACCEL_2_MULTIREAD_BIT true
96
97 /* CUSTOM VALUES FOR SENSOR 3 */
98 #define ST_ACCEL_3_WAI_EXP 0x40
99 #define ST_ACCEL_3_ODR_ADDR 0x20
100 #define ST_ACCEL_3_ODR_MASK 0xf0
101 #define ST_ACCEL_3_ODR_AVL_3HZ_VAL 0x01
102 #define ST_ACCEL_3_ODR_AVL_6HZ_VAL 0x02
103 #define ST_ACCEL_3_ODR_AVL_12HZ_VAL 0x03
104 #define ST_ACCEL_3_ODR_AVL_25HZ_VAL 0x04
105 #define ST_ACCEL_3_ODR_AVL_50HZ_VAL 0x05
106 #define ST_ACCEL_3_ODR_AVL_100HZ_VAL 0x06
107 #define ST_ACCEL_3_ODR_AVL_200HZ_VAL 0x07
108 #define ST_ACCEL_3_ODR_AVL_400HZ_VAL 0x08
109 #define ST_ACCEL_3_ODR_AVL_800HZ_VAL 0x09
110 #define ST_ACCEL_3_ODR_AVL_1600HZ_VAL 0x0a
111 #define ST_ACCEL_3_FS_ADDR 0x24
112 #define ST_ACCEL_3_FS_MASK 0x38
113 #define ST_ACCEL_3_FS_AVL_2_VAL 0X00
114 #define ST_ACCEL_3_FS_AVL_4_VAL 0X01
115 #define ST_ACCEL_3_FS_AVL_6_VAL 0x02
116 #define ST_ACCEL_3_FS_AVL_8_VAL 0x03
117 #define ST_ACCEL_3_FS_AVL_16_VAL 0x04
118 #define ST_ACCEL_3_FS_AVL_2_GAIN IIO_G_TO_M_S_2(61)
119 #define ST_ACCEL_3_FS_AVL_4_GAIN IIO_G_TO_M_S_2(122)
120 #define ST_ACCEL_3_FS_AVL_6_GAIN IIO_G_TO_M_S_2(183)
121 #define ST_ACCEL_3_FS_AVL_8_GAIN IIO_G_TO_M_S_2(244)
122 #define ST_ACCEL_3_FS_AVL_16_GAIN IIO_G_TO_M_S_2(732)
123 #define ST_ACCEL_3_BDU_ADDR 0x20
124 #define ST_ACCEL_3_BDU_MASK 0x08
125 #define ST_ACCEL_3_DRDY_IRQ_ADDR 0x23
126 #define ST_ACCEL_3_DRDY_IRQ_INT1_MASK 0x80
127 #define ST_ACCEL_3_DRDY_IRQ_INT2_MASK 0x00
128 #define ST_ACCEL_3_IG1_EN_ADDR 0x23
129 #define ST_ACCEL_3_IG1_EN_MASK 0x08
130 #define ST_ACCEL_3_MULTIREAD_BIT false
131
132 /* CUSTOM VALUES FOR SENSOR 4 */
133 #define ST_ACCEL_4_WAI_EXP 0x3a
134 #define ST_ACCEL_4_ODR_ADDR 0x20
135 #define ST_ACCEL_4_ODR_MASK 0x30 /* DF1 and DF0 */
136 #define ST_ACCEL_4_ODR_AVL_40HZ_VAL 0x00
137 #define ST_ACCEL_4_ODR_AVL_160HZ_VAL 0x01
138 #define ST_ACCEL_4_ODR_AVL_640HZ_VAL 0x02
139 #define ST_ACCEL_4_ODR_AVL_2560HZ_VAL 0x03
140 #define ST_ACCEL_4_PW_ADDR 0x20
141 #define ST_ACCEL_4_PW_MASK 0xc0
142 #define ST_ACCEL_4_FS_ADDR 0x21
143 #define ST_ACCEL_4_FS_MASK 0x80
144 #define ST_ACCEL_4_FS_AVL_2_VAL 0X00
145 #define ST_ACCEL_4_FS_AVL_6_VAL 0X01
146 #define ST_ACCEL_4_FS_AVL_2_GAIN IIO_G_TO_M_S_2(1024)
147 #define ST_ACCEL_4_FS_AVL_6_GAIN IIO_G_TO_M_S_2(340)
148 #define ST_ACCEL_4_BDU_ADDR 0x21
149 #define ST_ACCEL_4_BDU_MASK 0x40
150 #define ST_ACCEL_4_DRDY_IRQ_ADDR 0x21
151 #define ST_ACCEL_4_DRDY_IRQ_INT1_MASK 0x04
152 #define ST_ACCEL_4_MULTIREAD_BIT true
153
154 /* CUSTOM VALUES FOR SENSOR 5 */
155 #define ST_ACCEL_5_WAI_EXP 0x3b
156 #define ST_ACCEL_5_ODR_ADDR 0x20
157 #define ST_ACCEL_5_ODR_MASK 0x80
158 #define ST_ACCEL_5_ODR_AVL_100HZ_VAL 0x00
159 #define ST_ACCEL_5_ODR_AVL_400HZ_VAL 0x01
160 #define ST_ACCEL_5_PW_ADDR 0x20
161 #define ST_ACCEL_5_PW_MASK 0x40
162 #define ST_ACCEL_5_FS_ADDR 0x20
163 #define ST_ACCEL_5_FS_MASK 0x20
164 #define ST_ACCEL_5_FS_AVL_2_VAL 0X00
165 #define ST_ACCEL_5_FS_AVL_8_VAL 0X01
166 /* TODO: check these resulting gain settings, these are not in the datsheet */
167 #define ST_ACCEL_5_FS_AVL_2_GAIN IIO_G_TO_M_S_2(18000)
168 #define ST_ACCEL_5_FS_AVL_8_GAIN IIO_G_TO_M_S_2(72000)
169 #define ST_ACCEL_5_DRDY_IRQ_ADDR 0x22
170 #define ST_ACCEL_5_DRDY_IRQ_INT1_MASK 0x04
171 #define ST_ACCEL_5_DRDY_IRQ_INT2_MASK 0x20
172 #define ST_ACCEL_5_IG1_EN_ADDR 0x21
173 #define ST_ACCEL_5_IG1_EN_MASK 0x08
174 #define ST_ACCEL_5_MULTIREAD_BIT false
175
176 static const struct iio_chan_spec st_accel_8bit_channels[] = {
177 ST_SENSORS_LSM_CHANNELS(IIO_ACCEL,
178 BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
179 ST_SENSORS_SCAN_X, 1, IIO_MOD_X, 's', IIO_LE, 8, 8,
180 ST_ACCEL_DEFAULT_OUT_X_L_ADDR+1),
181 ST_SENSORS_LSM_CHANNELS(IIO_ACCEL,
182 BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
183 ST_SENSORS_SCAN_Y, 1, IIO_MOD_Y, 's', IIO_LE, 8, 8,
184 ST_ACCEL_DEFAULT_OUT_Y_L_ADDR+1),
185 ST_SENSORS_LSM_CHANNELS(IIO_ACCEL,
186 BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
187 ST_SENSORS_SCAN_Z, 1, IIO_MOD_Z, 's', IIO_LE, 8, 8,
188 ST_ACCEL_DEFAULT_OUT_Z_L_ADDR+1),
189 IIO_CHAN_SOFT_TIMESTAMP(3)
190 };
191
192 static const struct iio_chan_spec st_accel_12bit_channels[] = {
193 ST_SENSORS_LSM_CHANNELS(IIO_ACCEL,
194 BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
195 ST_SENSORS_SCAN_X, 1, IIO_MOD_X, 's', IIO_LE, 12, 16,
196 ST_ACCEL_DEFAULT_OUT_X_L_ADDR),
197 ST_SENSORS_LSM_CHANNELS(IIO_ACCEL,
198 BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
199 ST_SENSORS_SCAN_Y, 1, IIO_MOD_Y, 's', IIO_LE, 12, 16,
200 ST_ACCEL_DEFAULT_OUT_Y_L_ADDR),
201 ST_SENSORS_LSM_CHANNELS(IIO_ACCEL,
202 BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
203 ST_SENSORS_SCAN_Z, 1, IIO_MOD_Z, 's', IIO_LE, 12, 16,
204 ST_ACCEL_DEFAULT_OUT_Z_L_ADDR),
205 IIO_CHAN_SOFT_TIMESTAMP(3)
206 };
207
208 static const struct iio_chan_spec st_accel_16bit_channels[] = {
209 ST_SENSORS_LSM_CHANNELS(IIO_ACCEL,
210 BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
211 ST_SENSORS_SCAN_X, 1, IIO_MOD_X, 's', IIO_LE, 16, 16,
212 ST_ACCEL_DEFAULT_OUT_X_L_ADDR),
213 ST_SENSORS_LSM_CHANNELS(IIO_ACCEL,
214 BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
215 ST_SENSORS_SCAN_Y, 1, IIO_MOD_Y, 's', IIO_LE, 16, 16,
216 ST_ACCEL_DEFAULT_OUT_Y_L_ADDR),
217 ST_SENSORS_LSM_CHANNELS(IIO_ACCEL,
218 BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
219 ST_SENSORS_SCAN_Z, 1, IIO_MOD_Z, 's', IIO_LE, 16, 16,
220 ST_ACCEL_DEFAULT_OUT_Z_L_ADDR),
221 IIO_CHAN_SOFT_TIMESTAMP(3)
222 };
223
224 static const struct st_sensor_settings st_accel_sensors_settings[] = {
225 {
226 .wai = ST_ACCEL_1_WAI_EXP,
227 .wai_addr = ST_SENSORS_DEFAULT_WAI_ADDRESS,
228 .sensors_supported = {
229 [0] = LIS3DH_ACCEL_DEV_NAME,
230 [1] = LSM303DLHC_ACCEL_DEV_NAME,
231 [2] = LSM330D_ACCEL_DEV_NAME,
232 [3] = LSM330DL_ACCEL_DEV_NAME,
233 [4] = LSM330DLC_ACCEL_DEV_NAME,
234 [5] = LSM303AGR_ACCEL_DEV_NAME,
235 [6] = LIS2DH12_ACCEL_DEV_NAME,
236 },
237 .ch = (struct iio_chan_spec *)st_accel_12bit_channels,
238 .odr = {
239 .addr = ST_ACCEL_1_ODR_ADDR,
240 .mask = ST_ACCEL_1_ODR_MASK,
241 .odr_avl = {
242 { 1, ST_ACCEL_1_ODR_AVL_1HZ_VAL, },
243 { 10, ST_ACCEL_1_ODR_AVL_10HZ_VAL, },
244 { 25, ST_ACCEL_1_ODR_AVL_25HZ_VAL, },
245 { 50, ST_ACCEL_1_ODR_AVL_50HZ_VAL, },
246 { 100, ST_ACCEL_1_ODR_AVL_100HZ_VAL, },
247 { 200, ST_ACCEL_1_ODR_AVL_200HZ_VAL, },
248 { 400, ST_ACCEL_1_ODR_AVL_400HZ_VAL, },
249 { 1600, ST_ACCEL_1_ODR_AVL_1600HZ_VAL, },
250 },
251 },
252 .pw = {
253 .addr = ST_ACCEL_1_ODR_ADDR,
254 .mask = ST_ACCEL_1_ODR_MASK,
255 .value_off = ST_SENSORS_DEFAULT_POWER_OFF_VALUE,
256 },
257 .enable_axis = {
258 .addr = ST_SENSORS_DEFAULT_AXIS_ADDR,
259 .mask = ST_SENSORS_DEFAULT_AXIS_MASK,
260 },
261 .fs = {
262 .addr = ST_ACCEL_1_FS_ADDR,
263 .mask = ST_ACCEL_1_FS_MASK,
264 .fs_avl = {
265 [0] = {
266 .num = ST_ACCEL_FS_AVL_2G,
267 .value = ST_ACCEL_1_FS_AVL_2_VAL,
268 .gain = ST_ACCEL_1_FS_AVL_2_GAIN,
269 },
270 [1] = {
271 .num = ST_ACCEL_FS_AVL_4G,
272 .value = ST_ACCEL_1_FS_AVL_4_VAL,
273 .gain = ST_ACCEL_1_FS_AVL_4_GAIN,
274 },
275 [2] = {
276 .num = ST_ACCEL_FS_AVL_8G,
277 .value = ST_ACCEL_1_FS_AVL_8_VAL,
278 .gain = ST_ACCEL_1_FS_AVL_8_GAIN,
279 },
280 [3] = {
281 .num = ST_ACCEL_FS_AVL_16G,
282 .value = ST_ACCEL_1_FS_AVL_16_VAL,
283 .gain = ST_ACCEL_1_FS_AVL_16_GAIN,
284 },
285 },
286 },
287 .bdu = {
288 .addr = ST_ACCEL_1_BDU_ADDR,
289 .mask = ST_ACCEL_1_BDU_MASK,
290 },
291 .drdy_irq = {
292 .addr = ST_ACCEL_1_DRDY_IRQ_ADDR,
293 .mask_int1 = ST_ACCEL_1_DRDY_IRQ_INT1_MASK,
294 .mask_int2 = ST_ACCEL_1_DRDY_IRQ_INT2_MASK,
295 },
296 .multi_read_bit = ST_ACCEL_1_MULTIREAD_BIT,
297 .bootime = 2,
298 },
299 {
300 .wai = ST_ACCEL_2_WAI_EXP,
301 .wai_addr = ST_SENSORS_DEFAULT_WAI_ADDRESS,
302 .sensors_supported = {
303 [0] = LIS331DLH_ACCEL_DEV_NAME,
304 [1] = LSM303DL_ACCEL_DEV_NAME,
305 [2] = LSM303DLH_ACCEL_DEV_NAME,
306 [3] = LSM303DLM_ACCEL_DEV_NAME,
307 },
308 .ch = (struct iio_chan_spec *)st_accel_12bit_channels,
309 .odr = {
310 .addr = ST_ACCEL_2_ODR_ADDR,
311 .mask = ST_ACCEL_2_ODR_MASK,
312 .odr_avl = {
313 { 50, ST_ACCEL_2_ODR_AVL_50HZ_VAL, },
314 { 100, ST_ACCEL_2_ODR_AVL_100HZ_VAL, },
315 { 400, ST_ACCEL_2_ODR_AVL_400HZ_VAL, },
316 { 1000, ST_ACCEL_2_ODR_AVL_1000HZ_VAL, },
317 },
318 },
319 .pw = {
320 .addr = ST_ACCEL_2_PW_ADDR,
321 .mask = ST_ACCEL_2_PW_MASK,
322 .value_on = ST_SENSORS_DEFAULT_POWER_ON_VALUE,
323 .value_off = ST_SENSORS_DEFAULT_POWER_OFF_VALUE,
324 },
325 .enable_axis = {
326 .addr = ST_SENSORS_DEFAULT_AXIS_ADDR,
327 .mask = ST_SENSORS_DEFAULT_AXIS_MASK,
328 },
329 .fs = {
330 .addr = ST_ACCEL_2_FS_ADDR,
331 .mask = ST_ACCEL_2_FS_MASK,
332 .fs_avl = {
333 [0] = {
334 .num = ST_ACCEL_FS_AVL_2G,
335 .value = ST_ACCEL_2_FS_AVL_2_VAL,
336 .gain = ST_ACCEL_2_FS_AVL_2_GAIN,
337 },
338 [1] = {
339 .num = ST_ACCEL_FS_AVL_4G,
340 .value = ST_ACCEL_2_FS_AVL_4_VAL,
341 .gain = ST_ACCEL_2_FS_AVL_4_GAIN,
342 },
343 [2] = {
344 .num = ST_ACCEL_FS_AVL_8G,
345 .value = ST_ACCEL_2_FS_AVL_8_VAL,
346 .gain = ST_ACCEL_2_FS_AVL_8_GAIN,
347 },
348 },
349 },
350 .bdu = {
351 .addr = ST_ACCEL_2_BDU_ADDR,
352 .mask = ST_ACCEL_2_BDU_MASK,
353 },
354 .drdy_irq = {
355 .addr = ST_ACCEL_2_DRDY_IRQ_ADDR,
356 .mask_int1 = ST_ACCEL_2_DRDY_IRQ_INT1_MASK,
357 .mask_int2 = ST_ACCEL_2_DRDY_IRQ_INT2_MASK,
358 },
359 .multi_read_bit = ST_ACCEL_2_MULTIREAD_BIT,
360 .bootime = 2,
361 },
362 {
363 .wai = ST_ACCEL_3_WAI_EXP,
364 .wai_addr = ST_SENSORS_DEFAULT_WAI_ADDRESS,
365 .sensors_supported = {
366 [0] = LSM330_ACCEL_DEV_NAME,
367 },
368 .ch = (struct iio_chan_spec *)st_accel_16bit_channels,
369 .odr = {
370 .addr = ST_ACCEL_3_ODR_ADDR,
371 .mask = ST_ACCEL_3_ODR_MASK,
372 .odr_avl = {
373 { 3, ST_ACCEL_3_ODR_AVL_3HZ_VAL },
374 { 6, ST_ACCEL_3_ODR_AVL_6HZ_VAL, },
375 { 12, ST_ACCEL_3_ODR_AVL_12HZ_VAL, },
376 { 25, ST_ACCEL_3_ODR_AVL_25HZ_VAL, },
377 { 50, ST_ACCEL_3_ODR_AVL_50HZ_VAL, },
378 { 100, ST_ACCEL_3_ODR_AVL_100HZ_VAL, },
379 { 200, ST_ACCEL_3_ODR_AVL_200HZ_VAL, },
380 { 400, ST_ACCEL_3_ODR_AVL_400HZ_VAL, },
381 { 800, ST_ACCEL_3_ODR_AVL_800HZ_VAL, },
382 { 1600, ST_ACCEL_3_ODR_AVL_1600HZ_VAL, },
383 },
384 },
385 .pw = {
386 .addr = ST_ACCEL_3_ODR_ADDR,
387 .mask = ST_ACCEL_3_ODR_MASK,
388 .value_off = ST_SENSORS_DEFAULT_POWER_OFF_VALUE,
389 },
390 .enable_axis = {
391 .addr = ST_SENSORS_DEFAULT_AXIS_ADDR,
392 .mask = ST_SENSORS_DEFAULT_AXIS_MASK,
393 },
394 .fs = {
395 .addr = ST_ACCEL_3_FS_ADDR,
396 .mask = ST_ACCEL_3_FS_MASK,
397 .fs_avl = {
398 [0] = {
399 .num = ST_ACCEL_FS_AVL_2G,
400 .value = ST_ACCEL_3_FS_AVL_2_VAL,
401 .gain = ST_ACCEL_3_FS_AVL_2_GAIN,
402 },
403 [1] = {
404 .num = ST_ACCEL_FS_AVL_4G,
405 .value = ST_ACCEL_3_FS_AVL_4_VAL,
406 .gain = ST_ACCEL_3_FS_AVL_4_GAIN,
407 },
408 [2] = {
409 .num = ST_ACCEL_FS_AVL_6G,
410 .value = ST_ACCEL_3_FS_AVL_6_VAL,
411 .gain = ST_ACCEL_3_FS_AVL_6_GAIN,
412 },
413 [3] = {
414 .num = ST_ACCEL_FS_AVL_8G,
415 .value = ST_ACCEL_3_FS_AVL_8_VAL,
416 .gain = ST_ACCEL_3_FS_AVL_8_GAIN,
417 },
418 [4] = {
419 .num = ST_ACCEL_FS_AVL_16G,
420 .value = ST_ACCEL_3_FS_AVL_16_VAL,
421 .gain = ST_ACCEL_3_FS_AVL_16_GAIN,
422 },
423 },
424 },
425 .bdu = {
426 .addr = ST_ACCEL_3_BDU_ADDR,
427 .mask = ST_ACCEL_3_BDU_MASK,
428 },
429 .drdy_irq = {
430 .addr = ST_ACCEL_3_DRDY_IRQ_ADDR,
431 .mask_int1 = ST_ACCEL_3_DRDY_IRQ_INT1_MASK,
432 .mask_int2 = ST_ACCEL_3_DRDY_IRQ_INT2_MASK,
433 .ig1 = {
434 .en_addr = ST_ACCEL_3_IG1_EN_ADDR,
435 .en_mask = ST_ACCEL_3_IG1_EN_MASK,
436 },
437 },
438 .multi_read_bit = ST_ACCEL_3_MULTIREAD_BIT,
439 .bootime = 2,
440 },
441 {
442 .wai = ST_ACCEL_4_WAI_EXP,
443 .wai_addr = ST_SENSORS_DEFAULT_WAI_ADDRESS,
444 .sensors_supported = {
445 [0] = LIS3LV02DL_ACCEL_DEV_NAME,
446 },
447 .ch = (struct iio_chan_spec *)st_accel_12bit_channels,
448 .odr = {
449 .addr = ST_ACCEL_4_ODR_ADDR,
450 .mask = ST_ACCEL_4_ODR_MASK,
451 .odr_avl = {
452 { 40, ST_ACCEL_4_ODR_AVL_40HZ_VAL },
453 { 160, ST_ACCEL_4_ODR_AVL_160HZ_VAL, },
454 { 640, ST_ACCEL_4_ODR_AVL_640HZ_VAL, },
455 { 2560, ST_ACCEL_4_ODR_AVL_2560HZ_VAL, },
456 },
457 },
458 .pw = {
459 .addr = ST_ACCEL_4_PW_ADDR,
460 .mask = ST_ACCEL_4_PW_MASK,
461 .value_on = ST_SENSORS_DEFAULT_POWER_ON_VALUE,
462 .value_off = ST_SENSORS_DEFAULT_POWER_OFF_VALUE,
463 },
464 .enable_axis = {
465 .addr = ST_SENSORS_DEFAULT_AXIS_ADDR,
466 .mask = ST_SENSORS_DEFAULT_AXIS_MASK,
467 },
468 .fs = {
469 .addr = ST_ACCEL_4_FS_ADDR,
470 .mask = ST_ACCEL_4_FS_MASK,
471 .fs_avl = {
472 [0] = {
473 .num = ST_ACCEL_FS_AVL_2G,
474 .value = ST_ACCEL_4_FS_AVL_2_VAL,
475 .gain = ST_ACCEL_4_FS_AVL_2_GAIN,
476 },
477 [1] = {
478 .num = ST_ACCEL_FS_AVL_6G,
479 .value = ST_ACCEL_4_FS_AVL_6_VAL,
480 .gain = ST_ACCEL_4_FS_AVL_6_GAIN,
481 },
482 },
483 },
484 .bdu = {
485 .addr = ST_ACCEL_4_BDU_ADDR,
486 .mask = ST_ACCEL_4_BDU_MASK,
487 },
488 .drdy_irq = {
489 .addr = ST_ACCEL_4_DRDY_IRQ_ADDR,
490 .mask_int1 = ST_ACCEL_4_DRDY_IRQ_INT1_MASK,
491 },
492 .multi_read_bit = ST_ACCEL_4_MULTIREAD_BIT,
493 .bootime = 2, /* guess */
494 },
495 {
496 .wai = ST_ACCEL_5_WAI_EXP,
497 .wai_addr = ST_SENSORS_DEFAULT_WAI_ADDRESS,
498 .sensors_supported = {
499 [0] = LIS331DL_ACCEL_DEV_NAME,
500 },
501 .ch = (struct iio_chan_spec *)st_accel_8bit_channels,
502 .odr = {
503 .addr = ST_ACCEL_5_ODR_ADDR,
504 .mask = ST_ACCEL_5_ODR_MASK,
505 .odr_avl = {
506 { 100, ST_ACCEL_5_ODR_AVL_100HZ_VAL },
507 { 400, ST_ACCEL_5_ODR_AVL_400HZ_VAL, },
508 },
509 },
510 .pw = {
511 .addr = ST_ACCEL_5_PW_ADDR,
512 .mask = ST_ACCEL_5_PW_MASK,
513 .value_on = ST_SENSORS_DEFAULT_POWER_ON_VALUE,
514 .value_off = ST_SENSORS_DEFAULT_POWER_OFF_VALUE,
515 },
516 .enable_axis = {
517 .addr = ST_SENSORS_DEFAULT_AXIS_ADDR,
518 .mask = ST_SENSORS_DEFAULT_AXIS_MASK,
519 },
520 .fs = {
521 .addr = ST_ACCEL_5_FS_ADDR,
522 .mask = ST_ACCEL_5_FS_MASK,
523 .fs_avl = {
524 [0] = {
525 .num = ST_ACCEL_FS_AVL_2G,
526 .value = ST_ACCEL_5_FS_AVL_2_VAL,
527 .gain = ST_ACCEL_5_FS_AVL_2_GAIN,
528 },
529 [1] = {
530 .num = ST_ACCEL_FS_AVL_8G,
531 .value = ST_ACCEL_5_FS_AVL_8_VAL,
532 .gain = ST_ACCEL_5_FS_AVL_8_GAIN,
533 },
534 },
535 },
536 .drdy_irq = {
537 .addr = ST_ACCEL_5_DRDY_IRQ_ADDR,
538 .mask_int1 = ST_ACCEL_5_DRDY_IRQ_INT1_MASK,
539 .mask_int2 = ST_ACCEL_5_DRDY_IRQ_INT2_MASK,
540 },
541 .multi_read_bit = ST_ACCEL_5_MULTIREAD_BIT,
542 .bootime = 2, /* guess */
543 },
544 };
545
546 static int st_accel_read_raw(struct iio_dev *indio_dev,
547 struct iio_chan_spec const *ch, int *val,
548 int *val2, long mask)
549 {
550 int err;
551 struct st_sensor_data *adata = iio_priv(indio_dev);
552
553 switch (mask) {
554 case IIO_CHAN_INFO_RAW:
555 err = st_sensors_read_info_raw(indio_dev, ch, val);
556 if (err < 0)
557 goto read_error;
558
559 return IIO_VAL_INT;
560 case IIO_CHAN_INFO_SCALE:
561 *val = 0;
562 *val2 = adata->current_fullscale->gain;
563 return IIO_VAL_INT_PLUS_MICRO;
564 case IIO_CHAN_INFO_SAMP_FREQ:
565 *val = adata->odr;
566 return IIO_VAL_INT;
567 default:
568 return -EINVAL;
569 }
570
571 read_error:
572 return err;
573 }
574
575 static int st_accel_write_raw(struct iio_dev *indio_dev,
576 struct iio_chan_spec const *chan, int val, int val2, long mask)
577 {
578 int err;
579
580 switch (mask) {
581 case IIO_CHAN_INFO_SCALE:
582 err = st_sensors_set_fullscale_by_gain(indio_dev, val2);
583 break;
584 case IIO_CHAN_INFO_SAMP_FREQ:
585 if (val2)
586 return -EINVAL;
587 mutex_lock(&indio_dev->mlock);
588 err = st_sensors_set_odr(indio_dev, val);
589 mutex_unlock(&indio_dev->mlock);
590 return err;
591 default:
592 return -EINVAL;
593 }
594
595 return err;
596 }
597
598 static ST_SENSORS_DEV_ATTR_SAMP_FREQ_AVAIL();
599 static ST_SENSORS_DEV_ATTR_SCALE_AVAIL(in_accel_scale_available);
600
601 static struct attribute *st_accel_attributes[] = {
602 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
603 &iio_dev_attr_in_accel_scale_available.dev_attr.attr,
604 NULL,
605 };
606
607 static const struct attribute_group st_accel_attribute_group = {
608 .attrs = st_accel_attributes,
609 };
610
611 static const struct iio_info accel_info = {
612 .driver_module = THIS_MODULE,
613 .attrs = &st_accel_attribute_group,
614 .read_raw = &st_accel_read_raw,
615 .write_raw = &st_accel_write_raw,
616 .debugfs_reg_access = &st_sensors_debugfs_reg_access,
617 };
618
619 #ifdef CONFIG_IIO_TRIGGER
620 static const struct iio_trigger_ops st_accel_trigger_ops = {
621 .owner = THIS_MODULE,
622 .set_trigger_state = ST_ACCEL_TRIGGER_SET_STATE,
623 };
624 #define ST_ACCEL_TRIGGER_OPS (&st_accel_trigger_ops)
625 #else
626 #define ST_ACCEL_TRIGGER_OPS NULL
627 #endif
628
629 int st_accel_common_probe(struct iio_dev *indio_dev)
630 {
631 struct st_sensor_data *adata = iio_priv(indio_dev);
632 int irq = adata->get_irq_data_ready(indio_dev);
633 int err;
634
635 indio_dev->modes = INDIO_DIRECT_MODE;
636 indio_dev->info = &accel_info;
637 mutex_init(&adata->tb.buf_lock);
638
639 st_sensors_power_enable(indio_dev);
640
641 err = st_sensors_check_device_support(indio_dev,
642 ARRAY_SIZE(st_accel_sensors_settings),
643 st_accel_sensors_settings);
644 if (err < 0)
645 return err;
646
647 adata->num_data_channels = ST_ACCEL_NUMBER_DATA_CHANNELS;
648 adata->multiread_bit = adata->sensor_settings->multi_read_bit;
649 indio_dev->channels = adata->sensor_settings->ch;
650 indio_dev->num_channels = ST_SENSORS_NUMBER_ALL_CHANNELS;
651
652 adata->current_fullscale = (struct st_sensor_fullscale_avl *)
653 &adata->sensor_settings->fs.fs_avl[0];
654 adata->odr = adata->sensor_settings->odr.odr_avl[0].hz;
655
656 if (!adata->dev->platform_data)
657 adata->dev->platform_data =
658 (struct st_sensors_platform_data *)&default_accel_pdata;
659
660 err = st_sensors_init_sensor(indio_dev, adata->dev->platform_data);
661 if (err < 0)
662 return err;
663
664 err = st_accel_allocate_ring(indio_dev);
665 if (err < 0)
666 return err;
667
668 if (irq > 0) {
669 err = st_sensors_allocate_trigger(indio_dev,
670 ST_ACCEL_TRIGGER_OPS);
671 if (err < 0)
672 goto st_accel_probe_trigger_error;
673 }
674
675 err = iio_device_register(indio_dev);
676 if (err)
677 goto st_accel_device_register_error;
678
679 dev_info(&indio_dev->dev, "registered accelerometer %s\n",
680 indio_dev->name);
681
682 return 0;
683
684 st_accel_device_register_error:
685 if (irq > 0)
686 st_sensors_deallocate_trigger(indio_dev);
687 st_accel_probe_trigger_error:
688 st_accel_deallocate_ring(indio_dev);
689
690 return err;
691 }
692 EXPORT_SYMBOL(st_accel_common_probe);
693
694 void st_accel_common_remove(struct iio_dev *indio_dev)
695 {
696 struct st_sensor_data *adata = iio_priv(indio_dev);
697
698 st_sensors_power_disable(indio_dev);
699
700 iio_device_unregister(indio_dev);
701 if (adata->get_irq_data_ready(indio_dev) > 0)
702 st_sensors_deallocate_trigger(indio_dev);
703
704 st_accel_deallocate_ring(indio_dev);
705 }
706 EXPORT_SYMBOL(st_accel_common_remove);
707
708 MODULE_AUTHOR("Denis Ciocca <denis.ciocca@st.com>");
709 MODULE_DESCRIPTION("STMicroelectronics accelerometers driver");
710 MODULE_LICENSE("GPL v2");