drivers/iio/adc/max1027.c

   1  /*
   2   * iio/adc/max1027.c
   3   * Copyright (C) 2014 Philippe Reynes
   4   *
   5   * based on linux/drivers/iio/ad7923.c
   6   * Copyright 2011 Analog Devices Inc (from AD7923 Driver)
   7   * Copyright 2012 CS Systemes d'Information
   8   *
   9   * This program is free software; you can redistribute it and/or modify
  10   * it under the terms of the GNU General Public License version 2 as
  11   * published by the Free Software Foundation.
  12   *
  13   * max1027.c
  14   *
  15   * Partial support for max1027 and similar chips.
  16   */
  17
  18 #include <linux/kernel.h>
  19 #include <linux/module.h>
  20 #include <linux/spi/spi.h>
  21 #include <linux/delay.h>
  22
  23 #include <linux/iio/iio.h>
  24 #include <linux/iio/buffer.h>
  25 #include <linux/iio/trigger.h>
  26 #include <linux/iio/trigger_consumer.h>
  27 #include <linux/iio/triggered_buffer.h>
  28
  29 #define MAX1027_CONV_REG  BIT(7)
  30 #define MAX1027_SETUP_REG BIT(6)
  31 #define MAX1027_AVG_REG   BIT(5)
  32 #define MAX1027_RST_REG   BIT(4)
  33
  34 /* conversion register */
  35 #define MAX1027_TEMP      BIT(0)
  36 #define MAX1027_SCAN_0_N  (0x00 << 1)
  37 #define MAX1027_SCAN_N_M  (0x01 << 1)
  38 #define MAX1027_SCAN_N    (0x02 << 1)
  39 #define MAX1027_NOSCAN    (0x03 << 1)
  40 #define MAX1027_CHAN(n)   ((n) << 3)
  41
  42 /* setup register */
  43 #define MAX1027_UNIPOLAR  0x02
  44 #define MAX1027_BIPOLAR   0x03
  45 #define MAX1027_REF_MODE0 (0x00 << 2)
  46 #define MAX1027_REF_MODE1 (0x01 << 2)
  47 #define MAX1027_REF_MODE2 (0x02 << 2)
  48 #define MAX1027_REF_MODE3 (0x03 << 2)
  49 #define MAX1027_CKS_MODE0 (0x00 << 4)
  50 #define MAX1027_CKS_MODE1 (0x01 << 4)
  51 #define MAX1027_CKS_MODE2 (0x02 << 4)
  52 #define MAX1027_CKS_MODE3 (0x03 << 4)
  53
  54 /* averaging register */
  55 #define MAX1027_NSCAN_4   0x00
  56 #define MAX1027_NSCAN_8   0x01
  57 #define MAX1027_NSCAN_12  0x02
  58 #define MAX1027_NSCAN_16  0x03
  59 #define MAX1027_NAVG_4    (0x00 << 2)
  60 #define MAX1027_NAVG_8    (0x01 << 2)
  61 #define MAX1027_NAVG_16   (0x02 << 2)
  62 #define MAX1027_NAVG_32   (0x03 << 2)
  63 #define MAX1027_AVG_EN    BIT(4)
  64
  65 enum max1027_id {
  66         max1027,
  67         max1029,
  68         max1031,
  69 };
  70
  71 static const struct spi_device_id max1027_id[] = {
  72         {"max1027", max1027},
  73         {"max1029", max1029},
  74         {"max1031", max1031},
  75         {}
  76 };
  77 MODULE_DEVICE_TABLE(spi, max1027_id);
  78
  79 #ifdef CONFIG_OF
  80 static const struct of_device_id max1027_adc_dt_ids[] = {
  81         { .compatible = "maxim,max1027" },
  82         { .compatible = "maxim,max1029" },
  83         { .compatible = "maxim,max1031" },
  84         {},
  85 };
  86 MODULE_DEVICE_TABLE(of, max1027_adc_dt_ids);
  87 #endif
  88
  89 #define MAX1027_V_CHAN(index)                                           \
  90         {                                                               \
  91                 .type = IIO_VOLTAGE,                                    \
  92                 .indexed = 1,                                           \
  93                 .channel = index,                                       \
  94                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),           \
  95                 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),   \
  96                 .scan_index = index + 1,                                \
  97                 .scan_type = {                                          \
  98                         .sign = 'u',                                    \
  99                         .realbits = 10,                                 \
 100                         .storagebits = 16,                              \
 101                         .shift = 2,                                     \
 102                         .endianness = IIO_BE,                           \
 103                 },                                                      \
 104         }
 105
 106 #define MAX1027_T_CHAN                                                  \
 107         {                                                               \
 108                 .type = IIO_TEMP,                                       \
 109                 .channel = 0,                                           \
 110                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),           \
 111                 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),   \
 112                 .scan_index = 0,                                        \
 113                 .scan_type = {                                          \
 114                         .sign = 'u',                                    \
 115                         .realbits = 12,                                 \
 116                         .storagebits = 16,                              \
 117                         .endianness = IIO_BE,                           \
 118                 },                                                      \
 119         }
 120
 121 static const struct iio_chan_spec max1027_channels[] = {
 122         MAX1027_T_CHAN,
 123         MAX1027_V_CHAN(0),
 124         MAX1027_V_CHAN(1),
 125         MAX1027_V_CHAN(2),
 126         MAX1027_V_CHAN(3),
 127         MAX1027_V_CHAN(4),
 128         MAX1027_V_CHAN(5),
 129         MAX1027_V_CHAN(6),
 130         MAX1027_V_CHAN(7)
 131 };
 132
 133 static const struct iio_chan_spec max1029_channels[] = {
 134         MAX1027_T_CHAN,
 135         MAX1027_V_CHAN(0),
 136         MAX1027_V_CHAN(1),
 137         MAX1027_V_CHAN(2),
 138         MAX1027_V_CHAN(3),
 139         MAX1027_V_CHAN(4),
 140         MAX1027_V_CHAN(5),
 141         MAX1027_V_CHAN(6),
 142         MAX1027_V_CHAN(7),
 143         MAX1027_V_CHAN(8),
 144         MAX1027_V_CHAN(9),
 145         MAX1027_V_CHAN(10),
 146         MAX1027_V_CHAN(11)
 147 };
 148
 149 static const struct iio_chan_spec max1031_channels[] = {
 150         MAX1027_T_CHAN,
 151         MAX1027_V_CHAN(0),
 152         MAX1027_V_CHAN(1),
 153         MAX1027_V_CHAN(2),
 154         MAX1027_V_CHAN(3),
 155         MAX1027_V_CHAN(4),
 156         MAX1027_V_CHAN(5),
 157         MAX1027_V_CHAN(6),
 158         MAX1027_V_CHAN(7),
 159         MAX1027_V_CHAN(8),
 160         MAX1027_V_CHAN(9),
 161         MAX1027_V_CHAN(10),
 162         MAX1027_V_CHAN(11),
 163         MAX1027_V_CHAN(12),
 164         MAX1027_V_CHAN(13),
 165         MAX1027_V_CHAN(14),
 166         MAX1027_V_CHAN(15)
 167 };
 168
 169 static const unsigned long max1027_available_scan_masks[] = {
 170         0x000001ff,
 171         0x00000000,
 172 };
 173
 174 static const unsigned long max1029_available_scan_masks[] = {
 175         0x00001fff,
 176         0x00000000,
 177 };
 178
 179 static const unsigned long max1031_available_scan_masks[] = {
 180         0x0001ffff,
 181         0x00000000,
 182 };
 183
 184 struct max1027_chip_info {
 185         const struct iio_chan_spec *channels;
 186         unsigned int num_channels;
 187         const unsigned long *available_scan_masks;
 188 };
 189
 190 static const struct max1027_chip_info max1027_chip_info_tbl[] = {
 191         [max1027] = {
 192                 .channels = max1027_channels,
 193                 .num_channels = ARRAY_SIZE(max1027_channels),
 194                 .available_scan_masks = max1027_available_scan_masks,
 195         },
 196         [max1029] = {
 197                 .channels = max1029_channels,
 198                 .num_channels = ARRAY_SIZE(max1029_channels),
 199                 .available_scan_masks = max1029_available_scan_masks,
 200         },
 201         [max1031] = {
 202                 .channels = max1031_channels,
 203                 .num_channels = ARRAY_SIZE(max1031_channels),
 204                 .available_scan_masks = max1031_available_scan_masks,
 205         },
 206 };
 207
 208 struct max1027_state {
 209         const struct max1027_chip_info  *info;
 210         struct spi_device               *spi;
 211         struct iio_trigger              *trig;
 212         __be16                          *buffer;
 213         struct mutex                    lock;
 214
 215         u8                              reg ____cacheline_aligned;
 216 };
 217
 218 static int max1027_read_single_value(struct iio_dev *indio_dev,
 219                                      struct iio_chan_spec const *chan,
 220                                      int *val)
 221 {
 222         int ret;
 223         struct max1027_state *st = iio_priv(indio_dev);
 224
 225         if (iio_buffer_enabled(indio_dev)) {
 226                 dev_warn(&indio_dev->dev, "trigger mode already enabled");
 227                 return -EBUSY;
 228         }
 229
 230         /* Start acquisition on conversion register write */
 231         st->reg = MAX1027_SETUP_REG | MAX1027_REF_MODE2 | MAX1027_CKS_MODE2;
 232         ret = spi_write(st->spi, &st->reg, 1);
 233         if (ret < 0) {
 234                 dev_err(&indio_dev->dev,
 235                         "Failed to configure setup register\n");
 236                 return ret;
 237         }
 238
 239         /* Configure conversion register with the requested chan */
 240         st->reg = MAX1027_CONV_REG | MAX1027_CHAN(chan->channel) |
 241                   MAX1027_NOSCAN | !!(chan->type == IIO_TEMP);
 242         ret = spi_write(st->spi, &st->reg, 1);
 243         if (ret < 0) {
 244                 dev_err(&indio_dev->dev,
 245                         "Failed to configure conversion register\n");
 246                 return ret;
 247         }
 248
 249         /*
 250          * For an unknown reason, when we use the mode "10" (write
 251          * conversion register), the interrupt doesn't occur every time.
 252          * So we just wait 1 ms.
 253          */
 254         mdelay(1);
 255
 256         /* Read result */
 257         ret = spi_read(st->spi, st->buffer, (chan->type == IIO_TEMP) ? 4 : 2);
 258         if (ret < 0)
 259                 return ret;
 260
 261         *val = be16_to_cpu(st->buffer[0]);
 262
 263         return IIO_VAL_INT;
 264 }
 265
 266 static int max1027_read_raw(struct iio_dev *indio_dev,
 267                             struct iio_chan_spec const *chan,
 268                             int *val, int *val2, long mask)
 269 {
 270         int ret = 0;
 271         struct max1027_state *st = iio_priv(indio_dev);
 272
 273         mutex_lock(&st->lock);
 274
 275         switch (mask) {
 276         case IIO_CHAN_INFO_RAW:
 277                 ret = max1027_read_single_value(indio_dev, chan, val);
 278                 break;
 279         case IIO_CHAN_INFO_SCALE:
 280                 switch (chan->type) {
 281                 case IIO_TEMP:
 282                         *val = 1;
 283                         *val2 = 8;
 284                         ret = IIO_VAL_FRACTIONAL;
 285                         break;
 286                 case IIO_VOLTAGE:
 287                         *val = 2500;
 288                         *val2 = 10;
 289                         ret = IIO_VAL_FRACTIONAL_LOG2;
 290                         break;
 291                 default:
 292                         ret = -EINVAL;
 293                         break;
 294                 }
 295                 break;
 296         default:
 297                 ret = -EINVAL;
 298                 break;
 299         }
 300
 301         mutex_unlock(&st->lock);
 302
 303         return ret;
 304 }
 305
 306 static int max1027_debugfs_reg_access(struct iio_dev *indio_dev,
 307                                       unsigned reg, unsigned writeval,
 308                                       unsigned *readval)
 309 {
 310         struct max1027_state *st = iio_priv(indio_dev);
 311         u8 *val = (u8 *)st->buffer;
 312
 313         if (readval != NULL)
 314                 return -EINVAL;
 315
 316         *val = (u8)writeval;
 317         return spi_write(st->spi, val, 1);
 318 }
 319
 320 static int max1027_validate_trigger(struct iio_dev *indio_dev,
 321                                     struct iio_trigger *trig)
 322 {
 323         struct max1027_state *st = iio_priv(indio_dev);
 324
 325         if (st->trig != trig)
 326                 return -EINVAL;
 327
 328         return 0;
 329 }
 330
 331 static int max1027_set_trigger_state(struct iio_trigger *trig, bool state)
 332 {
 333         struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
 334         struct max1027_state *st = iio_priv(indio_dev);
 335         int ret;
 336
 337         if (state) {
 338                 /* Start acquisition on cnvst */
 339                 st->reg = MAX1027_SETUP_REG | MAX1027_CKS_MODE0 |
 340                           MAX1027_REF_MODE2;
 341                 ret = spi_write(st->spi, &st->reg, 1);
 342                 if (ret < 0)
 343                         return ret;
 344
 345                 /* Scan from 0 to max */
 346                 st->reg = MAX1027_CONV_REG | MAX1027_CHAN(0) |
 347                           MAX1027_SCAN_N_M | MAX1027_TEMP;
 348                 ret = spi_write(st->spi, &st->reg, 1);
 349                 if (ret < 0)
 350                         return ret;
 351         } else {
 352                 /* Start acquisition on conversion register write */
 353                 st->reg = MAX1027_SETUP_REG | MAX1027_CKS_MODE2 |
 354                           MAX1027_REF_MODE2;
 355                 ret = spi_write(st->spi, &st->reg, 1);
 356                 if (ret < 0)
 357                         return ret;
 358         }
 359
 360         return 0;
 361 }
 362
 363 static int max1027_validate_device(struct iio_trigger *trig,
 364                                    struct iio_dev *indio_dev)
 365 {
 366         struct iio_dev *indio = iio_trigger_get_drvdata(trig);
 367
 368         if (indio != indio_dev)
 369                 return -EINVAL;
 370
 371         return 0;
 372 }
 373
 374 static irqreturn_t max1027_trigger_handler(int irq, void *private)
 375 {
 376         struct iio_poll_func *pf = (struct iio_poll_func *)private;
 377         struct iio_dev *indio_dev = pf->indio_dev;
 378         struct max1027_state *st = iio_priv(indio_dev);
 379
 380         pr_debug("%s(irq=%d, private=0x%p)\n", __func__, irq, private);
 381
 382         /* fill buffer with all channel */
 383         spi_read(st->spi, st->buffer, indio_dev->masklength * 2);
 384
 385         iio_push_to_buffers(indio_dev, st->buffer);
 386
 387         iio_trigger_notify_done(indio_dev->trig);
 388
 389         return IRQ_HANDLED;
 390 }
 391
 392 static const struct iio_trigger_ops max1027_trigger_ops = {
 393         .owner = THIS_MODULE,
 394         .validate_device = &max1027_validate_device,
 395         .set_trigger_state = &max1027_set_trigger_state,
 396 };
 397
 398 static const struct iio_info max1027_info = {
 399         .driver_module = THIS_MODULE,
 400         .read_raw = &max1027_read_raw,
 401         .validate_trigger = &max1027_validate_trigger,
 402         .debugfs_reg_access = &max1027_debugfs_reg_access,
 403 };
 404
 405 static int max1027_probe(struct spi_device *spi)
 406 {
 407         int ret;
 408         struct iio_dev *indio_dev;
 409         struct max1027_state *st;
 410
 411         pr_debug("%s: probe(spi = 0x%p)\n", __func__, spi);
 412
 413         indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
 414         if (indio_dev == NULL) {
 415                 pr_err("Can't allocate iio device\n");
 416                 return -ENOMEM;
 417         }
 418
 419         spi_set_drvdata(spi, indio_dev);
 420
 421         st = iio_priv(indio_dev);
 422         st->spi = spi;
 423         st->info = &max1027_chip_info_tbl[spi_get_device_id(spi)->driver_data];
 424
 425         mutex_init(&st->lock);
 426
 427         indio_dev->name = spi_get_device_id(spi)->name;
 428         indio_dev->dev.parent = &spi->dev;
 429         indio_dev->info = &max1027_info;
 430         indio_dev->modes = INDIO_DIRECT_MODE;
 431         indio_dev->channels = st->info->channels;
 432         indio_dev->num_channels = st->info->num_channels;
 433         indio_dev->available_scan_masks = st->info->available_scan_masks;
 434
 435         st->buffer = devm_kmalloc(&indio_dev->dev,
 436                                   indio_dev->num_channels * 2,
 437                                   GFP_KERNEL);
 438         if (st->buffer == NULL) {
 439                 dev_err(&indio_dev->dev, "Can't allocate buffer\n");
 440                 return -ENOMEM;
 441         }
 442
 443         ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time,
 444                                          &max1027_trigger_handler, NULL);
 445         if (ret < 0) {
 446                 dev_err(&indio_dev->dev, "Failed to setup buffer\n");
 447                 return ret;
 448         }
 449
 450         st->trig = devm_iio_trigger_alloc(&spi->dev, "%s-trigger",
 451                                                         indio_dev->name);
 452         if (st->trig == NULL) {
 453                 ret = -ENOMEM;
 454                 dev_err(&indio_dev->dev, "Failed to allocate iio trigger\n");
 455                 goto fail_trigger_alloc;
 456         }
 457
 458         st->trig->ops = &max1027_trigger_ops;
 459         st->trig->dev.parent = &spi->dev;
 460         iio_trigger_set_drvdata(st->trig, indio_dev);
 461         iio_trigger_register(st->trig);
 462
 463         ret = devm_request_threaded_irq(&spi->dev, spi->irq,
 464                                         iio_trigger_generic_data_rdy_poll,
 465                                         NULL,
 466                                         IRQF_TRIGGER_FALLING,
 467                                         spi->dev.driver->name, st->trig);
 468         if (ret < 0) {
 469                 dev_err(&indio_dev->dev, "Failed to allocate IRQ.\n");
 470                 goto fail_dev_register;
 471         }
 472
 473         /* Disable averaging */
 474         st->reg = MAX1027_AVG_REG;
 475         ret = spi_write(st->spi, &st->reg, 1);
 476         if (ret < 0) {
 477                 dev_err(&indio_dev->dev, "Failed to configure averaging register\n");
 478                 goto fail_dev_register;
 479         }
 480
 481         ret = iio_device_register(indio_dev);
 482         if (ret < 0) {
 483                 dev_err(&indio_dev->dev, "Failed to register iio device\n");
 484                 goto fail_dev_register;
 485         }
 486
 487         return 0;
 488
 489 fail_dev_register:
 490 fail_trigger_alloc:
 491         iio_triggered_buffer_cleanup(indio_dev);
 492
 493         return ret;
 494 }
 495
 496 static int max1027_remove(struct spi_device *spi)
 497 {
 498         struct iio_dev *indio_dev = spi_get_drvdata(spi);
 499
 500         pr_debug("%s: remove(spi = 0x%p)\n", __func__, spi);
 501
 502         iio_device_unregister(indio_dev);
 503         iio_triggered_buffer_cleanup(indio_dev);
 504
 505         return 0;
 506 }
 507
 508 static struct spi_driver max1027_driver = {
 509         .driver = {
 510                 .name   = "max1027",
 511                 .of_match_table = of_match_ptr(max1027_adc_dt_ids),
 512         },
 513         .probe          = max1027_probe,
 514         .remove         = max1027_remove,
 515         .id_table       = max1027_id,
 516 };
 517 module_spi_driver(max1027_driver);
 518
 519 MODULE_AUTHOR("Philippe Reynes <tremyfr@yahoo.fr>");
 520 MODULE_DESCRIPTION("MAX1027/MAX1029/MAX1031 ADC");
 521 MODULE_LICENSE("GPL v2");