1 // SPDX-License-Identifier: GPL-2.0
3 * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
5 * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
8 #include <linux/bitfield.h>
10 #include <linux/clk-provider.h>
11 #include <linux/delay.h>
13 #include <linux/iio/iio.h>
14 #include <linux/module.h>
15 #include <linux/nvmem-consumer.h>
16 #include <linux/interrupt.h>
18 #include <linux/of_irq.h>
19 #include <linux/of_device.h>
20 #include <linux/platform_device.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/mfd/syscon.h>
25 #define MESON_SAR_ADC_REG0 0x00
26 #define MESON_SAR_ADC_REG0_PANEL_DETECT BIT(31)
27 #define MESON_SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28)
28 #define MESON_SAR_ADC_REG0_DELTA_BUSY BIT(30)
29 #define MESON_SAR_ADC_REG0_AVG_BUSY BIT(29)
30 #define MESON_SAR_ADC_REG0_SAMPLE_BUSY BIT(28)
31 #define MESON_SAR_ADC_REG0_FIFO_FULL BIT(27)
32 #define MESON_SAR_ADC_REG0_FIFO_EMPTY BIT(26)
33 #define MESON_SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)
34 #define MESON_SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19)
35 #define MESON_SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)
36 #define MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15)
37 #define MESON_SAR_ADC_REG0_SAMPLING_STOP BIT(14)
38 #define MESON_SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12)
39 #define MESON_SAR_ADC_REG0_DETECT_IRQ_POL BIT(10)
40 #define MESON_SAR_ADC_REG0_DETECT_IRQ_EN BIT(9)
41 #define MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)
42 #define MESON_SAR_ADC_REG0_FIFO_IRQ_EN BIT(3)
43 #define MESON_SAR_ADC_REG0_SAMPLING_START BIT(2)
44 #define MESON_SAR_ADC_REG0_CONTINUOUS_EN BIT(1)
45 #define MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0)
47 #define MESON_SAR_ADC_CHAN_LIST 0x04
48 #define MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)
49 #define MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(_chan) \
50 (GENMASK(2, 0) << ((_chan) * 3))
52 #define MESON_SAR_ADC_AVG_CNTL 0x08
53 #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \
55 #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \
56 (GENMASK(17, 16) << ((_chan) * 2))
57 #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \
59 #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \
60 (GENMASK(1, 0) << ((_chan) * 2))
62 #define MESON_SAR_ADC_REG3 0x0c
63 #define MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31)
64 #define MESON_SAR_ADC_REG3_CLK_EN BIT(30)
65 #define MESON_SAR_ADC_REG3_BL30_INITIALIZED BIT(28)
66 #define MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27)
67 #define MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26)
68 #define MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23)
69 #define MESON_SAR_ADC_REG3_DETECT_EN BIT(22)
70 #define MESON_SAR_ADC_REG3_ADC_EN BIT(21)
71 #define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
72 #define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
73 #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
74 #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
75 #define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
76 #define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
78 #define MESON_SAR_ADC_DELAY 0x10
79 #define MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24)
80 #define MESON_SAR_ADC_DELAY_BL30_BUSY BIT(15)
81 #define MESON_SAR_ADC_DELAY_KERNEL_BUSY BIT(14)
82 #define MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16)
83 #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8)
84 #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0)
86 #define MESON_SAR_ADC_LAST_RD 0x14
87 #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16)
88 #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0)
90 #define MESON_SAR_ADC_FIFO_RD 0x18
91 #define MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12)
92 #define MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0)
94 #define MESON_SAR_ADC_AUX_SW 0x1c
95 #define MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(_chan) \
96 (8 + (((_chan) - 2) * 3))
97 #define MESON_SAR_ADC_AUX_SW_VREF_P_MUX BIT(6)
98 #define MESON_SAR_ADC_AUX_SW_VREF_N_MUX BIT(5)
99 #define MESON_SAR_ADC_AUX_SW_MODE_SEL BIT(4)
100 #define MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3)
101 #define MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2)
102 #define MESON_SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1)
103 #define MESON_SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0)
105 #define MESON_SAR_ADC_CHAN_10_SW 0x20
106 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23)
107 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22)
108 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21)
109 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20)
110 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19)
111 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18)
112 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17)
113 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16)
114 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7)
115 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6)
116 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5)
117 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4)
118 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3)
119 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2)
120 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1)
121 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0)
123 #define MESON_SAR_ADC_DETECT_IDLE_SW 0x24
124 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26)
125 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK GENMASK(25, 23)
126 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_P_MUX BIT(22)
127 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_N_MUX BIT(21)
128 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20)
129 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YP_DRIVE_SW BIT(19)
130 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XP_DRIVE_SW BIT(18)
131 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YM_DRIVE_SW BIT(17)
132 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XM_DRIVE_SW BIT(16)
133 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK GENMASK(9, 7)
134 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_P_MUX BIT(6)
135 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_N_MUX BIT(5)
136 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4)
137 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YP_DRIVE_SW BIT(3)
138 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XP_DRIVE_SW BIT(2)
139 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YM_DRIVE_SW BIT(1)
140 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XM_DRIVE_SW BIT(0)
142 #define MESON_SAR_ADC_DELTA_10 0x28
143 #define MESON_SAR_ADC_DELTA_10_TEMP_SEL BIT(27)
144 #define MESON_SAR_ADC_DELTA_10_TS_REVE1 BIT(26)
145 #define MESON_SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16)
146 #define MESON_SAR_ADC_DELTA_10_TS_REVE0 BIT(15)
147 #define MESON_SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11)
148 #define MESON_SAR_ADC_DELTA_10_TS_VBG_EN BIT(10)
149 #define MESON_SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0)
152 * NOTE: registers from here are undocumented (the vendor Linux kernel driver
153 * and u-boot source served as reference). These only seem to be relevant on
156 #define MESON_SAR_ADC_REG11 0x2c
157 #define MESON_SAR_ADC_REG11_BANDGAP_EN BIT(13)
159 #define MESON_SAR_ADC_REG13 0x34
160 #define MESON_SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8)
162 #define MESON_SAR_ADC_MAX_FIFO_SIZE 32
163 #define MESON_SAR_ADC_TIMEOUT 100 /* ms */
164 #define MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL 6
165 #define MESON_SAR_ADC_TEMP_OFFSET 27
167 /* temperature sensor calibration information in eFuse */
168 #define MESON_SAR_ADC_EFUSE_BYTES 4
169 #define MESON_SAR_ADC_EFUSE_BYTE3_UPPER_ADC_VAL GENMASK(6, 0)
170 #define MESON_SAR_ADC_EFUSE_BYTE3_IS_CALIBRATED BIT(7)
172 #define MESON_HHI_DPLL_TOP_0 0x318
173 #define MESON_HHI_DPLL_TOP_0_TSC_BIT4 BIT(9)
175 /* for use with IIO_VAL_INT_PLUS_MICRO */
176 #define MILLION 1000000
178 #define MESON_SAR_ADC_CHAN(_chan) { \
179 .type = IIO_VOLTAGE, \
183 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
184 BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
185 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
186 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_CALIBBIAS) | \
187 BIT(IIO_CHAN_INFO_CALIBSCALE), \
188 .datasheet_name = "SAR_ADC_CH"#_chan, \
191 #define MESON_SAR_ADC_TEMP_CHAN(_chan) { \
194 .address = MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL, \
195 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
196 BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
197 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | \
198 BIT(IIO_CHAN_INFO_SCALE), \
199 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_CALIBBIAS) | \
200 BIT(IIO_CHAN_INFO_CALIBSCALE), \
201 .datasheet_name = "TEMP_SENSOR", \
204 static const struct iio_chan_spec meson_sar_adc_iio_channels
[] = {
205 MESON_SAR_ADC_CHAN(0),
206 MESON_SAR_ADC_CHAN(1),
207 MESON_SAR_ADC_CHAN(2),
208 MESON_SAR_ADC_CHAN(3),
209 MESON_SAR_ADC_CHAN(4),
210 MESON_SAR_ADC_CHAN(5),
211 MESON_SAR_ADC_CHAN(6),
212 MESON_SAR_ADC_CHAN(7),
213 IIO_CHAN_SOFT_TIMESTAMP(8),
216 static const struct iio_chan_spec meson_sar_adc_and_temp_iio_channels
[] = {
217 MESON_SAR_ADC_CHAN(0),
218 MESON_SAR_ADC_CHAN(1),
219 MESON_SAR_ADC_CHAN(2),
220 MESON_SAR_ADC_CHAN(3),
221 MESON_SAR_ADC_CHAN(4),
222 MESON_SAR_ADC_CHAN(5),
223 MESON_SAR_ADC_CHAN(6),
224 MESON_SAR_ADC_CHAN(7),
225 MESON_SAR_ADC_TEMP_CHAN(8),
226 IIO_CHAN_SOFT_TIMESTAMP(9),
229 enum meson_sar_adc_avg_mode
{
231 MEAN_AVERAGING
= 0x1,
232 MEDIAN_AVERAGING
= 0x2,
235 enum meson_sar_adc_num_samples
{
242 enum meson_sar_adc_chan7_mux_sel
{
244 CHAN7_MUX_VDD_DIV4
= 0x1,
245 CHAN7_MUX_VDD_DIV2
= 0x2,
246 CHAN7_MUX_VDD_MUL3_DIV4
= 0x3,
248 CHAN7_MUX_CH7_INPUT
= 0x7,
251 struct meson_sar_adc_param
{
252 bool has_bl30_integration
;
253 unsigned long clock_rate
;
255 unsigned int resolution
;
256 const struct regmap_config
*regmap_config
;
257 u8 temperature_trimming_bits
;
258 unsigned int temperature_multiplier
;
259 unsigned int temperature_divider
;
262 struct meson_sar_adc_data
{
263 const struct meson_sar_adc_param
*param
;
267 struct meson_sar_adc_priv
{
268 struct regmap
*regmap
;
269 struct regulator
*vref
;
270 const struct meson_sar_adc_param
*param
;
272 struct clk
*core_clk
;
273 struct clk
*adc_sel_clk
;
275 struct clk_gate clk_gate
;
276 struct clk
*adc_div_clk
;
277 struct clk_divider clk_div
;
278 struct completion done
;
281 struct regmap
*tsc_regmap
;
282 bool temperature_sensor_calibrated
;
283 u8 temperature_sensor_coefficient
;
284 u16 temperature_sensor_adc_val
;
287 static const struct regmap_config meson_sar_adc_regmap_config_gxbb
= {
291 .max_register
= MESON_SAR_ADC_REG13
,
294 static const struct regmap_config meson_sar_adc_regmap_config_meson8
= {
298 .max_register
= MESON_SAR_ADC_DELTA_10
,
301 static unsigned int meson_sar_adc_get_fifo_count(struct iio_dev
*indio_dev
)
303 struct meson_sar_adc_priv
*priv
= iio_priv(indio_dev
);
306 regmap_read(priv
->regmap
, MESON_SAR_ADC_REG0
, ®val
);
308 return FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK
, regval
);
311 static int meson_sar_adc_calib_val(struct iio_dev
*indio_dev
, int val
)
313 struct meson_sar_adc_priv
*priv
= iio_priv(indio_dev
);
316 /* use val_calib = scale * val_raw + offset calibration function */
317 tmp
= div_s64((s64
)val
* priv
->calibscale
, MILLION
) + priv
->calibbias
;
319 return clamp(tmp
, 0, (1 << priv
->param
->resolution
) - 1);
322 static int meson_sar_adc_wait_busy_clear(struct iio_dev
*indio_dev
)
324 struct meson_sar_adc_priv
*priv
= iio_priv(indio_dev
);
325 int regval
, timeout
= 10000;
328 * NOTE: we need a small delay before reading the status, otherwise
329 * the sample engine may not have started internally (which would
330 * seem to us that sampling is already finished).
334 regmap_read(priv
->regmap
, MESON_SAR_ADC_REG0
, ®val
);
335 } while (FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK
, regval
) && timeout
--);
343 static int meson_sar_adc_read_raw_sample(struct iio_dev
*indio_dev
,
344 const struct iio_chan_spec
*chan
,
347 struct meson_sar_adc_priv
*priv
= iio_priv(indio_dev
);
348 int regval
, fifo_chan
, fifo_val
, count
;
350 if(!wait_for_completion_timeout(&priv
->done
,
351 msecs_to_jiffies(MESON_SAR_ADC_TIMEOUT
)))
354 count
= meson_sar_adc_get_fifo_count(indio_dev
);
356 dev_err(&indio_dev
->dev
,
357 "ADC FIFO has %d element(s) instead of one\n", count
);
361 regmap_read(priv
->regmap
, MESON_SAR_ADC_FIFO_RD
, ®val
);
362 fifo_chan
= FIELD_GET(MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK
, regval
);
363 if (fifo_chan
!= chan
->address
) {
364 dev_err(&indio_dev
->dev
,
365 "ADC FIFO entry belongs to channel %d instead of %lu\n",
366 fifo_chan
, chan
->address
);
370 fifo_val
= FIELD_GET(MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK
, regval
);
371 fifo_val
&= GENMASK(priv
->param
->resolution
- 1, 0);
372 *val
= meson_sar_adc_calib_val(indio_dev
, fifo_val
);
377 static void meson_sar_adc_set_averaging(struct iio_dev
*indio_dev
,
378 const struct iio_chan_spec
*chan
,
379 enum meson_sar_adc_avg_mode mode
,
380 enum meson_sar_adc_num_samples samples
)
382 struct meson_sar_adc_priv
*priv
= iio_priv(indio_dev
);
383 int val
, address
= chan
->address
;
385 val
= samples
<< MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(address
);
386 regmap_update_bits(priv
->regmap
, MESON_SAR_ADC_AVG_CNTL
,
387 MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(address
),
390 val
= mode
<< MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(address
);
391 regmap_update_bits(priv
->regmap
, MESON_SAR_ADC_AVG_CNTL
,
392 MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(address
), val
);
395 static void meson_sar_adc_enable_channel(struct iio_dev
*indio_dev
,
396 const struct iio_chan_spec
*chan
)
398 struct meson_sar_adc_priv
*priv
= iio_priv(indio_dev
);
402 * the SAR ADC engine allows sampling multiple channels at the same
403 * time. to keep it simple we're only working with one *internal*
404 * channel, which starts counting at index 0 (which means: count = 1).
406 regval
= FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK
, 0);
407 regmap_update_bits(priv
->regmap
, MESON_SAR_ADC_CHAN_LIST
,
408 MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK
, regval
);
410 /* map channel index 0 to the channel which we want to read */
411 regval
= FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0),
413 regmap_update_bits(priv
->regmap
, MESON_SAR_ADC_CHAN_LIST
,
414 MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), regval
);
416 regval
= FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK
,
418 regmap_update_bits(priv
->regmap
, MESON_SAR_ADC_DETECT_IDLE_SW
,
419 MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK
,
422 regval
= FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK
,
424 regmap_update_bits(priv
->regmap
, MESON_SAR_ADC_DETECT_IDLE_SW
,
425 MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK
,
428 if (chan
->address
== MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL
) {
429 if (chan
->type
== IIO_TEMP
)
430 regval
= MESON_SAR_ADC_DELTA_10_TEMP_SEL
;
434 regmap_update_bits(priv
->regmap
,
435 MESON_SAR_ADC_DELTA_10
,
436 MESON_SAR_ADC_DELTA_10_TEMP_SEL
, regval
);
440 static void meson_sar_adc_set_chan7_mux(struct iio_dev
*indio_dev
,
441 enum meson_sar_adc_chan7_mux_sel sel
)
443 struct meson_sar_adc_priv
*priv
= iio_priv(indio_dev
);
446 regval
= FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK
, sel
);
447 regmap_update_bits(priv
->regmap
, MESON_SAR_ADC_REG3
,
448 MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK
, regval
);
450 usleep_range(10, 20);
453 static void meson_sar_adc_start_sample_engine(struct iio_dev
*indio_dev
)
455 struct meson_sar_adc_priv
*priv
= iio_priv(indio_dev
);
457 reinit_completion(&priv
->done
);
459 regmap_update_bits(priv
->regmap
, MESON_SAR_ADC_REG0
,
460 MESON_SAR_ADC_REG0_FIFO_IRQ_EN
,
461 MESON_SAR_ADC_REG0_FIFO_IRQ_EN
);
463 regmap_update_bits(priv
->regmap
, MESON_SAR_ADC_REG0
,
464 MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE
,
465 MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE
);
467 regmap_update_bits(priv
->regmap
, MESON_SAR_ADC_REG0
,
468 MESON_SAR_ADC_REG0_SAMPLING_START
,
469 MESON_SAR_ADC_REG0_SAMPLING_START
);
472 static void meson_sar_adc_stop_sample_engine(struct iio_dev
*indio_dev
)
474 struct meson_sar_adc_priv
*priv
= iio_priv(indio_dev
);
476 regmap_update_bits(priv
->regmap
, MESON_SAR_ADC_REG0
,
477 MESON_SAR_ADC_REG0_FIFO_IRQ_EN
, 0);
479 regmap_update_bits(priv
->regmap
, MESON_SAR_ADC_REG0
,
480 MESON_SAR_ADC_REG0_SAMPLING_STOP
,
481 MESON_SAR_ADC_REG0_SAMPLING_STOP
);
483 /* wait until all modules are stopped */
484 meson_sar_adc_wait_busy_clear(indio_dev
);
486 regmap_update_bits(priv
->regmap
, MESON_SAR_ADC_REG0
,
487 MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE
, 0);
490 static int meson_sar_adc_lock(struct iio_dev
*indio_dev
)
492 struct meson_sar_adc_priv
*priv
= iio_priv(indio_dev
);
493 int val
, timeout
= 10000;
495 mutex_lock(&indio_dev
->mlock
);
497 if (priv
->param
->has_bl30_integration
) {
498 /* prevent BL30 from using the SAR ADC while we are using it */
499 regmap_update_bits(priv
->regmap
, MESON_SAR_ADC_DELAY
,
500 MESON_SAR_ADC_DELAY_KERNEL_BUSY
,
501 MESON_SAR_ADC_DELAY_KERNEL_BUSY
);
504 * wait until BL30 releases it's lock (so we can use the SAR
509 regmap_read(priv
->regmap
, MESON_SAR_ADC_DELAY
, &val
);
510 } while (val
& MESON_SAR_ADC_DELAY_BL30_BUSY
&& timeout
--);
513 mutex_unlock(&indio_dev
->mlock
);
521 static void meson_sar_adc_unlock(struct iio_dev
*indio_dev
)
523 struct meson_sar_adc_priv
*priv
= iio_priv(indio_dev
);
525 if (priv
->param
->has_bl30_integration
)
526 /* allow BL30 to use the SAR ADC again */
527 regmap_update_bits(priv
->regmap
, MESON_SAR_ADC_DELAY
,
528 MESON_SAR_ADC_DELAY_KERNEL_BUSY
, 0);
530 mutex_unlock(&indio_dev
->mlock
);
533 static void meson_sar_adc_clear_fifo(struct iio_dev
*indio_dev
)
535 struct meson_sar_adc_priv
*priv
= iio_priv(indio_dev
);
536 unsigned int count
, tmp
;
538 for (count
= 0; count
< MESON_SAR_ADC_MAX_FIFO_SIZE
; count
++) {
539 if (!meson_sar_adc_get_fifo_count(indio_dev
))
542 regmap_read(priv
->regmap
, MESON_SAR_ADC_FIFO_RD
, &tmp
);
546 static int meson_sar_adc_get_sample(struct iio_dev
*indio_dev
,
547 const struct iio_chan_spec
*chan
,
548 enum meson_sar_adc_avg_mode avg_mode
,
549 enum meson_sar_adc_num_samples avg_samples
,
552 struct meson_sar_adc_priv
*priv
= iio_priv(indio_dev
);
555 if (chan
->type
== IIO_TEMP
&& !priv
->temperature_sensor_calibrated
)
558 ret
= meson_sar_adc_lock(indio_dev
);
562 /* clear the FIFO to make sure we're not reading old values */
563 meson_sar_adc_clear_fifo(indio_dev
);
565 meson_sar_adc_set_averaging(indio_dev
, chan
, avg_mode
, avg_samples
);
567 meson_sar_adc_enable_channel(indio_dev
, chan
);
569 meson_sar_adc_start_sample_engine(indio_dev
);
570 ret
= meson_sar_adc_read_raw_sample(indio_dev
, chan
, val
);
571 meson_sar_adc_stop_sample_engine(indio_dev
);
573 meson_sar_adc_unlock(indio_dev
);
576 dev_warn(indio_dev
->dev
.parent
,
577 "failed to read sample for channel %lu: %d\n",
585 static int meson_sar_adc_iio_info_read_raw(struct iio_dev
*indio_dev
,
586 const struct iio_chan_spec
*chan
,
587 int *val
, int *val2
, long mask
)
589 struct meson_sar_adc_priv
*priv
= iio_priv(indio_dev
);
593 case IIO_CHAN_INFO_RAW
:
594 return meson_sar_adc_get_sample(indio_dev
, chan
, NO_AVERAGING
,
598 case IIO_CHAN_INFO_AVERAGE_RAW
:
599 return meson_sar_adc_get_sample(indio_dev
, chan
,
600 MEAN_AVERAGING
, EIGHT_SAMPLES
,
604 case IIO_CHAN_INFO_SCALE
:
605 if (chan
->type
== IIO_VOLTAGE
) {
606 ret
= regulator_get_voltage(priv
->vref
);
608 dev_err(indio_dev
->dev
.parent
,
609 "failed to get vref voltage: %d\n",
615 *val2
= priv
->param
->resolution
;
616 return IIO_VAL_FRACTIONAL_LOG2
;
617 } else if (chan
->type
== IIO_TEMP
) {
618 /* SoC specific multiplier and divider */
619 *val
= priv
->param
->temperature_multiplier
;
620 *val2
= priv
->param
->temperature_divider
;
622 /* celsius to millicelsius */
625 return IIO_VAL_FRACTIONAL
;
630 case IIO_CHAN_INFO_CALIBBIAS
:
631 *val
= priv
->calibbias
;
634 case IIO_CHAN_INFO_CALIBSCALE
:
635 *val
= priv
->calibscale
/ MILLION
;
636 *val2
= priv
->calibscale
% MILLION
;
637 return IIO_VAL_INT_PLUS_MICRO
;
639 case IIO_CHAN_INFO_OFFSET
:
640 *val
= DIV_ROUND_CLOSEST(MESON_SAR_ADC_TEMP_OFFSET
*
641 priv
->param
->temperature_divider
,
642 priv
->param
->temperature_multiplier
);
643 *val
-= priv
->temperature_sensor_adc_val
;
651 static int meson_sar_adc_clk_init(struct iio_dev
*indio_dev
,
654 struct meson_sar_adc_priv
*priv
= iio_priv(indio_dev
);
655 struct clk_init_data init
;
656 const char *clk_parents
[1];
658 init
.name
= devm_kasprintf(&indio_dev
->dev
, GFP_KERNEL
, "%s#adc_div",
659 dev_name(indio_dev
->dev
.parent
));
664 init
.ops
= &clk_divider_ops
;
665 clk_parents
[0] = __clk_get_name(priv
->clkin
);
666 init
.parent_names
= clk_parents
;
667 init
.num_parents
= 1;
669 priv
->clk_div
.reg
= base
+ MESON_SAR_ADC_REG3
;
670 priv
->clk_div
.shift
= MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT
;
671 priv
->clk_div
.width
= MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH
;
672 priv
->clk_div
.hw
.init
= &init
;
673 priv
->clk_div
.flags
= 0;
675 priv
->adc_div_clk
= devm_clk_register(&indio_dev
->dev
,
677 if (WARN_ON(IS_ERR(priv
->adc_div_clk
)))
678 return PTR_ERR(priv
->adc_div_clk
);
680 init
.name
= devm_kasprintf(&indio_dev
->dev
, GFP_KERNEL
, "%s#adc_en",
681 dev_name(indio_dev
->dev
.parent
));
685 init
.flags
= CLK_SET_RATE_PARENT
;
686 init
.ops
= &clk_gate_ops
;
687 clk_parents
[0] = __clk_get_name(priv
->adc_div_clk
);
688 init
.parent_names
= clk_parents
;
689 init
.num_parents
= 1;
691 priv
->clk_gate
.reg
= base
+ MESON_SAR_ADC_REG3
;
692 priv
->clk_gate
.bit_idx
= __ffs(MESON_SAR_ADC_REG3_CLK_EN
);
693 priv
->clk_gate
.hw
.init
= &init
;
695 priv
->adc_clk
= devm_clk_register(&indio_dev
->dev
, &priv
->clk_gate
.hw
);
696 if (WARN_ON(IS_ERR(priv
->adc_clk
)))
697 return PTR_ERR(priv
->adc_clk
);
702 static int meson_sar_adc_temp_sensor_init(struct iio_dev
*indio_dev
)
704 struct meson_sar_adc_priv
*priv
= iio_priv(indio_dev
);
705 u8
*buf
, trimming_bits
, trimming_mask
, upper_adc_val
;
706 struct nvmem_cell
*temperature_calib
;
710 temperature_calib
= devm_nvmem_cell_get(&indio_dev
->dev
,
711 "temperature_calib");
712 if (IS_ERR(temperature_calib
)) {
713 ret
= PTR_ERR(temperature_calib
);
716 * leave the temperature sensor disabled if no calibration data
717 * was passed via nvmem-cells.
722 return dev_err_probe(indio_dev
->dev
.parent
, ret
,
723 "failed to get temperature_calib cell\n");
727 syscon_regmap_lookup_by_phandle(indio_dev
->dev
.parent
->of_node
,
728 "amlogic,hhi-sysctrl");
729 if (IS_ERR(priv
->tsc_regmap
)) {
730 dev_err(indio_dev
->dev
.parent
,
731 "failed to get amlogic,hhi-sysctrl regmap\n");
732 return PTR_ERR(priv
->tsc_regmap
);
735 read_len
= MESON_SAR_ADC_EFUSE_BYTES
;
736 buf
= nvmem_cell_read(temperature_calib
, &read_len
);
738 dev_err(indio_dev
->dev
.parent
,
739 "failed to read temperature_calib cell\n");
741 } else if (read_len
!= MESON_SAR_ADC_EFUSE_BYTES
) {
743 dev_err(indio_dev
->dev
.parent
,
744 "invalid read size of temperature_calib cell\n");
748 trimming_bits
= priv
->param
->temperature_trimming_bits
;
749 trimming_mask
= BIT(trimming_bits
) - 1;
751 priv
->temperature_sensor_calibrated
=
752 buf
[3] & MESON_SAR_ADC_EFUSE_BYTE3_IS_CALIBRATED
;
753 priv
->temperature_sensor_coefficient
= buf
[2] & trimming_mask
;
755 upper_adc_val
= FIELD_GET(MESON_SAR_ADC_EFUSE_BYTE3_UPPER_ADC_VAL
,
758 priv
->temperature_sensor_adc_val
= buf
[2];
759 priv
->temperature_sensor_adc_val
|= upper_adc_val
<< BITS_PER_BYTE
;
760 priv
->temperature_sensor_adc_val
>>= trimming_bits
;
767 static int meson_sar_adc_init(struct iio_dev
*indio_dev
)
769 struct meson_sar_adc_priv
*priv
= iio_priv(indio_dev
);
773 * make sure we start at CH7 input since the other muxes are only used
774 * for internal calibration.
776 meson_sar_adc_set_chan7_mux(indio_dev
, CHAN7_MUX_CH7_INPUT
);
778 if (priv
->param
->has_bl30_integration
) {
780 * leave sampling delay and the input clocks as configured by
781 * BL30 to make sure BL30 gets the values it expects when
782 * reading the temperature sensor.
784 regmap_read(priv
->regmap
, MESON_SAR_ADC_REG3
, ®val
);
785 if (regval
& MESON_SAR_ADC_REG3_BL30_INITIALIZED
)
789 meson_sar_adc_stop_sample_engine(indio_dev
);
792 * disable this bit as seems to be only relevant for Meson6 (based
793 * on the vendor driver), which we don't support at the moment.
795 regmap_update_bits(priv
->regmap
, MESON_SAR_ADC_REG0
,
796 MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL
, 0);
798 /* disable all channels by default */
799 regmap_write(priv
->regmap
, MESON_SAR_ADC_CHAN_LIST
, 0x0);
801 regmap_update_bits(priv
->regmap
, MESON_SAR_ADC_REG3
,
802 MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE
, 0);
803 regmap_update_bits(priv
->regmap
, MESON_SAR_ADC_REG3
,
804 MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY
,
805 MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY
);
807 /* delay between two samples = (10+1) * 1uS */
808 regmap_update_bits(priv
->regmap
, MESON_SAR_ADC_DELAY
,
809 MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK
,
810 FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK
,
812 regmap_update_bits(priv
->regmap
, MESON_SAR_ADC_DELAY
,
813 MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK
,
814 FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK
,
817 /* delay between two samples = (10+1) * 1uS */
818 regmap_update_bits(priv
->regmap
, MESON_SAR_ADC_DELAY
,
819 MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK
,
820 FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK
,
822 regmap_update_bits(priv
->regmap
, MESON_SAR_ADC_DELAY
,
823 MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK
,
824 FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK
,
828 * set up the input channel muxes in MESON_SAR_ADC_CHAN_10_SW
829 * (0 = SAR_ADC_CH0, 1 = SAR_ADC_CH1)
831 regval
= FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK
, 0);
832 regmap_update_bits(priv
->regmap
, MESON_SAR_ADC_CHAN_10_SW
,
833 MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK
,
835 regval
= FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK
, 1);
836 regmap_update_bits(priv
->regmap
, MESON_SAR_ADC_CHAN_10_SW
,
837 MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK
,
841 * set up the input channel muxes in MESON_SAR_ADC_AUX_SW
842 * (2 = SAR_ADC_CH2, 3 = SAR_ADC_CH3, ...) and enable
843 * MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW and
844 * MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW like the vendor driver.
847 for (i
= 2; i
<= 7; i
++)
848 regval
|= i
<< MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(i
);
849 regval
|= MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW
;
850 regval
|= MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW
;
851 regmap_write(priv
->regmap
, MESON_SAR_ADC_AUX_SW
, regval
);
853 if (priv
->temperature_sensor_calibrated
) {
854 regmap_update_bits(priv
->regmap
, MESON_SAR_ADC_DELTA_10
,
855 MESON_SAR_ADC_DELTA_10_TS_REVE1
,
856 MESON_SAR_ADC_DELTA_10_TS_REVE1
);
857 regmap_update_bits(priv
->regmap
, MESON_SAR_ADC_DELTA_10
,
858 MESON_SAR_ADC_DELTA_10_TS_REVE0
,
859 MESON_SAR_ADC_DELTA_10_TS_REVE0
);
862 * set bits [3:0] of the TSC (temperature sensor coefficient)
863 * to get the correct values when reading the temperature.
865 regval
= FIELD_PREP(MESON_SAR_ADC_DELTA_10_TS_C_MASK
,
866 priv
->temperature_sensor_coefficient
);
867 regmap_update_bits(priv
->regmap
, MESON_SAR_ADC_DELTA_10
,
868 MESON_SAR_ADC_DELTA_10_TS_C_MASK
, regval
);
870 if (priv
->param
->temperature_trimming_bits
== 5) {
871 if (priv
->temperature_sensor_coefficient
& BIT(4))
872 regval
= MESON_HHI_DPLL_TOP_0_TSC_BIT4
;
877 * bit [4] (the 5th bit when starting to count at 1)
878 * of the TSC is located in the HHI register area.
880 regmap_update_bits(priv
->tsc_regmap
,
881 MESON_HHI_DPLL_TOP_0
,
882 MESON_HHI_DPLL_TOP_0_TSC_BIT4
,
886 regmap_update_bits(priv
->regmap
, MESON_SAR_ADC_DELTA_10
,
887 MESON_SAR_ADC_DELTA_10_TS_REVE1
, 0);
888 regmap_update_bits(priv
->regmap
, MESON_SAR_ADC_DELTA_10
,
889 MESON_SAR_ADC_DELTA_10_TS_REVE0
, 0);
892 ret
= clk_set_parent(priv
->adc_sel_clk
, priv
->clkin
);
894 dev_err(indio_dev
->dev
.parent
,
895 "failed to set adc parent to clkin\n");
899 ret
= clk_set_rate(priv
->adc_clk
, priv
->param
->clock_rate
);
901 dev_err(indio_dev
->dev
.parent
,
902 "failed to set adc clock rate\n");
909 static void meson_sar_adc_set_bandgap(struct iio_dev
*indio_dev
, bool on_off
)
911 struct meson_sar_adc_priv
*priv
= iio_priv(indio_dev
);
912 const struct meson_sar_adc_param
*param
= priv
->param
;
915 if (param
->bandgap_reg
== MESON_SAR_ADC_REG11
)
916 enable_mask
= MESON_SAR_ADC_REG11_BANDGAP_EN
;
918 enable_mask
= MESON_SAR_ADC_DELTA_10_TS_VBG_EN
;
920 regmap_update_bits(priv
->regmap
, param
->bandgap_reg
, enable_mask
,
921 on_off
? enable_mask
: 0);
924 static int meson_sar_adc_hw_enable(struct iio_dev
*indio_dev
)
926 struct meson_sar_adc_priv
*priv
= iio_priv(indio_dev
);
930 ret
= meson_sar_adc_lock(indio_dev
);
934 ret
= regulator_enable(priv
->vref
);
936 dev_err(indio_dev
->dev
.parent
,
937 "failed to enable vref regulator\n");
941 ret
= clk_prepare_enable(priv
->core_clk
);
943 dev_err(indio_dev
->dev
.parent
, "failed to enable core clk\n");
947 regval
= FIELD_PREP(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK
, 1);
948 regmap_update_bits(priv
->regmap
, MESON_SAR_ADC_REG0
,
949 MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK
, regval
);
951 meson_sar_adc_set_bandgap(indio_dev
, true);
953 regmap_update_bits(priv
->regmap
, MESON_SAR_ADC_REG3
,
954 MESON_SAR_ADC_REG3_ADC_EN
,
955 MESON_SAR_ADC_REG3_ADC_EN
);
959 ret
= clk_prepare_enable(priv
->adc_clk
);
961 dev_err(indio_dev
->dev
.parent
, "failed to enable adc clk\n");
965 meson_sar_adc_unlock(indio_dev
);
970 regmap_update_bits(priv
->regmap
, MESON_SAR_ADC_REG3
,
971 MESON_SAR_ADC_REG3_ADC_EN
, 0);
972 meson_sar_adc_set_bandgap(indio_dev
, false);
973 clk_disable_unprepare(priv
->core_clk
);
975 regulator_disable(priv
->vref
);
977 meson_sar_adc_unlock(indio_dev
);
982 static int meson_sar_adc_hw_disable(struct iio_dev
*indio_dev
)
984 struct meson_sar_adc_priv
*priv
= iio_priv(indio_dev
);
987 ret
= meson_sar_adc_lock(indio_dev
);
991 clk_disable_unprepare(priv
->adc_clk
);
993 regmap_update_bits(priv
->regmap
, MESON_SAR_ADC_REG3
,
994 MESON_SAR_ADC_REG3_ADC_EN
, 0);
996 meson_sar_adc_set_bandgap(indio_dev
, false);
998 clk_disable_unprepare(priv
->core_clk
);
1000 regulator_disable(priv
->vref
);
1002 meson_sar_adc_unlock(indio_dev
);
1007 static irqreturn_t
meson_sar_adc_irq(int irq
, void *data
)
1009 struct iio_dev
*indio_dev
= data
;
1010 struct meson_sar_adc_priv
*priv
= iio_priv(indio_dev
);
1011 unsigned int cnt
, threshold
;
1014 regmap_read(priv
->regmap
, MESON_SAR_ADC_REG0
, ®val
);
1015 cnt
= FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK
, regval
);
1016 threshold
= FIELD_GET(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK
, regval
);
1018 if (cnt
< threshold
)
1021 complete(&priv
->done
);
1026 static int meson_sar_adc_calib(struct iio_dev
*indio_dev
)
1028 struct meson_sar_adc_priv
*priv
= iio_priv(indio_dev
);
1029 int ret
, nominal0
, nominal1
, value0
, value1
;
1031 /* use points 25% and 75% for calibration */
1032 nominal0
= (1 << priv
->param
->resolution
) / 4;
1033 nominal1
= (1 << priv
->param
->resolution
) * 3 / 4;
1035 meson_sar_adc_set_chan7_mux(indio_dev
, CHAN7_MUX_VDD_DIV4
);
1036 usleep_range(10, 20);
1037 ret
= meson_sar_adc_get_sample(indio_dev
,
1038 &indio_dev
->channels
[7],
1039 MEAN_AVERAGING
, EIGHT_SAMPLES
, &value0
);
1043 meson_sar_adc_set_chan7_mux(indio_dev
, CHAN7_MUX_VDD_MUL3_DIV4
);
1044 usleep_range(10, 20);
1045 ret
= meson_sar_adc_get_sample(indio_dev
,
1046 &indio_dev
->channels
[7],
1047 MEAN_AVERAGING
, EIGHT_SAMPLES
, &value1
);
1051 if (value1
<= value0
) {
1056 priv
->calibscale
= div_s64((nominal1
- nominal0
) * (s64
)MILLION
,
1058 priv
->calibbias
= nominal0
- div_s64((s64
)value0
* priv
->calibscale
,
1062 meson_sar_adc_set_chan7_mux(indio_dev
, CHAN7_MUX_CH7_INPUT
);
1067 static const struct iio_info meson_sar_adc_iio_info
= {
1068 .read_raw
= meson_sar_adc_iio_info_read_raw
,
1071 static const struct meson_sar_adc_param meson_sar_adc_meson8_param
= {
1072 .has_bl30_integration
= false,
1073 .clock_rate
= 1150000,
1074 .bandgap_reg
= MESON_SAR_ADC_DELTA_10
,
1075 .regmap_config
= &meson_sar_adc_regmap_config_meson8
,
1077 .temperature_trimming_bits
= 4,
1078 .temperature_multiplier
= 18 * 10000,
1079 .temperature_divider
= 1024 * 10 * 85,
1082 static const struct meson_sar_adc_param meson_sar_adc_meson8b_param
= {
1083 .has_bl30_integration
= false,
1084 .clock_rate
= 1150000,
1085 .bandgap_reg
= MESON_SAR_ADC_DELTA_10
,
1086 .regmap_config
= &meson_sar_adc_regmap_config_meson8
,
1088 .temperature_trimming_bits
= 5,
1089 .temperature_multiplier
= 10,
1090 .temperature_divider
= 32,
1093 static const struct meson_sar_adc_param meson_sar_adc_gxbb_param
= {
1094 .has_bl30_integration
= true,
1095 .clock_rate
= 1200000,
1096 .bandgap_reg
= MESON_SAR_ADC_REG11
,
1097 .regmap_config
= &meson_sar_adc_regmap_config_gxbb
,
1101 static const struct meson_sar_adc_param meson_sar_adc_gxl_param
= {
1102 .has_bl30_integration
= true,
1103 .clock_rate
= 1200000,
1104 .bandgap_reg
= MESON_SAR_ADC_REG11
,
1105 .regmap_config
= &meson_sar_adc_regmap_config_gxbb
,
1109 static const struct meson_sar_adc_data meson_sar_adc_meson8_data
= {
1110 .param
= &meson_sar_adc_meson8_param
,
1111 .name
= "meson-meson8-saradc",
1114 static const struct meson_sar_adc_data meson_sar_adc_meson8b_data
= {
1115 .param
= &meson_sar_adc_meson8b_param
,
1116 .name
= "meson-meson8b-saradc",
1119 static const struct meson_sar_adc_data meson_sar_adc_meson8m2_data
= {
1120 .param
= &meson_sar_adc_meson8b_param
,
1121 .name
= "meson-meson8m2-saradc",
1124 static const struct meson_sar_adc_data meson_sar_adc_gxbb_data
= {
1125 .param
= &meson_sar_adc_gxbb_param
,
1126 .name
= "meson-gxbb-saradc",
1129 static const struct meson_sar_adc_data meson_sar_adc_gxl_data
= {
1130 .param
= &meson_sar_adc_gxl_param
,
1131 .name
= "meson-gxl-saradc",
1134 static const struct meson_sar_adc_data meson_sar_adc_gxm_data
= {
1135 .param
= &meson_sar_adc_gxl_param
,
1136 .name
= "meson-gxm-saradc",
1139 static const struct meson_sar_adc_data meson_sar_adc_axg_data
= {
1140 .param
= &meson_sar_adc_gxl_param
,
1141 .name
= "meson-axg-saradc",
1144 static const struct meson_sar_adc_data meson_sar_adc_g12a_data
= {
1145 .param
= &meson_sar_adc_gxl_param
,
1146 .name
= "meson-g12a-saradc",
1149 static const struct of_device_id meson_sar_adc_of_match
[] = {
1151 .compatible
= "amlogic,meson8-saradc",
1152 .data
= &meson_sar_adc_meson8_data
,
1154 .compatible
= "amlogic,meson8b-saradc",
1155 .data
= &meson_sar_adc_meson8b_data
,
1157 .compatible
= "amlogic,meson8m2-saradc",
1158 .data
= &meson_sar_adc_meson8m2_data
,
1160 .compatible
= "amlogic,meson-gxbb-saradc",
1161 .data
= &meson_sar_adc_gxbb_data
,
1163 .compatible
= "amlogic,meson-gxl-saradc",
1164 .data
= &meson_sar_adc_gxl_data
,
1166 .compatible
= "amlogic,meson-gxm-saradc",
1167 .data
= &meson_sar_adc_gxm_data
,
1169 .compatible
= "amlogic,meson-axg-saradc",
1170 .data
= &meson_sar_adc_axg_data
,
1172 .compatible
= "amlogic,meson-g12a-saradc",
1173 .data
= &meson_sar_adc_g12a_data
,
1177 MODULE_DEVICE_TABLE(of
, meson_sar_adc_of_match
);
1179 static int meson_sar_adc_probe(struct platform_device
*pdev
)
1181 const struct meson_sar_adc_data
*match_data
;
1182 struct meson_sar_adc_priv
*priv
;
1183 struct iio_dev
*indio_dev
;
1187 indio_dev
= devm_iio_device_alloc(&pdev
->dev
, sizeof(*priv
));
1189 dev_err(&pdev
->dev
, "failed allocating iio device\n");
1193 priv
= iio_priv(indio_dev
);
1194 init_completion(&priv
->done
);
1196 match_data
= of_device_get_match_data(&pdev
->dev
);
1198 dev_err(&pdev
->dev
, "failed to get match data\n");
1202 priv
->param
= match_data
->param
;
1204 indio_dev
->name
= match_data
->name
;
1205 indio_dev
->modes
= INDIO_DIRECT_MODE
;
1206 indio_dev
->info
= &meson_sar_adc_iio_info
;
1208 base
= devm_platform_ioremap_resource(pdev
, 0);
1210 return PTR_ERR(base
);
1212 priv
->regmap
= devm_regmap_init_mmio(&pdev
->dev
, base
,
1213 priv
->param
->regmap_config
);
1214 if (IS_ERR(priv
->regmap
))
1215 return PTR_ERR(priv
->regmap
);
1217 irq
= irq_of_parse_and_map(pdev
->dev
.of_node
, 0);
1221 ret
= devm_request_irq(&pdev
->dev
, irq
, meson_sar_adc_irq
, IRQF_SHARED
,
1222 dev_name(&pdev
->dev
), indio_dev
);
1226 priv
->clkin
= devm_clk_get(&pdev
->dev
, "clkin");
1227 if (IS_ERR(priv
->clkin
)) {
1228 dev_err(&pdev
->dev
, "failed to get clkin\n");
1229 return PTR_ERR(priv
->clkin
);
1232 priv
->core_clk
= devm_clk_get(&pdev
->dev
, "core");
1233 if (IS_ERR(priv
->core_clk
)) {
1234 dev_err(&pdev
->dev
, "failed to get core clk\n");
1235 return PTR_ERR(priv
->core_clk
);
1238 priv
->adc_clk
= devm_clk_get(&pdev
->dev
, "adc_clk");
1239 if (IS_ERR(priv
->adc_clk
)) {
1240 if (PTR_ERR(priv
->adc_clk
) == -ENOENT
) {
1241 priv
->adc_clk
= NULL
;
1243 dev_err(&pdev
->dev
, "failed to get adc clk\n");
1244 return PTR_ERR(priv
->adc_clk
);
1248 priv
->adc_sel_clk
= devm_clk_get(&pdev
->dev
, "adc_sel");
1249 if (IS_ERR(priv
->adc_sel_clk
)) {
1250 if (PTR_ERR(priv
->adc_sel_clk
) == -ENOENT
) {
1251 priv
->adc_sel_clk
= NULL
;
1253 dev_err(&pdev
->dev
, "failed to get adc_sel clk\n");
1254 return PTR_ERR(priv
->adc_sel_clk
);
1258 /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */
1259 if (!priv
->adc_clk
) {
1260 ret
= meson_sar_adc_clk_init(indio_dev
, base
);
1265 priv
->vref
= devm_regulator_get(&pdev
->dev
, "vref");
1266 if (IS_ERR(priv
->vref
)) {
1267 dev_err(&pdev
->dev
, "failed to get vref regulator\n");
1268 return PTR_ERR(priv
->vref
);
1271 priv
->calibscale
= MILLION
;
1273 if (priv
->param
->temperature_trimming_bits
) {
1274 ret
= meson_sar_adc_temp_sensor_init(indio_dev
);
1279 if (priv
->temperature_sensor_calibrated
) {
1280 indio_dev
->channels
= meson_sar_adc_and_temp_iio_channels
;
1281 indio_dev
->num_channels
=
1282 ARRAY_SIZE(meson_sar_adc_and_temp_iio_channels
);
1284 indio_dev
->channels
= meson_sar_adc_iio_channels
;
1285 indio_dev
->num_channels
=
1286 ARRAY_SIZE(meson_sar_adc_iio_channels
);
1289 ret
= meson_sar_adc_init(indio_dev
);
1293 ret
= meson_sar_adc_hw_enable(indio_dev
);
1297 ret
= meson_sar_adc_calib(indio_dev
);
1299 dev_warn(&pdev
->dev
, "calibration failed\n");
1301 platform_set_drvdata(pdev
, indio_dev
);
1303 ret
= iio_device_register(indio_dev
);
1310 meson_sar_adc_hw_disable(indio_dev
);
1315 static int meson_sar_adc_remove(struct platform_device
*pdev
)
1317 struct iio_dev
*indio_dev
= platform_get_drvdata(pdev
);
1319 iio_device_unregister(indio_dev
);
1321 return meson_sar_adc_hw_disable(indio_dev
);
1324 static int __maybe_unused
meson_sar_adc_suspend(struct device
*dev
)
1326 struct iio_dev
*indio_dev
= dev_get_drvdata(dev
);
1328 return meson_sar_adc_hw_disable(indio_dev
);
1331 static int __maybe_unused
meson_sar_adc_resume(struct device
*dev
)
1333 struct iio_dev
*indio_dev
= dev_get_drvdata(dev
);
1335 return meson_sar_adc_hw_enable(indio_dev
);
1338 static SIMPLE_DEV_PM_OPS(meson_sar_adc_pm_ops
,
1339 meson_sar_adc_suspend
, meson_sar_adc_resume
);
1341 static struct platform_driver meson_sar_adc_driver
= {
1342 .probe
= meson_sar_adc_probe
,
1343 .remove
= meson_sar_adc_remove
,
1345 .name
= "meson-saradc",
1346 .of_match_table
= meson_sar_adc_of_match
,
1347 .pm
= &meson_sar_adc_pm_ops
,
1351 module_platform_driver(meson_sar_adc_driver
);
1353 MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
1354 MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver");
1355 MODULE_LICENSE("GPL v2");