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Merge tag 'block-5.9-2020-08-14' of git://git.kernel.dk/linux-block
[mirror_ubuntu-hirsute-kernel.git] / drivers / iio / adc / meson_saradc.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
4 *
5 * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/delay.h>
12 #include <linux/io.h>
13 #include <linux/iio/iio.h>
14 #include <linux/module.h>
15 #include <linux/nvmem-consumer.h>
16 #include <linux/interrupt.h>
17 #include <linux/of.h>
18 #include <linux/of_irq.h>
19 #include <linux/of_device.h>
20 #include <linux/platform_device.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/mfd/syscon.h>
24
25 #define MESON_SAR_ADC_REG0 0x00
26 #define MESON_SAR_ADC_REG0_PANEL_DETECT BIT(31)
27 #define MESON_SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28)
28 #define MESON_SAR_ADC_REG0_DELTA_BUSY BIT(30)
29 #define MESON_SAR_ADC_REG0_AVG_BUSY BIT(29)
30 #define MESON_SAR_ADC_REG0_SAMPLE_BUSY BIT(28)
31 #define MESON_SAR_ADC_REG0_FIFO_FULL BIT(27)
32 #define MESON_SAR_ADC_REG0_FIFO_EMPTY BIT(26)
33 #define MESON_SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)
34 #define MESON_SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19)
35 #define MESON_SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)
36 #define MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15)
37 #define MESON_SAR_ADC_REG0_SAMPLING_STOP BIT(14)
38 #define MESON_SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12)
39 #define MESON_SAR_ADC_REG0_DETECT_IRQ_POL BIT(10)
40 #define MESON_SAR_ADC_REG0_DETECT_IRQ_EN BIT(9)
41 #define MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)
42 #define MESON_SAR_ADC_REG0_FIFO_IRQ_EN BIT(3)
43 #define MESON_SAR_ADC_REG0_SAMPLING_START BIT(2)
44 #define MESON_SAR_ADC_REG0_CONTINUOUS_EN BIT(1)
45 #define MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0)
46
47 #define MESON_SAR_ADC_CHAN_LIST 0x04
48 #define MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)
49 #define MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(_chan) \
50 (GENMASK(2, 0) << ((_chan) * 3))
51
52 #define MESON_SAR_ADC_AVG_CNTL 0x08
53 #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \
54 (16 + ((_chan) * 2))
55 #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \
56 (GENMASK(17, 16) << ((_chan) * 2))
57 #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \
58 (0 + ((_chan) * 2))
59 #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \
60 (GENMASK(1, 0) << ((_chan) * 2))
61
62 #define MESON_SAR_ADC_REG3 0x0c
63 #define MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31)
64 #define MESON_SAR_ADC_REG3_CLK_EN BIT(30)
65 #define MESON_SAR_ADC_REG3_BL30_INITIALIZED BIT(28)
66 #define MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27)
67 #define MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26)
68 #define MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23)
69 #define MESON_SAR_ADC_REG3_DETECT_EN BIT(22)
70 #define MESON_SAR_ADC_REG3_ADC_EN BIT(21)
71 #define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
72 #define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
73 #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
74 #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
75 #define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
76 #define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
77
78 #define MESON_SAR_ADC_DELAY 0x10
79 #define MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24)
80 #define MESON_SAR_ADC_DELAY_BL30_BUSY BIT(15)
81 #define MESON_SAR_ADC_DELAY_KERNEL_BUSY BIT(14)
82 #define MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16)
83 #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8)
84 #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0)
85
86 #define MESON_SAR_ADC_LAST_RD 0x14
87 #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16)
88 #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0)
89
90 #define MESON_SAR_ADC_FIFO_RD 0x18
91 #define MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12)
92 #define MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0)
93
94 #define MESON_SAR_ADC_AUX_SW 0x1c
95 #define MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(_chan) \
96 (8 + (((_chan) - 2) * 3))
97 #define MESON_SAR_ADC_AUX_SW_VREF_P_MUX BIT(6)
98 #define MESON_SAR_ADC_AUX_SW_VREF_N_MUX BIT(5)
99 #define MESON_SAR_ADC_AUX_SW_MODE_SEL BIT(4)
100 #define MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3)
101 #define MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2)
102 #define MESON_SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1)
103 #define MESON_SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0)
104
105 #define MESON_SAR_ADC_CHAN_10_SW 0x20
106 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23)
107 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22)
108 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21)
109 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20)
110 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19)
111 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18)
112 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17)
113 #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16)
114 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7)
115 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6)
116 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5)
117 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4)
118 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3)
119 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2)
120 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1)
121 #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0)
122
123 #define MESON_SAR_ADC_DETECT_IDLE_SW 0x24
124 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26)
125 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK GENMASK(25, 23)
126 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_P_MUX BIT(22)
127 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_N_MUX BIT(21)
128 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20)
129 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YP_DRIVE_SW BIT(19)
130 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XP_DRIVE_SW BIT(18)
131 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YM_DRIVE_SW BIT(17)
132 #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XM_DRIVE_SW BIT(16)
133 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK GENMASK(9, 7)
134 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_P_MUX BIT(6)
135 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_N_MUX BIT(5)
136 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4)
137 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YP_DRIVE_SW BIT(3)
138 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XP_DRIVE_SW BIT(2)
139 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YM_DRIVE_SW BIT(1)
140 #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XM_DRIVE_SW BIT(0)
141
142 #define MESON_SAR_ADC_DELTA_10 0x28
143 #define MESON_SAR_ADC_DELTA_10_TEMP_SEL BIT(27)
144 #define MESON_SAR_ADC_DELTA_10_TS_REVE1 BIT(26)
145 #define MESON_SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16)
146 #define MESON_SAR_ADC_DELTA_10_TS_REVE0 BIT(15)
147 #define MESON_SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11)
148 #define MESON_SAR_ADC_DELTA_10_TS_VBG_EN BIT(10)
149 #define MESON_SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0)
150
151 /*
152 * NOTE: registers from here are undocumented (the vendor Linux kernel driver
153 * and u-boot source served as reference). These only seem to be relevant on
154 * GXBB and newer.
155 */
156 #define MESON_SAR_ADC_REG11 0x2c
157 #define MESON_SAR_ADC_REG11_BANDGAP_EN BIT(13)
158
159 #define MESON_SAR_ADC_REG13 0x34
160 #define MESON_SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8)
161
162 #define MESON_SAR_ADC_MAX_FIFO_SIZE 32
163 #define MESON_SAR_ADC_TIMEOUT 100 /* ms */
164 #define MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL 6
165 #define MESON_SAR_ADC_TEMP_OFFSET 27
166
167 /* temperature sensor calibration information in eFuse */
168 #define MESON_SAR_ADC_EFUSE_BYTES 4
169 #define MESON_SAR_ADC_EFUSE_BYTE3_UPPER_ADC_VAL GENMASK(6, 0)
170 #define MESON_SAR_ADC_EFUSE_BYTE3_IS_CALIBRATED BIT(7)
171
172 #define MESON_HHI_DPLL_TOP_0 0x318
173 #define MESON_HHI_DPLL_TOP_0_TSC_BIT4 BIT(9)
174
175 /* for use with IIO_VAL_INT_PLUS_MICRO */
176 #define MILLION 1000000
177
178 #define MESON_SAR_ADC_CHAN(_chan) { \
179 .type = IIO_VOLTAGE, \
180 .indexed = 1, \
181 .channel = _chan, \
182 .address = _chan, \
183 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
184 BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
185 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
186 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_CALIBBIAS) | \
187 BIT(IIO_CHAN_INFO_CALIBSCALE), \
188 .datasheet_name = "SAR_ADC_CH"#_chan, \
189 }
190
191 #define MESON_SAR_ADC_TEMP_CHAN(_chan) { \
192 .type = IIO_TEMP, \
193 .channel = _chan, \
194 .address = MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL, \
195 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
196 BIT(IIO_CHAN_INFO_AVERAGE_RAW), \
197 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) | \
198 BIT(IIO_CHAN_INFO_SCALE), \
199 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_CALIBBIAS) | \
200 BIT(IIO_CHAN_INFO_CALIBSCALE), \
201 .datasheet_name = "TEMP_SENSOR", \
202 }
203
204 static const struct iio_chan_spec meson_sar_adc_iio_channels[] = {
205 MESON_SAR_ADC_CHAN(0),
206 MESON_SAR_ADC_CHAN(1),
207 MESON_SAR_ADC_CHAN(2),
208 MESON_SAR_ADC_CHAN(3),
209 MESON_SAR_ADC_CHAN(4),
210 MESON_SAR_ADC_CHAN(5),
211 MESON_SAR_ADC_CHAN(6),
212 MESON_SAR_ADC_CHAN(7),
213 IIO_CHAN_SOFT_TIMESTAMP(8),
214 };
215
216 static const struct iio_chan_spec meson_sar_adc_and_temp_iio_channels[] = {
217 MESON_SAR_ADC_CHAN(0),
218 MESON_SAR_ADC_CHAN(1),
219 MESON_SAR_ADC_CHAN(2),
220 MESON_SAR_ADC_CHAN(3),
221 MESON_SAR_ADC_CHAN(4),
222 MESON_SAR_ADC_CHAN(5),
223 MESON_SAR_ADC_CHAN(6),
224 MESON_SAR_ADC_CHAN(7),
225 MESON_SAR_ADC_TEMP_CHAN(8),
226 IIO_CHAN_SOFT_TIMESTAMP(9),
227 };
228
229 enum meson_sar_adc_avg_mode {
230 NO_AVERAGING = 0x0,
231 MEAN_AVERAGING = 0x1,
232 MEDIAN_AVERAGING = 0x2,
233 };
234
235 enum meson_sar_adc_num_samples {
236 ONE_SAMPLE = 0x0,
237 TWO_SAMPLES = 0x1,
238 FOUR_SAMPLES = 0x2,
239 EIGHT_SAMPLES = 0x3,
240 };
241
242 enum meson_sar_adc_chan7_mux_sel {
243 CHAN7_MUX_VSS = 0x0,
244 CHAN7_MUX_VDD_DIV4 = 0x1,
245 CHAN7_MUX_VDD_DIV2 = 0x2,
246 CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,
247 CHAN7_MUX_VDD = 0x4,
248 CHAN7_MUX_CH7_INPUT = 0x7,
249 };
250
251 struct meson_sar_adc_param {
252 bool has_bl30_integration;
253 unsigned long clock_rate;
254 u32 bandgap_reg;
255 unsigned int resolution;
256 const struct regmap_config *regmap_config;
257 u8 temperature_trimming_bits;
258 unsigned int temperature_multiplier;
259 unsigned int temperature_divider;
260 };
261
262 struct meson_sar_adc_data {
263 const struct meson_sar_adc_param *param;
264 const char *name;
265 };
266
267 struct meson_sar_adc_priv {
268 struct regmap *regmap;
269 struct regulator *vref;
270 const struct meson_sar_adc_param *param;
271 struct clk *clkin;
272 struct clk *core_clk;
273 struct clk *adc_sel_clk;
274 struct clk *adc_clk;
275 struct clk_gate clk_gate;
276 struct clk *adc_div_clk;
277 struct clk_divider clk_div;
278 struct completion done;
279 int calibbias;
280 int calibscale;
281 struct regmap *tsc_regmap;
282 bool temperature_sensor_calibrated;
283 u8 temperature_sensor_coefficient;
284 u16 temperature_sensor_adc_val;
285 };
286
287 static const struct regmap_config meson_sar_adc_regmap_config_gxbb = {
288 .reg_bits = 8,
289 .val_bits = 32,
290 .reg_stride = 4,
291 .max_register = MESON_SAR_ADC_REG13,
292 };
293
294 static const struct regmap_config meson_sar_adc_regmap_config_meson8 = {
295 .reg_bits = 8,
296 .val_bits = 32,
297 .reg_stride = 4,
298 .max_register = MESON_SAR_ADC_DELTA_10,
299 };
300
301 static unsigned int meson_sar_adc_get_fifo_count(struct iio_dev *indio_dev)
302 {
303 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
304 u32 regval;
305
306 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval);
307
308 return FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
309 }
310
311 static int meson_sar_adc_calib_val(struct iio_dev *indio_dev, int val)
312 {
313 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
314 int tmp;
315
316 /* use val_calib = scale * val_raw + offset calibration function */
317 tmp = div_s64((s64)val * priv->calibscale, MILLION) + priv->calibbias;
318
319 return clamp(tmp, 0, (1 << priv->param->resolution) - 1);
320 }
321
322 static int meson_sar_adc_wait_busy_clear(struct iio_dev *indio_dev)
323 {
324 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
325 int regval, timeout = 10000;
326
327 /*
328 * NOTE: we need a small delay before reading the status, otherwise
329 * the sample engine may not have started internally (which would
330 * seem to us that sampling is already finished).
331 */
332 do {
333 udelay(1);
334 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval);
335 } while (FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, regval) && timeout--);
336
337 if (timeout < 0)
338 return -ETIMEDOUT;
339
340 return 0;
341 }
342
343 static int meson_sar_adc_read_raw_sample(struct iio_dev *indio_dev,
344 const struct iio_chan_spec *chan,
345 int *val)
346 {
347 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
348 int regval, fifo_chan, fifo_val, count;
349
350 if(!wait_for_completion_timeout(&priv->done,
351 msecs_to_jiffies(MESON_SAR_ADC_TIMEOUT)))
352 return -ETIMEDOUT;
353
354 count = meson_sar_adc_get_fifo_count(indio_dev);
355 if (count != 1) {
356 dev_err(&indio_dev->dev,
357 "ADC FIFO has %d element(s) instead of one\n", count);
358 return -EINVAL;
359 }
360
361 regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &regval);
362 fifo_chan = FIELD_GET(MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval);
363 if (fifo_chan != chan->address) {
364 dev_err(&indio_dev->dev,
365 "ADC FIFO entry belongs to channel %d instead of %lu\n",
366 fifo_chan, chan->address);
367 return -EINVAL;
368 }
369
370 fifo_val = FIELD_GET(MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK, regval);
371 fifo_val &= GENMASK(priv->param->resolution - 1, 0);
372 *val = meson_sar_adc_calib_val(indio_dev, fifo_val);
373
374 return 0;
375 }
376
377 static void meson_sar_adc_set_averaging(struct iio_dev *indio_dev,
378 const struct iio_chan_spec *chan,
379 enum meson_sar_adc_avg_mode mode,
380 enum meson_sar_adc_num_samples samples)
381 {
382 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
383 int val, address = chan->address;
384
385 val = samples << MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(address);
386 regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
387 MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(address),
388 val);
389
390 val = mode << MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(address);
391 regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
392 MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(address), val);
393 }
394
395 static void meson_sar_adc_enable_channel(struct iio_dev *indio_dev,
396 const struct iio_chan_spec *chan)
397 {
398 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
399 u32 regval;
400
401 /*
402 * the SAR ADC engine allows sampling multiple channels at the same
403 * time. to keep it simple we're only working with one *internal*
404 * channel, which starts counting at index 0 (which means: count = 1).
405 */
406 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);
407 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
408 MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);
409
410 /* map channel index 0 to the channel which we want to read */
411 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0),
412 chan->address);
413 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
414 MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), regval);
415
416 regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
417 chan->address);
418 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
419 MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
420 regval);
421
422 regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
423 chan->address);
424 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
425 MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
426 regval);
427
428 if (chan->address == MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL) {
429 if (chan->type == IIO_TEMP)
430 regval = MESON_SAR_ADC_DELTA_10_TEMP_SEL;
431 else
432 regval = 0;
433
434 regmap_update_bits(priv->regmap,
435 MESON_SAR_ADC_DELTA_10,
436 MESON_SAR_ADC_DELTA_10_TEMP_SEL, regval);
437 }
438 }
439
440 static void meson_sar_adc_set_chan7_mux(struct iio_dev *indio_dev,
441 enum meson_sar_adc_chan7_mux_sel sel)
442 {
443 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
444 u32 regval;
445
446 regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);
447 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
448 MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);
449
450 usleep_range(10, 20);
451 }
452
453 static void meson_sar_adc_start_sample_engine(struct iio_dev *indio_dev)
454 {
455 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
456
457 reinit_completion(&priv->done);
458
459 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
460 MESON_SAR_ADC_REG0_FIFO_IRQ_EN,
461 MESON_SAR_ADC_REG0_FIFO_IRQ_EN);
462
463 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
464 MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE,
465 MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
466
467 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
468 MESON_SAR_ADC_REG0_SAMPLING_START,
469 MESON_SAR_ADC_REG0_SAMPLING_START);
470 }
471
472 static void meson_sar_adc_stop_sample_engine(struct iio_dev *indio_dev)
473 {
474 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
475
476 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
477 MESON_SAR_ADC_REG0_FIFO_IRQ_EN, 0);
478
479 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
480 MESON_SAR_ADC_REG0_SAMPLING_STOP,
481 MESON_SAR_ADC_REG0_SAMPLING_STOP);
482
483 /* wait until all modules are stopped */
484 meson_sar_adc_wait_busy_clear(indio_dev);
485
486 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
487 MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0);
488 }
489
490 static int meson_sar_adc_lock(struct iio_dev *indio_dev)
491 {
492 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
493 int val, timeout = 10000;
494
495 mutex_lock(&indio_dev->mlock);
496
497 if (priv->param->has_bl30_integration) {
498 /* prevent BL30 from using the SAR ADC while we are using it */
499 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
500 MESON_SAR_ADC_DELAY_KERNEL_BUSY,
501 MESON_SAR_ADC_DELAY_KERNEL_BUSY);
502
503 /*
504 * wait until BL30 releases it's lock (so we can use the SAR
505 * ADC)
506 */
507 do {
508 udelay(1);
509 regmap_read(priv->regmap, MESON_SAR_ADC_DELAY, &val);
510 } while (val & MESON_SAR_ADC_DELAY_BL30_BUSY && timeout--);
511
512 if (timeout < 0) {
513 mutex_unlock(&indio_dev->mlock);
514 return -ETIMEDOUT;
515 }
516 }
517
518 return 0;
519 }
520
521 static void meson_sar_adc_unlock(struct iio_dev *indio_dev)
522 {
523 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
524
525 if (priv->param->has_bl30_integration)
526 /* allow BL30 to use the SAR ADC again */
527 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
528 MESON_SAR_ADC_DELAY_KERNEL_BUSY, 0);
529
530 mutex_unlock(&indio_dev->mlock);
531 }
532
533 static void meson_sar_adc_clear_fifo(struct iio_dev *indio_dev)
534 {
535 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
536 unsigned int count, tmp;
537
538 for (count = 0; count < MESON_SAR_ADC_MAX_FIFO_SIZE; count++) {
539 if (!meson_sar_adc_get_fifo_count(indio_dev))
540 break;
541
542 regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &tmp);
543 }
544 }
545
546 static int meson_sar_adc_get_sample(struct iio_dev *indio_dev,
547 const struct iio_chan_spec *chan,
548 enum meson_sar_adc_avg_mode avg_mode,
549 enum meson_sar_adc_num_samples avg_samples,
550 int *val)
551 {
552 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
553 int ret;
554
555 if (chan->type == IIO_TEMP && !priv->temperature_sensor_calibrated)
556 return -ENOTSUPP;
557
558 ret = meson_sar_adc_lock(indio_dev);
559 if (ret)
560 return ret;
561
562 /* clear the FIFO to make sure we're not reading old values */
563 meson_sar_adc_clear_fifo(indio_dev);
564
565 meson_sar_adc_set_averaging(indio_dev, chan, avg_mode, avg_samples);
566
567 meson_sar_adc_enable_channel(indio_dev, chan);
568
569 meson_sar_adc_start_sample_engine(indio_dev);
570 ret = meson_sar_adc_read_raw_sample(indio_dev, chan, val);
571 meson_sar_adc_stop_sample_engine(indio_dev);
572
573 meson_sar_adc_unlock(indio_dev);
574
575 if (ret) {
576 dev_warn(indio_dev->dev.parent,
577 "failed to read sample for channel %lu: %d\n",
578 chan->address, ret);
579 return ret;
580 }
581
582 return IIO_VAL_INT;
583 }
584
585 static int meson_sar_adc_iio_info_read_raw(struct iio_dev *indio_dev,
586 const struct iio_chan_spec *chan,
587 int *val, int *val2, long mask)
588 {
589 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
590 int ret;
591
592 switch (mask) {
593 case IIO_CHAN_INFO_RAW:
594 return meson_sar_adc_get_sample(indio_dev, chan, NO_AVERAGING,
595 ONE_SAMPLE, val);
596 break;
597
598 case IIO_CHAN_INFO_AVERAGE_RAW:
599 return meson_sar_adc_get_sample(indio_dev, chan,
600 MEAN_AVERAGING, EIGHT_SAMPLES,
601 val);
602 break;
603
604 case IIO_CHAN_INFO_SCALE:
605 if (chan->type == IIO_VOLTAGE) {
606 ret = regulator_get_voltage(priv->vref);
607 if (ret < 0) {
608 dev_err(indio_dev->dev.parent,
609 "failed to get vref voltage: %d\n",
610 ret);
611 return ret;
612 }
613
614 *val = ret / 1000;
615 *val2 = priv->param->resolution;
616 return IIO_VAL_FRACTIONAL_LOG2;
617 } else if (chan->type == IIO_TEMP) {
618 /* SoC specific multiplier and divider */
619 *val = priv->param->temperature_multiplier;
620 *val2 = priv->param->temperature_divider;
621
622 /* celsius to millicelsius */
623 *val *= 1000;
624
625 return IIO_VAL_FRACTIONAL;
626 } else {
627 return -EINVAL;
628 }
629
630 case IIO_CHAN_INFO_CALIBBIAS:
631 *val = priv->calibbias;
632 return IIO_VAL_INT;
633
634 case IIO_CHAN_INFO_CALIBSCALE:
635 *val = priv->calibscale / MILLION;
636 *val2 = priv->calibscale % MILLION;
637 return IIO_VAL_INT_PLUS_MICRO;
638
639 case IIO_CHAN_INFO_OFFSET:
640 *val = DIV_ROUND_CLOSEST(MESON_SAR_ADC_TEMP_OFFSET *
641 priv->param->temperature_divider,
642 priv->param->temperature_multiplier);
643 *val -= priv->temperature_sensor_adc_val;
644 return IIO_VAL_INT;
645
646 default:
647 return -EINVAL;
648 }
649 }
650
651 static int meson_sar_adc_clk_init(struct iio_dev *indio_dev,
652 void __iomem *base)
653 {
654 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
655 struct clk_init_data init;
656 const char *clk_parents[1];
657
658 init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_div",
659 dev_name(indio_dev->dev.parent));
660 if (!init.name)
661 return -ENOMEM;
662
663 init.flags = 0;
664 init.ops = &clk_divider_ops;
665 clk_parents[0] = __clk_get_name(priv->clkin);
666 init.parent_names = clk_parents;
667 init.num_parents = 1;
668
669 priv->clk_div.reg = base + MESON_SAR_ADC_REG3;
670 priv->clk_div.shift = MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT;
671 priv->clk_div.width = MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH;
672 priv->clk_div.hw.init = &init;
673 priv->clk_div.flags = 0;
674
675 priv->adc_div_clk = devm_clk_register(&indio_dev->dev,
676 &priv->clk_div.hw);
677 if (WARN_ON(IS_ERR(priv->adc_div_clk)))
678 return PTR_ERR(priv->adc_div_clk);
679
680 init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_en",
681 dev_name(indio_dev->dev.parent));
682 if (!init.name)
683 return -ENOMEM;
684
685 init.flags = CLK_SET_RATE_PARENT;
686 init.ops = &clk_gate_ops;
687 clk_parents[0] = __clk_get_name(priv->adc_div_clk);
688 init.parent_names = clk_parents;
689 init.num_parents = 1;
690
691 priv->clk_gate.reg = base + MESON_SAR_ADC_REG3;
692 priv->clk_gate.bit_idx = __ffs(MESON_SAR_ADC_REG3_CLK_EN);
693 priv->clk_gate.hw.init = &init;
694
695 priv->adc_clk = devm_clk_register(&indio_dev->dev, &priv->clk_gate.hw);
696 if (WARN_ON(IS_ERR(priv->adc_clk)))
697 return PTR_ERR(priv->adc_clk);
698
699 return 0;
700 }
701
702 static int meson_sar_adc_temp_sensor_init(struct iio_dev *indio_dev)
703 {
704 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
705 u8 *buf, trimming_bits, trimming_mask, upper_adc_val;
706 struct nvmem_cell *temperature_calib;
707 size_t read_len;
708 int ret;
709
710 temperature_calib = devm_nvmem_cell_get(&indio_dev->dev,
711 "temperature_calib");
712 if (IS_ERR(temperature_calib)) {
713 ret = PTR_ERR(temperature_calib);
714
715 /*
716 * leave the temperature sensor disabled if no calibration data
717 * was passed via nvmem-cells.
718 */
719 if (ret == -ENODEV)
720 return 0;
721
722 if (ret != -EPROBE_DEFER)
723 dev_err(indio_dev->dev.parent,
724 "failed to get temperature_calib cell\n");
725
726 return ret;
727 }
728
729 priv->tsc_regmap =
730 syscon_regmap_lookup_by_phandle(indio_dev->dev.parent->of_node,
731 "amlogic,hhi-sysctrl");
732 if (IS_ERR(priv->tsc_regmap)) {
733 dev_err(indio_dev->dev.parent,
734 "failed to get amlogic,hhi-sysctrl regmap\n");
735 return PTR_ERR(priv->tsc_regmap);
736 }
737
738 read_len = MESON_SAR_ADC_EFUSE_BYTES;
739 buf = nvmem_cell_read(temperature_calib, &read_len);
740 if (IS_ERR(buf)) {
741 dev_err(indio_dev->dev.parent,
742 "failed to read temperature_calib cell\n");
743 return PTR_ERR(buf);
744 } else if (read_len != MESON_SAR_ADC_EFUSE_BYTES) {
745 kfree(buf);
746 dev_err(indio_dev->dev.parent,
747 "invalid read size of temperature_calib cell\n");
748 return -EINVAL;
749 }
750
751 trimming_bits = priv->param->temperature_trimming_bits;
752 trimming_mask = BIT(trimming_bits) - 1;
753
754 priv->temperature_sensor_calibrated =
755 buf[3] & MESON_SAR_ADC_EFUSE_BYTE3_IS_CALIBRATED;
756 priv->temperature_sensor_coefficient = buf[2] & trimming_mask;
757
758 upper_adc_val = FIELD_GET(MESON_SAR_ADC_EFUSE_BYTE3_UPPER_ADC_VAL,
759 buf[3]);
760
761 priv->temperature_sensor_adc_val = buf[2];
762 priv->temperature_sensor_adc_val |= upper_adc_val << BITS_PER_BYTE;
763 priv->temperature_sensor_adc_val >>= trimming_bits;
764
765 kfree(buf);
766
767 return 0;
768 }
769
770 static int meson_sar_adc_init(struct iio_dev *indio_dev)
771 {
772 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
773 int regval, i, ret;
774
775 /*
776 * make sure we start at CH7 input since the other muxes are only used
777 * for internal calibration.
778 */
779 meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
780
781 if (priv->param->has_bl30_integration) {
782 /*
783 * leave sampling delay and the input clocks as configured by
784 * BL30 to make sure BL30 gets the values it expects when
785 * reading the temperature sensor.
786 */
787 regmap_read(priv->regmap, MESON_SAR_ADC_REG3, &regval);
788 if (regval & MESON_SAR_ADC_REG3_BL30_INITIALIZED)
789 return 0;
790 }
791
792 meson_sar_adc_stop_sample_engine(indio_dev);
793
794 /*
795 * disable this bit as seems to be only relevant for Meson6 (based
796 * on the vendor driver), which we don't support at the moment.
797 */
798 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
799 MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL, 0);
800
801 /* disable all channels by default */
802 regmap_write(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 0x0);
803
804 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
805 MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0);
806 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
807 MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY,
808 MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY);
809
810 /* delay between two samples = (10+1) * 1uS */
811 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
812 MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
813 FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK,
814 10));
815 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
816 MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
817 FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
818 0));
819
820 /* delay between two samples = (10+1) * 1uS */
821 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
822 MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
823 FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
824 10));
825 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
826 MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
827 FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
828 1));
829
830 /*
831 * set up the input channel muxes in MESON_SAR_ADC_CHAN_10_SW
832 * (0 = SAR_ADC_CH0, 1 = SAR_ADC_CH1)
833 */
834 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK, 0);
835 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
836 MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK,
837 regval);
838 regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK, 1);
839 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
840 MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK,
841 regval);
842
843 /*
844 * set up the input channel muxes in MESON_SAR_ADC_AUX_SW
845 * (2 = SAR_ADC_CH2, 3 = SAR_ADC_CH3, ...) and enable
846 * MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW and
847 * MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW like the vendor driver.
848 */
849 regval = 0;
850 for (i = 2; i <= 7; i++)
851 regval |= i << MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(i);
852 regval |= MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW;
853 regval |= MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW;
854 regmap_write(priv->regmap, MESON_SAR_ADC_AUX_SW, regval);
855
856 if (priv->temperature_sensor_calibrated) {
857 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
858 MESON_SAR_ADC_DELTA_10_TS_REVE1,
859 MESON_SAR_ADC_DELTA_10_TS_REVE1);
860 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
861 MESON_SAR_ADC_DELTA_10_TS_REVE0,
862 MESON_SAR_ADC_DELTA_10_TS_REVE0);
863
864 /*
865 * set bits [3:0] of the TSC (temperature sensor coefficient)
866 * to get the correct values when reading the temperature.
867 */
868 regval = FIELD_PREP(MESON_SAR_ADC_DELTA_10_TS_C_MASK,
869 priv->temperature_sensor_coefficient);
870 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
871 MESON_SAR_ADC_DELTA_10_TS_C_MASK, regval);
872
873 if (priv->param->temperature_trimming_bits == 5) {
874 if (priv->temperature_sensor_coefficient & BIT(4))
875 regval = MESON_HHI_DPLL_TOP_0_TSC_BIT4;
876 else
877 regval = 0;
878
879 /*
880 * bit [4] (the 5th bit when starting to count at 1)
881 * of the TSC is located in the HHI register area.
882 */
883 regmap_update_bits(priv->tsc_regmap,
884 MESON_HHI_DPLL_TOP_0,
885 MESON_HHI_DPLL_TOP_0_TSC_BIT4,
886 regval);
887 }
888 } else {
889 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
890 MESON_SAR_ADC_DELTA_10_TS_REVE1, 0);
891 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
892 MESON_SAR_ADC_DELTA_10_TS_REVE0, 0);
893 }
894
895 ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);
896 if (ret) {
897 dev_err(indio_dev->dev.parent,
898 "failed to set adc parent to clkin\n");
899 return ret;
900 }
901
902 ret = clk_set_rate(priv->adc_clk, priv->param->clock_rate);
903 if (ret) {
904 dev_err(indio_dev->dev.parent,
905 "failed to set adc clock rate\n");
906 return ret;
907 }
908
909 return 0;
910 }
911
912 static void meson_sar_adc_set_bandgap(struct iio_dev *indio_dev, bool on_off)
913 {
914 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
915 const struct meson_sar_adc_param *param = priv->param;
916 u32 enable_mask;
917
918 if (param->bandgap_reg == MESON_SAR_ADC_REG11)
919 enable_mask = MESON_SAR_ADC_REG11_BANDGAP_EN;
920 else
921 enable_mask = MESON_SAR_ADC_DELTA_10_TS_VBG_EN;
922
923 regmap_update_bits(priv->regmap, param->bandgap_reg, enable_mask,
924 on_off ? enable_mask : 0);
925 }
926
927 static int meson_sar_adc_hw_enable(struct iio_dev *indio_dev)
928 {
929 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
930 int ret;
931 u32 regval;
932
933 ret = meson_sar_adc_lock(indio_dev);
934 if (ret)
935 goto err_lock;
936
937 ret = regulator_enable(priv->vref);
938 if (ret < 0) {
939 dev_err(indio_dev->dev.parent,
940 "failed to enable vref regulator\n");
941 goto err_vref;
942 }
943
944 ret = clk_prepare_enable(priv->core_clk);
945 if (ret) {
946 dev_err(indio_dev->dev.parent, "failed to enable core clk\n");
947 goto err_core_clk;
948 }
949
950 regval = FIELD_PREP(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, 1);
951 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
952 MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval);
953
954 meson_sar_adc_set_bandgap(indio_dev, true);
955
956 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
957 MESON_SAR_ADC_REG3_ADC_EN,
958 MESON_SAR_ADC_REG3_ADC_EN);
959
960 udelay(5);
961
962 ret = clk_prepare_enable(priv->adc_clk);
963 if (ret) {
964 dev_err(indio_dev->dev.parent, "failed to enable adc clk\n");
965 goto err_adc_clk;
966 }
967
968 meson_sar_adc_unlock(indio_dev);
969
970 return 0;
971
972 err_adc_clk:
973 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
974 MESON_SAR_ADC_REG3_ADC_EN, 0);
975 meson_sar_adc_set_bandgap(indio_dev, false);
976 clk_disable_unprepare(priv->core_clk);
977 err_core_clk:
978 regulator_disable(priv->vref);
979 err_vref:
980 meson_sar_adc_unlock(indio_dev);
981 err_lock:
982 return ret;
983 }
984
985 static int meson_sar_adc_hw_disable(struct iio_dev *indio_dev)
986 {
987 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
988 int ret;
989
990 ret = meson_sar_adc_lock(indio_dev);
991 if (ret)
992 return ret;
993
994 clk_disable_unprepare(priv->adc_clk);
995
996 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
997 MESON_SAR_ADC_REG3_ADC_EN, 0);
998
999 meson_sar_adc_set_bandgap(indio_dev, false);
1000
1001 clk_disable_unprepare(priv->core_clk);
1002
1003 regulator_disable(priv->vref);
1004
1005 meson_sar_adc_unlock(indio_dev);
1006
1007 return 0;
1008 }
1009
1010 static irqreturn_t meson_sar_adc_irq(int irq, void *data)
1011 {
1012 struct iio_dev *indio_dev = data;
1013 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
1014 unsigned int cnt, threshold;
1015 u32 regval;
1016
1017 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval);
1018 cnt = FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
1019 threshold = FIELD_GET(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval);
1020
1021 if (cnt < threshold)
1022 return IRQ_NONE;
1023
1024 complete(&priv->done);
1025
1026 return IRQ_HANDLED;
1027 }
1028
1029 static int meson_sar_adc_calib(struct iio_dev *indio_dev)
1030 {
1031 struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
1032 int ret, nominal0, nominal1, value0, value1;
1033
1034 /* use points 25% and 75% for calibration */
1035 nominal0 = (1 << priv->param->resolution) / 4;
1036 nominal1 = (1 << priv->param->resolution) * 3 / 4;
1037
1038 meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_VDD_DIV4);
1039 usleep_range(10, 20);
1040 ret = meson_sar_adc_get_sample(indio_dev,
1041 &indio_dev->channels[7],
1042 MEAN_AVERAGING, EIGHT_SAMPLES, &value0);
1043 if (ret < 0)
1044 goto out;
1045
1046 meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_VDD_MUL3_DIV4);
1047 usleep_range(10, 20);
1048 ret = meson_sar_adc_get_sample(indio_dev,
1049 &indio_dev->channels[7],
1050 MEAN_AVERAGING, EIGHT_SAMPLES, &value1);
1051 if (ret < 0)
1052 goto out;
1053
1054 if (value1 <= value0) {
1055 ret = -EINVAL;
1056 goto out;
1057 }
1058
1059 priv->calibscale = div_s64((nominal1 - nominal0) * (s64)MILLION,
1060 value1 - value0);
1061 priv->calibbias = nominal0 - div_s64((s64)value0 * priv->calibscale,
1062 MILLION);
1063 ret = 0;
1064 out:
1065 meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
1066
1067 return ret;
1068 }
1069
1070 static const struct iio_info meson_sar_adc_iio_info = {
1071 .read_raw = meson_sar_adc_iio_info_read_raw,
1072 };
1073
1074 static const struct meson_sar_adc_param meson_sar_adc_meson8_param = {
1075 .has_bl30_integration = false,
1076 .clock_rate = 1150000,
1077 .bandgap_reg = MESON_SAR_ADC_DELTA_10,
1078 .regmap_config = &meson_sar_adc_regmap_config_meson8,
1079 .resolution = 10,
1080 .temperature_trimming_bits = 4,
1081 .temperature_multiplier = 18 * 10000,
1082 .temperature_divider = 1024 * 10 * 85,
1083 };
1084
1085 static const struct meson_sar_adc_param meson_sar_adc_meson8b_param = {
1086 .has_bl30_integration = false,
1087 .clock_rate = 1150000,
1088 .bandgap_reg = MESON_SAR_ADC_DELTA_10,
1089 .regmap_config = &meson_sar_adc_regmap_config_meson8,
1090 .resolution = 10,
1091 .temperature_trimming_bits = 5,
1092 .temperature_multiplier = 10,
1093 .temperature_divider = 32,
1094 };
1095
1096 static const struct meson_sar_adc_param meson_sar_adc_gxbb_param = {
1097 .has_bl30_integration = true,
1098 .clock_rate = 1200000,
1099 .bandgap_reg = MESON_SAR_ADC_REG11,
1100 .regmap_config = &meson_sar_adc_regmap_config_gxbb,
1101 .resolution = 10,
1102 };
1103
1104 static const struct meson_sar_adc_param meson_sar_adc_gxl_param = {
1105 .has_bl30_integration = true,
1106 .clock_rate = 1200000,
1107 .bandgap_reg = MESON_SAR_ADC_REG11,
1108 .regmap_config = &meson_sar_adc_regmap_config_gxbb,
1109 .resolution = 12,
1110 };
1111
1112 static const struct meson_sar_adc_data meson_sar_adc_meson8_data = {
1113 .param = &meson_sar_adc_meson8_param,
1114 .name = "meson-meson8-saradc",
1115 };
1116
1117 static const struct meson_sar_adc_data meson_sar_adc_meson8b_data = {
1118 .param = &meson_sar_adc_meson8b_param,
1119 .name = "meson-meson8b-saradc",
1120 };
1121
1122 static const struct meson_sar_adc_data meson_sar_adc_meson8m2_data = {
1123 .param = &meson_sar_adc_meson8b_param,
1124 .name = "meson-meson8m2-saradc",
1125 };
1126
1127 static const struct meson_sar_adc_data meson_sar_adc_gxbb_data = {
1128 .param = &meson_sar_adc_gxbb_param,
1129 .name = "meson-gxbb-saradc",
1130 };
1131
1132 static const struct meson_sar_adc_data meson_sar_adc_gxl_data = {
1133 .param = &meson_sar_adc_gxl_param,
1134 .name = "meson-gxl-saradc",
1135 };
1136
1137 static const struct meson_sar_adc_data meson_sar_adc_gxm_data = {
1138 .param = &meson_sar_adc_gxl_param,
1139 .name = "meson-gxm-saradc",
1140 };
1141
1142 static const struct meson_sar_adc_data meson_sar_adc_axg_data = {
1143 .param = &meson_sar_adc_gxl_param,
1144 .name = "meson-axg-saradc",
1145 };
1146
1147 static const struct meson_sar_adc_data meson_sar_adc_g12a_data = {
1148 .param = &meson_sar_adc_gxl_param,
1149 .name = "meson-g12a-saradc",
1150 };
1151
1152 static const struct of_device_id meson_sar_adc_of_match[] = {
1153 {
1154 .compatible = "amlogic,meson8-saradc",
1155 .data = &meson_sar_adc_meson8_data,
1156 },
1157 {
1158 .compatible = "amlogic,meson8b-saradc",
1159 .data = &meson_sar_adc_meson8b_data,
1160 },
1161 {
1162 .compatible = "amlogic,meson8m2-saradc",
1163 .data = &meson_sar_adc_meson8m2_data,
1164 },
1165 {
1166 .compatible = "amlogic,meson-gxbb-saradc",
1167 .data = &meson_sar_adc_gxbb_data,
1168 }, {
1169 .compatible = "amlogic,meson-gxl-saradc",
1170 .data = &meson_sar_adc_gxl_data,
1171 }, {
1172 .compatible = "amlogic,meson-gxm-saradc",
1173 .data = &meson_sar_adc_gxm_data,
1174 }, {
1175 .compatible = "amlogic,meson-axg-saradc",
1176 .data = &meson_sar_adc_axg_data,
1177 }, {
1178 .compatible = "amlogic,meson-g12a-saradc",
1179 .data = &meson_sar_adc_g12a_data,
1180 },
1181 {},
1182 };
1183 MODULE_DEVICE_TABLE(of, meson_sar_adc_of_match);
1184
1185 static int meson_sar_adc_probe(struct platform_device *pdev)
1186 {
1187 const struct meson_sar_adc_data *match_data;
1188 struct meson_sar_adc_priv *priv;
1189 struct iio_dev *indio_dev;
1190 void __iomem *base;
1191 int irq, ret;
1192
1193 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
1194 if (!indio_dev) {
1195 dev_err(&pdev->dev, "failed allocating iio device\n");
1196 return -ENOMEM;
1197 }
1198
1199 priv = iio_priv(indio_dev);
1200 init_completion(&priv->done);
1201
1202 match_data = of_device_get_match_data(&pdev->dev);
1203 if (!match_data) {
1204 dev_err(&pdev->dev, "failed to get match data\n");
1205 return -ENODEV;
1206 }
1207
1208 priv->param = match_data->param;
1209
1210 indio_dev->name = match_data->name;
1211 indio_dev->modes = INDIO_DIRECT_MODE;
1212 indio_dev->info = &meson_sar_adc_iio_info;
1213
1214 base = devm_platform_ioremap_resource(pdev, 0);
1215 if (IS_ERR(base))
1216 return PTR_ERR(base);
1217
1218 priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
1219 priv->param->regmap_config);
1220 if (IS_ERR(priv->regmap))
1221 return PTR_ERR(priv->regmap);
1222
1223 irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1224 if (!irq)
1225 return -EINVAL;
1226
1227 ret = devm_request_irq(&pdev->dev, irq, meson_sar_adc_irq, IRQF_SHARED,
1228 dev_name(&pdev->dev), indio_dev);
1229 if (ret)
1230 return ret;
1231
1232 priv->clkin = devm_clk_get(&pdev->dev, "clkin");
1233 if (IS_ERR(priv->clkin)) {
1234 dev_err(&pdev->dev, "failed to get clkin\n");
1235 return PTR_ERR(priv->clkin);
1236 }
1237
1238 priv->core_clk = devm_clk_get(&pdev->dev, "core");
1239 if (IS_ERR(priv->core_clk)) {
1240 dev_err(&pdev->dev, "failed to get core clk\n");
1241 return PTR_ERR(priv->core_clk);
1242 }
1243
1244 priv->adc_clk = devm_clk_get(&pdev->dev, "adc_clk");
1245 if (IS_ERR(priv->adc_clk)) {
1246 if (PTR_ERR(priv->adc_clk) == -ENOENT) {
1247 priv->adc_clk = NULL;
1248 } else {
1249 dev_err(&pdev->dev, "failed to get adc clk\n");
1250 return PTR_ERR(priv->adc_clk);
1251 }
1252 }
1253
1254 priv->adc_sel_clk = devm_clk_get(&pdev->dev, "adc_sel");
1255 if (IS_ERR(priv->adc_sel_clk)) {
1256 if (PTR_ERR(priv->adc_sel_clk) == -ENOENT) {
1257 priv->adc_sel_clk = NULL;
1258 } else {
1259 dev_err(&pdev->dev, "failed to get adc_sel clk\n");
1260 return PTR_ERR(priv->adc_sel_clk);
1261 }
1262 }
1263
1264 /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */
1265 if (!priv->adc_clk) {
1266 ret = meson_sar_adc_clk_init(indio_dev, base);
1267 if (ret)
1268 return ret;
1269 }
1270
1271 priv->vref = devm_regulator_get(&pdev->dev, "vref");
1272 if (IS_ERR(priv->vref)) {
1273 dev_err(&pdev->dev, "failed to get vref regulator\n");
1274 return PTR_ERR(priv->vref);
1275 }
1276
1277 priv->calibscale = MILLION;
1278
1279 if (priv->param->temperature_trimming_bits) {
1280 ret = meson_sar_adc_temp_sensor_init(indio_dev);
1281 if (ret)
1282 return ret;
1283 }
1284
1285 if (priv->temperature_sensor_calibrated) {
1286 indio_dev->channels = meson_sar_adc_and_temp_iio_channels;
1287 indio_dev->num_channels =
1288 ARRAY_SIZE(meson_sar_adc_and_temp_iio_channels);
1289 } else {
1290 indio_dev->channels = meson_sar_adc_iio_channels;
1291 indio_dev->num_channels =
1292 ARRAY_SIZE(meson_sar_adc_iio_channels);
1293 }
1294
1295 ret = meson_sar_adc_init(indio_dev);
1296 if (ret)
1297 goto err;
1298
1299 ret = meson_sar_adc_hw_enable(indio_dev);
1300 if (ret)
1301 goto err;
1302
1303 ret = meson_sar_adc_calib(indio_dev);
1304 if (ret)
1305 dev_warn(&pdev->dev, "calibration failed\n");
1306
1307 platform_set_drvdata(pdev, indio_dev);
1308
1309 ret = iio_device_register(indio_dev);
1310 if (ret)
1311 goto err_hw;
1312
1313 return 0;
1314
1315 err_hw:
1316 meson_sar_adc_hw_disable(indio_dev);
1317 err:
1318 return ret;
1319 }
1320
1321 static int meson_sar_adc_remove(struct platform_device *pdev)
1322 {
1323 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
1324
1325 iio_device_unregister(indio_dev);
1326
1327 return meson_sar_adc_hw_disable(indio_dev);
1328 }
1329
1330 static int __maybe_unused meson_sar_adc_suspend(struct device *dev)
1331 {
1332 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1333
1334 return meson_sar_adc_hw_disable(indio_dev);
1335 }
1336
1337 static int __maybe_unused meson_sar_adc_resume(struct device *dev)
1338 {
1339 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1340
1341 return meson_sar_adc_hw_enable(indio_dev);
1342 }
1343
1344 static SIMPLE_DEV_PM_OPS(meson_sar_adc_pm_ops,
1345 meson_sar_adc_suspend, meson_sar_adc_resume);
1346
1347 static struct platform_driver meson_sar_adc_driver = {
1348 .probe = meson_sar_adc_probe,
1349 .remove = meson_sar_adc_remove,
1350 .driver = {
1351 .name = "meson-saradc",
1352 .of_match_table = meson_sar_adc_of_match,
1353 .pm = &meson_sar_adc_pm_ops,
1354 },
1355 };
1356
1357 module_platform_driver(meson_sar_adc_driver);
1358
1359 MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
1360 MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver");
1361 MODULE_LICENSE("GPL v2");
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