2 * This file is part of STM32 ADC driver
4 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
5 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE.
16 * See the GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
22 #include <linux/clk.h>
23 #include <linux/delay.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/dmaengine.h>
26 #include <linux/iio/iio.h>
27 #include <linux/iio/buffer.h>
28 #include <linux/iio/timer/stm32-timer-trigger.h>
29 #include <linux/iio/trigger.h>
30 #include <linux/iio/trigger_consumer.h>
31 #include <linux/iio/triggered_buffer.h>
32 #include <linux/interrupt.h>
34 #include <linux/iopoll.h>
35 #include <linux/module.h>
36 #include <linux/platform_device.h>
38 #include <linux/of_device.h>
40 #include "stm32-adc-core.h"
42 /* STM32F4 - Registers for each ADC instance */
43 #define STM32F4_ADC_SR 0x00
44 #define STM32F4_ADC_CR1 0x04
45 #define STM32F4_ADC_CR2 0x08
46 #define STM32F4_ADC_SMPR1 0x0C
47 #define STM32F4_ADC_SMPR2 0x10
48 #define STM32F4_ADC_HTR 0x24
49 #define STM32F4_ADC_LTR 0x28
50 #define STM32F4_ADC_SQR1 0x2C
51 #define STM32F4_ADC_SQR2 0x30
52 #define STM32F4_ADC_SQR3 0x34
53 #define STM32F4_ADC_JSQR 0x38
54 #define STM32F4_ADC_JDR1 0x3C
55 #define STM32F4_ADC_JDR2 0x40
56 #define STM32F4_ADC_JDR3 0x44
57 #define STM32F4_ADC_JDR4 0x48
58 #define STM32F4_ADC_DR 0x4C
60 /* STM32F4_ADC_SR - bit fields */
61 #define STM32F4_STRT BIT(4)
62 #define STM32F4_EOC BIT(1)
64 /* STM32F4_ADC_CR1 - bit fields */
65 #define STM32F4_RES_SHIFT 24
66 #define STM32F4_RES_MASK GENMASK(25, 24)
67 #define STM32F4_SCAN BIT(8)
68 #define STM32F4_EOCIE BIT(5)
70 /* STM32F4_ADC_CR2 - bit fields */
71 #define STM32F4_SWSTART BIT(30)
72 #define STM32F4_EXTEN_SHIFT 28
73 #define STM32F4_EXTEN_MASK GENMASK(29, 28)
74 #define STM32F4_EXTSEL_SHIFT 24
75 #define STM32F4_EXTSEL_MASK GENMASK(27, 24)
76 #define STM32F4_EOCS BIT(10)
77 #define STM32F4_DDS BIT(9)
78 #define STM32F4_DMA BIT(8)
79 #define STM32F4_ADON BIT(0)
81 /* STM32H7 - Registers for each ADC instance */
82 #define STM32H7_ADC_ISR 0x00
83 #define STM32H7_ADC_IER 0x04
84 #define STM32H7_ADC_CR 0x08
85 #define STM32H7_ADC_CFGR 0x0C
86 #define STM32H7_ADC_PCSEL 0x1C
87 #define STM32H7_ADC_SQR1 0x30
88 #define STM32H7_ADC_SQR2 0x34
89 #define STM32H7_ADC_SQR3 0x38
90 #define STM32H7_ADC_SQR4 0x3C
91 #define STM32H7_ADC_DR 0x40
92 #define STM32H7_ADC_CALFACT 0xC4
93 #define STM32H7_ADC_CALFACT2 0xC8
95 /* STM32H7_ADC_ISR - bit fields */
96 #define STM32H7_EOC BIT(2)
97 #define STM32H7_ADRDY BIT(0)
99 /* STM32H7_ADC_IER - bit fields */
100 #define STM32H7_EOCIE STM32H7_EOC
102 /* STM32H7_ADC_CR - bit fields */
103 #define STM32H7_ADCAL BIT(31)
104 #define STM32H7_ADCALDIF BIT(30)
105 #define STM32H7_DEEPPWD BIT(29)
106 #define STM32H7_ADVREGEN BIT(28)
107 #define STM32H7_LINCALRDYW6 BIT(27)
108 #define STM32H7_LINCALRDYW5 BIT(26)
109 #define STM32H7_LINCALRDYW4 BIT(25)
110 #define STM32H7_LINCALRDYW3 BIT(24)
111 #define STM32H7_LINCALRDYW2 BIT(23)
112 #define STM32H7_LINCALRDYW1 BIT(22)
113 #define STM32H7_ADCALLIN BIT(16)
114 #define STM32H7_BOOST BIT(8)
115 #define STM32H7_ADSTP BIT(4)
116 #define STM32H7_ADSTART BIT(2)
117 #define STM32H7_ADDIS BIT(1)
118 #define STM32H7_ADEN BIT(0)
120 /* STM32H7_ADC_CFGR bit fields */
121 #define STM32H7_EXTEN_SHIFT 10
122 #define STM32H7_EXTEN_MASK GENMASK(11, 10)
123 #define STM32H7_EXTSEL_SHIFT 5
124 #define STM32H7_EXTSEL_MASK GENMASK(9, 5)
125 #define STM32H7_RES_SHIFT 2
126 #define STM32H7_RES_MASK GENMASK(4, 2)
127 #define STM32H7_DMNGT_SHIFT 0
128 #define STM32H7_DMNGT_MASK GENMASK(1, 0)
130 enum stm32h7_adc_dmngt
{
131 STM32H7_DMNGT_DR_ONLY
, /* Regular data in DR only */
132 STM32H7_DMNGT_DMA_ONESHOT
, /* DMA one shot mode */
133 STM32H7_DMNGT_DFSDM
, /* DFSDM mode */
134 STM32H7_DMNGT_DMA_CIRC
, /* DMA circular mode */
137 /* STM32H7_ADC_CALFACT - bit fields */
138 #define STM32H7_CALFACT_D_SHIFT 16
139 #define STM32H7_CALFACT_D_MASK GENMASK(26, 16)
140 #define STM32H7_CALFACT_S_SHIFT 0
141 #define STM32H7_CALFACT_S_MASK GENMASK(10, 0)
143 /* STM32H7_ADC_CALFACT2 - bit fields */
144 #define STM32H7_LINCALFACT_SHIFT 0
145 #define STM32H7_LINCALFACT_MASK GENMASK(29, 0)
147 /* Number of linear calibration shadow registers / LINCALRDYW control bits */
148 #define STM32H7_LINCALFACT_NUM 6
150 /* BOOST bit must be set on STM32H7 when ADC clock is above 20MHz */
151 #define STM32H7_BOOST_CLKRATE 20000000UL
153 #define STM32_ADC_MAX_SQ 16 /* SQ1..SQ16 */
154 #define STM32_ADC_TIMEOUT_US 100000
155 #define STM32_ADC_TIMEOUT (msecs_to_jiffies(STM32_ADC_TIMEOUT_US / 1000))
157 #define STM32_DMA_BUFFER_SIZE PAGE_SIZE
159 /* External trigger enable */
160 enum stm32_adc_exten
{
162 STM32_EXTEN_HWTRIG_RISING_EDGE
,
163 STM32_EXTEN_HWTRIG_FALLING_EDGE
,
164 STM32_EXTEN_HWTRIG_BOTH_EDGES
,
167 /* extsel - trigger mux selection value */
168 enum stm32_adc_extsel
{
188 * struct stm32_adc_trig_info - ADC trigger info
189 * @name: name of the trigger, corresponding to its source
190 * @extsel: trigger selection
192 struct stm32_adc_trig_info
{
194 enum stm32_adc_extsel extsel
;
198 * struct stm32_adc_calib - optional adc calibration data
199 * @calfact_s: Calibration offset for single ended channels
200 * @calfact_d: Calibration offset in differential
201 * @lincalfact: Linearity calibration factor
203 struct stm32_adc_calib
{
206 u32 lincalfact
[STM32H7_LINCALFACT_NUM
];
210 * stm32_adc_regs - stm32 ADC misc registers & bitfield desc
211 * @reg: register offset
212 * @mask: bitfield mask
215 struct stm32_adc_regs
{
222 * stm32_adc_regspec - stm32 registers definition, compatible dependent data
223 * @dr: data register offset
224 * @ier_eoc: interrupt enable register & eocie bitfield
225 * @isr_eoc: interrupt status register & eoc bitfield
226 * @sqr: reference to sequence registers array
227 * @exten: trigger control register & bitfield
228 * @extsel: trigger selection register & bitfield
229 * @res: resolution selection register & bitfield
231 struct stm32_adc_regspec
{
233 const struct stm32_adc_regs ier_eoc
;
234 const struct stm32_adc_regs isr_eoc
;
235 const struct stm32_adc_regs
*sqr
;
236 const struct stm32_adc_regs exten
;
237 const struct stm32_adc_regs extsel
;
238 const struct stm32_adc_regs res
;
244 * stm32_adc_cfg - stm32 compatible configuration data
245 * @regs: registers descriptions
246 * @adc_info: per instance input channels definitions
247 * @trigs: external trigger sources
248 * @clk_required: clock is required
249 * @selfcalib: optional routine for self-calibration
250 * @prepare: optional prepare routine (power-up, enable)
251 * @start_conv: routine to start conversions
252 * @stop_conv: routine to stop conversions
253 * @unprepare: optional unprepare routine (disable, power-down)
255 struct stm32_adc_cfg
{
256 const struct stm32_adc_regspec
*regs
;
257 const struct stm32_adc_info
*adc_info
;
258 struct stm32_adc_trig_info
*trigs
;
260 int (*selfcalib
)(struct stm32_adc
*);
261 int (*prepare
)(struct stm32_adc
*);
262 void (*start_conv
)(struct stm32_adc
*, bool dma
);
263 void (*stop_conv
)(struct stm32_adc
*);
264 void (*unprepare
)(struct stm32_adc
*);
268 * struct stm32_adc - private data of each ADC IIO instance
269 * @common: reference to ADC block common data
270 * @offset: ADC instance register offset in ADC block
271 * @cfg: compatible configuration data
272 * @completion: end of single conversion completion
273 * @buffer: data buffer
274 * @clk: clock for this adc instance
275 * @irq: interrupt for this adc instance
277 * @bufi: data buffer index
278 * @num_conv: expected number of scan conversions
279 * @res: data resolution (e.g. RES bitfield value)
280 * @trigger_polarity: external trigger polarity (e.g. exten)
281 * @dma_chan: dma channel
282 * @rx_buf: dma rx buffer cpu address
283 * @rx_dma_buf: dma rx buffer bus address
284 * @rx_buf_sz: dma rx buffer size
285 * @pcsel bitmask to preselect channels on some devices
286 * @cal: optional calibration data on some devices
289 struct stm32_adc_common
*common
;
291 const struct stm32_adc_cfg
*cfg
;
292 struct completion completion
;
293 u16 buffer
[STM32_ADC_MAX_SQ
];
296 spinlock_t lock
; /* interrupt lock */
298 unsigned int num_conv
;
300 u32 trigger_polarity
;
301 struct dma_chan
*dma_chan
;
303 dma_addr_t rx_dma_buf
;
304 unsigned int rx_buf_sz
;
306 struct stm32_adc_calib cal
;
310 * struct stm32_adc_chan_spec - specification of stm32 adc channel
311 * @type: IIO channel type
312 * @channel: channel number (single ended)
313 * @name: channel name (single ended)
315 struct stm32_adc_chan_spec
{
316 enum iio_chan_type type
;
322 * struct stm32_adc_info - stm32 ADC, per instance config data
323 * @channels: Reference to stm32 channels spec
324 * @max_channels: Number of channels
325 * @resolutions: available resolutions
326 * @num_res: number of available resolutions
328 struct stm32_adc_info
{
329 const struct stm32_adc_chan_spec
*channels
;
331 const unsigned int *resolutions
;
332 const unsigned int num_res
;
336 * Input definitions common for all instances:
337 * stm32f4 can have up to 16 channels
338 * stm32h7 can have up to 20 channels
340 static const struct stm32_adc_chan_spec stm32_adc_channels
[] = {
341 { IIO_VOLTAGE
, 0, "in0" },
342 { IIO_VOLTAGE
, 1, "in1" },
343 { IIO_VOLTAGE
, 2, "in2" },
344 { IIO_VOLTAGE
, 3, "in3" },
345 { IIO_VOLTAGE
, 4, "in4" },
346 { IIO_VOLTAGE
, 5, "in5" },
347 { IIO_VOLTAGE
, 6, "in6" },
348 { IIO_VOLTAGE
, 7, "in7" },
349 { IIO_VOLTAGE
, 8, "in8" },
350 { IIO_VOLTAGE
, 9, "in9" },
351 { IIO_VOLTAGE
, 10, "in10" },
352 { IIO_VOLTAGE
, 11, "in11" },
353 { IIO_VOLTAGE
, 12, "in12" },
354 { IIO_VOLTAGE
, 13, "in13" },
355 { IIO_VOLTAGE
, 14, "in14" },
356 { IIO_VOLTAGE
, 15, "in15" },
357 { IIO_VOLTAGE
, 16, "in16" },
358 { IIO_VOLTAGE
, 17, "in17" },
359 { IIO_VOLTAGE
, 18, "in18" },
360 { IIO_VOLTAGE
, 19, "in19" },
363 static const unsigned int stm32f4_adc_resolutions
[] = {
364 /* sorted values so the index matches RES[1:0] in STM32F4_ADC_CR1 */
368 static const struct stm32_adc_info stm32f4_adc_info
= {
369 .channels
= stm32_adc_channels
,
371 .resolutions
= stm32f4_adc_resolutions
,
372 .num_res
= ARRAY_SIZE(stm32f4_adc_resolutions
),
375 static const unsigned int stm32h7_adc_resolutions
[] = {
376 /* sorted values so the index matches RES[2:0] in STM32H7_ADC_CFGR */
380 static const struct stm32_adc_info stm32h7_adc_info
= {
381 .channels
= stm32_adc_channels
,
383 .resolutions
= stm32h7_adc_resolutions
,
384 .num_res
= ARRAY_SIZE(stm32h7_adc_resolutions
),
388 * stm32f4_sq - describe regular sequence registers
389 * - L: sequence len (register & bit field)
390 * - SQ1..SQ16: sequence entries (register & bit field)
392 static const struct stm32_adc_regs stm32f4_sq
[STM32_ADC_MAX_SQ
+ 1] = {
393 /* L: len bit field description to be kept as first element */
394 { STM32F4_ADC_SQR1
, GENMASK(23, 20), 20 },
395 /* SQ1..SQ16 registers & bit fields (reg, mask, shift) */
396 { STM32F4_ADC_SQR3
, GENMASK(4, 0), 0 },
397 { STM32F4_ADC_SQR3
, GENMASK(9, 5), 5 },
398 { STM32F4_ADC_SQR3
, GENMASK(14, 10), 10 },
399 { STM32F4_ADC_SQR3
, GENMASK(19, 15), 15 },
400 { STM32F4_ADC_SQR3
, GENMASK(24, 20), 20 },
401 { STM32F4_ADC_SQR3
, GENMASK(29, 25), 25 },
402 { STM32F4_ADC_SQR2
, GENMASK(4, 0), 0 },
403 { STM32F4_ADC_SQR2
, GENMASK(9, 5), 5 },
404 { STM32F4_ADC_SQR2
, GENMASK(14, 10), 10 },
405 { STM32F4_ADC_SQR2
, GENMASK(19, 15), 15 },
406 { STM32F4_ADC_SQR2
, GENMASK(24, 20), 20 },
407 { STM32F4_ADC_SQR2
, GENMASK(29, 25), 25 },
408 { STM32F4_ADC_SQR1
, GENMASK(4, 0), 0 },
409 { STM32F4_ADC_SQR1
, GENMASK(9, 5), 5 },
410 { STM32F4_ADC_SQR1
, GENMASK(14, 10), 10 },
411 { STM32F4_ADC_SQR1
, GENMASK(19, 15), 15 },
414 /* STM32F4 external trigger sources for all instances */
415 static struct stm32_adc_trig_info stm32f4_adc_trigs
[] = {
416 { TIM1_CH1
, STM32_EXT0
},
417 { TIM1_CH2
, STM32_EXT1
},
418 { TIM1_CH3
, STM32_EXT2
},
419 { TIM2_CH2
, STM32_EXT3
},
420 { TIM2_CH3
, STM32_EXT4
},
421 { TIM2_CH4
, STM32_EXT5
},
422 { TIM2_TRGO
, STM32_EXT6
},
423 { TIM3_CH1
, STM32_EXT7
},
424 { TIM3_TRGO
, STM32_EXT8
},
425 { TIM4_CH4
, STM32_EXT9
},
426 { TIM5_CH1
, STM32_EXT10
},
427 { TIM5_CH2
, STM32_EXT11
},
428 { TIM5_CH3
, STM32_EXT12
},
429 { TIM8_CH1
, STM32_EXT13
},
430 { TIM8_TRGO
, STM32_EXT14
},
434 static const struct stm32_adc_regspec stm32f4_adc_regspec
= {
435 .dr
= STM32F4_ADC_DR
,
436 .ier_eoc
= { STM32F4_ADC_CR1
, STM32F4_EOCIE
},
437 .isr_eoc
= { STM32F4_ADC_SR
, STM32F4_EOC
},
439 .exten
= { STM32F4_ADC_CR2
, STM32F4_EXTEN_MASK
, STM32F4_EXTEN_SHIFT
},
440 .extsel
= { STM32F4_ADC_CR2
, STM32F4_EXTSEL_MASK
,
441 STM32F4_EXTSEL_SHIFT
},
442 .res
= { STM32F4_ADC_CR1
, STM32F4_RES_MASK
, STM32F4_RES_SHIFT
},
445 static const struct stm32_adc_regs stm32h7_sq
[STM32_ADC_MAX_SQ
+ 1] = {
446 /* L: len bit field description to be kept as first element */
447 { STM32H7_ADC_SQR1
, GENMASK(3, 0), 0 },
448 /* SQ1..SQ16 registers & bit fields (reg, mask, shift) */
449 { STM32H7_ADC_SQR1
, GENMASK(10, 6), 6 },
450 { STM32H7_ADC_SQR1
, GENMASK(16, 12), 12 },
451 { STM32H7_ADC_SQR1
, GENMASK(22, 18), 18 },
452 { STM32H7_ADC_SQR1
, GENMASK(28, 24), 24 },
453 { STM32H7_ADC_SQR2
, GENMASK(4, 0), 0 },
454 { STM32H7_ADC_SQR2
, GENMASK(10, 6), 6 },
455 { STM32H7_ADC_SQR2
, GENMASK(16, 12), 12 },
456 { STM32H7_ADC_SQR2
, GENMASK(22, 18), 18 },
457 { STM32H7_ADC_SQR2
, GENMASK(28, 24), 24 },
458 { STM32H7_ADC_SQR3
, GENMASK(4, 0), 0 },
459 { STM32H7_ADC_SQR3
, GENMASK(10, 6), 6 },
460 { STM32H7_ADC_SQR3
, GENMASK(16, 12), 12 },
461 { STM32H7_ADC_SQR3
, GENMASK(22, 18), 18 },
462 { STM32H7_ADC_SQR3
, GENMASK(28, 24), 24 },
463 { STM32H7_ADC_SQR4
, GENMASK(4, 0), 0 },
464 { STM32H7_ADC_SQR4
, GENMASK(10, 6), 6 },
467 /* STM32H7 external trigger sources for all instances */
468 static struct stm32_adc_trig_info stm32h7_adc_trigs
[] = {
469 { TIM1_CH1
, STM32_EXT0
},
470 { TIM1_CH2
, STM32_EXT1
},
471 { TIM1_CH3
, STM32_EXT2
},
472 { TIM2_CH2
, STM32_EXT3
},
473 { TIM3_TRGO
, STM32_EXT4
},
474 { TIM4_CH4
, STM32_EXT5
},
475 { TIM8_TRGO
, STM32_EXT7
},
476 { TIM8_TRGO2
, STM32_EXT8
},
477 { TIM1_TRGO
, STM32_EXT9
},
478 { TIM1_TRGO2
, STM32_EXT10
},
479 { TIM2_TRGO
, STM32_EXT11
},
480 { TIM4_TRGO
, STM32_EXT12
},
481 { TIM6_TRGO
, STM32_EXT13
},
482 { TIM3_CH4
, STM32_EXT15
},
486 static const struct stm32_adc_regspec stm32h7_adc_regspec
= {
487 .dr
= STM32H7_ADC_DR
,
488 .ier_eoc
= { STM32H7_ADC_IER
, STM32H7_EOCIE
},
489 .isr_eoc
= { STM32H7_ADC_ISR
, STM32H7_EOC
},
491 .exten
= { STM32H7_ADC_CFGR
, STM32H7_EXTEN_MASK
, STM32H7_EXTEN_SHIFT
},
492 .extsel
= { STM32H7_ADC_CFGR
, STM32H7_EXTSEL_MASK
,
493 STM32H7_EXTSEL_SHIFT
},
494 .res
= { STM32H7_ADC_CFGR
, STM32H7_RES_MASK
, STM32H7_RES_SHIFT
},
498 * STM32 ADC registers access routines
499 * @adc: stm32 adc instance
500 * @reg: reg offset in adc instance
502 * Note: All instances share same base, with 0x0, 0x100 or 0x200 offset resp.
503 * for adc1, adc2 and adc3.
505 static u32
stm32_adc_readl(struct stm32_adc
*adc
, u32 reg
)
507 return readl_relaxed(adc
->common
->base
+ adc
->offset
+ reg
);
510 #define stm32_adc_readl_addr(addr) stm32_adc_readl(adc, addr)
512 #define stm32_adc_readl_poll_timeout(reg, val, cond, sleep_us, timeout_us) \
513 readx_poll_timeout(stm32_adc_readl_addr, reg, val, \
514 cond, sleep_us, timeout_us)
516 static u16
stm32_adc_readw(struct stm32_adc
*adc
, u32 reg
)
518 return readw_relaxed(adc
->common
->base
+ adc
->offset
+ reg
);
521 static void stm32_adc_writel(struct stm32_adc
*adc
, u32 reg
, u32 val
)
523 writel_relaxed(val
, adc
->common
->base
+ adc
->offset
+ reg
);
526 static void stm32_adc_set_bits(struct stm32_adc
*adc
, u32 reg
, u32 bits
)
530 spin_lock_irqsave(&adc
->lock
, flags
);
531 stm32_adc_writel(adc
, reg
, stm32_adc_readl(adc
, reg
) | bits
);
532 spin_unlock_irqrestore(&adc
->lock
, flags
);
535 static void stm32_adc_clr_bits(struct stm32_adc
*adc
, u32 reg
, u32 bits
)
539 spin_lock_irqsave(&adc
->lock
, flags
);
540 stm32_adc_writel(adc
, reg
, stm32_adc_readl(adc
, reg
) & ~bits
);
541 spin_unlock_irqrestore(&adc
->lock
, flags
);
545 * stm32_adc_conv_irq_enable() - Enable end of conversion interrupt
546 * @adc: stm32 adc instance
548 static void stm32_adc_conv_irq_enable(struct stm32_adc
*adc
)
550 stm32_adc_set_bits(adc
, adc
->cfg
->regs
->ier_eoc
.reg
,
551 adc
->cfg
->regs
->ier_eoc
.mask
);
555 * stm32_adc_conv_irq_disable() - Disable end of conversion interrupt
556 * @adc: stm32 adc instance
558 static void stm32_adc_conv_irq_disable(struct stm32_adc
*adc
)
560 stm32_adc_clr_bits(adc
, adc
->cfg
->regs
->ier_eoc
.reg
,
561 adc
->cfg
->regs
->ier_eoc
.mask
);
564 static void stm32_adc_set_res(struct stm32_adc
*adc
)
566 const struct stm32_adc_regs
*res
= &adc
->cfg
->regs
->res
;
569 val
= stm32_adc_readl(adc
, res
->reg
);
570 val
= (val
& ~res
->mask
) | (adc
->res
<< res
->shift
);
571 stm32_adc_writel(adc
, res
->reg
, val
);
575 * stm32f4_adc_start_conv() - Start conversions for regular channels.
576 * @adc: stm32 adc instance
577 * @dma: use dma to transfer conversion result
579 * Start conversions for regular channels.
580 * Also take care of normal or DMA mode. Circular DMA may be used for regular
581 * conversions, in IIO buffer modes. Otherwise, use ADC interrupt with direct
582 * DR read instead (e.g. read_raw, or triggered buffer mode without DMA).
584 static void stm32f4_adc_start_conv(struct stm32_adc
*adc
, bool dma
)
586 stm32_adc_set_bits(adc
, STM32F4_ADC_CR1
, STM32F4_SCAN
);
589 stm32_adc_set_bits(adc
, STM32F4_ADC_CR2
,
590 STM32F4_DMA
| STM32F4_DDS
);
592 stm32_adc_set_bits(adc
, STM32F4_ADC_CR2
, STM32F4_EOCS
| STM32F4_ADON
);
594 /* Wait for Power-up time (tSTAB from datasheet) */
597 /* Software start ? (e.g. trigger detection disabled ?) */
598 if (!(stm32_adc_readl(adc
, STM32F4_ADC_CR2
) & STM32F4_EXTEN_MASK
))
599 stm32_adc_set_bits(adc
, STM32F4_ADC_CR2
, STM32F4_SWSTART
);
602 static void stm32f4_adc_stop_conv(struct stm32_adc
*adc
)
604 stm32_adc_clr_bits(adc
, STM32F4_ADC_CR2
, STM32F4_EXTEN_MASK
);
605 stm32_adc_clr_bits(adc
, STM32F4_ADC_SR
, STM32F4_STRT
);
607 stm32_adc_clr_bits(adc
, STM32F4_ADC_CR1
, STM32F4_SCAN
);
608 stm32_adc_clr_bits(adc
, STM32F4_ADC_CR2
,
609 STM32F4_ADON
| STM32F4_DMA
| STM32F4_DDS
);
612 static void stm32h7_adc_start_conv(struct stm32_adc
*adc
, bool dma
)
614 enum stm32h7_adc_dmngt dmngt
;
619 dmngt
= STM32H7_DMNGT_DMA_CIRC
;
621 dmngt
= STM32H7_DMNGT_DR_ONLY
;
623 spin_lock_irqsave(&adc
->lock
, flags
);
624 val
= stm32_adc_readl(adc
, STM32H7_ADC_CFGR
);
625 val
= (val
& ~STM32H7_DMNGT_MASK
) | (dmngt
<< STM32H7_DMNGT_SHIFT
);
626 stm32_adc_writel(adc
, STM32H7_ADC_CFGR
, val
);
627 spin_unlock_irqrestore(&adc
->lock
, flags
);
629 stm32_adc_set_bits(adc
, STM32H7_ADC_CR
, STM32H7_ADSTART
);
632 static void stm32h7_adc_stop_conv(struct stm32_adc
*adc
)
634 struct iio_dev
*indio_dev
= iio_priv_to_dev(adc
);
638 stm32_adc_set_bits(adc
, STM32H7_ADC_CR
, STM32H7_ADSTP
);
640 ret
= stm32_adc_readl_poll_timeout(STM32H7_ADC_CR
, val
,
641 !(val
& (STM32H7_ADSTART
)),
642 100, STM32_ADC_TIMEOUT_US
);
644 dev_warn(&indio_dev
->dev
, "stop failed\n");
646 stm32_adc_clr_bits(adc
, STM32H7_ADC_CFGR
, STM32H7_DMNGT_MASK
);
649 static void stm32h7_adc_exit_pwr_down(struct stm32_adc
*adc
)
651 /* Exit deep power down, then enable ADC voltage regulator */
652 stm32_adc_clr_bits(adc
, STM32H7_ADC_CR
, STM32H7_DEEPPWD
);
653 stm32_adc_set_bits(adc
, STM32H7_ADC_CR
, STM32H7_ADVREGEN
);
655 if (adc
->common
->rate
> STM32H7_BOOST_CLKRATE
)
656 stm32_adc_set_bits(adc
, STM32H7_ADC_CR
, STM32H7_BOOST
);
658 /* Wait for startup time */
659 usleep_range(10, 20);
662 static void stm32h7_adc_enter_pwr_down(struct stm32_adc
*adc
)
664 stm32_adc_clr_bits(adc
, STM32H7_ADC_CR
, STM32H7_BOOST
);
666 /* Setting DEEPPWD disables ADC vreg and clears ADVREGEN */
667 stm32_adc_set_bits(adc
, STM32H7_ADC_CR
, STM32H7_DEEPPWD
);
670 static int stm32h7_adc_enable(struct stm32_adc
*adc
)
672 struct iio_dev
*indio_dev
= iio_priv_to_dev(adc
);
676 /* Clear ADRDY by writing one, then enable ADC */
677 stm32_adc_set_bits(adc
, STM32H7_ADC_ISR
, STM32H7_ADRDY
);
678 stm32_adc_set_bits(adc
, STM32H7_ADC_CR
, STM32H7_ADEN
);
680 /* Poll for ADRDY to be set (after adc startup time) */
681 ret
= stm32_adc_readl_poll_timeout(STM32H7_ADC_ISR
, val
,
683 100, STM32_ADC_TIMEOUT_US
);
685 stm32_adc_clr_bits(adc
, STM32H7_ADC_CR
, STM32H7_ADEN
);
686 dev_err(&indio_dev
->dev
, "Failed to enable ADC\n");
692 static void stm32h7_adc_disable(struct stm32_adc
*adc
)
694 struct iio_dev
*indio_dev
= iio_priv_to_dev(adc
);
698 /* Disable ADC and wait until it's effectively disabled */
699 stm32_adc_set_bits(adc
, STM32H7_ADC_CR
, STM32H7_ADDIS
);
700 ret
= stm32_adc_readl_poll_timeout(STM32H7_ADC_CR
, val
,
701 !(val
& STM32H7_ADEN
), 100,
702 STM32_ADC_TIMEOUT_US
);
704 dev_warn(&indio_dev
->dev
, "Failed to disable\n");
708 * stm32h7_adc_read_selfcalib() - read calibration shadow regs, save result
709 * @adc: stm32 adc instance
711 static int stm32h7_adc_read_selfcalib(struct stm32_adc
*adc
)
713 struct iio_dev
*indio_dev
= iio_priv_to_dev(adc
);
715 u32 lincalrdyw_mask
, val
;
717 /* Enable adc so LINCALRDYW1..6 bits are writable */
718 ret
= stm32h7_adc_enable(adc
);
722 /* Read linearity calibration */
723 lincalrdyw_mask
= STM32H7_LINCALRDYW6
;
724 for (i
= STM32H7_LINCALFACT_NUM
- 1; i
>= 0; i
--) {
725 /* Clear STM32H7_LINCALRDYW[6..1]: transfer calib to CALFACT2 */
726 stm32_adc_clr_bits(adc
, STM32H7_ADC_CR
, lincalrdyw_mask
);
728 /* Poll: wait calib data to be ready in CALFACT2 register */
729 ret
= stm32_adc_readl_poll_timeout(STM32H7_ADC_CR
, val
,
730 !(val
& lincalrdyw_mask
),
731 100, STM32_ADC_TIMEOUT_US
);
733 dev_err(&indio_dev
->dev
, "Failed to read calfact\n");
737 val
= stm32_adc_readl(adc
, STM32H7_ADC_CALFACT2
);
738 adc
->cal
.lincalfact
[i
] = (val
& STM32H7_LINCALFACT_MASK
);
739 adc
->cal
.lincalfact
[i
] >>= STM32H7_LINCALFACT_SHIFT
;
741 lincalrdyw_mask
>>= 1;
744 /* Read offset calibration */
745 val
= stm32_adc_readl(adc
, STM32H7_ADC_CALFACT
);
746 adc
->cal
.calfact_s
= (val
& STM32H7_CALFACT_S_MASK
);
747 adc
->cal
.calfact_s
>>= STM32H7_CALFACT_S_SHIFT
;
748 adc
->cal
.calfact_d
= (val
& STM32H7_CALFACT_D_MASK
);
749 adc
->cal
.calfact_d
>>= STM32H7_CALFACT_D_SHIFT
;
752 stm32h7_adc_disable(adc
);
758 * stm32h7_adc_restore_selfcalib() - Restore saved self-calibration result
759 * @adc: stm32 adc instance
760 * Note: ADC must be enabled, with no on-going conversions.
762 static int stm32h7_adc_restore_selfcalib(struct stm32_adc
*adc
)
764 struct iio_dev
*indio_dev
= iio_priv_to_dev(adc
);
766 u32 lincalrdyw_mask
, val
;
768 val
= (adc
->cal
.calfact_s
<< STM32H7_CALFACT_S_SHIFT
) |
769 (adc
->cal
.calfact_d
<< STM32H7_CALFACT_D_SHIFT
);
770 stm32_adc_writel(adc
, STM32H7_ADC_CALFACT
, val
);
772 lincalrdyw_mask
= STM32H7_LINCALRDYW6
;
773 for (i
= STM32H7_LINCALFACT_NUM
- 1; i
>= 0; i
--) {
775 * Write saved calibration data to shadow registers:
776 * Write CALFACT2, and set LINCALRDYW[6..1] bit to trigger
777 * data write. Then poll to wait for complete transfer.
779 val
= adc
->cal
.lincalfact
[i
] << STM32H7_LINCALFACT_SHIFT
;
780 stm32_adc_writel(adc
, STM32H7_ADC_CALFACT2
, val
);
781 stm32_adc_set_bits(adc
, STM32H7_ADC_CR
, lincalrdyw_mask
);
782 ret
= stm32_adc_readl_poll_timeout(STM32H7_ADC_CR
, val
,
783 val
& lincalrdyw_mask
,
784 100, STM32_ADC_TIMEOUT_US
);
786 dev_err(&indio_dev
->dev
, "Failed to write calfact\n");
791 * Read back calibration data, has two effects:
792 * - It ensures bits LINCALRDYW[6..1] are kept cleared
793 * for next time calibration needs to be restored.
794 * - BTW, bit clear triggers a read, then check data has been
797 stm32_adc_clr_bits(adc
, STM32H7_ADC_CR
, lincalrdyw_mask
);
798 ret
= stm32_adc_readl_poll_timeout(STM32H7_ADC_CR
, val
,
799 !(val
& lincalrdyw_mask
),
800 100, STM32_ADC_TIMEOUT_US
);
802 dev_err(&indio_dev
->dev
, "Failed to read calfact\n");
805 val
= stm32_adc_readl(adc
, STM32H7_ADC_CALFACT2
);
806 if (val
!= adc
->cal
.lincalfact
[i
] << STM32H7_LINCALFACT_SHIFT
) {
807 dev_err(&indio_dev
->dev
, "calfact not consistent\n");
811 lincalrdyw_mask
>>= 1;
818 * Fixed timeout value for ADC calibration.
820 * - low clock frequency
821 * - maximum prescalers
822 * Calibration requires:
823 * - 131,072 ADC clock cycle for the linear calibration
824 * - 20 ADC clock cycle for the offset calibration
826 * Set to 100ms for now
828 #define STM32H7_ADC_CALIB_TIMEOUT_US 100000
831 * stm32h7_adc_selfcalib() - Procedure to calibrate ADC (from power down)
832 * @adc: stm32 adc instance
833 * Exit from power down, calibrate ADC, then return to power down.
835 static int stm32h7_adc_selfcalib(struct stm32_adc
*adc
)
837 struct iio_dev
*indio_dev
= iio_priv_to_dev(adc
);
841 stm32h7_adc_exit_pwr_down(adc
);
844 * Select calibration mode:
845 * - Offset calibration for single ended inputs
846 * - No linearity calibration (do it later, before reading it)
848 stm32_adc_clr_bits(adc
, STM32H7_ADC_CR
, STM32H7_ADCALDIF
);
849 stm32_adc_clr_bits(adc
, STM32H7_ADC_CR
, STM32H7_ADCALLIN
);
851 /* Start calibration, then wait for completion */
852 stm32_adc_set_bits(adc
, STM32H7_ADC_CR
, STM32H7_ADCAL
);
853 ret
= stm32_adc_readl_poll_timeout(STM32H7_ADC_CR
, val
,
854 !(val
& STM32H7_ADCAL
), 100,
855 STM32H7_ADC_CALIB_TIMEOUT_US
);
857 dev_err(&indio_dev
->dev
, "calibration failed\n");
862 * Select calibration mode, then start calibration:
863 * - Offset calibration for differential input
864 * - Linearity calibration (needs to be done only once for single/diff)
865 * will run simultaneously with offset calibration.
867 stm32_adc_set_bits(adc
, STM32H7_ADC_CR
,
868 STM32H7_ADCALDIF
| STM32H7_ADCALLIN
);
869 stm32_adc_set_bits(adc
, STM32H7_ADC_CR
, STM32H7_ADCAL
);
870 ret
= stm32_adc_readl_poll_timeout(STM32H7_ADC_CR
, val
,
871 !(val
& STM32H7_ADCAL
), 100,
872 STM32H7_ADC_CALIB_TIMEOUT_US
);
874 dev_err(&indio_dev
->dev
, "calibration failed\n");
878 stm32_adc_clr_bits(adc
, STM32H7_ADC_CR
,
879 STM32H7_ADCALDIF
| STM32H7_ADCALLIN
);
881 /* Read calibration result for future reference */
882 ret
= stm32h7_adc_read_selfcalib(adc
);
885 stm32h7_adc_enter_pwr_down(adc
);
891 * stm32h7_adc_prepare() - Leave power down mode to enable ADC.
892 * @adc: stm32 adc instance
893 * Leave power down mode.
895 * Restore calibration data.
896 * Pre-select channels that may be used in PCSEL (required by input MUX / IO).
898 static int stm32h7_adc_prepare(struct stm32_adc
*adc
)
902 stm32h7_adc_exit_pwr_down(adc
);
904 ret
= stm32h7_adc_enable(adc
);
908 ret
= stm32h7_adc_restore_selfcalib(adc
);
912 stm32_adc_writel(adc
, STM32H7_ADC_PCSEL
, adc
->pcsel
);
917 stm32h7_adc_disable(adc
);
919 stm32h7_adc_enter_pwr_down(adc
);
924 static void stm32h7_adc_unprepare(struct stm32_adc
*adc
)
926 stm32h7_adc_disable(adc
);
927 stm32h7_adc_enter_pwr_down(adc
);
931 * stm32_adc_conf_scan_seq() - Build regular channels scan sequence
932 * @indio_dev: IIO device
933 * @scan_mask: channels to be converted
935 * Conversion sequence :
936 * Configure ADC scan sequence based on selected channels in scan_mask.
937 * Add channels to SQR registers, from scan_mask LSB to MSB, then
938 * program sequence len.
940 static int stm32_adc_conf_scan_seq(struct iio_dev
*indio_dev
,
941 const unsigned long *scan_mask
)
943 struct stm32_adc
*adc
= iio_priv(indio_dev
);
944 const struct stm32_adc_regs
*sqr
= adc
->cfg
->regs
->sqr
;
945 const struct iio_chan_spec
*chan
;
949 for_each_set_bit(bit
, scan_mask
, indio_dev
->masklength
) {
950 chan
= indio_dev
->channels
+ bit
;
952 * Assign one channel per SQ entry in regular
953 * sequence, starting with SQ1.
956 if (i
> STM32_ADC_MAX_SQ
)
959 dev_dbg(&indio_dev
->dev
, "%s chan %d to SQ%d\n",
960 __func__
, chan
->channel
, i
);
962 val
= stm32_adc_readl(adc
, sqr
[i
].reg
);
964 val
|= chan
->channel
<< sqr
[i
].shift
;
965 stm32_adc_writel(adc
, sqr
[i
].reg
, val
);
972 val
= stm32_adc_readl(adc
, sqr
[0].reg
);
974 val
|= ((i
- 1) << sqr
[0].shift
);
975 stm32_adc_writel(adc
, sqr
[0].reg
, val
);
981 * stm32_adc_get_trig_extsel() - Get external trigger selection
984 * Returns trigger extsel value, if trig matches, -EINVAL otherwise.
986 static int stm32_adc_get_trig_extsel(struct iio_dev
*indio_dev
,
987 struct iio_trigger
*trig
)
989 struct stm32_adc
*adc
= iio_priv(indio_dev
);
992 /* lookup triggers registered by stm32 timer trigger driver */
993 for (i
= 0; adc
->cfg
->trigs
[i
].name
; i
++) {
995 * Checking both stm32 timer trigger type and trig name
996 * should be safe against arbitrary trigger names.
998 if (is_stm32_timer_trigger(trig
) &&
999 !strcmp(adc
->cfg
->trigs
[i
].name
, trig
->name
)) {
1000 return adc
->cfg
->trigs
[i
].extsel
;
1008 * stm32_adc_set_trig() - Set a regular trigger
1009 * @indio_dev: IIO device
1010 * @trig: IIO trigger
1012 * Set trigger source/polarity (e.g. SW, or HW with polarity) :
1013 * - if HW trigger disabled (e.g. trig == NULL, conversion launched by sw)
1014 * - if HW trigger enabled, set source & polarity
1016 static int stm32_adc_set_trig(struct iio_dev
*indio_dev
,
1017 struct iio_trigger
*trig
)
1019 struct stm32_adc
*adc
= iio_priv(indio_dev
);
1020 u32 val
, extsel
= 0, exten
= STM32_EXTEN_SWTRIG
;
1021 unsigned long flags
;
1025 ret
= stm32_adc_get_trig_extsel(indio_dev
, trig
);
1029 /* set trigger source and polarity (default to rising edge) */
1031 exten
= adc
->trigger_polarity
+ STM32_EXTEN_HWTRIG_RISING_EDGE
;
1034 spin_lock_irqsave(&adc
->lock
, flags
);
1035 val
= stm32_adc_readl(adc
, adc
->cfg
->regs
->exten
.reg
);
1036 val
&= ~(adc
->cfg
->regs
->exten
.mask
| adc
->cfg
->regs
->extsel
.mask
);
1037 val
|= exten
<< adc
->cfg
->regs
->exten
.shift
;
1038 val
|= extsel
<< adc
->cfg
->regs
->extsel
.shift
;
1039 stm32_adc_writel(adc
, adc
->cfg
->regs
->exten
.reg
, val
);
1040 spin_unlock_irqrestore(&adc
->lock
, flags
);
1045 static int stm32_adc_set_trig_pol(struct iio_dev
*indio_dev
,
1046 const struct iio_chan_spec
*chan
,
1049 struct stm32_adc
*adc
= iio_priv(indio_dev
);
1051 adc
->trigger_polarity
= type
;
1056 static int stm32_adc_get_trig_pol(struct iio_dev
*indio_dev
,
1057 const struct iio_chan_spec
*chan
)
1059 struct stm32_adc
*adc
= iio_priv(indio_dev
);
1061 return adc
->trigger_polarity
;
1064 static const char * const stm32_trig_pol_items
[] = {
1065 "rising-edge", "falling-edge", "both-edges",
1068 static const struct iio_enum stm32_adc_trig_pol
= {
1069 .items
= stm32_trig_pol_items
,
1070 .num_items
= ARRAY_SIZE(stm32_trig_pol_items
),
1071 .get
= stm32_adc_get_trig_pol
,
1072 .set
= stm32_adc_set_trig_pol
,
1076 * stm32_adc_single_conv() - Performs a single conversion
1077 * @indio_dev: IIO device
1078 * @chan: IIO channel
1079 * @res: conversion result
1081 * The function performs a single conversion on a given channel:
1082 * - Program sequencer with one channel (e.g. in SQ1 with len = 1)
1084 * - Start conversion, then wait for interrupt completion.
1086 static int stm32_adc_single_conv(struct iio_dev
*indio_dev
,
1087 const struct iio_chan_spec
*chan
,
1090 struct stm32_adc
*adc
= iio_priv(indio_dev
);
1091 const struct stm32_adc_regspec
*regs
= adc
->cfg
->regs
;
1096 reinit_completion(&adc
->completion
);
1100 if (adc
->cfg
->prepare
) {
1101 ret
= adc
->cfg
->prepare(adc
);
1106 /* Program chan number in regular sequence (SQ1) */
1107 val
= stm32_adc_readl(adc
, regs
->sqr
[1].reg
);
1108 val
&= ~regs
->sqr
[1].mask
;
1109 val
|= chan
->channel
<< regs
->sqr
[1].shift
;
1110 stm32_adc_writel(adc
, regs
->sqr
[1].reg
, val
);
1112 /* Set regular sequence len (0 for 1 conversion) */
1113 stm32_adc_clr_bits(adc
, regs
->sqr
[0].reg
, regs
->sqr
[0].mask
);
1115 /* Trigger detection disabled (conversion can be launched in SW) */
1116 stm32_adc_clr_bits(adc
, regs
->exten
.reg
, regs
->exten
.mask
);
1118 stm32_adc_conv_irq_enable(adc
);
1120 adc
->cfg
->start_conv(adc
, false);
1122 timeout
= wait_for_completion_interruptible_timeout(
1123 &adc
->completion
, STM32_ADC_TIMEOUT
);
1126 } else if (timeout
< 0) {
1129 *res
= adc
->buffer
[0];
1133 adc
->cfg
->stop_conv(adc
);
1135 stm32_adc_conv_irq_disable(adc
);
1137 if (adc
->cfg
->unprepare
)
1138 adc
->cfg
->unprepare(adc
);
1143 static int stm32_adc_read_raw(struct iio_dev
*indio_dev
,
1144 struct iio_chan_spec
const *chan
,
1145 int *val
, int *val2
, long mask
)
1147 struct stm32_adc
*adc
= iio_priv(indio_dev
);
1151 case IIO_CHAN_INFO_RAW
:
1152 ret
= iio_device_claim_direct_mode(indio_dev
);
1155 if (chan
->type
== IIO_VOLTAGE
)
1156 ret
= stm32_adc_single_conv(indio_dev
, chan
, val
);
1159 iio_device_release_direct_mode(indio_dev
);
1162 case IIO_CHAN_INFO_SCALE
:
1163 *val
= adc
->common
->vref_mv
;
1164 *val2
= chan
->scan_type
.realbits
;
1165 return IIO_VAL_FRACTIONAL_LOG2
;
1172 static irqreturn_t
stm32_adc_isr(int irq
, void *data
)
1174 struct stm32_adc
*adc
= data
;
1175 struct iio_dev
*indio_dev
= iio_priv_to_dev(adc
);
1176 const struct stm32_adc_regspec
*regs
= adc
->cfg
->regs
;
1177 u32 status
= stm32_adc_readl(adc
, regs
->isr_eoc
.reg
);
1179 if (status
& regs
->isr_eoc
.mask
) {
1180 /* Reading DR also clears EOC status flag */
1181 adc
->buffer
[adc
->bufi
] = stm32_adc_readw(adc
, regs
->dr
);
1182 if (iio_buffer_enabled(indio_dev
)) {
1184 if (adc
->bufi
>= adc
->num_conv
) {
1185 stm32_adc_conv_irq_disable(adc
);
1186 iio_trigger_poll(indio_dev
->trig
);
1189 complete(&adc
->completion
);
1198 * stm32_adc_validate_trigger() - validate trigger for stm32 adc
1199 * @indio_dev: IIO device
1200 * @trig: new trigger
1202 * Returns: 0 if trig matches one of the triggers registered by stm32 adc
1203 * driver, -EINVAL otherwise.
1205 static int stm32_adc_validate_trigger(struct iio_dev
*indio_dev
,
1206 struct iio_trigger
*trig
)
1208 return stm32_adc_get_trig_extsel(indio_dev
, trig
) < 0 ? -EINVAL
: 0;
1211 static int stm32_adc_set_watermark(struct iio_dev
*indio_dev
, unsigned int val
)
1213 struct stm32_adc
*adc
= iio_priv(indio_dev
);
1214 unsigned int watermark
= STM32_DMA_BUFFER_SIZE
/ 2;
1217 * dma cyclic transfers are used, buffer is split into two periods.
1219 * - always one buffer (period) dma is working on
1220 * - one buffer (period) driver can push with iio_trigger_poll().
1222 watermark
= min(watermark
, val
* (unsigned)(sizeof(u16
)));
1223 adc
->rx_buf_sz
= watermark
* 2;
1228 static int stm32_adc_update_scan_mode(struct iio_dev
*indio_dev
,
1229 const unsigned long *scan_mask
)
1231 struct stm32_adc
*adc
= iio_priv(indio_dev
);
1234 adc
->num_conv
= bitmap_weight(scan_mask
, indio_dev
->masklength
);
1236 ret
= stm32_adc_conf_scan_seq(indio_dev
, scan_mask
);
1243 static int stm32_adc_of_xlate(struct iio_dev
*indio_dev
,
1244 const struct of_phandle_args
*iiospec
)
1248 for (i
= 0; i
< indio_dev
->num_channels
; i
++)
1249 if (indio_dev
->channels
[i
].channel
== iiospec
->args
[0])
1256 * stm32_adc_debugfs_reg_access - read or write register value
1258 * To read a value from an ADC register:
1259 * echo [ADC reg offset] > direct_reg_access
1260 * cat direct_reg_access
1262 * To write a value in a ADC register:
1263 * echo [ADC_reg_offset] [value] > direct_reg_access
1265 static int stm32_adc_debugfs_reg_access(struct iio_dev
*indio_dev
,
1266 unsigned reg
, unsigned writeval
,
1269 struct stm32_adc
*adc
= iio_priv(indio_dev
);
1272 stm32_adc_writel(adc
, reg
, writeval
);
1274 *readval
= stm32_adc_readl(adc
, reg
);
1279 static const struct iio_info stm32_adc_iio_info
= {
1280 .read_raw
= stm32_adc_read_raw
,
1281 .validate_trigger
= stm32_adc_validate_trigger
,
1282 .hwfifo_set_watermark
= stm32_adc_set_watermark
,
1283 .update_scan_mode
= stm32_adc_update_scan_mode
,
1284 .debugfs_reg_access
= stm32_adc_debugfs_reg_access
,
1285 .of_xlate
= stm32_adc_of_xlate
,
1286 .driver_module
= THIS_MODULE
,
1289 static unsigned int stm32_adc_dma_residue(struct stm32_adc
*adc
)
1291 struct dma_tx_state state
;
1292 enum dma_status status
;
1294 status
= dmaengine_tx_status(adc
->dma_chan
,
1295 adc
->dma_chan
->cookie
,
1297 if (status
== DMA_IN_PROGRESS
) {
1298 /* Residue is size in bytes from end of buffer */
1299 unsigned int i
= adc
->rx_buf_sz
- state
.residue
;
1302 /* Return available bytes */
1304 size
= i
- adc
->bufi
;
1306 size
= adc
->rx_buf_sz
+ i
- adc
->bufi
;
1314 static void stm32_adc_dma_buffer_done(void *data
)
1316 struct iio_dev
*indio_dev
= data
;
1318 iio_trigger_poll_chained(indio_dev
->trig
);
1321 static int stm32_adc_dma_start(struct iio_dev
*indio_dev
)
1323 struct stm32_adc
*adc
= iio_priv(indio_dev
);
1324 struct dma_async_tx_descriptor
*desc
;
1325 dma_cookie_t cookie
;
1331 dev_dbg(&indio_dev
->dev
, "%s size=%d watermark=%d\n", __func__
,
1332 adc
->rx_buf_sz
, adc
->rx_buf_sz
/ 2);
1334 /* Prepare a DMA cyclic transaction */
1335 desc
= dmaengine_prep_dma_cyclic(adc
->dma_chan
,
1337 adc
->rx_buf_sz
, adc
->rx_buf_sz
/ 2,
1339 DMA_PREP_INTERRUPT
);
1343 desc
->callback
= stm32_adc_dma_buffer_done
;
1344 desc
->callback_param
= indio_dev
;
1346 cookie
= dmaengine_submit(desc
);
1347 ret
= dma_submit_error(cookie
);
1349 dmaengine_terminate_all(adc
->dma_chan
);
1353 /* Issue pending DMA requests */
1354 dma_async_issue_pending(adc
->dma_chan
);
1359 static int stm32_adc_buffer_postenable(struct iio_dev
*indio_dev
)
1361 struct stm32_adc
*adc
= iio_priv(indio_dev
);
1364 if (adc
->cfg
->prepare
) {
1365 ret
= adc
->cfg
->prepare(adc
);
1370 ret
= stm32_adc_set_trig(indio_dev
, indio_dev
->trig
);
1372 dev_err(&indio_dev
->dev
, "Can't set trigger\n");
1376 ret
= stm32_adc_dma_start(indio_dev
);
1378 dev_err(&indio_dev
->dev
, "Can't start dma\n");
1382 ret
= iio_triggered_buffer_postenable(indio_dev
);
1386 /* Reset adc buffer index */
1390 stm32_adc_conv_irq_enable(adc
);
1392 adc
->cfg
->start_conv(adc
, !!adc
->dma_chan
);
1398 dmaengine_terminate_all(adc
->dma_chan
);
1400 stm32_adc_set_trig(indio_dev
, NULL
);
1402 if (adc
->cfg
->unprepare
)
1403 adc
->cfg
->unprepare(adc
);
1408 static int stm32_adc_buffer_predisable(struct iio_dev
*indio_dev
)
1410 struct stm32_adc
*adc
= iio_priv(indio_dev
);
1413 adc
->cfg
->stop_conv(adc
);
1415 stm32_adc_conv_irq_disable(adc
);
1417 ret
= iio_triggered_buffer_predisable(indio_dev
);
1419 dev_err(&indio_dev
->dev
, "predisable failed\n");
1422 dmaengine_terminate_all(adc
->dma_chan
);
1424 if (stm32_adc_set_trig(indio_dev
, NULL
))
1425 dev_err(&indio_dev
->dev
, "Can't clear trigger\n");
1427 if (adc
->cfg
->unprepare
)
1428 adc
->cfg
->unprepare(adc
);
1433 static const struct iio_buffer_setup_ops stm32_adc_buffer_setup_ops
= {
1434 .postenable
= &stm32_adc_buffer_postenable
,
1435 .predisable
= &stm32_adc_buffer_predisable
,
1438 static irqreturn_t
stm32_adc_trigger_handler(int irq
, void *p
)
1440 struct iio_poll_func
*pf
= p
;
1441 struct iio_dev
*indio_dev
= pf
->indio_dev
;
1442 struct stm32_adc
*adc
= iio_priv(indio_dev
);
1444 dev_dbg(&indio_dev
->dev
, "%s bufi=%d\n", __func__
, adc
->bufi
);
1446 if (!adc
->dma_chan
) {
1447 /* reset buffer index */
1449 iio_push_to_buffers_with_timestamp(indio_dev
, adc
->buffer
,
1452 int residue
= stm32_adc_dma_residue(adc
);
1454 while (residue
>= indio_dev
->scan_bytes
) {
1455 u16
*buffer
= (u16
*)&adc
->rx_buf
[adc
->bufi
];
1457 iio_push_to_buffers_with_timestamp(indio_dev
, buffer
,
1459 residue
-= indio_dev
->scan_bytes
;
1460 adc
->bufi
+= indio_dev
->scan_bytes
;
1461 if (adc
->bufi
>= adc
->rx_buf_sz
)
1466 iio_trigger_notify_done(indio_dev
->trig
);
1468 /* re-enable eoc irq */
1470 stm32_adc_conv_irq_enable(adc
);
1475 static const struct iio_chan_spec_ext_info stm32_adc_ext_info
[] = {
1476 IIO_ENUM("trigger_polarity", IIO_SHARED_BY_ALL
, &stm32_adc_trig_pol
),
1478 .name
= "trigger_polarity_available",
1479 .shared
= IIO_SHARED_BY_ALL
,
1480 .read
= iio_enum_available_read
,
1481 .private = (uintptr_t)&stm32_adc_trig_pol
,
1486 static int stm32_adc_of_get_resolution(struct iio_dev
*indio_dev
)
1488 struct device_node
*node
= indio_dev
->dev
.of_node
;
1489 struct stm32_adc
*adc
= iio_priv(indio_dev
);
1493 if (of_property_read_u32(node
, "assigned-resolution-bits", &res
))
1494 res
= adc
->cfg
->adc_info
->resolutions
[0];
1496 for (i
= 0; i
< adc
->cfg
->adc_info
->num_res
; i
++)
1497 if (res
== adc
->cfg
->adc_info
->resolutions
[i
])
1499 if (i
>= adc
->cfg
->adc_info
->num_res
) {
1500 dev_err(&indio_dev
->dev
, "Bad resolution: %u bits\n", res
);
1504 dev_dbg(&indio_dev
->dev
, "Using %u bits resolution\n", res
);
1510 static void stm32_adc_chan_init_one(struct iio_dev
*indio_dev
,
1511 struct iio_chan_spec
*chan
,
1512 const struct stm32_adc_chan_spec
*channel
,
1515 struct stm32_adc
*adc
= iio_priv(indio_dev
);
1517 chan
->type
= channel
->type
;
1518 chan
->channel
= channel
->channel
;
1519 chan
->datasheet_name
= channel
->name
;
1520 chan
->scan_index
= scan_index
;
1522 chan
->info_mask_separate
= BIT(IIO_CHAN_INFO_RAW
);
1523 chan
->info_mask_shared_by_type
= BIT(IIO_CHAN_INFO_SCALE
);
1524 chan
->scan_type
.sign
= 'u';
1525 chan
->scan_type
.realbits
= adc
->cfg
->adc_info
->resolutions
[adc
->res
];
1526 chan
->scan_type
.storagebits
= 16;
1527 chan
->ext_info
= stm32_adc_ext_info
;
1529 /* pre-build selected channels mask */
1530 adc
->pcsel
|= BIT(chan
->channel
);
1533 static int stm32_adc_chan_of_init(struct iio_dev
*indio_dev
)
1535 struct device_node
*node
= indio_dev
->dev
.of_node
;
1536 struct stm32_adc
*adc
= iio_priv(indio_dev
);
1537 const struct stm32_adc_info
*adc_info
= adc
->cfg
->adc_info
;
1538 struct property
*prop
;
1540 struct iio_chan_spec
*channels
;
1541 int scan_index
= 0, num_channels
;
1544 num_channels
= of_property_count_u32_elems(node
, "st,adc-channels");
1545 if (num_channels
< 0 ||
1546 num_channels
>= adc_info
->max_channels
) {
1547 dev_err(&indio_dev
->dev
, "Bad st,adc-channels?\n");
1548 return num_channels
< 0 ? num_channels
: -EINVAL
;
1551 channels
= devm_kcalloc(&indio_dev
->dev
, num_channels
,
1552 sizeof(struct iio_chan_spec
), GFP_KERNEL
);
1556 of_property_for_each_u32(node
, "st,adc-channels", prop
, cur
, val
) {
1557 if (val
>= adc_info
->max_channels
) {
1558 dev_err(&indio_dev
->dev
, "Invalid channel %d\n", val
);
1561 stm32_adc_chan_init_one(indio_dev
, &channels
[scan_index
],
1562 &adc_info
->channels
[val
],
1567 indio_dev
->num_channels
= scan_index
;
1568 indio_dev
->channels
= channels
;
1573 static int stm32_adc_dma_request(struct iio_dev
*indio_dev
)
1575 struct stm32_adc
*adc
= iio_priv(indio_dev
);
1576 struct dma_slave_config config
;
1579 adc
->dma_chan
= dma_request_slave_channel(&indio_dev
->dev
, "rx");
1583 adc
->rx_buf
= dma_alloc_coherent(adc
->dma_chan
->device
->dev
,
1584 STM32_DMA_BUFFER_SIZE
,
1585 &adc
->rx_dma_buf
, GFP_KERNEL
);
1591 /* Configure DMA channel to read data register */
1592 memset(&config
, 0, sizeof(config
));
1593 config
.src_addr
= (dma_addr_t
)adc
->common
->phys_base
;
1594 config
.src_addr
+= adc
->offset
+ adc
->cfg
->regs
->dr
;
1595 config
.src_addr_width
= DMA_SLAVE_BUSWIDTH_2_BYTES
;
1597 ret
= dmaengine_slave_config(adc
->dma_chan
, &config
);
1604 dma_free_coherent(adc
->dma_chan
->device
->dev
, STM32_DMA_BUFFER_SIZE
,
1605 adc
->rx_buf
, adc
->rx_dma_buf
);
1607 dma_release_channel(adc
->dma_chan
);
1612 static int stm32_adc_probe(struct platform_device
*pdev
)
1614 struct iio_dev
*indio_dev
;
1615 struct device
*dev
= &pdev
->dev
;
1616 struct stm32_adc
*adc
;
1619 if (!pdev
->dev
.of_node
)
1622 indio_dev
= devm_iio_device_alloc(&pdev
->dev
, sizeof(*adc
));
1626 adc
= iio_priv(indio_dev
);
1627 adc
->common
= dev_get_drvdata(pdev
->dev
.parent
);
1628 spin_lock_init(&adc
->lock
);
1629 init_completion(&adc
->completion
);
1630 adc
->cfg
= (const struct stm32_adc_cfg
*)
1631 of_match_device(dev
->driver
->of_match_table
, dev
)->data
;
1633 indio_dev
->name
= dev_name(&pdev
->dev
);
1634 indio_dev
->dev
.parent
= &pdev
->dev
;
1635 indio_dev
->dev
.of_node
= pdev
->dev
.of_node
;
1636 indio_dev
->info
= &stm32_adc_iio_info
;
1637 indio_dev
->modes
= INDIO_DIRECT_MODE
;
1639 platform_set_drvdata(pdev
, adc
);
1641 ret
= of_property_read_u32(pdev
->dev
.of_node
, "reg", &adc
->offset
);
1643 dev_err(&pdev
->dev
, "missing reg property\n");
1647 adc
->irq
= platform_get_irq(pdev
, 0);
1649 dev_err(&pdev
->dev
, "failed to get irq\n");
1653 ret
= devm_request_irq(&pdev
->dev
, adc
->irq
, stm32_adc_isr
,
1654 0, pdev
->name
, adc
);
1656 dev_err(&pdev
->dev
, "failed to request IRQ\n");
1660 adc
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
1661 if (IS_ERR(adc
->clk
)) {
1662 ret
= PTR_ERR(adc
->clk
);
1663 if (ret
== -ENOENT
&& !adc
->cfg
->clk_required
) {
1666 dev_err(&pdev
->dev
, "Can't get clock\n");
1672 ret
= clk_prepare_enable(adc
->clk
);
1674 dev_err(&pdev
->dev
, "clk enable failed\n");
1679 ret
= stm32_adc_of_get_resolution(indio_dev
);
1681 goto err_clk_disable
;
1682 stm32_adc_set_res(adc
);
1684 if (adc
->cfg
->selfcalib
) {
1685 ret
= adc
->cfg
->selfcalib(adc
);
1687 goto err_clk_disable
;
1690 ret
= stm32_adc_chan_of_init(indio_dev
);
1692 goto err_clk_disable
;
1694 ret
= stm32_adc_dma_request(indio_dev
);
1696 goto err_clk_disable
;
1698 ret
= iio_triggered_buffer_setup(indio_dev
,
1699 &iio_pollfunc_store_time
,
1700 &stm32_adc_trigger_handler
,
1701 &stm32_adc_buffer_setup_ops
);
1703 dev_err(&pdev
->dev
, "buffer setup failed\n");
1704 goto err_dma_disable
;
1707 ret
= iio_device_register(indio_dev
);
1709 dev_err(&pdev
->dev
, "iio dev register failed\n");
1710 goto err_buffer_cleanup
;
1716 iio_triggered_buffer_cleanup(indio_dev
);
1719 if (adc
->dma_chan
) {
1720 dma_free_coherent(adc
->dma_chan
->device
->dev
,
1721 STM32_DMA_BUFFER_SIZE
,
1722 adc
->rx_buf
, adc
->rx_dma_buf
);
1723 dma_release_channel(adc
->dma_chan
);
1727 clk_disable_unprepare(adc
->clk
);
1732 static int stm32_adc_remove(struct platform_device
*pdev
)
1734 struct stm32_adc
*adc
= platform_get_drvdata(pdev
);
1735 struct iio_dev
*indio_dev
= iio_priv_to_dev(adc
);
1737 iio_device_unregister(indio_dev
);
1738 iio_triggered_buffer_cleanup(indio_dev
);
1739 if (adc
->dma_chan
) {
1740 dma_free_coherent(adc
->dma_chan
->device
->dev
,
1741 STM32_DMA_BUFFER_SIZE
,
1742 adc
->rx_buf
, adc
->rx_dma_buf
);
1743 dma_release_channel(adc
->dma_chan
);
1746 clk_disable_unprepare(adc
->clk
);
1751 static const struct stm32_adc_cfg stm32f4_adc_cfg
= {
1752 .regs
= &stm32f4_adc_regspec
,
1753 .adc_info
= &stm32f4_adc_info
,
1754 .trigs
= stm32f4_adc_trigs
,
1755 .clk_required
= true,
1756 .start_conv
= stm32f4_adc_start_conv
,
1757 .stop_conv
= stm32f4_adc_stop_conv
,
1760 static const struct stm32_adc_cfg stm32h7_adc_cfg
= {
1761 .regs
= &stm32h7_adc_regspec
,
1762 .adc_info
= &stm32h7_adc_info
,
1763 .trigs
= stm32h7_adc_trigs
,
1764 .selfcalib
= stm32h7_adc_selfcalib
,
1765 .start_conv
= stm32h7_adc_start_conv
,
1766 .stop_conv
= stm32h7_adc_stop_conv
,
1767 .prepare
= stm32h7_adc_prepare
,
1768 .unprepare
= stm32h7_adc_unprepare
,
1771 static const struct of_device_id stm32_adc_of_match
[] = {
1772 { .compatible
= "st,stm32f4-adc", .data
= (void *)&stm32f4_adc_cfg
},
1773 { .compatible
= "st,stm32h7-adc", .data
= (void *)&stm32h7_adc_cfg
},
1776 MODULE_DEVICE_TABLE(of
, stm32_adc_of_match
);
1778 static struct platform_driver stm32_adc_driver
= {
1779 .probe
= stm32_adc_probe
,
1780 .remove
= stm32_adc_remove
,
1782 .name
= "stm32-adc",
1783 .of_match_table
= stm32_adc_of_match
,
1786 module_platform_driver(stm32_adc_driver
);
1788 MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
1789 MODULE_DESCRIPTION("STMicroelectronics STM32 ADC IIO driver");
1790 MODULE_LICENSE("GPL v2");
1791 MODULE_ALIAS("platform:stm32-adc");