2 * ADS1015 - Texas Instruments Analog-to-Digital Converter
4 * Copyright (c) 2016, Intel Corporation.
6 * This file is subject to the terms and conditions of version 2 of
7 * the GNU General Public License. See the file COPYING in the main
8 * directory of this archive for more details.
10 * IIO driver for ADS1015 ADC 7-bit I2C slave address:
11 * * 0x48 - ADDR connected to Ground
12 * * 0x49 - ADDR connected to Vdd
13 * * 0x4A - ADDR connected to SDA
14 * * 0x4B - ADDR connected to SCL
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/i2c.h>
20 #include <linux/regmap.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/mutex.h>
23 #include <linux/delay.h>
25 #include <linux/i2c/ads1015.h>
27 #include <linux/iio/iio.h>
28 #include <linux/iio/types.h>
29 #include <linux/iio/sysfs.h>
30 #include <linux/iio/buffer.h>
31 #include <linux/iio/triggered_buffer.h>
32 #include <linux/iio/trigger_consumer.h>
34 #define ADS1015_DRV_NAME "ads1015"
36 #define ADS1015_CONV_REG 0x00
37 #define ADS1015_CFG_REG 0x01
39 #define ADS1015_CFG_DR_SHIFT 5
40 #define ADS1015_CFG_MOD_SHIFT 8
41 #define ADS1015_CFG_PGA_SHIFT 9
42 #define ADS1015_CFG_MUX_SHIFT 12
44 #define ADS1015_CFG_DR_MASK GENMASK(7, 5)
45 #define ADS1015_CFG_MOD_MASK BIT(8)
46 #define ADS1015_CFG_PGA_MASK GENMASK(11, 9)
47 #define ADS1015_CFG_MUX_MASK GENMASK(14, 12)
49 /* device operating modes */
50 #define ADS1015_CONTINUOUS 0
51 #define ADS1015_SINGLESHOT 1
53 #define ADS1015_SLEEP_DELAY_MS 2000
54 #define ADS1015_DEFAULT_PGA 2
55 #define ADS1015_DEFAULT_DATA_RATE 4
56 #define ADS1015_DEFAULT_CHAN 0
63 enum ads1015_channels
{
64 ADS1015_AIN0_AIN1
= 0,
75 static const unsigned int ads1015_data_rate
[] = {
76 128, 250, 490, 920, 1600, 2400, 3300, 3300
79 static const unsigned int ads1115_data_rate
[] = {
80 8, 16, 32, 64, 128, 250, 475, 860
97 #define ADS1015_V_CHAN(_chan, _addr) { \
98 .type = IIO_VOLTAGE, \
102 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
103 BIT(IIO_CHAN_INFO_SCALE) | \
104 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
105 .scan_index = _addr, \
111 .endianness = IIO_CPU, \
113 .datasheet_name = "AIN"#_chan, \
116 #define ADS1015_V_DIFF_CHAN(_chan, _chan2, _addr) { \
117 .type = IIO_VOLTAGE, \
122 .channel2 = _chan2, \
123 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
124 BIT(IIO_CHAN_INFO_SCALE) | \
125 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
126 .scan_index = _addr, \
132 .endianness = IIO_CPU, \
134 .datasheet_name = "AIN"#_chan"-AIN"#_chan2, \
137 #define ADS1115_V_CHAN(_chan, _addr) { \
138 .type = IIO_VOLTAGE, \
142 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
143 BIT(IIO_CHAN_INFO_SCALE) | \
144 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
145 .scan_index = _addr, \
150 .endianness = IIO_CPU, \
152 .datasheet_name = "AIN"#_chan, \
155 #define ADS1115_V_DIFF_CHAN(_chan, _chan2, _addr) { \
156 .type = IIO_VOLTAGE, \
161 .channel2 = _chan2, \
162 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
163 BIT(IIO_CHAN_INFO_SCALE) | \
164 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
165 .scan_index = _addr, \
170 .endianness = IIO_CPU, \
172 .datasheet_name = "AIN"#_chan"-AIN"#_chan2, \
175 struct ads1015_data
{
176 struct regmap
*regmap
;
178 * Protects ADC ops, e.g: concurrent sysfs/buffered
179 * data reads, configuration updates
182 struct ads1015_channel_data channel_data
[ADS1015_CHANNELS
];
184 unsigned int *data_rate
;
187 static bool ads1015_is_writeable_reg(struct device
*dev
, unsigned int reg
)
189 return (reg
== ADS1015_CFG_REG
);
192 static const struct regmap_config ads1015_regmap_config
= {
195 .max_register
= ADS1015_CFG_REG
,
196 .writeable_reg
= ads1015_is_writeable_reg
,
199 static const struct iio_chan_spec ads1015_channels
[] = {
200 ADS1015_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1
),
201 ADS1015_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3
),
202 ADS1015_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3
),
203 ADS1015_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3
),
204 ADS1015_V_CHAN(0, ADS1015_AIN0
),
205 ADS1015_V_CHAN(1, ADS1015_AIN1
),
206 ADS1015_V_CHAN(2, ADS1015_AIN2
),
207 ADS1015_V_CHAN(3, ADS1015_AIN3
),
208 IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP
),
211 static const struct iio_chan_spec ads1115_channels
[] = {
212 ADS1115_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1
),
213 ADS1115_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3
),
214 ADS1115_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3
),
215 ADS1115_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3
),
216 ADS1115_V_CHAN(0, ADS1015_AIN0
),
217 ADS1115_V_CHAN(1, ADS1015_AIN1
),
218 ADS1115_V_CHAN(2, ADS1015_AIN2
),
219 ADS1115_V_CHAN(3, ADS1015_AIN3
),
220 IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP
),
223 static int ads1015_set_power_state(struct ads1015_data
*data
, bool on
)
226 struct device
*dev
= regmap_get_device(data
->regmap
);
229 ret
= pm_runtime_get_sync(dev
);
231 pm_runtime_put_noidle(dev
);
233 pm_runtime_mark_last_busy(dev
);
234 ret
= pm_runtime_put_autosuspend(dev
);
241 int ads1015_get_adc_result(struct ads1015_data
*data
, int chan
, int *val
)
243 int ret
, pga
, dr
, conv_time
;
246 if (chan
< 0 || chan
>= ADS1015_CHANNELS
)
249 pga
= data
->channel_data
[chan
].pga
;
250 dr
= data
->channel_data
[chan
].data_rate
;
252 ret
= regmap_update_bits_check(data
->regmap
, ADS1015_CFG_REG
,
253 ADS1015_CFG_MUX_MASK
|
254 ADS1015_CFG_PGA_MASK
,
255 chan
<< ADS1015_CFG_MUX_SHIFT
|
256 pga
<< ADS1015_CFG_PGA_SHIFT
,
262 conv_time
= DIV_ROUND_UP(USEC_PER_SEC
, data
->data_rate
[dr
]);
263 usleep_range(conv_time
, conv_time
+ 1);
266 return regmap_read(data
->regmap
, ADS1015_CONV_REG
, val
);
269 static irqreturn_t
ads1015_trigger_handler(int irq
, void *p
)
271 struct iio_poll_func
*pf
= p
;
272 struct iio_dev
*indio_dev
= pf
->indio_dev
;
273 struct ads1015_data
*data
= iio_priv(indio_dev
);
274 s16 buf
[8]; /* 1x s16 ADC val + 3x s16 padding + 4x s16 timestamp */
277 memset(buf
, 0, sizeof(buf
));
279 mutex_lock(&data
->lock
);
280 chan
= find_first_bit(indio_dev
->active_scan_mask
,
281 indio_dev
->masklength
);
282 ret
= ads1015_get_adc_result(data
, chan
, &res
);
284 mutex_unlock(&data
->lock
);
289 mutex_unlock(&data
->lock
);
291 iio_push_to_buffers_with_timestamp(indio_dev
, buf
,
292 iio_get_time_ns(indio_dev
));
295 iio_trigger_notify_done(indio_dev
->trig
);
300 static int ads1015_set_scale(struct ads1015_data
*data
, int chan
,
301 int scale
, int uscale
)
303 int i
, ret
, rindex
= -1;
305 for (i
= 0; i
< ARRAY_SIZE(ads1015_scale
); i
++)
306 if (ads1015_scale
[i
].scale
== scale
&&
307 ads1015_scale
[i
].uscale
== uscale
) {
314 ret
= regmap_update_bits(data
->regmap
, ADS1015_CFG_REG
,
315 ADS1015_CFG_PGA_MASK
,
316 rindex
<< ADS1015_CFG_PGA_SHIFT
);
320 data
->channel_data
[chan
].pga
= rindex
;
325 static int ads1015_set_data_rate(struct ads1015_data
*data
, int chan
, int rate
)
327 int i
, ret
, rindex
= -1;
329 for (i
= 0; i
< ARRAY_SIZE(ads1015_data_rate
); i
++)
330 if (data
->data_rate
[i
] == rate
) {
337 ret
= regmap_update_bits(data
->regmap
, ADS1015_CFG_REG
,
339 rindex
<< ADS1015_CFG_DR_SHIFT
);
343 data
->channel_data
[chan
].data_rate
= rindex
;
348 static int ads1015_read_raw(struct iio_dev
*indio_dev
,
349 struct iio_chan_spec
const *chan
, int *val
,
350 int *val2
, long mask
)
353 struct ads1015_data
*data
= iio_priv(indio_dev
);
355 mutex_lock(&indio_dev
->mlock
);
356 mutex_lock(&data
->lock
);
358 case IIO_CHAN_INFO_RAW
: {
359 int shift
= chan
->scan_type
.shift
;
361 if (iio_buffer_enabled(indio_dev
)) {
366 ret
= ads1015_set_power_state(data
, true);
370 ret
= ads1015_get_adc_result(data
, chan
->address
, val
);
372 ads1015_set_power_state(data
, false);
376 *val
= sign_extend32(*val
>> shift
, 15 - shift
);
378 ret
= ads1015_set_power_state(data
, false);
385 case IIO_CHAN_INFO_SCALE
:
386 idx
= data
->channel_data
[chan
->address
].pga
;
387 *val
= ads1015_scale
[idx
].scale
;
388 *val2
= ads1015_scale
[idx
].uscale
;
389 ret
= IIO_VAL_INT_PLUS_MICRO
;
391 case IIO_CHAN_INFO_SAMP_FREQ
:
392 idx
= data
->channel_data
[chan
->address
].data_rate
;
393 *val
= data
->data_rate
[idx
];
400 mutex_unlock(&data
->lock
);
401 mutex_unlock(&indio_dev
->mlock
);
406 static int ads1015_write_raw(struct iio_dev
*indio_dev
,
407 struct iio_chan_spec
const *chan
, int val
,
410 struct ads1015_data
*data
= iio_priv(indio_dev
);
413 mutex_lock(&data
->lock
);
415 case IIO_CHAN_INFO_SCALE
:
416 ret
= ads1015_set_scale(data
, chan
->address
, val
, val2
);
418 case IIO_CHAN_INFO_SAMP_FREQ
:
419 ret
= ads1015_set_data_rate(data
, chan
->address
, val
);
425 mutex_unlock(&data
->lock
);
430 static int ads1015_buffer_preenable(struct iio_dev
*indio_dev
)
432 return ads1015_set_power_state(iio_priv(indio_dev
), true);
435 static int ads1015_buffer_postdisable(struct iio_dev
*indio_dev
)
437 return ads1015_set_power_state(iio_priv(indio_dev
), false);
440 static const struct iio_buffer_setup_ops ads1015_buffer_setup_ops
= {
441 .preenable
= ads1015_buffer_preenable
,
442 .postenable
= iio_triggered_buffer_postenable
,
443 .predisable
= iio_triggered_buffer_predisable
,
444 .postdisable
= ads1015_buffer_postdisable
,
445 .validate_scan_mask
= &iio_validate_scan_mask_onehot
,
448 static IIO_CONST_ATTR(scale_available
, "3 2 1 0.5 0.25 0.125");
450 static IIO_CONST_ATTR_NAMED(ads1015_sampling_frequency_available
,
451 sampling_frequency_available
, "128 250 490 920 1600 2400 3300");
452 static IIO_CONST_ATTR_NAMED(ads1115_sampling_frequency_available
,
453 sampling_frequency_available
, "8 16 32 64 128 250 475 860");
455 static struct attribute
*ads1015_attributes
[] = {
456 &iio_const_attr_scale_available
.dev_attr
.attr
,
457 &iio_const_attr_ads1015_sampling_frequency_available
.dev_attr
.attr
,
461 static const struct attribute_group ads1015_attribute_group
= {
462 .attrs
= ads1015_attributes
,
465 static struct attribute
*ads1115_attributes
[] = {
466 &iio_const_attr_scale_available
.dev_attr
.attr
,
467 &iio_const_attr_ads1115_sampling_frequency_available
.dev_attr
.attr
,
471 static const struct attribute_group ads1115_attribute_group
= {
472 .attrs
= ads1115_attributes
,
475 static struct iio_info ads1015_info
= {
476 .driver_module
= THIS_MODULE
,
477 .read_raw
= ads1015_read_raw
,
478 .write_raw
= ads1015_write_raw
,
479 .attrs
= &ads1015_attribute_group
,
482 static struct iio_info ads1115_info
= {
483 .driver_module
= THIS_MODULE
,
484 .read_raw
= ads1015_read_raw
,
485 .write_raw
= ads1015_write_raw
,
486 .attrs
= &ads1115_attribute_group
,
490 static int ads1015_get_channels_config_of(struct i2c_client
*client
)
492 struct iio_dev
*indio_dev
= i2c_get_clientdata(client
);
493 struct ads1015_data
*data
= iio_priv(indio_dev
);
494 struct device_node
*node
;
496 if (!client
->dev
.of_node
||
497 !of_get_next_child(client
->dev
.of_node
, NULL
))
500 for_each_child_of_node(client
->dev
.of_node
, node
) {
502 unsigned int channel
;
503 unsigned int pga
= ADS1015_DEFAULT_PGA
;
504 unsigned int data_rate
= ADS1015_DEFAULT_DATA_RATE
;
506 if (of_property_read_u32(node
, "reg", &pval
)) {
507 dev_err(&client
->dev
, "invalid reg on %s\n",
513 if (channel
>= ADS1015_CHANNELS
) {
514 dev_err(&client
->dev
,
515 "invalid channel index %d on %s\n",
516 channel
, node
->full_name
);
520 if (!of_property_read_u32(node
, "ti,gain", &pval
)) {
523 dev_err(&client
->dev
, "invalid gain on %s\n",
529 if (!of_property_read_u32(node
, "ti,datarate", &pval
)) {
532 dev_err(&client
->dev
,
533 "invalid data_rate on %s\n",
539 data
->channel_data
[channel
].pga
= pga
;
540 data
->channel_data
[channel
].data_rate
= data_rate
;
547 static void ads1015_get_channels_config(struct i2c_client
*client
)
551 struct iio_dev
*indio_dev
= i2c_get_clientdata(client
);
552 struct ads1015_data
*data
= iio_priv(indio_dev
);
553 struct ads1015_platform_data
*pdata
= dev_get_platdata(&client
->dev
);
555 /* prefer platform data */
557 memcpy(data
->channel_data
, pdata
->channel_data
,
558 sizeof(data
->channel_data
));
563 if (!ads1015_get_channels_config_of(client
))
566 /* fallback on default configuration */
567 for (k
= 0; k
< ADS1015_CHANNELS
; ++k
) {
568 data
->channel_data
[k
].pga
= ADS1015_DEFAULT_PGA
;
569 data
->channel_data
[k
].data_rate
= ADS1015_DEFAULT_DATA_RATE
;
573 static int ads1015_probe(struct i2c_client
*client
,
574 const struct i2c_device_id
*id
)
576 struct iio_dev
*indio_dev
;
577 struct ads1015_data
*data
;
580 indio_dev
= devm_iio_device_alloc(&client
->dev
, sizeof(*data
));
584 data
= iio_priv(indio_dev
);
585 i2c_set_clientdata(client
, indio_dev
);
587 mutex_init(&data
->lock
);
589 indio_dev
->dev
.parent
= &client
->dev
;
590 indio_dev
->dev
.of_node
= client
->dev
.of_node
;
591 indio_dev
->name
= ADS1015_DRV_NAME
;
592 indio_dev
->modes
= INDIO_DIRECT_MODE
;
594 switch (id
->driver_data
) {
596 indio_dev
->channels
= ads1015_channels
;
597 indio_dev
->num_channels
= ARRAY_SIZE(ads1015_channels
);
598 indio_dev
->info
= &ads1015_info
;
599 data
->data_rate
= (unsigned int *) &ads1015_data_rate
;
602 indio_dev
->channels
= ads1115_channels
;
603 indio_dev
->num_channels
= ARRAY_SIZE(ads1115_channels
);
604 indio_dev
->info
= &ads1115_info
;
605 data
->data_rate
= (unsigned int *) &ads1115_data_rate
;
609 /* we need to keep this ABI the same as used by hwmon ADS1015 driver */
610 ads1015_get_channels_config(client
);
612 data
->regmap
= devm_regmap_init_i2c(client
, &ads1015_regmap_config
);
613 if (IS_ERR(data
->regmap
)) {
614 dev_err(&client
->dev
, "Failed to allocate register map\n");
615 return PTR_ERR(data
->regmap
);
618 ret
= iio_triggered_buffer_setup(indio_dev
, NULL
,
619 ads1015_trigger_handler
,
620 &ads1015_buffer_setup_ops
);
622 dev_err(&client
->dev
, "iio triggered buffer setup failed\n");
625 ret
= pm_runtime_set_active(&client
->dev
);
627 goto err_buffer_cleanup
;
628 pm_runtime_set_autosuspend_delay(&client
->dev
, ADS1015_SLEEP_DELAY_MS
);
629 pm_runtime_use_autosuspend(&client
->dev
);
630 pm_runtime_enable(&client
->dev
);
632 ret
= iio_device_register(indio_dev
);
634 dev_err(&client
->dev
, "Failed to register IIO device\n");
635 goto err_buffer_cleanup
;
641 iio_triggered_buffer_cleanup(indio_dev
);
646 static int ads1015_remove(struct i2c_client
*client
)
648 struct iio_dev
*indio_dev
= i2c_get_clientdata(client
);
649 struct ads1015_data
*data
= iio_priv(indio_dev
);
651 iio_device_unregister(indio_dev
);
653 pm_runtime_disable(&client
->dev
);
654 pm_runtime_set_suspended(&client
->dev
);
655 pm_runtime_put_noidle(&client
->dev
);
657 iio_triggered_buffer_cleanup(indio_dev
);
659 /* power down single shot mode */
660 return regmap_update_bits(data
->regmap
, ADS1015_CFG_REG
,
661 ADS1015_CFG_MOD_MASK
,
662 ADS1015_SINGLESHOT
<< ADS1015_CFG_MOD_SHIFT
);
666 static int ads1015_runtime_suspend(struct device
*dev
)
668 struct iio_dev
*indio_dev
= i2c_get_clientdata(to_i2c_client(dev
));
669 struct ads1015_data
*data
= iio_priv(indio_dev
);
671 return regmap_update_bits(data
->regmap
, ADS1015_CFG_REG
,
672 ADS1015_CFG_MOD_MASK
,
673 ADS1015_SINGLESHOT
<< ADS1015_CFG_MOD_SHIFT
);
676 static int ads1015_runtime_resume(struct device
*dev
)
678 struct iio_dev
*indio_dev
= i2c_get_clientdata(to_i2c_client(dev
));
679 struct ads1015_data
*data
= iio_priv(indio_dev
);
681 return regmap_update_bits(data
->regmap
, ADS1015_CFG_REG
,
682 ADS1015_CFG_MOD_MASK
,
683 ADS1015_CONTINUOUS
<< ADS1015_CFG_MOD_SHIFT
);
687 static const struct dev_pm_ops ads1015_pm_ops
= {
688 SET_RUNTIME_PM_OPS(ads1015_runtime_suspend
,
689 ads1015_runtime_resume
, NULL
)
692 static const struct i2c_device_id ads1015_id
[] = {
693 {"ads1015", ADS1015
},
694 {"ads1115", ADS1115
},
697 MODULE_DEVICE_TABLE(i2c
, ads1015_id
);
699 static struct i2c_driver ads1015_driver
= {
701 .name
= ADS1015_DRV_NAME
,
702 .pm
= &ads1015_pm_ops
,
704 .probe
= ads1015_probe
,
705 .remove
= ads1015_remove
,
706 .id_table
= ads1015_id
,
709 module_i2c_driver(ads1015_driver
);
711 MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com>");
712 MODULE_DESCRIPTION("Texas Instruments ADS1015 ADC driver");
713 MODULE_LICENSE("GPL v2");