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iio: adc: ti-ads1015: avoid getting stale result after runtime resume
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1 /*
2 * ADS1015 - Texas Instruments Analog-to-Digital Converter
3 *
4 * Copyright (c) 2016, Intel Corporation.
5 *
6 * This file is subject to the terms and conditions of version 2 of
7 * the GNU General Public License. See the file COPYING in the main
8 * directory of this archive for more details.
9 *
10 * IIO driver for ADS1015 ADC 7-bit I2C slave address:
11 * * 0x48 - ADDR connected to Ground
12 * * 0x49 - ADDR connected to Vdd
13 * * 0x4A - ADDR connected to SDA
14 * * 0x4B - ADDR connected to SCL
15 */
16
17 #include <linux/module.h>
18 #include <linux/of_device.h>
19 #include <linux/init.h>
20 #include <linux/i2c.h>
21 #include <linux/regmap.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/mutex.h>
24 #include <linux/delay.h>
25
26 #include <linux/platform_data/ads1015.h>
27
28 #include <linux/iio/iio.h>
29 #include <linux/iio/types.h>
30 #include <linux/iio/sysfs.h>
31 #include <linux/iio/buffer.h>
32 #include <linux/iio/triggered_buffer.h>
33 #include <linux/iio/trigger_consumer.h>
34
35 #define ADS1015_DRV_NAME "ads1015"
36
37 #define ADS1015_CONV_REG 0x00
38 #define ADS1015_CFG_REG 0x01
39
40 #define ADS1015_CFG_DR_SHIFT 5
41 #define ADS1015_CFG_MOD_SHIFT 8
42 #define ADS1015_CFG_PGA_SHIFT 9
43 #define ADS1015_CFG_MUX_SHIFT 12
44
45 #define ADS1015_CFG_DR_MASK GENMASK(7, 5)
46 #define ADS1015_CFG_MOD_MASK BIT(8)
47 #define ADS1015_CFG_PGA_MASK GENMASK(11, 9)
48 #define ADS1015_CFG_MUX_MASK GENMASK(14, 12)
49
50 /* device operating modes */
51 #define ADS1015_CONTINUOUS 0
52 #define ADS1015_SINGLESHOT 1
53
54 #define ADS1015_SLEEP_DELAY_MS 2000
55 #define ADS1015_DEFAULT_PGA 2
56 #define ADS1015_DEFAULT_DATA_RATE 4
57 #define ADS1015_DEFAULT_CHAN 0
58
59 enum chip_ids {
60 ADS1015,
61 ADS1115,
62 };
63
64 enum ads1015_channels {
65 ADS1015_AIN0_AIN1 = 0,
66 ADS1015_AIN0_AIN3,
67 ADS1015_AIN1_AIN3,
68 ADS1015_AIN2_AIN3,
69 ADS1015_AIN0,
70 ADS1015_AIN1,
71 ADS1015_AIN2,
72 ADS1015_AIN3,
73 ADS1015_TIMESTAMP,
74 };
75
76 static const unsigned int ads1015_data_rate[] = {
77 128, 250, 490, 920, 1600, 2400, 3300, 3300
78 };
79
80 static const unsigned int ads1115_data_rate[] = {
81 8, 16, 32, 64, 128, 250, 475, 860
82 };
83
84 /*
85 * Translation from PGA bits to full-scale positive and negative input voltage
86 * range in mV
87 */
88 static int ads1015_fullscale_range[] = {
89 6144, 4096, 2048, 1024, 512, 256, 256, 256
90 };
91
92 #define ADS1015_V_CHAN(_chan, _addr) { \
93 .type = IIO_VOLTAGE, \
94 .indexed = 1, \
95 .address = _addr, \
96 .channel = _chan, \
97 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
98 BIT(IIO_CHAN_INFO_SCALE) | \
99 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
100 .scan_index = _addr, \
101 .scan_type = { \
102 .sign = 's', \
103 .realbits = 12, \
104 .storagebits = 16, \
105 .shift = 4, \
106 .endianness = IIO_CPU, \
107 }, \
108 .datasheet_name = "AIN"#_chan, \
109 }
110
111 #define ADS1015_V_DIFF_CHAN(_chan, _chan2, _addr) { \
112 .type = IIO_VOLTAGE, \
113 .differential = 1, \
114 .indexed = 1, \
115 .address = _addr, \
116 .channel = _chan, \
117 .channel2 = _chan2, \
118 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
119 BIT(IIO_CHAN_INFO_SCALE) | \
120 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
121 .scan_index = _addr, \
122 .scan_type = { \
123 .sign = 's', \
124 .realbits = 12, \
125 .storagebits = 16, \
126 .shift = 4, \
127 .endianness = IIO_CPU, \
128 }, \
129 .datasheet_name = "AIN"#_chan"-AIN"#_chan2, \
130 }
131
132 #define ADS1115_V_CHAN(_chan, _addr) { \
133 .type = IIO_VOLTAGE, \
134 .indexed = 1, \
135 .address = _addr, \
136 .channel = _chan, \
137 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
138 BIT(IIO_CHAN_INFO_SCALE) | \
139 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
140 .scan_index = _addr, \
141 .scan_type = { \
142 .sign = 's', \
143 .realbits = 16, \
144 .storagebits = 16, \
145 .endianness = IIO_CPU, \
146 }, \
147 .datasheet_name = "AIN"#_chan, \
148 }
149
150 #define ADS1115_V_DIFF_CHAN(_chan, _chan2, _addr) { \
151 .type = IIO_VOLTAGE, \
152 .differential = 1, \
153 .indexed = 1, \
154 .address = _addr, \
155 .channel = _chan, \
156 .channel2 = _chan2, \
157 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
158 BIT(IIO_CHAN_INFO_SCALE) | \
159 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
160 .scan_index = _addr, \
161 .scan_type = { \
162 .sign = 's', \
163 .realbits = 16, \
164 .storagebits = 16, \
165 .endianness = IIO_CPU, \
166 }, \
167 .datasheet_name = "AIN"#_chan"-AIN"#_chan2, \
168 }
169
170 struct ads1015_data {
171 struct regmap *regmap;
172 /*
173 * Protects ADC ops, e.g: concurrent sysfs/buffered
174 * data reads, configuration updates
175 */
176 struct mutex lock;
177 struct ads1015_channel_data channel_data[ADS1015_CHANNELS];
178
179 unsigned int *data_rate;
180 /*
181 * Set to true when the ADC is switched to the continuous-conversion
182 * mode and exits from a power-down state. This flag is used to avoid
183 * getting the stale result from the conversion register.
184 */
185 bool conv_invalid;
186 };
187
188 static bool ads1015_is_writeable_reg(struct device *dev, unsigned int reg)
189 {
190 return (reg == ADS1015_CFG_REG);
191 }
192
193 static const struct regmap_config ads1015_regmap_config = {
194 .reg_bits = 8,
195 .val_bits = 16,
196 .max_register = ADS1015_CFG_REG,
197 .writeable_reg = ads1015_is_writeable_reg,
198 };
199
200 static const struct iio_chan_spec ads1015_channels[] = {
201 ADS1015_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1),
202 ADS1015_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3),
203 ADS1015_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3),
204 ADS1015_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3),
205 ADS1015_V_CHAN(0, ADS1015_AIN0),
206 ADS1015_V_CHAN(1, ADS1015_AIN1),
207 ADS1015_V_CHAN(2, ADS1015_AIN2),
208 ADS1015_V_CHAN(3, ADS1015_AIN3),
209 IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
210 };
211
212 static const struct iio_chan_spec ads1115_channels[] = {
213 ADS1115_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1),
214 ADS1115_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3),
215 ADS1115_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3),
216 ADS1115_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3),
217 ADS1115_V_CHAN(0, ADS1015_AIN0),
218 ADS1115_V_CHAN(1, ADS1015_AIN1),
219 ADS1115_V_CHAN(2, ADS1015_AIN2),
220 ADS1115_V_CHAN(3, ADS1015_AIN3),
221 IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
222 };
223
224 static int ads1015_set_power_state(struct ads1015_data *data, bool on)
225 {
226 int ret;
227 struct device *dev = regmap_get_device(data->regmap);
228
229 if (on) {
230 ret = pm_runtime_get_sync(dev);
231 if (ret < 0)
232 pm_runtime_put_noidle(dev);
233 } else {
234 pm_runtime_mark_last_busy(dev);
235 ret = pm_runtime_put_autosuspend(dev);
236 }
237
238 return ret;
239 }
240
241 static
242 int ads1015_get_adc_result(struct ads1015_data *data, int chan, int *val)
243 {
244 int ret, pga, dr, conv_time;
245 bool change;
246
247 if (chan < 0 || chan >= ADS1015_CHANNELS)
248 return -EINVAL;
249
250 pga = data->channel_data[chan].pga;
251 dr = data->channel_data[chan].data_rate;
252
253 ret = regmap_update_bits_check(data->regmap, ADS1015_CFG_REG,
254 ADS1015_CFG_MUX_MASK |
255 ADS1015_CFG_PGA_MASK |
256 ADS1015_CFG_DR_MASK,
257 chan << ADS1015_CFG_MUX_SHIFT |
258 pga << ADS1015_CFG_PGA_SHIFT |
259 dr << ADS1015_CFG_DR_SHIFT,
260 &change);
261 if (ret < 0)
262 return ret;
263
264 if (change || data->conv_invalid) {
265 conv_time = DIV_ROUND_UP(USEC_PER_SEC, data->data_rate[dr]);
266 usleep_range(conv_time, conv_time + 1);
267 data->conv_invalid = false;
268 }
269
270 return regmap_read(data->regmap, ADS1015_CONV_REG, val);
271 }
272
273 static irqreturn_t ads1015_trigger_handler(int irq, void *p)
274 {
275 struct iio_poll_func *pf = p;
276 struct iio_dev *indio_dev = pf->indio_dev;
277 struct ads1015_data *data = iio_priv(indio_dev);
278 s16 buf[8]; /* 1x s16 ADC val + 3x s16 padding + 4x s16 timestamp */
279 int chan, ret, res;
280
281 memset(buf, 0, sizeof(buf));
282
283 mutex_lock(&data->lock);
284 chan = find_first_bit(indio_dev->active_scan_mask,
285 indio_dev->masklength);
286 ret = ads1015_get_adc_result(data, chan, &res);
287 if (ret < 0) {
288 mutex_unlock(&data->lock);
289 goto err;
290 }
291
292 buf[0] = res;
293 mutex_unlock(&data->lock);
294
295 iio_push_to_buffers_with_timestamp(indio_dev, buf,
296 iio_get_time_ns(indio_dev));
297
298 err:
299 iio_trigger_notify_done(indio_dev->trig);
300
301 return IRQ_HANDLED;
302 }
303
304 static int ads1015_set_scale(struct ads1015_data *data,
305 struct iio_chan_spec const *chan,
306 int scale, int uscale)
307 {
308 int i, ret, rindex = -1;
309 int fullscale = div_s64((scale * 1000000LL + uscale) <<
310 (chan->scan_type.realbits - 1), 1000000);
311
312 for (i = 0; i < ARRAY_SIZE(ads1015_fullscale_range); i++) {
313 if (ads1015_fullscale_range[i] == fullscale) {
314 rindex = i;
315 break;
316 }
317 }
318 if (rindex < 0)
319 return -EINVAL;
320
321 ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
322 ADS1015_CFG_PGA_MASK,
323 rindex << ADS1015_CFG_PGA_SHIFT);
324 if (ret < 0)
325 return ret;
326
327 data->channel_data[chan->address].pga = rindex;
328
329 return 0;
330 }
331
332 static int ads1015_set_data_rate(struct ads1015_data *data, int chan, int rate)
333 {
334 int i;
335
336 for (i = 0; i < ARRAY_SIZE(ads1015_data_rate); i++) {
337 if (data->data_rate[i] == rate) {
338 data->channel_data[chan].data_rate = i;
339 return 0;
340 }
341 }
342
343 return -EINVAL;
344 }
345
346 static int ads1015_read_raw(struct iio_dev *indio_dev,
347 struct iio_chan_spec const *chan, int *val,
348 int *val2, long mask)
349 {
350 int ret, idx;
351 struct ads1015_data *data = iio_priv(indio_dev);
352
353 mutex_lock(&indio_dev->mlock);
354 mutex_lock(&data->lock);
355 switch (mask) {
356 case IIO_CHAN_INFO_RAW: {
357 int shift = chan->scan_type.shift;
358
359 if (iio_buffer_enabled(indio_dev)) {
360 ret = -EBUSY;
361 break;
362 }
363
364 ret = ads1015_set_power_state(data, true);
365 if (ret < 0)
366 break;
367
368 ret = ads1015_get_adc_result(data, chan->address, val);
369 if (ret < 0) {
370 ads1015_set_power_state(data, false);
371 break;
372 }
373
374 *val = sign_extend32(*val >> shift, 15 - shift);
375
376 ret = ads1015_set_power_state(data, false);
377 if (ret < 0)
378 break;
379
380 ret = IIO_VAL_INT;
381 break;
382 }
383 case IIO_CHAN_INFO_SCALE:
384 idx = data->channel_data[chan->address].pga;
385 *val = ads1015_fullscale_range[idx];
386 *val2 = chan->scan_type.realbits - 1;
387 ret = IIO_VAL_FRACTIONAL_LOG2;
388 break;
389 case IIO_CHAN_INFO_SAMP_FREQ:
390 idx = data->channel_data[chan->address].data_rate;
391 *val = data->data_rate[idx];
392 ret = IIO_VAL_INT;
393 break;
394 default:
395 ret = -EINVAL;
396 break;
397 }
398 mutex_unlock(&data->lock);
399 mutex_unlock(&indio_dev->mlock);
400
401 return ret;
402 }
403
404 static int ads1015_write_raw(struct iio_dev *indio_dev,
405 struct iio_chan_spec const *chan, int val,
406 int val2, long mask)
407 {
408 struct ads1015_data *data = iio_priv(indio_dev);
409 int ret;
410
411 mutex_lock(&data->lock);
412 switch (mask) {
413 case IIO_CHAN_INFO_SCALE:
414 ret = ads1015_set_scale(data, chan, val, val2);
415 break;
416 case IIO_CHAN_INFO_SAMP_FREQ:
417 ret = ads1015_set_data_rate(data, chan->address, val);
418 break;
419 default:
420 ret = -EINVAL;
421 break;
422 }
423 mutex_unlock(&data->lock);
424
425 return ret;
426 }
427
428 static int ads1015_buffer_preenable(struct iio_dev *indio_dev)
429 {
430 return ads1015_set_power_state(iio_priv(indio_dev), true);
431 }
432
433 static int ads1015_buffer_postdisable(struct iio_dev *indio_dev)
434 {
435 return ads1015_set_power_state(iio_priv(indio_dev), false);
436 }
437
438 static const struct iio_buffer_setup_ops ads1015_buffer_setup_ops = {
439 .preenable = ads1015_buffer_preenable,
440 .postenable = iio_triggered_buffer_postenable,
441 .predisable = iio_triggered_buffer_predisable,
442 .postdisable = ads1015_buffer_postdisable,
443 .validate_scan_mask = &iio_validate_scan_mask_onehot,
444 };
445
446 static IIO_CONST_ATTR_NAMED(ads1015_scale_available, scale_available,
447 "3 2 1 0.5 0.25 0.125");
448 static IIO_CONST_ATTR_NAMED(ads1115_scale_available, scale_available,
449 "0.1875 0.125 0.0625 0.03125 0.015625 0.007813");
450
451 static IIO_CONST_ATTR_NAMED(ads1015_sampling_frequency_available,
452 sampling_frequency_available, "128 250 490 920 1600 2400 3300");
453 static IIO_CONST_ATTR_NAMED(ads1115_sampling_frequency_available,
454 sampling_frequency_available, "8 16 32 64 128 250 475 860");
455
456 static struct attribute *ads1015_attributes[] = {
457 &iio_const_attr_ads1015_scale_available.dev_attr.attr,
458 &iio_const_attr_ads1015_sampling_frequency_available.dev_attr.attr,
459 NULL,
460 };
461
462 static const struct attribute_group ads1015_attribute_group = {
463 .attrs = ads1015_attributes,
464 };
465
466 static struct attribute *ads1115_attributes[] = {
467 &iio_const_attr_ads1115_scale_available.dev_attr.attr,
468 &iio_const_attr_ads1115_sampling_frequency_available.dev_attr.attr,
469 NULL,
470 };
471
472 static const struct attribute_group ads1115_attribute_group = {
473 .attrs = ads1115_attributes,
474 };
475
476 static const struct iio_info ads1015_info = {
477 .driver_module = THIS_MODULE,
478 .read_raw = ads1015_read_raw,
479 .write_raw = ads1015_write_raw,
480 .attrs = &ads1015_attribute_group,
481 };
482
483 static const struct iio_info ads1115_info = {
484 .driver_module = THIS_MODULE,
485 .read_raw = ads1015_read_raw,
486 .write_raw = ads1015_write_raw,
487 .attrs = &ads1115_attribute_group,
488 };
489
490 #ifdef CONFIG_OF
491 static int ads1015_get_channels_config_of(struct i2c_client *client)
492 {
493 struct iio_dev *indio_dev = i2c_get_clientdata(client);
494 struct ads1015_data *data = iio_priv(indio_dev);
495 struct device_node *node;
496
497 if (!client->dev.of_node ||
498 !of_get_next_child(client->dev.of_node, NULL))
499 return -EINVAL;
500
501 for_each_child_of_node(client->dev.of_node, node) {
502 u32 pval;
503 unsigned int channel;
504 unsigned int pga = ADS1015_DEFAULT_PGA;
505 unsigned int data_rate = ADS1015_DEFAULT_DATA_RATE;
506
507 if (of_property_read_u32(node, "reg", &pval)) {
508 dev_err(&client->dev, "invalid reg on %s\n",
509 node->full_name);
510 continue;
511 }
512
513 channel = pval;
514 if (channel >= ADS1015_CHANNELS) {
515 dev_err(&client->dev,
516 "invalid channel index %d on %s\n",
517 channel, node->full_name);
518 continue;
519 }
520
521 if (!of_property_read_u32(node, "ti,gain", &pval)) {
522 pga = pval;
523 if (pga > 6) {
524 dev_err(&client->dev, "invalid gain on %s\n",
525 node->full_name);
526 of_node_put(node);
527 return -EINVAL;
528 }
529 }
530
531 if (!of_property_read_u32(node, "ti,datarate", &pval)) {
532 data_rate = pval;
533 if (data_rate > 7) {
534 dev_err(&client->dev,
535 "invalid data_rate on %s\n",
536 node->full_name);
537 of_node_put(node);
538 return -EINVAL;
539 }
540 }
541
542 data->channel_data[channel].pga = pga;
543 data->channel_data[channel].data_rate = data_rate;
544 }
545
546 return 0;
547 }
548 #endif
549
550 static void ads1015_get_channels_config(struct i2c_client *client)
551 {
552 unsigned int k;
553
554 struct iio_dev *indio_dev = i2c_get_clientdata(client);
555 struct ads1015_data *data = iio_priv(indio_dev);
556 struct ads1015_platform_data *pdata = dev_get_platdata(&client->dev);
557
558 /* prefer platform data */
559 if (pdata) {
560 memcpy(data->channel_data, pdata->channel_data,
561 sizeof(data->channel_data));
562 return;
563 }
564
565 #ifdef CONFIG_OF
566 if (!ads1015_get_channels_config_of(client))
567 return;
568 #endif
569 /* fallback on default configuration */
570 for (k = 0; k < ADS1015_CHANNELS; ++k) {
571 data->channel_data[k].pga = ADS1015_DEFAULT_PGA;
572 data->channel_data[k].data_rate = ADS1015_DEFAULT_DATA_RATE;
573 }
574 }
575
576 static int ads1015_probe(struct i2c_client *client,
577 const struct i2c_device_id *id)
578 {
579 struct iio_dev *indio_dev;
580 struct ads1015_data *data;
581 int ret;
582 enum chip_ids chip;
583
584 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
585 if (!indio_dev)
586 return -ENOMEM;
587
588 data = iio_priv(indio_dev);
589 i2c_set_clientdata(client, indio_dev);
590
591 mutex_init(&data->lock);
592
593 indio_dev->dev.parent = &client->dev;
594 indio_dev->dev.of_node = client->dev.of_node;
595 indio_dev->name = ADS1015_DRV_NAME;
596 indio_dev->modes = INDIO_DIRECT_MODE;
597
598 if (client->dev.of_node)
599 chip = (enum chip_ids)of_device_get_match_data(&client->dev);
600 else
601 chip = id->driver_data;
602 switch (chip) {
603 case ADS1015:
604 indio_dev->channels = ads1015_channels;
605 indio_dev->num_channels = ARRAY_SIZE(ads1015_channels);
606 indio_dev->info = &ads1015_info;
607 data->data_rate = (unsigned int *) &ads1015_data_rate;
608 break;
609 case ADS1115:
610 indio_dev->channels = ads1115_channels;
611 indio_dev->num_channels = ARRAY_SIZE(ads1115_channels);
612 indio_dev->info = &ads1115_info;
613 data->data_rate = (unsigned int *) &ads1115_data_rate;
614 break;
615 }
616
617 /* we need to keep this ABI the same as used by hwmon ADS1015 driver */
618 ads1015_get_channels_config(client);
619
620 data->regmap = devm_regmap_init_i2c(client, &ads1015_regmap_config);
621 if (IS_ERR(data->regmap)) {
622 dev_err(&client->dev, "Failed to allocate register map\n");
623 return PTR_ERR(data->regmap);
624 }
625
626 ret = iio_triggered_buffer_setup(indio_dev, NULL,
627 ads1015_trigger_handler,
628 &ads1015_buffer_setup_ops);
629 if (ret < 0) {
630 dev_err(&client->dev, "iio triggered buffer setup failed\n");
631 return ret;
632 }
633
634 ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
635 ADS1015_CFG_MOD_MASK,
636 ADS1015_CONTINUOUS << ADS1015_CFG_MOD_SHIFT);
637 if (ret)
638 return ret;
639
640 data->conv_invalid = true;
641
642 ret = pm_runtime_set_active(&client->dev);
643 if (ret)
644 goto err_buffer_cleanup;
645 pm_runtime_set_autosuspend_delay(&client->dev, ADS1015_SLEEP_DELAY_MS);
646 pm_runtime_use_autosuspend(&client->dev);
647 pm_runtime_enable(&client->dev);
648
649 ret = iio_device_register(indio_dev);
650 if (ret < 0) {
651 dev_err(&client->dev, "Failed to register IIO device\n");
652 goto err_buffer_cleanup;
653 }
654
655 return 0;
656
657 err_buffer_cleanup:
658 iio_triggered_buffer_cleanup(indio_dev);
659
660 return ret;
661 }
662
663 static int ads1015_remove(struct i2c_client *client)
664 {
665 struct iio_dev *indio_dev = i2c_get_clientdata(client);
666 struct ads1015_data *data = iio_priv(indio_dev);
667
668 iio_device_unregister(indio_dev);
669
670 pm_runtime_disable(&client->dev);
671 pm_runtime_set_suspended(&client->dev);
672 pm_runtime_put_noidle(&client->dev);
673
674 iio_triggered_buffer_cleanup(indio_dev);
675
676 /* power down single shot mode */
677 return regmap_update_bits(data->regmap, ADS1015_CFG_REG,
678 ADS1015_CFG_MOD_MASK,
679 ADS1015_SINGLESHOT << ADS1015_CFG_MOD_SHIFT);
680 }
681
682 #ifdef CONFIG_PM
683 static int ads1015_runtime_suspend(struct device *dev)
684 {
685 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
686 struct ads1015_data *data = iio_priv(indio_dev);
687
688 return regmap_update_bits(data->regmap, ADS1015_CFG_REG,
689 ADS1015_CFG_MOD_MASK,
690 ADS1015_SINGLESHOT << ADS1015_CFG_MOD_SHIFT);
691 }
692
693 static int ads1015_runtime_resume(struct device *dev)
694 {
695 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
696 struct ads1015_data *data = iio_priv(indio_dev);
697 int ret;
698
699 ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
700 ADS1015_CFG_MOD_MASK,
701 ADS1015_CONTINUOUS << ADS1015_CFG_MOD_SHIFT);
702 if (!ret)
703 data->conv_invalid = true;
704
705 return ret;
706 }
707 #endif
708
709 static const struct dev_pm_ops ads1015_pm_ops = {
710 SET_RUNTIME_PM_OPS(ads1015_runtime_suspend,
711 ads1015_runtime_resume, NULL)
712 };
713
714 static const struct i2c_device_id ads1015_id[] = {
715 {"ads1015", ADS1015},
716 {"ads1115", ADS1115},
717 {}
718 };
719 MODULE_DEVICE_TABLE(i2c, ads1015_id);
720
721 static const struct of_device_id ads1015_of_match[] = {
722 {
723 .compatible = "ti,ads1015",
724 .data = (void *)ADS1015
725 },
726 {
727 .compatible = "ti,ads1115",
728 .data = (void *)ADS1115
729 },
730 {}
731 };
732 MODULE_DEVICE_TABLE(of, ads1015_of_match);
733
734 static struct i2c_driver ads1015_driver = {
735 .driver = {
736 .name = ADS1015_DRV_NAME,
737 .of_match_table = ads1015_of_match,
738 .pm = &ads1015_pm_ops,
739 },
740 .probe = ads1015_probe,
741 .remove = ads1015_remove,
742 .id_table = ads1015_id,
743 };
744
745 module_i2c_driver(ads1015_driver);
746
747 MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com>");
748 MODULE_DESCRIPTION("Texas Instruments ADS1015 ADC driver");
749 MODULE_LICENSE("GPL v2");