drivers/iio/dac/ad5755.c

   1 /*
   2  * AD5755, AD5755-1, AD5757, AD5735, AD5737 Digital to analog converters driver
   3  *
   4  * Copyright 2012 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2.
   7  */
   8
   9 #include <linux/device.h>
  10 #include <linux/err.h>
  11 #include <linux/module.h>
  12 #include <linux/kernel.h>
  13 #include <linux/spi/spi.h>
  14 #include <linux/slab.h>
  15 #include <linux/sysfs.h>
  16 #include <linux/delay.h>
  17 #include <linux/iio/iio.h>
  18 #include <linux/iio/sysfs.h>
  19 #include <linux/platform_data/ad5755.h>
  20
  21 #define AD5755_NUM_CHANNELS 4
  22
  23 #define AD5755_ADDR(x)                  ((x) << 16)
  24
  25 #define AD5755_WRITE_REG_DATA(chan)     (chan)
  26 #define AD5755_WRITE_REG_GAIN(chan)     (0x08 | (chan))
  27 #define AD5755_WRITE_REG_OFFSET(chan)   (0x10 | (chan))
  28 #define AD5755_WRITE_REG_CTRL(chan)     (0x1c | (chan))
  29
  30 #define AD5755_READ_REG_DATA(chan)      (chan)
  31 #define AD5755_READ_REG_CTRL(chan)      (0x4 | (chan))
  32 #define AD5755_READ_REG_GAIN(chan)      (0x8 | (chan))
  33 #define AD5755_READ_REG_OFFSET(chan)    (0xc | (chan))
  34 #define AD5755_READ_REG_CLEAR(chan)     (0x10 | (chan))
  35 #define AD5755_READ_REG_SLEW(chan)      (0x14 | (chan))
  36 #define AD5755_READ_REG_STATUS          0x18
  37 #define AD5755_READ_REG_MAIN            0x19
  38 #define AD5755_READ_REG_DC_DC           0x1a
  39
  40 #define AD5755_CTRL_REG_SLEW    0x0
  41 #define AD5755_CTRL_REG_MAIN    0x1
  42 #define AD5755_CTRL_REG_DAC     0x2
  43 #define AD5755_CTRL_REG_DC_DC   0x3
  44 #define AD5755_CTRL_REG_SW      0x4
  45
  46 #define AD5755_READ_FLAG 0x800000
  47
  48 #define AD5755_NOOP 0x1CE000
  49
  50 #define AD5755_DAC_INT_EN                       BIT(8)
  51 #define AD5755_DAC_CLR_EN                       BIT(7)
  52 #define AD5755_DAC_OUT_EN                       BIT(6)
  53 #define AD5755_DAC_INT_CURRENT_SENSE_RESISTOR   BIT(5)
  54 #define AD5755_DAC_DC_DC_EN                     BIT(4)
  55 #define AD5755_DAC_VOLTAGE_OVERRANGE_EN         BIT(3)
  56
  57 #define AD5755_DC_DC_MAXV                       0
  58 #define AD5755_DC_DC_FREQ_SHIFT                 2
  59 #define AD5755_DC_DC_PHASE_SHIFT                4
  60 #define AD5755_EXT_DC_DC_COMP_RES               BIT(6)
  61
  62 #define AD5755_SLEW_STEP_SIZE_SHIFT             0
  63 #define AD5755_SLEW_RATE_SHIFT                  3
  64 #define AD5755_SLEW_ENABLE                      BIT(12)
  65
  66 /**
  67  * struct ad5755_chip_info - chip specific information
  68  * @channel_template:   channel specification
  69  * @calib_shift:        shift for the calibration data registers
  70  * @has_voltage_out:    whether the chip has voltage outputs
  71  */
  72 struct ad5755_chip_info {
  73         const struct iio_chan_spec channel_template;
  74         unsigned int calib_shift;
  75         bool has_voltage_out;
  76 };
  77
  78 /**
  79  * struct ad5755_state - driver instance specific data
  80  * @spi:        spi device the driver is attached to
  81  * @chip_info:  chip model specific constants, available modes etc
  82  * @pwr_down:   bitmask which contains  hether a channel is powered down or not
  83  * @ctrl:       software shadow of the channel ctrl registers
  84  * @channels:   iio channel spec for the device
  85  * @data:       spi transfer buffers
  86  */
  87 struct ad5755_state {
  88         struct spi_device               *spi;
  89         const struct ad5755_chip_info   *chip_info;
  90         unsigned int                    pwr_down;
  91         unsigned int                    ctrl[AD5755_NUM_CHANNELS];
  92         struct iio_chan_spec            channels[AD5755_NUM_CHANNELS];
  93
  94         /*
  95          * DMA (thus cache coherency maintenance) requires the
  96          * transfer buffers to live in their own cache lines.
  97          */
  98
  99         union {
 100                 __be32 d32;
 101                 u8 d8[4];
 102         } data[2] ____cacheline_aligned;
 103 };
 104
 105 enum ad5755_type {
 106         ID_AD5755,
 107         ID_AD5757,
 108         ID_AD5735,
 109         ID_AD5737,
 110 };
 111
 112 static int ad5755_write_unlocked(struct iio_dev *indio_dev,
 113         unsigned int reg, unsigned int val)
 114 {
 115         struct ad5755_state *st = iio_priv(indio_dev);
 116
 117         st->data[0].d32 = cpu_to_be32((reg << 16) | val);
 118
 119         return spi_write(st->spi, &st->data[0].d8[1], 3);
 120 }
 121
 122 static int ad5755_write_ctrl_unlocked(struct iio_dev *indio_dev,
 123         unsigned int channel, unsigned int reg, unsigned int val)
 124 {
 125         return ad5755_write_unlocked(indio_dev,
 126                 AD5755_WRITE_REG_CTRL(channel), (reg << 13) | val);
 127 }
 128
 129 static int ad5755_write(struct iio_dev *indio_dev, unsigned int reg,
 130         unsigned int val)
 131 {
 132         int ret;
 133
 134         mutex_lock(&indio_dev->mlock);
 135         ret = ad5755_write_unlocked(indio_dev, reg, val);
 136         mutex_unlock(&indio_dev->mlock);
 137
 138         return ret;
 139 }
 140
 141 static int ad5755_write_ctrl(struct iio_dev *indio_dev, unsigned int channel,
 142         unsigned int reg, unsigned int val)
 143 {
 144         int ret;
 145
 146         mutex_lock(&indio_dev->mlock);
 147         ret = ad5755_write_ctrl_unlocked(indio_dev, channel, reg, val);
 148         mutex_unlock(&indio_dev->mlock);
 149
 150         return ret;
 151 }
 152
 153 static int ad5755_read(struct iio_dev *indio_dev, unsigned int addr)
 154 {
 155         struct ad5755_state *st = iio_priv(indio_dev);
 156         int ret;
 157         struct spi_transfer t[] = {
 158                 {
 159                         .tx_buf = &st->data[0].d8[1],
 160                         .len = 3,
 161                         .cs_change = 1,
 162                 }, {
 163                         .tx_buf = &st->data[1].d8[1],
 164                         .rx_buf = &st->data[1].d8[1],
 165                         .len = 3,
 166                 },
 167         };
 168
 169         mutex_lock(&indio_dev->mlock);
 170
 171         st->data[0].d32 = cpu_to_be32(AD5755_READ_FLAG | (addr << 16));
 172         st->data[1].d32 = cpu_to_be32(AD5755_NOOP);
 173
 174         ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
 175         if (ret >= 0)
 176                 ret = be32_to_cpu(st->data[1].d32) & 0xffff;
 177
 178         mutex_unlock(&indio_dev->mlock);
 179
 180         return ret;
 181 }
 182
 183 static int ad5755_update_dac_ctrl(struct iio_dev *indio_dev,
 184         unsigned int channel, unsigned int set, unsigned int clr)
 185 {
 186         struct ad5755_state *st = iio_priv(indio_dev);
 187         int ret;
 188
 189         st->ctrl[channel] |= set;
 190         st->ctrl[channel] &= ~clr;
 191
 192         ret = ad5755_write_ctrl_unlocked(indio_dev, channel,
 193                 AD5755_CTRL_REG_DAC, st->ctrl[channel]);
 194
 195         return ret;
 196 }
 197
 198 static int ad5755_set_channel_pwr_down(struct iio_dev *indio_dev,
 199         unsigned int channel, bool pwr_down)
 200 {
 201         struct ad5755_state *st = iio_priv(indio_dev);
 202         unsigned int mask = BIT(channel);
 203
 204         mutex_lock(&indio_dev->mlock);
 205
 206         if ((bool)(st->pwr_down & mask) == pwr_down)
 207                 goto out_unlock;
 208
 209         if (!pwr_down) {
 210                 st->pwr_down &= ~mask;
 211                 ad5755_update_dac_ctrl(indio_dev, channel,
 212                         AD5755_DAC_INT_EN | AD5755_DAC_DC_DC_EN, 0);
 213                 udelay(200);
 214                 ad5755_update_dac_ctrl(indio_dev, channel,
 215                         AD5755_DAC_OUT_EN, 0);
 216         } else {
 217                 st->pwr_down |= mask;
 218                 ad5755_update_dac_ctrl(indio_dev, channel,
 219                         0, AD5755_DAC_INT_EN | AD5755_DAC_OUT_EN |
 220                                 AD5755_DAC_DC_DC_EN);
 221         }
 222
 223 out_unlock:
 224         mutex_unlock(&indio_dev->mlock);
 225
 226         return 0;
 227 }
 228
 229 static const int ad5755_min_max_table[][2] = {
 230         [AD5755_MODE_VOLTAGE_0V_5V] = { 0, 5000 },
 231         [AD5755_MODE_VOLTAGE_0V_10V] = { 0, 10000 },
 232         [AD5755_MODE_VOLTAGE_PLUSMINUS_5V] = { -5000, 5000 },
 233         [AD5755_MODE_VOLTAGE_PLUSMINUS_10V] = { -10000, 10000 },
 234         [AD5755_MODE_CURRENT_4mA_20mA] = { 4, 20 },
 235         [AD5755_MODE_CURRENT_0mA_20mA] = { 0, 20 },
 236         [AD5755_MODE_CURRENT_0mA_24mA] = { 0, 24 },
 237 };
 238
 239 static void ad5755_get_min_max(struct ad5755_state *st,
 240         struct iio_chan_spec const *chan, int *min, int *max)
 241 {
 242         enum ad5755_mode mode = st->ctrl[chan->channel] & 7;
 243         *min = ad5755_min_max_table[mode][0];
 244         *max = ad5755_min_max_table[mode][1];
 245 }
 246
 247 static inline int ad5755_get_offset(struct ad5755_state *st,
 248         struct iio_chan_spec const *chan)
 249 {
 250         int min, max;
 251
 252         ad5755_get_min_max(st, chan, &min, &max);
 253         return (min * (1 << chan->scan_type.realbits)) / (max - min);
 254 }
 255
 256 static int ad5755_chan_reg_info(struct ad5755_state *st,
 257         struct iio_chan_spec const *chan, long info, bool write,
 258         unsigned int *reg, unsigned int *shift, unsigned int *offset)
 259 {
 260         switch (info) {
 261         case IIO_CHAN_INFO_RAW:
 262                 if (write)
 263                         *reg = AD5755_WRITE_REG_DATA(chan->address);
 264                 else
 265                         *reg = AD5755_READ_REG_DATA(chan->address);
 266                 *shift = chan->scan_type.shift;
 267                 *offset = 0;
 268                 break;
 269         case IIO_CHAN_INFO_CALIBBIAS:
 270                 if (write)
 271                         *reg = AD5755_WRITE_REG_OFFSET(chan->address);
 272                 else
 273                         *reg = AD5755_READ_REG_OFFSET(chan->address);
 274                 *shift = st->chip_info->calib_shift;
 275                 *offset = 32768;
 276                 break;
 277         case IIO_CHAN_INFO_CALIBSCALE:
 278                 if (write)
 279                         *reg =  AD5755_WRITE_REG_GAIN(chan->address);
 280                 else
 281                         *reg =  AD5755_READ_REG_GAIN(chan->address);
 282                 *shift = st->chip_info->calib_shift;
 283                 *offset = 0;
 284                 break;
 285         default:
 286                 return -EINVAL;
 287         }
 288
 289         return 0;
 290 }
 291
 292 static int ad5755_read_raw(struct iio_dev *indio_dev,
 293         const struct iio_chan_spec *chan, int *val, int *val2, long info)
 294 {
 295         struct ad5755_state *st = iio_priv(indio_dev);
 296         unsigned int reg, shift, offset;
 297         int min, max;
 298         int ret;
 299
 300         switch (info) {
 301         case IIO_CHAN_INFO_SCALE:
 302                 ad5755_get_min_max(st, chan, &min, &max);
 303                 *val = max - min;
 304                 *val2 = chan->scan_type.realbits;
 305                 return IIO_VAL_FRACTIONAL_LOG2;
 306         case IIO_CHAN_INFO_OFFSET:
 307                 *val = ad5755_get_offset(st, chan);
 308                 return IIO_VAL_INT;
 309         default:
 310                 ret = ad5755_chan_reg_info(st, chan, info, false,
 311                                                 &reg, &shift, &offset);
 312                 if (ret)
 313                         return ret;
 314
 315                 ret = ad5755_read(indio_dev, reg);
 316                 if (ret < 0)
 317                         return ret;
 318
 319                 *val = (ret - offset) >> shift;
 320
 321                 return IIO_VAL_INT;
 322         }
 323
 324         return -EINVAL;
 325 }
 326
 327 static int ad5755_write_raw(struct iio_dev *indio_dev,
 328         const struct iio_chan_spec *chan, int val, int val2, long info)
 329 {
 330         struct ad5755_state *st = iio_priv(indio_dev);
 331         unsigned int shift, reg, offset;
 332         int ret;
 333
 334         ret = ad5755_chan_reg_info(st, chan, info, true,
 335                                         &reg, &shift, &offset);
 336         if (ret)
 337                 return ret;
 338
 339         val <<= shift;
 340         val += offset;
 341
 342         if (val < 0 || val > 0xffff)
 343                 return -EINVAL;
 344
 345         return ad5755_write(indio_dev, reg, val);
 346 }
 347
 348 static ssize_t ad5755_read_powerdown(struct iio_dev *indio_dev, uintptr_t priv,
 349         const struct iio_chan_spec *chan, char *buf)
 350 {
 351         struct ad5755_state *st = iio_priv(indio_dev);
 352
 353         return sprintf(buf, "%d\n",
 354                        (bool)(st->pwr_down & (1 << chan->channel)));
 355 }
 356
 357 static ssize_t ad5755_write_powerdown(struct iio_dev *indio_dev, uintptr_t priv,
 358         struct iio_chan_spec const *chan, const char *buf, size_t len)
 359 {
 360         bool pwr_down;
 361         int ret;
 362
 363         ret = strtobool(buf, &pwr_down);
 364         if (ret)
 365                 return ret;
 366
 367         ret = ad5755_set_channel_pwr_down(indio_dev, chan->channel, pwr_down);
 368         return ret ? ret : len;
 369 }
 370
 371 static const struct iio_info ad5755_info = {
 372         .read_raw = ad5755_read_raw,
 373         .write_raw = ad5755_write_raw,
 374         .driver_module = THIS_MODULE,
 375 };
 376
 377 static const struct iio_chan_spec_ext_info ad5755_ext_info[] = {
 378         {
 379                 .name = "powerdown",
 380                 .read = ad5755_read_powerdown,
 381                 .write = ad5755_write_powerdown,
 382                 .shared = IIO_SEPARATE,
 383         },
 384         { },
 385 };
 386
 387 #define AD5755_CHANNEL(_bits) {                                 \
 388         .indexed = 1,                                           \
 389         .output = 1,                                            \
 390         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |          \
 391                 BIT(IIO_CHAN_INFO_SCALE) |                      \
 392                 BIT(IIO_CHAN_INFO_OFFSET) |                     \
 393                 BIT(IIO_CHAN_INFO_CALIBSCALE) |                 \
 394                 BIT(IIO_CHAN_INFO_CALIBBIAS),                   \
 395         .scan_type = {                                          \
 396                 .sign = 'u',                                    \
 397                 .realbits = (_bits),                            \
 398                 .storagebits = 16,                              \
 399                 .shift = 16 - (_bits),                          \
 400         },                                                      \
 401         .ext_info = ad5755_ext_info,                            \
 402 }
 403
 404 static const struct ad5755_chip_info ad5755_chip_info_tbl[] = {
 405         [ID_AD5735] = {
 406                 .channel_template = AD5755_CHANNEL(14),
 407                 .has_voltage_out = true,
 408                 .calib_shift = 4,
 409         },
 410         [ID_AD5737] = {
 411                 .channel_template = AD5755_CHANNEL(14),
 412                 .has_voltage_out = false,
 413                 .calib_shift = 4,
 414         },
 415         [ID_AD5755] = {
 416                 .channel_template = AD5755_CHANNEL(16),
 417                 .has_voltage_out = true,
 418                 .calib_shift = 0,
 419         },
 420         [ID_AD5757] = {
 421                 .channel_template = AD5755_CHANNEL(16),
 422                 .has_voltage_out = false,
 423                 .calib_shift = 0,
 424         },
 425 };
 426
 427 static bool ad5755_is_valid_mode(struct ad5755_state *st, enum ad5755_mode mode)
 428 {
 429         switch (mode) {
 430         case AD5755_MODE_VOLTAGE_0V_5V:
 431         case AD5755_MODE_VOLTAGE_0V_10V:
 432         case AD5755_MODE_VOLTAGE_PLUSMINUS_5V:
 433         case AD5755_MODE_VOLTAGE_PLUSMINUS_10V:
 434                 return st->chip_info->has_voltage_out;
 435         case AD5755_MODE_CURRENT_4mA_20mA:
 436         case AD5755_MODE_CURRENT_0mA_20mA:
 437         case AD5755_MODE_CURRENT_0mA_24mA:
 438                 return true;
 439         default:
 440                 return false;
 441         }
 442 }
 443
 444 static int ad5755_setup_pdata(struct iio_dev *indio_dev,
 445                               const struct ad5755_platform_data *pdata)
 446 {
 447         struct ad5755_state *st = iio_priv(indio_dev);
 448         unsigned int val;
 449         unsigned int i;
 450         int ret;
 451
 452         if (pdata->dc_dc_phase > AD5755_DC_DC_PHASE_90_DEGREE ||
 453                 pdata->dc_dc_freq > AD5755_DC_DC_FREQ_650kHZ ||
 454                 pdata->dc_dc_maxv > AD5755_DC_DC_MAXV_29V5)
 455                 return -EINVAL;
 456
 457         val = pdata->dc_dc_maxv << AD5755_DC_DC_MAXV;
 458         val |= pdata->dc_dc_freq << AD5755_DC_DC_FREQ_SHIFT;
 459         val |= pdata->dc_dc_phase << AD5755_DC_DC_PHASE_SHIFT;
 460         if (pdata->ext_dc_dc_compenstation_resistor)
 461                 val |= AD5755_EXT_DC_DC_COMP_RES;
 462
 463         ret = ad5755_write_ctrl(indio_dev, 0, AD5755_CTRL_REG_DC_DC, val);
 464         if (ret < 0)
 465                 return ret;
 466
 467         for (i = 0; i < ARRAY_SIZE(pdata->dac); ++i) {
 468                 val = pdata->dac[i].slew.step_size <<
 469                         AD5755_SLEW_STEP_SIZE_SHIFT;
 470                 val |= pdata->dac[i].slew.rate <<
 471                         AD5755_SLEW_RATE_SHIFT;
 472                 if (pdata->dac[i].slew.enable)
 473                         val |= AD5755_SLEW_ENABLE;
 474
 475                 ret = ad5755_write_ctrl(indio_dev, i,
 476                                         AD5755_CTRL_REG_SLEW, val);
 477                 if (ret < 0)
 478                         return ret;
 479         }
 480
 481         for (i = 0; i < ARRAY_SIZE(pdata->dac); ++i) {
 482                 if (!ad5755_is_valid_mode(st, pdata->dac[i].mode))
 483                         return -EINVAL;
 484
 485                 val = 0;
 486                 if (!pdata->dac[i].ext_current_sense_resistor)
 487                         val |= AD5755_DAC_INT_CURRENT_SENSE_RESISTOR;
 488                 if (pdata->dac[i].enable_voltage_overrange)
 489                         val |= AD5755_DAC_VOLTAGE_OVERRANGE_EN;
 490                 val |= pdata->dac[i].mode;
 491
 492                 ret = ad5755_update_dac_ctrl(indio_dev, i, val, 0);
 493                 if (ret < 0)
 494                         return ret;
 495         }
 496
 497         return 0;
 498 }
 499
 500 static bool ad5755_is_voltage_mode(enum ad5755_mode mode)
 501 {
 502         switch (mode) {
 503         case AD5755_MODE_VOLTAGE_0V_5V:
 504         case AD5755_MODE_VOLTAGE_0V_10V:
 505         case AD5755_MODE_VOLTAGE_PLUSMINUS_5V:
 506         case AD5755_MODE_VOLTAGE_PLUSMINUS_10V:
 507                 return true;
 508         default:
 509                 return false;
 510         }
 511 }
 512
 513 static int ad5755_init_channels(struct iio_dev *indio_dev,
 514                                 const struct ad5755_platform_data *pdata)
 515 {
 516         struct ad5755_state *st = iio_priv(indio_dev);
 517         struct iio_chan_spec *channels = st->channels;
 518         unsigned int i;
 519
 520         for (i = 0; i < AD5755_NUM_CHANNELS; ++i) {
 521                 channels[i] = st->chip_info->channel_template;
 522                 channels[i].channel = i;
 523                 channels[i].address = i;
 524                 if (pdata && ad5755_is_voltage_mode(pdata->dac[i].mode))
 525                         channels[i].type = IIO_VOLTAGE;
 526                 else
 527                         channels[i].type = IIO_CURRENT;
 528         }
 529
 530         indio_dev->channels = channels;
 531
 532         return 0;
 533 }
 534
 535 #define AD5755_DEFAULT_DAC_PDATA { \
 536                 .mode = AD5755_MODE_CURRENT_4mA_20mA, \
 537                 .ext_current_sense_resistor = true, \
 538                 .enable_voltage_overrange = false, \
 539                 .slew = { \
 540                         .enable = false, \
 541                         .rate = AD5755_SLEW_RATE_64k, \
 542                         .step_size = AD5755_SLEW_STEP_SIZE_1, \
 543                 }, \
 544         }
 545
 546 static const struct ad5755_platform_data ad5755_default_pdata = {
 547         .ext_dc_dc_compenstation_resistor = false,
 548         .dc_dc_phase = AD5755_DC_DC_PHASE_ALL_SAME_EDGE,
 549         .dc_dc_freq = AD5755_DC_DC_FREQ_410kHZ,
 550         .dc_dc_maxv = AD5755_DC_DC_MAXV_23V,
 551         .dac = {
 552                 [0] = AD5755_DEFAULT_DAC_PDATA,
 553                 [1] = AD5755_DEFAULT_DAC_PDATA,
 554                 [2] = AD5755_DEFAULT_DAC_PDATA,
 555                 [3] = AD5755_DEFAULT_DAC_PDATA,
 556         },
 557 };
 558
 559 static int ad5755_probe(struct spi_device *spi)
 560 {
 561         enum ad5755_type type = spi_get_device_id(spi)->driver_data;
 562         const struct ad5755_platform_data *pdata = dev_get_platdata(&spi->dev);
 563         struct iio_dev *indio_dev;
 564         struct ad5755_state *st;
 565         int ret;
 566
 567         indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
 568         if (indio_dev == NULL) {
 569                 dev_err(&spi->dev, "Failed to allocate iio device\n");
 570                 return  -ENOMEM;
 571         }
 572
 573         st = iio_priv(indio_dev);
 574         spi_set_drvdata(spi, indio_dev);
 575
 576         st->chip_info = &ad5755_chip_info_tbl[type];
 577         st->spi = spi;
 578         st->pwr_down = 0xf;
 579
 580         indio_dev->dev.parent = &spi->dev;
 581         indio_dev->name = spi_get_device_id(spi)->name;
 582         indio_dev->info = &ad5755_info;
 583         indio_dev->modes = INDIO_DIRECT_MODE;
 584         indio_dev->num_channels = AD5755_NUM_CHANNELS;
 585
 586         if (!pdata)
 587                 pdata = &ad5755_default_pdata;
 588
 589         ret = ad5755_init_channels(indio_dev, pdata);
 590         if (ret)
 591                 return ret;
 592
 593         ret = ad5755_setup_pdata(indio_dev, pdata);
 594         if (ret)
 595                 return ret;
 596
 597         return devm_iio_device_register(&spi->dev, indio_dev);
 598 }
 599
 600 static const struct spi_device_id ad5755_id[] = {
 601         { "ad5755", ID_AD5755 },
 602         { "ad5755-1", ID_AD5755 },
 603         { "ad5757", ID_AD5757 },
 604         { "ad5735", ID_AD5735 },
 605         { "ad5737", ID_AD5737 },
 606         {}
 607 };
 608 MODULE_DEVICE_TABLE(spi, ad5755_id);
 609
 610 static struct spi_driver ad5755_driver = {
 611         .driver = {
 612                 .name = "ad5755",
 613                 .owner = THIS_MODULE,
 614         },
 615         .probe = ad5755_probe,
 616         .id_table = ad5755_id,
 617 };
 618 module_spi_driver(ad5755_driver);
 619
 620 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
 621 MODULE_DESCRIPTION("Analog Devices AD5755/55-1/57/35/37 DAC");
 622 MODULE_LICENSE("GPL v2");