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iio: imu: st_lsm6dsx: Avoid potential array overflow in st_lsm6dsx_set_odr()
[mirror_ubuntu-jammy-kernel.git] / drivers / iio / imu / adis16475.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * ADIS16475 IMU driver
4 *
5 * Copyright 2019 Analog Devices Inc.
6 */
7 #include <linux/bitfield.h>
8 #include <linux/bitops.h>
9 #include <linux/clk.h>
10 #include <linux/debugfs.h>
11 #include <linux/delay.h>
12 #include <linux/device.h>
13 #include <linux/kernel.h>
14 #include <linux/iio/buffer.h>
15 #include <linux/iio/iio.h>
16 #include <linux/iio/imu/adis.h>
17 #include <linux/iio/trigger_consumer.h>
18 #include <linux/irq.h>
19 #include <linux/lcm.h>
20 #include <linux/math.h>
21 #include <linux/module.h>
22 #include <linux/mod_devicetable.h>
23 #include <linux/property.h>
24 #include <linux/spi/spi.h>
25
26 #define ADIS16475_REG_DIAG_STAT 0x02
27 #define ADIS16475_REG_X_GYRO_L 0x04
28 #define ADIS16475_REG_Y_GYRO_L 0x08
29 #define ADIS16475_REG_Z_GYRO_L 0x0C
30 #define ADIS16475_REG_X_ACCEL_L 0x10
31 #define ADIS16475_REG_Y_ACCEL_L 0x14
32 #define ADIS16475_REG_Z_ACCEL_L 0x18
33 #define ADIS16475_REG_TEMP_OUT 0x1c
34 #define ADIS16475_REG_X_GYRO_BIAS_L 0x40
35 #define ADIS16475_REG_Y_GYRO_BIAS_L 0x44
36 #define ADIS16475_REG_Z_GYRO_BIAS_L 0x48
37 #define ADIS16475_REG_X_ACCEL_BIAS_L 0x4c
38 #define ADIS16475_REG_Y_ACCEL_BIAS_L 0x50
39 #define ADIS16475_REG_Z_ACCEL_BIAS_L 0x54
40 #define ADIS16475_REG_FILT_CTRL 0x5c
41 #define ADIS16475_FILT_CTRL_MASK GENMASK(2, 0)
42 #define ADIS16475_FILT_CTRL(x) FIELD_PREP(ADIS16475_FILT_CTRL_MASK, x)
43 #define ADIS16475_REG_MSG_CTRL 0x60
44 #define ADIS16475_MSG_CTRL_DR_POL_MASK BIT(0)
45 #define ADIS16475_MSG_CTRL_DR_POL(x) \
46 FIELD_PREP(ADIS16475_MSG_CTRL_DR_POL_MASK, x)
47 #define ADIS16475_SYNC_MODE_MASK GENMASK(4, 2)
48 #define ADIS16475_SYNC_MODE(x) FIELD_PREP(ADIS16475_SYNC_MODE_MASK, x)
49 #define ADIS16475_REG_UP_SCALE 0x62
50 #define ADIS16475_REG_DEC_RATE 0x64
51 #define ADIS16475_REG_GLOB_CMD 0x68
52 #define ADIS16475_REG_FIRM_REV 0x6c
53 #define ADIS16475_REG_FIRM_DM 0x6e
54 #define ADIS16475_REG_FIRM_Y 0x70
55 #define ADIS16475_REG_PROD_ID 0x72
56 #define ADIS16475_REG_SERIAL_NUM 0x74
57 #define ADIS16475_REG_FLASH_CNT 0x7c
58 #define ADIS16500_BURST32_MASK BIT(9)
59 #define ADIS16500_BURST32(x) FIELD_PREP(ADIS16500_BURST32_MASK, x)
60 /* number of data elements in burst mode */
61 #define ADIS16475_BURST32_MAX_DATA 32
62 #define ADIS16475_BURST_MAX_DATA 20
63 #define ADIS16475_MAX_SCAN_DATA 20
64 /* spi max speed in brust mode */
65 #define ADIS16475_BURST_MAX_SPEED 1000000
66 #define ADIS16475_LSB_DEC_MASK BIT(0)
67 #define ADIS16475_LSB_FIR_MASK BIT(1)
68
69 enum {
70 ADIS16475_SYNC_DIRECT = 1,
71 ADIS16475_SYNC_SCALED,
72 ADIS16475_SYNC_OUTPUT,
73 ADIS16475_SYNC_PULSE = 5,
74 };
75
76 struct adis16475_sync {
77 u16 sync_mode;
78 u16 min_rate;
79 u16 max_rate;
80 };
81
82 struct adis16475_chip_info {
83 const struct iio_chan_spec *channels;
84 const struct adis16475_sync *sync;
85 const struct adis_data adis_data;
86 const char *name;
87 u32 num_channels;
88 u32 gyro_max_val;
89 u32 gyro_max_scale;
90 u32 accel_max_val;
91 u32 accel_max_scale;
92 u32 temp_scale;
93 u32 int_clk;
94 u16 max_dec;
95 u8 num_sync;
96 bool has_burst32;
97 };
98
99 struct adis16475 {
100 const struct adis16475_chip_info *info;
101 struct adis adis;
102 u32 clk_freq;
103 bool burst32;
104 unsigned long lsb_flag;
105 u16 sync_mode;
106 /* Alignment needed for the timestamp */
107 __be16 data[ADIS16475_MAX_SCAN_DATA] __aligned(8);
108 };
109
110 enum {
111 ADIS16475_SCAN_GYRO_X,
112 ADIS16475_SCAN_GYRO_Y,
113 ADIS16475_SCAN_GYRO_Z,
114 ADIS16475_SCAN_ACCEL_X,
115 ADIS16475_SCAN_ACCEL_Y,
116 ADIS16475_SCAN_ACCEL_Z,
117 ADIS16475_SCAN_TEMP,
118 ADIS16475_SCAN_DIAG_S_FLAGS,
119 ADIS16475_SCAN_CRC_FAILURE,
120 };
121
122 static bool low_rate_allow;
123 module_param(low_rate_allow, bool, 0444);
124 MODULE_PARM_DESC(low_rate_allow,
125 "Allow IMU rates below the minimum advisable when external clk is used in SCALED mode (default: N)");
126
127 #ifdef CONFIG_DEBUG_FS
128 static ssize_t adis16475_show_firmware_revision(struct file *file,
129 char __user *userbuf,
130 size_t count, loff_t *ppos)
131 {
132 struct adis16475 *st = file->private_data;
133 char buf[7];
134 size_t len;
135 u16 rev;
136 int ret;
137
138 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FIRM_REV, &rev);
139 if (ret)
140 return ret;
141
142 len = scnprintf(buf, sizeof(buf), "%x.%x\n", rev >> 8, rev & 0xff);
143
144 return simple_read_from_buffer(userbuf, count, ppos, buf, len);
145 }
146
147 static const struct file_operations adis16475_firmware_revision_fops = {
148 .open = simple_open,
149 .read = adis16475_show_firmware_revision,
150 .llseek = default_llseek,
151 .owner = THIS_MODULE,
152 };
153
154 static ssize_t adis16475_show_firmware_date(struct file *file,
155 char __user *userbuf,
156 size_t count, loff_t *ppos)
157 {
158 struct adis16475 *st = file->private_data;
159 u16 md, year;
160 char buf[12];
161 size_t len;
162 int ret;
163
164 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FIRM_Y, &year);
165 if (ret)
166 return ret;
167
168 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FIRM_DM, &md);
169 if (ret)
170 return ret;
171
172 len = snprintf(buf, sizeof(buf), "%.2x-%.2x-%.4x\n", md >> 8, md & 0xff,
173 year);
174
175 return simple_read_from_buffer(userbuf, count, ppos, buf, len);
176 }
177
178 static const struct file_operations adis16475_firmware_date_fops = {
179 .open = simple_open,
180 .read = adis16475_show_firmware_date,
181 .llseek = default_llseek,
182 .owner = THIS_MODULE,
183 };
184
185 static int adis16475_show_serial_number(void *arg, u64 *val)
186 {
187 struct adis16475 *st = arg;
188 u16 serial;
189 int ret;
190
191 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_SERIAL_NUM, &serial);
192 if (ret)
193 return ret;
194
195 *val = serial;
196
197 return 0;
198 }
199 DEFINE_DEBUGFS_ATTRIBUTE(adis16475_serial_number_fops,
200 adis16475_show_serial_number, NULL, "0x%.4llx\n");
201
202 static int adis16475_show_product_id(void *arg, u64 *val)
203 {
204 struct adis16475 *st = arg;
205 u16 prod_id;
206 int ret;
207
208 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_PROD_ID, &prod_id);
209 if (ret)
210 return ret;
211
212 *val = prod_id;
213
214 return 0;
215 }
216 DEFINE_DEBUGFS_ATTRIBUTE(adis16475_product_id_fops,
217 adis16475_show_product_id, NULL, "%llu\n");
218
219 static int adis16475_show_flash_count(void *arg, u64 *val)
220 {
221 struct adis16475 *st = arg;
222 u32 flash_count;
223 int ret;
224
225 ret = adis_read_reg_32(&st->adis, ADIS16475_REG_FLASH_CNT,
226 &flash_count);
227 if (ret)
228 return ret;
229
230 *val = flash_count;
231
232 return 0;
233 }
234 DEFINE_DEBUGFS_ATTRIBUTE(adis16475_flash_count_fops,
235 adis16475_show_flash_count, NULL, "%lld\n");
236
237 static void adis16475_debugfs_init(struct iio_dev *indio_dev)
238 {
239 struct adis16475 *st = iio_priv(indio_dev);
240 struct dentry *d = iio_get_debugfs_dentry(indio_dev);
241
242 debugfs_create_file_unsafe("serial_number", 0400,
243 d, st, &adis16475_serial_number_fops);
244 debugfs_create_file_unsafe("product_id", 0400,
245 d, st, &adis16475_product_id_fops);
246 debugfs_create_file_unsafe("flash_count", 0400,
247 d, st, &adis16475_flash_count_fops);
248 debugfs_create_file("firmware_revision", 0400,
249 d, st, &adis16475_firmware_revision_fops);
250 debugfs_create_file("firmware_date", 0400, d,
251 st, &adis16475_firmware_date_fops);
252 }
253 #else
254 static void adis16475_debugfs_init(struct iio_dev *indio_dev)
255 {
256 }
257 #endif
258
259 static int adis16475_get_freq(struct adis16475 *st, u32 *freq)
260 {
261 int ret;
262 u16 dec;
263 u32 sample_rate = st->clk_freq;
264
265 adis_dev_lock(&st->adis);
266
267 if (st->sync_mode == ADIS16475_SYNC_SCALED) {
268 u16 sync_scale;
269
270 ret = __adis_read_reg_16(&st->adis, ADIS16475_REG_UP_SCALE, &sync_scale);
271 if (ret)
272 goto error;
273
274 sample_rate = st->clk_freq * sync_scale;
275 }
276
277 ret = __adis_read_reg_16(&st->adis, ADIS16475_REG_DEC_RATE, &dec);
278 if (ret)
279 goto error;
280
281 adis_dev_unlock(&st->adis);
282
283 *freq = DIV_ROUND_CLOSEST(sample_rate, dec + 1);
284
285 return 0;
286 error:
287 adis_dev_unlock(&st->adis);
288 return ret;
289 }
290
291 static int adis16475_set_freq(struct adis16475 *st, const u32 freq)
292 {
293 u16 dec;
294 int ret;
295 u32 sample_rate = st->clk_freq;
296
297 if (!freq)
298 return -EINVAL;
299
300 adis_dev_lock(&st->adis);
301 /*
302 * When using sync scaled mode, the input clock needs to be scaled so that we have
303 * an IMU sample rate between (optimally) 1900 and 2100. After this, we can use the
304 * decimation filter to lower the sampling rate in order to get what the user wants.
305 * Optimally, the user sample rate is a multiple of both the IMU sample rate and
306 * the input clock. Hence, calculating the sync_scale dynamically gives us better
307 * chances of achieving a perfect/integer value for DEC_RATE. The math here is:
308 * 1. lcm of the input clock and the desired output rate.
309 * 2. get the highest multiple of the previous result lower than the adis max rate.
310 * 3. The last result becomes the IMU sample rate. Use that to calculate SYNC_SCALE
311 * and DEC_RATE (to get the user output rate)
312 */
313 if (st->sync_mode == ADIS16475_SYNC_SCALED) {
314 unsigned long scaled_rate = lcm(st->clk_freq, freq);
315 int sync_scale;
316
317 /*
318 * If lcm is bigger than the IMU maximum sampling rate there's no perfect
319 * solution. In this case, we get the highest multiple of the input clock
320 * lower than the IMU max sample rate.
321 */
322 if (scaled_rate > 2100000)
323 scaled_rate = 2100000 / st->clk_freq * st->clk_freq;
324 else
325 scaled_rate = 2100000 / scaled_rate * scaled_rate;
326
327 /*
328 * This is not an hard requirement but it's not advised to run the IMU
329 * with a sample rate lower than 4000Hz due to possible undersampling
330 * issues. However, there are users that might really want to take the risk.
331 * Hence, we provide a module parameter for them. If set, we allow sample
332 * rates lower than 4KHz. By default, we won't allow this and we just roundup
333 * the rate to the next multiple of the input clock bigger than 4KHz. This
334 * is done like this as in some cases (when DEC_RATE is 0) might give
335 * us the closest value to the one desired by the user...
336 */
337 if (scaled_rate < 1900000 && !low_rate_allow)
338 scaled_rate = roundup(1900000, st->clk_freq);
339
340 sync_scale = scaled_rate / st->clk_freq;
341 ret = __adis_write_reg_16(&st->adis, ADIS16475_REG_UP_SCALE, sync_scale);
342 if (ret)
343 goto error;
344
345 sample_rate = scaled_rate;
346 }
347
348 dec = DIV_ROUND_CLOSEST(sample_rate, freq);
349
350 if (dec)
351 dec--;
352
353 if (dec > st->info->max_dec)
354 dec = st->info->max_dec;
355
356 ret = __adis_write_reg_16(&st->adis, ADIS16475_REG_DEC_RATE, dec);
357 if (ret)
358 goto error;
359
360 adis_dev_unlock(&st->adis);
361 /*
362 * If decimation is used, then gyro and accel data will have meaningful
363 * bits on the LSB registers. This info is used on the trigger handler.
364 */
365 assign_bit(ADIS16475_LSB_DEC_MASK, &st->lsb_flag, dec);
366
367 return 0;
368 error:
369 adis_dev_unlock(&st->adis);
370 return ret;
371 }
372
373 /* The values are approximated. */
374 static const u32 adis16475_3db_freqs[] = {
375 [0] = 720, /* Filter disabled, full BW (~720Hz) */
376 [1] = 360,
377 [2] = 164,
378 [3] = 80,
379 [4] = 40,
380 [5] = 20,
381 [6] = 10,
382 };
383
384 static int adis16475_get_filter(struct adis16475 *st, u32 *filter)
385 {
386 u16 filter_sz;
387 int ret;
388 const int mask = ADIS16475_FILT_CTRL_MASK;
389
390 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FILT_CTRL, &filter_sz);
391 if (ret)
392 return ret;
393
394 *filter = adis16475_3db_freqs[filter_sz & mask];
395
396 return 0;
397 }
398
399 static int adis16475_set_filter(struct adis16475 *st, const u32 filter)
400 {
401 int i = ARRAY_SIZE(adis16475_3db_freqs);
402 int ret;
403
404 while (--i) {
405 if (adis16475_3db_freqs[i] >= filter)
406 break;
407 }
408
409 ret = adis_write_reg_16(&st->adis, ADIS16475_REG_FILT_CTRL,
410 ADIS16475_FILT_CTRL(i));
411 if (ret)
412 return ret;
413
414 /*
415 * If FIR is used, then gyro and accel data will have meaningful
416 * bits on the LSB registers. This info is used on the trigger handler.
417 */
418 assign_bit(ADIS16475_LSB_FIR_MASK, &st->lsb_flag, i);
419
420 return 0;
421 }
422
423 static const u32 adis16475_calib_regs[] = {
424 [ADIS16475_SCAN_GYRO_X] = ADIS16475_REG_X_GYRO_BIAS_L,
425 [ADIS16475_SCAN_GYRO_Y] = ADIS16475_REG_Y_GYRO_BIAS_L,
426 [ADIS16475_SCAN_GYRO_Z] = ADIS16475_REG_Z_GYRO_BIAS_L,
427 [ADIS16475_SCAN_ACCEL_X] = ADIS16475_REG_X_ACCEL_BIAS_L,
428 [ADIS16475_SCAN_ACCEL_Y] = ADIS16475_REG_Y_ACCEL_BIAS_L,
429 [ADIS16475_SCAN_ACCEL_Z] = ADIS16475_REG_Z_ACCEL_BIAS_L,
430 };
431
432 static int adis16475_read_raw(struct iio_dev *indio_dev,
433 const struct iio_chan_spec *chan,
434 int *val, int *val2, long info)
435 {
436 struct adis16475 *st = iio_priv(indio_dev);
437 int ret;
438 u32 tmp;
439
440 switch (info) {
441 case IIO_CHAN_INFO_RAW:
442 return adis_single_conversion(indio_dev, chan, 0, val);
443 case IIO_CHAN_INFO_SCALE:
444 switch (chan->type) {
445 case IIO_ANGL_VEL:
446 *val = st->info->gyro_max_val;
447 *val2 = st->info->gyro_max_scale;
448 return IIO_VAL_FRACTIONAL;
449 case IIO_ACCEL:
450 *val = st->info->accel_max_val;
451 *val2 = st->info->accel_max_scale;
452 return IIO_VAL_FRACTIONAL;
453 case IIO_TEMP:
454 *val = st->info->temp_scale;
455 return IIO_VAL_INT;
456 default:
457 return -EINVAL;
458 }
459 case IIO_CHAN_INFO_CALIBBIAS:
460 ret = adis_read_reg_32(&st->adis,
461 adis16475_calib_regs[chan->scan_index],
462 val);
463 if (ret)
464 return ret;
465
466 return IIO_VAL_INT;
467 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
468 ret = adis16475_get_filter(st, val);
469 if (ret)
470 return ret;
471
472 return IIO_VAL_INT;
473 case IIO_CHAN_INFO_SAMP_FREQ:
474 ret = adis16475_get_freq(st, &tmp);
475 if (ret)
476 return ret;
477
478 *val = tmp / 1000;
479 *val2 = (tmp % 1000) * 1000;
480 return IIO_VAL_INT_PLUS_MICRO;
481 default:
482 return -EINVAL;
483 }
484 }
485
486 static int adis16475_write_raw(struct iio_dev *indio_dev,
487 const struct iio_chan_spec *chan,
488 int val, int val2, long info)
489 {
490 struct adis16475 *st = iio_priv(indio_dev);
491 u32 tmp;
492
493 switch (info) {
494 case IIO_CHAN_INFO_SAMP_FREQ:
495 tmp = val * 1000 + val2 / 1000;
496 return adis16475_set_freq(st, tmp);
497 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
498 return adis16475_set_filter(st, val);
499 case IIO_CHAN_INFO_CALIBBIAS:
500 return adis_write_reg_32(&st->adis,
501 adis16475_calib_regs[chan->scan_index],
502 val);
503 default:
504 return -EINVAL;
505 }
506 }
507
508 #define ADIS16475_MOD_CHAN(_type, _mod, _address, _si, _r_bits, _s_bits) \
509 { \
510 .type = (_type), \
511 .modified = 1, \
512 .channel2 = (_mod), \
513 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
514 BIT(IIO_CHAN_INFO_CALIBBIAS), \
515 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
516 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
517 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
518 .address = (_address), \
519 .scan_index = (_si), \
520 .scan_type = { \
521 .sign = 's', \
522 .realbits = (_r_bits), \
523 .storagebits = (_s_bits), \
524 .endianness = IIO_BE, \
525 }, \
526 }
527
528 #define ADIS16475_GYRO_CHANNEL(_mod) \
529 ADIS16475_MOD_CHAN(IIO_ANGL_VEL, IIO_MOD_ ## _mod, \
530 ADIS16475_REG_ ## _mod ## _GYRO_L, \
531 ADIS16475_SCAN_GYRO_ ## _mod, 32, 32)
532
533 #define ADIS16475_ACCEL_CHANNEL(_mod) \
534 ADIS16475_MOD_CHAN(IIO_ACCEL, IIO_MOD_ ## _mod, \
535 ADIS16475_REG_ ## _mod ## _ACCEL_L, \
536 ADIS16475_SCAN_ACCEL_ ## _mod, 32, 32)
537
538 #define ADIS16475_TEMP_CHANNEL() { \
539 .type = IIO_TEMP, \
540 .indexed = 1, \
541 .channel = 0, \
542 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
543 BIT(IIO_CHAN_INFO_SCALE), \
544 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
545 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
546 .address = ADIS16475_REG_TEMP_OUT, \
547 .scan_index = ADIS16475_SCAN_TEMP, \
548 .scan_type = { \
549 .sign = 's', \
550 .realbits = 16, \
551 .storagebits = 16, \
552 .endianness = IIO_BE, \
553 }, \
554 }
555
556 static const struct iio_chan_spec adis16475_channels[] = {
557 ADIS16475_GYRO_CHANNEL(X),
558 ADIS16475_GYRO_CHANNEL(Y),
559 ADIS16475_GYRO_CHANNEL(Z),
560 ADIS16475_ACCEL_CHANNEL(X),
561 ADIS16475_ACCEL_CHANNEL(Y),
562 ADIS16475_ACCEL_CHANNEL(Z),
563 ADIS16475_TEMP_CHANNEL(),
564 IIO_CHAN_SOFT_TIMESTAMP(7)
565 };
566
567 enum adis16475_variant {
568 ADIS16470,
569 ADIS16475_1,
570 ADIS16475_2,
571 ADIS16475_3,
572 ADIS16477_1,
573 ADIS16477_2,
574 ADIS16477_3,
575 ADIS16465_1,
576 ADIS16465_2,
577 ADIS16465_3,
578 ADIS16467_1,
579 ADIS16467_2,
580 ADIS16467_3,
581 ADIS16500,
582 ADIS16505_1,
583 ADIS16505_2,
584 ADIS16505_3,
585 ADIS16507_1,
586 ADIS16507_2,
587 ADIS16507_3,
588 };
589
590 enum {
591 ADIS16475_DIAG_STAT_DATA_PATH = 1,
592 ADIS16475_DIAG_STAT_FLASH_MEM,
593 ADIS16475_DIAG_STAT_SPI,
594 ADIS16475_DIAG_STAT_STANDBY,
595 ADIS16475_DIAG_STAT_SENSOR,
596 ADIS16475_DIAG_STAT_MEMORY,
597 ADIS16475_DIAG_STAT_CLK,
598 };
599
600 static const char * const adis16475_status_error_msgs[] = {
601 [ADIS16475_DIAG_STAT_DATA_PATH] = "Data Path Overrun",
602 [ADIS16475_DIAG_STAT_FLASH_MEM] = "Flash memory update failure",
603 [ADIS16475_DIAG_STAT_SPI] = "SPI communication error",
604 [ADIS16475_DIAG_STAT_STANDBY] = "Standby mode",
605 [ADIS16475_DIAG_STAT_SENSOR] = "Sensor failure",
606 [ADIS16475_DIAG_STAT_MEMORY] = "Memory failure",
607 [ADIS16475_DIAG_STAT_CLK] = "Clock error",
608 };
609
610 static int adis16475_enable_irq(struct adis *adis, bool enable)
611 {
612 /*
613 * There is no way to gate the data-ready signal internally inside the
614 * ADIS16475. We can only control it's polarity...
615 */
616 if (enable)
617 enable_irq(adis->spi->irq);
618 else
619 disable_irq(adis->spi->irq);
620
621 return 0;
622 }
623
624 #define ADIS16475_DATA(_prod_id, _timeouts) \
625 { \
626 .msc_ctrl_reg = ADIS16475_REG_MSG_CTRL, \
627 .glob_cmd_reg = ADIS16475_REG_GLOB_CMD, \
628 .diag_stat_reg = ADIS16475_REG_DIAG_STAT, \
629 .prod_id_reg = ADIS16475_REG_PROD_ID, \
630 .prod_id = (_prod_id), \
631 .self_test_mask = BIT(2), \
632 .self_test_reg = ADIS16475_REG_GLOB_CMD, \
633 .cs_change_delay = 16, \
634 .read_delay = 5, \
635 .write_delay = 5, \
636 .status_error_msgs = adis16475_status_error_msgs, \
637 .status_error_mask = BIT(ADIS16475_DIAG_STAT_DATA_PATH) | \
638 BIT(ADIS16475_DIAG_STAT_FLASH_MEM) | \
639 BIT(ADIS16475_DIAG_STAT_SPI) | \
640 BIT(ADIS16475_DIAG_STAT_STANDBY) | \
641 BIT(ADIS16475_DIAG_STAT_SENSOR) | \
642 BIT(ADIS16475_DIAG_STAT_MEMORY) | \
643 BIT(ADIS16475_DIAG_STAT_CLK), \
644 .enable_irq = adis16475_enable_irq, \
645 .timeouts = (_timeouts), \
646 .burst_reg_cmd = ADIS16475_REG_GLOB_CMD, \
647 .burst_len = ADIS16475_BURST_MAX_DATA, \
648 .burst_max_len = ADIS16475_BURST32_MAX_DATA, \
649 .burst_max_speed_hz = ADIS16475_BURST_MAX_SPEED \
650 }
651
652 static const struct adis16475_sync adis16475_sync_mode[] = {
653 { ADIS16475_SYNC_OUTPUT },
654 { ADIS16475_SYNC_DIRECT, 1900, 2100 },
655 { ADIS16475_SYNC_SCALED, 1, 128 },
656 { ADIS16475_SYNC_PULSE, 1000, 2100 },
657 };
658
659 static const struct adis_timeout adis16475_timeouts = {
660 .reset_ms = 200,
661 .sw_reset_ms = 200,
662 .self_test_ms = 20,
663 };
664
665 static const struct adis_timeout adis1650x_timeouts = {
666 .reset_ms = 260,
667 .sw_reset_ms = 260,
668 .self_test_ms = 30,
669 };
670
671 static const struct adis16475_chip_info adis16475_chip_info[] = {
672 [ADIS16470] = {
673 .name = "adis16470",
674 .num_channels = ARRAY_SIZE(adis16475_channels),
675 .channels = adis16475_channels,
676 .gyro_max_val = 1,
677 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16),
678 .accel_max_val = 1,
679 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16),
680 .temp_scale = 100,
681 .int_clk = 2000,
682 .max_dec = 1999,
683 .sync = adis16475_sync_mode,
684 .num_sync = ARRAY_SIZE(adis16475_sync_mode),
685 .adis_data = ADIS16475_DATA(16470, &adis16475_timeouts),
686 },
687 [ADIS16475_1] = {
688 .name = "adis16475-1",
689 .num_channels = ARRAY_SIZE(adis16475_channels),
690 .channels = adis16475_channels,
691 .gyro_max_val = 1,
692 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16),
693 .accel_max_val = 1,
694 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16),
695 .temp_scale = 100,
696 .int_clk = 2000,
697 .max_dec = 1999,
698 .sync = adis16475_sync_mode,
699 .num_sync = ARRAY_SIZE(adis16475_sync_mode),
700 .adis_data = ADIS16475_DATA(16475, &adis16475_timeouts),
701 },
702 [ADIS16475_2] = {
703 .name = "adis16475-2",
704 .num_channels = ARRAY_SIZE(adis16475_channels),
705 .channels = adis16475_channels,
706 .gyro_max_val = 1,
707 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16),
708 .accel_max_val = 1,
709 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16),
710 .temp_scale = 100,
711 .int_clk = 2000,
712 .max_dec = 1999,
713 .sync = adis16475_sync_mode,
714 .num_sync = ARRAY_SIZE(adis16475_sync_mode),
715 .adis_data = ADIS16475_DATA(16475, &adis16475_timeouts),
716 },
717 [ADIS16475_3] = {
718 .name = "adis16475-3",
719 .num_channels = ARRAY_SIZE(adis16475_channels),
720 .channels = adis16475_channels,
721 .gyro_max_val = 1,
722 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16),
723 .accel_max_val = 1,
724 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16),
725 .temp_scale = 100,
726 .int_clk = 2000,
727 .max_dec = 1999,
728 .sync = adis16475_sync_mode,
729 .num_sync = ARRAY_SIZE(adis16475_sync_mode),
730 .adis_data = ADIS16475_DATA(16475, &adis16475_timeouts),
731 },
732 [ADIS16477_1] = {
733 .name = "adis16477-1",
734 .num_channels = ARRAY_SIZE(adis16475_channels),
735 .channels = adis16475_channels,
736 .gyro_max_val = 1,
737 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16),
738 .accel_max_val = 1,
739 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16),
740 .temp_scale = 100,
741 .int_clk = 2000,
742 .max_dec = 1999,
743 .sync = adis16475_sync_mode,
744 .num_sync = ARRAY_SIZE(adis16475_sync_mode),
745 .adis_data = ADIS16475_DATA(16477, &adis16475_timeouts),
746 },
747 [ADIS16477_2] = {
748 .name = "adis16477-2",
749 .num_channels = ARRAY_SIZE(adis16475_channels),
750 .channels = adis16475_channels,
751 .gyro_max_val = 1,
752 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16),
753 .accel_max_val = 1,
754 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16),
755 .temp_scale = 100,
756 .int_clk = 2000,
757 .max_dec = 1999,
758 .sync = adis16475_sync_mode,
759 .num_sync = ARRAY_SIZE(adis16475_sync_mode),
760 .adis_data = ADIS16475_DATA(16477, &adis16475_timeouts),
761 },
762 [ADIS16477_3] = {
763 .name = "adis16477-3",
764 .num_channels = ARRAY_SIZE(adis16475_channels),
765 .channels = adis16475_channels,
766 .gyro_max_val = 1,
767 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16),
768 .accel_max_val = 1,
769 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16),
770 .temp_scale = 100,
771 .int_clk = 2000,
772 .max_dec = 1999,
773 .sync = adis16475_sync_mode,
774 .num_sync = ARRAY_SIZE(adis16475_sync_mode),
775 .adis_data = ADIS16475_DATA(16477, &adis16475_timeouts),
776 },
777 [ADIS16465_1] = {
778 .name = "adis16465-1",
779 .num_channels = ARRAY_SIZE(adis16475_channels),
780 .channels = adis16475_channels,
781 .gyro_max_val = 1,
782 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16),
783 .accel_max_val = 1,
784 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16),
785 .temp_scale = 100,
786 .int_clk = 2000,
787 .max_dec = 1999,
788 .sync = adis16475_sync_mode,
789 .num_sync = ARRAY_SIZE(adis16475_sync_mode),
790 .adis_data = ADIS16475_DATA(16465, &adis16475_timeouts),
791 },
792 [ADIS16465_2] = {
793 .name = "adis16465-2",
794 .num_channels = ARRAY_SIZE(adis16475_channels),
795 .channels = adis16475_channels,
796 .gyro_max_val = 1,
797 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16),
798 .accel_max_val = 1,
799 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16),
800 .temp_scale = 100,
801 .int_clk = 2000,
802 .max_dec = 1999,
803 .sync = adis16475_sync_mode,
804 .num_sync = ARRAY_SIZE(adis16475_sync_mode),
805 .adis_data = ADIS16475_DATA(16465, &adis16475_timeouts),
806 },
807 [ADIS16465_3] = {
808 .name = "adis16465-3",
809 .num_channels = ARRAY_SIZE(adis16475_channels),
810 .channels = adis16475_channels,
811 .gyro_max_val = 1,
812 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16),
813 .accel_max_val = 1,
814 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16),
815 .temp_scale = 100,
816 .int_clk = 2000,
817 .max_dec = 1999,
818 .sync = adis16475_sync_mode,
819 .num_sync = ARRAY_SIZE(adis16475_sync_mode),
820 .adis_data = ADIS16475_DATA(16465, &adis16475_timeouts),
821 },
822 [ADIS16467_1] = {
823 .name = "adis16467-1",
824 .num_channels = ARRAY_SIZE(adis16475_channels),
825 .channels = adis16475_channels,
826 .gyro_max_val = 1,
827 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16),
828 .accel_max_val = 1,
829 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16),
830 .temp_scale = 100,
831 .int_clk = 2000,
832 .max_dec = 1999,
833 .sync = adis16475_sync_mode,
834 .num_sync = ARRAY_SIZE(adis16475_sync_mode),
835 .adis_data = ADIS16475_DATA(16467, &adis16475_timeouts),
836 },
837 [ADIS16467_2] = {
838 .name = "adis16467-2",
839 .num_channels = ARRAY_SIZE(adis16475_channels),
840 .channels = adis16475_channels,
841 .gyro_max_val = 1,
842 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16),
843 .accel_max_val = 1,
844 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16),
845 .temp_scale = 100,
846 .int_clk = 2000,
847 .max_dec = 1999,
848 .sync = adis16475_sync_mode,
849 .num_sync = ARRAY_SIZE(adis16475_sync_mode),
850 .adis_data = ADIS16475_DATA(16467, &adis16475_timeouts),
851 },
852 [ADIS16467_3] = {
853 .name = "adis16467-3",
854 .num_channels = ARRAY_SIZE(adis16475_channels),
855 .channels = adis16475_channels,
856 .gyro_max_val = 1,
857 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16),
858 .accel_max_val = 1,
859 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16),
860 .temp_scale = 100,
861 .int_clk = 2000,
862 .max_dec = 1999,
863 .sync = adis16475_sync_mode,
864 .num_sync = ARRAY_SIZE(adis16475_sync_mode),
865 .adis_data = ADIS16475_DATA(16467, &adis16475_timeouts),
866 },
867 [ADIS16500] = {
868 .name = "adis16500",
869 .num_channels = ARRAY_SIZE(adis16475_channels),
870 .channels = adis16475_channels,
871 .gyro_max_val = 1,
872 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16),
873 .accel_max_val = 392,
874 .accel_max_scale = 32000 << 16,
875 .temp_scale = 100,
876 .int_clk = 2000,
877 .max_dec = 1999,
878 .sync = adis16475_sync_mode,
879 /* pulse sync not supported */
880 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1,
881 .has_burst32 = true,
882 .adis_data = ADIS16475_DATA(16500, &adis1650x_timeouts),
883 },
884 [ADIS16505_1] = {
885 .name = "adis16505-1",
886 .num_channels = ARRAY_SIZE(adis16475_channels),
887 .channels = adis16475_channels,
888 .gyro_max_val = 1,
889 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16),
890 .accel_max_val = 78,
891 .accel_max_scale = 32000 << 16,
892 .temp_scale = 100,
893 .int_clk = 2000,
894 .max_dec = 1999,
895 .sync = adis16475_sync_mode,
896 /* pulse sync not supported */
897 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1,
898 .has_burst32 = true,
899 .adis_data = ADIS16475_DATA(16505, &adis1650x_timeouts),
900 },
901 [ADIS16505_2] = {
902 .name = "adis16505-2",
903 .num_channels = ARRAY_SIZE(adis16475_channels),
904 .channels = adis16475_channels,
905 .gyro_max_val = 1,
906 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16),
907 .accel_max_val = 78,
908 .accel_max_scale = 32000 << 16,
909 .temp_scale = 100,
910 .int_clk = 2000,
911 .max_dec = 1999,
912 .sync = adis16475_sync_mode,
913 /* pulse sync not supported */
914 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1,
915 .has_burst32 = true,
916 .adis_data = ADIS16475_DATA(16505, &adis1650x_timeouts),
917 },
918 [ADIS16505_3] = {
919 .name = "adis16505-3",
920 .num_channels = ARRAY_SIZE(adis16475_channels),
921 .channels = adis16475_channels,
922 .gyro_max_val = 1,
923 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16),
924 .accel_max_val = 78,
925 .accel_max_scale = 32000 << 16,
926 .temp_scale = 100,
927 .int_clk = 2000,
928 .max_dec = 1999,
929 .sync = adis16475_sync_mode,
930 /* pulse sync not supported */
931 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1,
932 .has_burst32 = true,
933 .adis_data = ADIS16475_DATA(16505, &adis1650x_timeouts),
934 },
935 [ADIS16507_1] = {
936 .name = "adis16507-1",
937 .num_channels = ARRAY_SIZE(adis16475_channels),
938 .channels = adis16475_channels,
939 .gyro_max_val = 1,
940 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16),
941 .accel_max_val = 392,
942 .accel_max_scale = 32000 << 16,
943 .temp_scale = 100,
944 .int_clk = 2000,
945 .max_dec = 1999,
946 .sync = adis16475_sync_mode,
947 /* pulse sync not supported */
948 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1,
949 .has_burst32 = true,
950 .adis_data = ADIS16475_DATA(16507, &adis1650x_timeouts),
951 },
952 [ADIS16507_2] = {
953 .name = "adis16507-2",
954 .num_channels = ARRAY_SIZE(adis16475_channels),
955 .channels = adis16475_channels,
956 .gyro_max_val = 1,
957 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16),
958 .accel_max_val = 392,
959 .accel_max_scale = 32000 << 16,
960 .temp_scale = 100,
961 .int_clk = 2000,
962 .max_dec = 1999,
963 .sync = adis16475_sync_mode,
964 /* pulse sync not supported */
965 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1,
966 .has_burst32 = true,
967 .adis_data = ADIS16475_DATA(16507, &adis1650x_timeouts),
968 },
969 [ADIS16507_3] = {
970 .name = "adis16507-3",
971 .num_channels = ARRAY_SIZE(adis16475_channels),
972 .channels = adis16475_channels,
973 .gyro_max_val = 1,
974 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16),
975 .accel_max_val = 392,
976 .accel_max_scale = 32000 << 16,
977 .temp_scale = 100,
978 .int_clk = 2000,
979 .max_dec = 1999,
980 .sync = adis16475_sync_mode,
981 /* pulse sync not supported */
982 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1,
983 .has_burst32 = true,
984 .adis_data = ADIS16475_DATA(16507, &adis1650x_timeouts),
985 },
986 };
987
988 static const struct iio_info adis16475_info = {
989 .read_raw = &adis16475_read_raw,
990 .write_raw = &adis16475_write_raw,
991 .update_scan_mode = adis_update_scan_mode,
992 .debugfs_reg_access = adis_debugfs_reg_access,
993 };
994
995 static bool adis16475_validate_crc(const u8 *buffer, u16 crc,
996 const bool burst32)
997 {
998 int i;
999 /* extra 6 elements for low gyro and accel */
1000 const u16 sz = burst32 ? ADIS16475_BURST32_MAX_DATA :
1001 ADIS16475_BURST_MAX_DATA;
1002
1003 for (i = 0; i < sz - 2; i++)
1004 crc -= buffer[i];
1005
1006 return crc == 0;
1007 }
1008
1009 static void adis16475_burst32_check(struct adis16475 *st)
1010 {
1011 int ret;
1012 struct adis *adis = &st->adis;
1013
1014 if (!st->info->has_burst32)
1015 return;
1016
1017 if (st->lsb_flag && !st->burst32) {
1018 const u16 en = ADIS16500_BURST32(1);
1019
1020 ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL,
1021 ADIS16500_BURST32_MASK, en);
1022 if (ret)
1023 return;
1024
1025 st->burst32 = true;
1026
1027 /*
1028 * In 32-bit mode we need extra 2 bytes for all gyro
1029 * and accel channels.
1030 */
1031 adis->burst_extra_len = 6 * sizeof(u16);
1032 adis->xfer[1].len += 6 * sizeof(u16);
1033 dev_dbg(&adis->spi->dev, "Enable burst32 mode, xfer:%d",
1034 adis->xfer[1].len);
1035
1036 } else if (!st->lsb_flag && st->burst32) {
1037 const u16 en = ADIS16500_BURST32(0);
1038
1039 ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL,
1040 ADIS16500_BURST32_MASK, en);
1041 if (ret)
1042 return;
1043
1044 st->burst32 = false;
1045
1046 /* Remove the extra bits */
1047 adis->burst_extra_len = 0;
1048 adis->xfer[1].len -= 6 * sizeof(u16);
1049 dev_dbg(&adis->spi->dev, "Disable burst32 mode, xfer:%d\n",
1050 adis->xfer[1].len);
1051 }
1052 }
1053
1054 static irqreturn_t adis16475_trigger_handler(int irq, void *p)
1055 {
1056 struct iio_poll_func *pf = p;
1057 struct iio_dev *indio_dev = pf->indio_dev;
1058 struct adis16475 *st = iio_priv(indio_dev);
1059 struct adis *adis = &st->adis;
1060 int ret, bit, i = 0;
1061 __be16 *buffer;
1062 u16 crc;
1063 bool valid;
1064 /* offset until the first element after gyro and accel */
1065 const u8 offset = st->burst32 ? 13 : 7;
1066
1067 ret = spi_sync(adis->spi, &adis->msg);
1068 if (ret)
1069 goto check_burst32;
1070
1071 buffer = adis->buffer;
1072
1073 crc = be16_to_cpu(buffer[offset + 2]);
1074 valid = adis16475_validate_crc(adis->buffer, crc, st->burst32);
1075 if (!valid) {
1076 dev_err(&adis->spi->dev, "Invalid crc\n");
1077 goto check_burst32;
1078 }
1079
1080 for_each_set_bit(bit, indio_dev->active_scan_mask,
1081 indio_dev->masklength) {
1082 /*
1083 * When burst mode is used, system flags is the first data
1084 * channel in the sequence, but the scan index is 7.
1085 */
1086 switch (bit) {
1087 case ADIS16475_SCAN_TEMP:
1088 st->data[i++] = buffer[offset];
1089 break;
1090 case ADIS16475_SCAN_GYRO_X ... ADIS16475_SCAN_ACCEL_Z:
1091 /*
1092 * The first 2 bytes on the received data are the
1093 * DIAG_STAT reg, hence the +1 offset here...
1094 */
1095 if (st->burst32) {
1096 /* upper 16 */
1097 st->data[i++] = buffer[bit * 2 + 2];
1098 /* lower 16 */
1099 st->data[i++] = buffer[bit * 2 + 1];
1100 } else {
1101 st->data[i++] = buffer[bit + 1];
1102 /*
1103 * Don't bother in doing the manual read if the
1104 * device supports burst32. burst32 will be
1105 * enabled in the next call to
1106 * adis16475_burst32_check()...
1107 */
1108 if (st->lsb_flag && !st->info->has_burst32) {
1109 u16 val = 0;
1110 const u32 reg = ADIS16475_REG_X_GYRO_L +
1111 bit * 4;
1112
1113 adis_read_reg_16(adis, reg, &val);
1114 st->data[i++] = cpu_to_be16(val);
1115 } else {
1116 /* lower not used */
1117 st->data[i++] = 0;
1118 }
1119 }
1120 break;
1121 }
1122 }
1123
1124 iio_push_to_buffers_with_timestamp(indio_dev, st->data, pf->timestamp);
1125 check_burst32:
1126 /*
1127 * We only check the burst mode at the end of the current capture since
1128 * it takes a full data ready cycle for the device to update the burst
1129 * array.
1130 */
1131 adis16475_burst32_check(st);
1132 iio_trigger_notify_done(indio_dev->trig);
1133
1134 return IRQ_HANDLED;
1135 }
1136
1137 static void adis16475_disable_clk(void *data)
1138 {
1139 clk_disable_unprepare((struct clk *)data);
1140 }
1141
1142 static int adis16475_config_sync_mode(struct adis16475 *st)
1143 {
1144 int ret;
1145 struct device *dev = &st->adis.spi->dev;
1146 const struct adis16475_sync *sync;
1147 u32 sync_mode;
1148
1149 /* default to internal clk */
1150 st->clk_freq = st->info->int_clk * 1000;
1151
1152 ret = device_property_read_u32(dev, "adi,sync-mode", &sync_mode);
1153 if (ret)
1154 return 0;
1155
1156 if (sync_mode >= st->info->num_sync) {
1157 dev_err(dev, "Invalid sync mode: %u for %s\n", sync_mode,
1158 st->info->name);
1159 return -EINVAL;
1160 }
1161
1162 sync = &st->info->sync[sync_mode];
1163 st->sync_mode = sync->sync_mode;
1164
1165 /* All the other modes require external input signal */
1166 if (sync->sync_mode != ADIS16475_SYNC_OUTPUT) {
1167 struct clk *clk = devm_clk_get(dev, NULL);
1168
1169 if (IS_ERR(clk))
1170 return PTR_ERR(clk);
1171
1172 ret = clk_prepare_enable(clk);
1173 if (ret)
1174 return ret;
1175
1176 ret = devm_add_action_or_reset(dev, adis16475_disable_clk, clk);
1177 if (ret)
1178 return ret;
1179
1180 st->clk_freq = clk_get_rate(clk);
1181 if (st->clk_freq < sync->min_rate ||
1182 st->clk_freq > sync->max_rate) {
1183 dev_err(dev,
1184 "Clk rate:%u not in a valid range:[%u %u]\n",
1185 st->clk_freq, sync->min_rate, sync->max_rate);
1186 return -EINVAL;
1187 }
1188
1189 if (sync->sync_mode == ADIS16475_SYNC_SCALED) {
1190 u16 up_scale;
1191
1192 /*
1193 * In sync scaled mode, the IMU sample rate is the clk_freq * sync_scale.
1194 * Hence, default the IMU sample rate to the highest multiple of the input
1195 * clock lower than the IMU max sample rate. The optimal range is
1196 * 1900-2100 sps...
1197 */
1198 up_scale = 2100 / st->clk_freq;
1199
1200 ret = __adis_write_reg_16(&st->adis,
1201 ADIS16475_REG_UP_SCALE,
1202 up_scale);
1203 if (ret)
1204 return ret;
1205 }
1206
1207 st->clk_freq *= 1000;
1208 }
1209 /*
1210 * Keep in mind that the mask for the clk modes in adis1650*
1211 * chips is different (1100 instead of 11100). However, we
1212 * are not configuring BIT(4) in these chips and the default
1213 * value is 0, so we are fine in doing the below operations.
1214 * I'm keeping this for simplicity and avoiding extra variables
1215 * in chip_info.
1216 */
1217 ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL,
1218 ADIS16475_SYNC_MODE_MASK, sync->sync_mode);
1219 if (ret)
1220 return ret;
1221
1222 usleep_range(250, 260);
1223
1224 return 0;
1225 }
1226
1227 static int adis16475_config_irq_pin(struct adis16475 *st)
1228 {
1229 int ret;
1230 struct irq_data *desc;
1231 u32 irq_type;
1232 u16 val = 0;
1233 u8 polarity;
1234 struct spi_device *spi = st->adis.spi;
1235
1236 desc = irq_get_irq_data(spi->irq);
1237 if (!desc) {
1238 dev_err(&spi->dev, "Could not find IRQ %d\n", spi->irq);
1239 return -EINVAL;
1240 }
1241 /*
1242 * It is possible to configure the data ready polarity. Furthermore, we
1243 * need to update the adis struct if we want data ready as active low.
1244 */
1245 irq_type = irqd_get_trigger_type(desc);
1246 if (irq_type == IRQ_TYPE_EDGE_RISING) {
1247 polarity = 1;
1248 st->adis.irq_flag = IRQF_TRIGGER_RISING;
1249 } else if (irq_type == IRQ_TYPE_EDGE_FALLING) {
1250 polarity = 0;
1251 st->adis.irq_flag = IRQF_TRIGGER_FALLING;
1252 } else {
1253 dev_err(&spi->dev, "Invalid interrupt type 0x%x specified\n",
1254 irq_type);
1255 return -EINVAL;
1256 }
1257
1258 /* We cannot mask the interrupt so ensure it's not enabled at request */
1259 st->adis.irq_flag |= IRQF_NO_AUTOEN;
1260
1261 val = ADIS16475_MSG_CTRL_DR_POL(polarity);
1262 ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL,
1263 ADIS16475_MSG_CTRL_DR_POL_MASK, val);
1264 if (ret)
1265 return ret;
1266 /*
1267 * There is a delay writing to any bits written to the MSC_CTRL
1268 * register. It should not be bigger than 200us, so 250 should be more
1269 * than enough!
1270 */
1271 usleep_range(250, 260);
1272
1273 return 0;
1274 }
1275
1276 static const struct of_device_id adis16475_of_match[] = {
1277 { .compatible = "adi,adis16470",
1278 .data = &adis16475_chip_info[ADIS16470] },
1279 { .compatible = "adi,adis16475-1",
1280 .data = &adis16475_chip_info[ADIS16475_1] },
1281 { .compatible = "adi,adis16475-2",
1282 .data = &adis16475_chip_info[ADIS16475_2] },
1283 { .compatible = "adi,adis16475-3",
1284 .data = &adis16475_chip_info[ADIS16475_3] },
1285 { .compatible = "adi,adis16477-1",
1286 .data = &adis16475_chip_info[ADIS16477_1] },
1287 { .compatible = "adi,adis16477-2",
1288 .data = &adis16475_chip_info[ADIS16477_2] },
1289 { .compatible = "adi,adis16477-3",
1290 .data = &adis16475_chip_info[ADIS16477_3] },
1291 { .compatible = "adi,adis16465-1",
1292 .data = &adis16475_chip_info[ADIS16465_1] },
1293 { .compatible = "adi,adis16465-2",
1294 .data = &adis16475_chip_info[ADIS16465_2] },
1295 { .compatible = "adi,adis16465-3",
1296 .data = &adis16475_chip_info[ADIS16465_3] },
1297 { .compatible = "adi,adis16467-1",
1298 .data = &adis16475_chip_info[ADIS16467_1] },
1299 { .compatible = "adi,adis16467-2",
1300 .data = &adis16475_chip_info[ADIS16467_2] },
1301 { .compatible = "adi,adis16467-3",
1302 .data = &adis16475_chip_info[ADIS16467_3] },
1303 { .compatible = "adi,adis16500",
1304 .data = &adis16475_chip_info[ADIS16500] },
1305 { .compatible = "adi,adis16505-1",
1306 .data = &adis16475_chip_info[ADIS16505_1] },
1307 { .compatible = "adi,adis16505-2",
1308 .data = &adis16475_chip_info[ADIS16505_2] },
1309 { .compatible = "adi,adis16505-3",
1310 .data = &adis16475_chip_info[ADIS16505_3] },
1311 { .compatible = "adi,adis16507-1",
1312 .data = &adis16475_chip_info[ADIS16507_1] },
1313 { .compatible = "adi,adis16507-2",
1314 .data = &adis16475_chip_info[ADIS16507_2] },
1315 { .compatible = "adi,adis16507-3",
1316 .data = &adis16475_chip_info[ADIS16507_3] },
1317 { },
1318 };
1319 MODULE_DEVICE_TABLE(of, adis16475_of_match);
1320
1321 static int adis16475_probe(struct spi_device *spi)
1322 {
1323 struct iio_dev *indio_dev;
1324 struct adis16475 *st;
1325 int ret;
1326
1327 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
1328 if (!indio_dev)
1329 return -ENOMEM;
1330
1331 st = iio_priv(indio_dev);
1332
1333 st->info = device_get_match_data(&spi->dev);
1334 if (!st->info)
1335 return -EINVAL;
1336
1337 ret = adis_init(&st->adis, indio_dev, spi, &st->info->adis_data);
1338 if (ret)
1339 return ret;
1340
1341 indio_dev->name = st->info->name;
1342 indio_dev->channels = st->info->channels;
1343 indio_dev->num_channels = st->info->num_channels;
1344 indio_dev->info = &adis16475_info;
1345 indio_dev->modes = INDIO_DIRECT_MODE;
1346
1347 ret = __adis_initial_startup(&st->adis);
1348 if (ret)
1349 return ret;
1350
1351 ret = adis16475_config_irq_pin(st);
1352 if (ret)
1353 return ret;
1354
1355 ret = adis16475_config_sync_mode(st);
1356 if (ret)
1357 return ret;
1358
1359 ret = devm_adis_setup_buffer_and_trigger(&st->adis, indio_dev,
1360 adis16475_trigger_handler);
1361 if (ret)
1362 return ret;
1363
1364 ret = devm_iio_device_register(&spi->dev, indio_dev);
1365 if (ret)
1366 return ret;
1367
1368 adis16475_debugfs_init(indio_dev);
1369
1370 return 0;
1371 }
1372
1373 static struct spi_driver adis16475_driver = {
1374 .driver = {
1375 .name = "adis16475",
1376 .of_match_table = adis16475_of_match,
1377 },
1378 .probe = adis16475_probe,
1379 };
1380 module_spi_driver(adis16475_driver);
1381
1382 MODULE_AUTHOR("Nuno Sa <nuno.sa@analog.com>");
1383 MODULE_DESCRIPTION("Analog Devices ADIS16475 IMU driver");
1384 MODULE_LICENSE("GPL");
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