drivers/iio/trigger/stm32-timer-trigger.c

   1 /*
   2  * Copyright (C) STMicroelectronics 2016
   3  *
   4  * Author: Benjamin Gaignard <benjamin.gaignard@st.com>
   5  *
   6  * License terms:  GNU General Public License (GPL), version 2
   7  */
   8
   9 #include <linux/iio/iio.h>
  10 #include <linux/iio/sysfs.h>
  11 #include <linux/iio/timer/stm32-timer-trigger.h>
  12 #include <linux/iio/trigger.h>
  13 #include <linux/mfd/stm32-timers.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16
  17 #define MAX_TRIGGERS 6
  18 #define MAX_VALIDS 5
  19
  20 /* List the triggers created by each timer */
  21 static const void *triggers_table[][MAX_TRIGGERS] = {
  22         { TIM1_TRGO, TIM1_CH1, TIM1_CH2, TIM1_CH3, TIM1_CH4,},
  23         { TIM2_TRGO, TIM2_CH1, TIM2_CH2, TIM2_CH3, TIM2_CH4,},
  24         { TIM3_TRGO, TIM3_CH1, TIM3_CH2, TIM3_CH3, TIM3_CH4,},
  25         { TIM4_TRGO, TIM4_CH1, TIM4_CH2, TIM4_CH3, TIM4_CH4,},
  26         { TIM5_TRGO, TIM5_CH1, TIM5_CH2, TIM5_CH3, TIM5_CH4,},
  27         { TIM6_TRGO,},
  28         { TIM7_TRGO,},
  29         { TIM8_TRGO, TIM8_CH1, TIM8_CH2, TIM8_CH3, TIM8_CH4,},
  30         { TIM9_TRGO, TIM9_CH1, TIM9_CH2,},
  31         { }, /* timer 10 */
  32         { }, /* timer 11 */
  33         { TIM12_TRGO, TIM12_CH1, TIM12_CH2,},
  34 };
  35
  36 /* List the triggers accepted by each timer */
  37 static const void *valids_table[][MAX_VALIDS] = {
  38         { TIM5_TRGO, TIM2_TRGO, TIM3_TRGO, TIM4_TRGO,},
  39         { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,},
  40         { TIM1_TRGO, TIM2_TRGO, TIM5_TRGO, TIM4_TRGO,},
  41         { TIM1_TRGO, TIM2_TRGO, TIM3_TRGO, TIM8_TRGO,},
  42         { TIM2_TRGO, TIM3_TRGO, TIM4_TRGO, TIM8_TRGO,},
  43         { }, /* timer 6 */
  44         { }, /* timer 7 */
  45         { TIM1_TRGO, TIM2_TRGO, TIM4_TRGO, TIM5_TRGO,},
  46         { TIM2_TRGO, TIM3_TRGO,},
  47         { }, /* timer 10 */
  48         { }, /* timer 11 */
  49         { TIM4_TRGO, TIM5_TRGO,},
  50 };
  51
  52 struct stm32_timer_trigger {
  53         struct device *dev;
  54         struct regmap *regmap;
  55         struct clk *clk;
  56         u32 max_arr;
  57         const void *triggers;
  58         const void *valids;
  59 };
  60
  61 static int stm32_timer_start(struct stm32_timer_trigger *priv,
  62                              unsigned int frequency)
  63 {
  64         unsigned long long prd, div;
  65         int prescaler = 0;
  66         u32 ccer, cr1;
  67
  68         /* Period and prescaler values depends of clock rate */
  69         div = (unsigned long long)clk_get_rate(priv->clk);
  70
  71         do_div(div, frequency);
  72
  73         prd = div;
  74
  75         /*
  76          * Increase prescaler value until we get a result that fit
  77          * with auto reload register maximum value.
  78          */
  79         while (div > priv->max_arr) {
  80                 prescaler++;
  81                 div = prd;
  82                 do_div(div, (prescaler + 1));
  83         }
  84         prd = div;
  85
  86         if (prescaler > MAX_TIM_PSC) {
  87                 dev_err(priv->dev, "prescaler exceeds the maximum value\n");
  88                 return -EINVAL;
  89         }
  90
  91         /* Check if nobody else use the timer */
  92         regmap_read(priv->regmap, TIM_CCER, &ccer);
  93         if (ccer & TIM_CCER_CCXE)
  94                 return -EBUSY;
  95
  96         regmap_read(priv->regmap, TIM_CR1, &cr1);
  97         if (!(cr1 & TIM_CR1_CEN))
  98                 clk_enable(priv->clk);
  99
 100         regmap_write(priv->regmap, TIM_PSC, prescaler);
 101         regmap_write(priv->regmap, TIM_ARR, prd - 1);
 102         regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);
 103
 104         /* Force master mode to update mode */
 105         regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS, 0x20);
 106
 107         /* Make sure that registers are updated */
 108         regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
 109
 110         /* Enable controller */
 111         regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);
 112
 113         return 0;
 114 }
 115
 116 static void stm32_timer_stop(struct stm32_timer_trigger *priv)
 117 {
 118         u32 ccer, cr1;
 119
 120         regmap_read(priv->regmap, TIM_CCER, &ccer);
 121         if (ccer & TIM_CCER_CCXE)
 122                 return;
 123
 124         regmap_read(priv->regmap, TIM_CR1, &cr1);
 125         if (cr1 & TIM_CR1_CEN)
 126                 clk_disable(priv->clk);
 127
 128         /* Stop timer */
 129         regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
 130         regmap_write(priv->regmap, TIM_PSC, 0);
 131         regmap_write(priv->regmap, TIM_ARR, 0);
 132
 133         /* Make sure that registers are updated */
 134         regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
 135 }
 136
 137 static ssize_t stm32_tt_store_frequency(struct device *dev,
 138                                         struct device_attribute *attr,
 139                                         const char *buf, size_t len)
 140 {
 141         struct iio_trigger *trig = to_iio_trigger(dev);
 142         struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig);
 143         unsigned int freq;
 144         int ret;
 145
 146         ret = kstrtouint(buf, 10, &freq);
 147         if (ret)
 148                 return ret;
 149
 150         if (freq == 0) {
 151                 stm32_timer_stop(priv);
 152         } else {
 153                 ret = stm32_timer_start(priv, freq);
 154                 if (ret)
 155                         return ret;
 156         }
 157
 158         return len;
 159 }
 160
 161 static ssize_t stm32_tt_read_frequency(struct device *dev,
 162                                        struct device_attribute *attr, char *buf)
 163 {
 164         struct iio_trigger *trig = to_iio_trigger(dev);
 165         struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig);
 166         u32 psc, arr, cr1;
 167         unsigned long long freq = 0;
 168
 169         regmap_read(priv->regmap, TIM_CR1, &cr1);
 170         regmap_read(priv->regmap, TIM_PSC, &psc);
 171         regmap_read(priv->regmap, TIM_ARR, &arr);
 172
 173         if (psc && arr && (cr1 & TIM_CR1_CEN)) {
 174                 freq = (unsigned long long)clk_get_rate(priv->clk);
 175                 do_div(freq, psc);
 176                 do_div(freq, arr);
 177         }
 178
 179         return sprintf(buf, "%d\n", (unsigned int)freq);
 180 }
 181
 182 static IIO_DEV_ATTR_SAMP_FREQ(0660,
 183                               stm32_tt_read_frequency,
 184                               stm32_tt_store_frequency);
 185
 186 static char *master_mode_table[] = {
 187         "reset",
 188         "enable",
 189         "update",
 190         "compare_pulse",
 191         "OC1REF",
 192         "OC2REF",
 193         "OC3REF",
 194         "OC4REF"
 195 };
 196
 197 static ssize_t stm32_tt_show_master_mode(struct device *dev,
 198                                          struct device_attribute *attr,
 199                                          char *buf)
 200 {
 201         struct stm32_timer_trigger *priv = dev_get_drvdata(dev);
 202         u32 cr2;
 203
 204         regmap_read(priv->regmap, TIM_CR2, &cr2);
 205         cr2 = (cr2 & TIM_CR2_MMS) >> TIM_CR2_MMS_SHIFT;
 206
 207         return snprintf(buf, PAGE_SIZE, "%s\n", master_mode_table[cr2]);
 208 }
 209
 210 static ssize_t stm32_tt_store_master_mode(struct device *dev,
 211                                           struct device_attribute *attr,
 212                                           const char *buf, size_t len)
 213 {
 214         struct stm32_timer_trigger *priv = dev_get_drvdata(dev);
 215         int i;
 216
 217         for (i = 0; i < ARRAY_SIZE(master_mode_table); i++) {
 218                 if (!strncmp(master_mode_table[i], buf,
 219                              strlen(master_mode_table[i]))) {
 220                         regmap_update_bits(priv->regmap, TIM_CR2,
 221                                            TIM_CR2_MMS, i << TIM_CR2_MMS_SHIFT);
 222                         /* Make sure that registers are updated */
 223                         regmap_update_bits(priv->regmap, TIM_EGR,
 224                                            TIM_EGR_UG, TIM_EGR_UG);
 225                         return len;
 226                 }
 227         }
 228
 229         return -EINVAL;
 230 }
 231
 232 static IIO_CONST_ATTR(master_mode_available,
 233         "reset enable update compare_pulse OC1REF OC2REF OC3REF OC4REF");
 234
 235 static IIO_DEVICE_ATTR(master_mode, 0660,
 236                        stm32_tt_show_master_mode,
 237                        stm32_tt_store_master_mode,
 238                        0);
 239
 240 static struct attribute *stm32_trigger_attrs[] = {
 241         &iio_dev_attr_sampling_frequency.dev_attr.attr,
 242         &iio_dev_attr_master_mode.dev_attr.attr,
 243         &iio_const_attr_master_mode_available.dev_attr.attr,
 244         NULL,
 245 };
 246
 247 static const struct attribute_group stm32_trigger_attr_group = {
 248         .attrs = stm32_trigger_attrs,
 249 };
 250
 251 static const struct attribute_group *stm32_trigger_attr_groups[] = {
 252         &stm32_trigger_attr_group,
 253         NULL,
 254 };
 255
 256 static const struct iio_trigger_ops timer_trigger_ops = {
 257         .owner = THIS_MODULE,
 258 };
 259
 260 static int stm32_setup_iio_triggers(struct stm32_timer_trigger *priv)
 261 {
 262         int ret;
 263         const char * const *cur = priv->triggers;
 264
 265         while (cur && *cur) {
 266                 struct iio_trigger *trig;
 267
 268                 trig = devm_iio_trigger_alloc(priv->dev, "%s", *cur);
 269                 if  (!trig)
 270                         return -ENOMEM;
 271
 272                 trig->dev.parent = priv->dev->parent;
 273                 trig->ops = &timer_trigger_ops;
 274
 275                 /*
 276                  * sampling frequency and master mode attributes
 277                  * should only be available on trgo trigger which
 278                  * is always the first in the list.
 279                  */
 280                 if (cur == priv->triggers)
 281                         trig->dev.groups = stm32_trigger_attr_groups;
 282
 283                 iio_trigger_set_drvdata(trig, priv);
 284
 285                 ret = devm_iio_trigger_register(priv->dev, trig);
 286                 if (ret)
 287                         return ret;
 288                 cur++;
 289         }
 290
 291         return 0;
 292 }
 293
 294 static int stm32_counter_read_raw(struct iio_dev *indio_dev,
 295                                   struct iio_chan_spec const *chan,
 296                                   int *val, int *val2, long mask)
 297 {
 298         struct stm32_timer_trigger *priv = iio_priv(indio_dev);
 299
 300         switch (mask) {
 301         case IIO_CHAN_INFO_RAW:
 302         {
 303                 u32 cnt;
 304
 305                 regmap_read(priv->regmap, TIM_CNT, &cnt);
 306                 *val = cnt;
 307
 308                 return IIO_VAL_INT;
 309         }
 310         case IIO_CHAN_INFO_SCALE:
 311         {
 312                 u32 smcr;
 313
 314                 regmap_read(priv->regmap, TIM_SMCR, &smcr);
 315                 smcr &= TIM_SMCR_SMS;
 316
 317                 *val = 1;
 318                 *val2 = 0;
 319
 320                 /* in quadrature case scale = 0.25 */
 321                 if (smcr == 3)
 322                         *val2 = 2;
 323
 324                 return IIO_VAL_FRACTIONAL_LOG2;
 325         }
 326         }
 327
 328         return -EINVAL;
 329 }
 330
 331 static int stm32_counter_write_raw(struct iio_dev *indio_dev,
 332                                    struct iio_chan_spec const *chan,
 333                                    int val, int val2, long mask)
 334 {
 335         struct stm32_timer_trigger *priv = iio_priv(indio_dev);
 336
 337         switch (mask) {
 338         case IIO_CHAN_INFO_RAW:
 339                 regmap_write(priv->regmap, TIM_CNT, val);
 340
 341                 return IIO_VAL_INT;
 342         case IIO_CHAN_INFO_SCALE:
 343                 /* fixed scale */
 344                 return -EINVAL;
 345         }
 346
 347         return -EINVAL;
 348 }
 349
 350 static const struct iio_info stm32_trigger_info = {
 351         .driver_module = THIS_MODULE,
 352         .read_raw = stm32_counter_read_raw,
 353         .write_raw = stm32_counter_write_raw
 354 };
 355
 356 static const char *const stm32_quadrature_modes[] = {
 357         "channel_A",
 358         "channel_B",
 359         "quadrature",
 360 };
 361
 362 static int stm32_set_quadrature_mode(struct iio_dev *indio_dev,
 363                                      const struct iio_chan_spec *chan,
 364                                      unsigned int mode)
 365 {
 366         struct stm32_timer_trigger *priv = iio_priv(indio_dev);
 367
 368         regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, mode + 1);
 369
 370         return 0;
 371 }
 372
 373 static int stm32_get_quadrature_mode(struct iio_dev *indio_dev,
 374                                      const struct iio_chan_spec *chan)
 375 {
 376         struct stm32_timer_trigger *priv = iio_priv(indio_dev);
 377         u32 smcr;
 378
 379         regmap_read(priv->regmap, TIM_SMCR, &smcr);
 380         smcr &= TIM_SMCR_SMS;
 381
 382         return smcr - 1;
 383 }
 384
 385 static const struct iio_enum stm32_quadrature_mode_enum = {
 386         .items = stm32_quadrature_modes,
 387         .num_items = ARRAY_SIZE(stm32_quadrature_modes),
 388         .set = stm32_set_quadrature_mode,
 389         .get = stm32_get_quadrature_mode
 390 };
 391
 392 static const char *const stm32_count_direction_states[] = {
 393         "up",
 394         "down"
 395 };
 396
 397 static int stm32_set_count_direction(struct iio_dev *indio_dev,
 398                                      const struct iio_chan_spec *chan,
 399                                      unsigned int mode)
 400 {
 401         struct stm32_timer_trigger *priv = iio_priv(indio_dev);
 402
 403         regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_DIR, mode);
 404
 405         return 0;
 406 }
 407
 408 static int stm32_get_count_direction(struct iio_dev *indio_dev,
 409                                      const struct iio_chan_spec *chan)
 410 {
 411         struct stm32_timer_trigger *priv = iio_priv(indio_dev);
 412         u32 cr1;
 413
 414         regmap_read(priv->regmap, TIM_CR1, &cr1);
 415
 416         return (cr1 & TIM_CR1_DIR);
 417 }
 418
 419 static const struct iio_enum stm32_count_direction_enum = {
 420         .items = stm32_count_direction_states,
 421         .num_items = ARRAY_SIZE(stm32_count_direction_states),
 422         .set = stm32_set_count_direction,
 423         .get = stm32_get_count_direction
 424 };
 425
 426 static ssize_t stm32_count_get_preset(struct iio_dev *indio_dev,
 427                                       uintptr_t private,
 428                                       const struct iio_chan_spec *chan,
 429                                       char *buf)
 430 {
 431         struct stm32_timer_trigger *priv = iio_priv(indio_dev);
 432         u32 arr;
 433
 434         regmap_read(priv->regmap, TIM_ARR, &arr);
 435
 436         return snprintf(buf, PAGE_SIZE, "%u\n", arr);
 437 }
 438
 439 static ssize_t stm32_count_set_preset(struct iio_dev *indio_dev,
 440                                       uintptr_t private,
 441                                       const struct iio_chan_spec *chan,
 442                                       const char *buf, size_t len)
 443 {
 444         struct stm32_timer_trigger *priv = iio_priv(indio_dev);
 445         unsigned int preset;
 446         int ret;
 447
 448         ret = kstrtouint(buf, 0, &preset);
 449         if (ret)
 450                 return ret;
 451
 452         regmap_write(priv->regmap, TIM_ARR, preset);
 453         regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);
 454
 455         return len;
 456 }
 457
 458 static const struct iio_chan_spec_ext_info stm32_trigger_count_info[] = {
 459         {
 460                 .name = "preset",
 461                 .shared = IIO_SEPARATE,
 462                 .read = stm32_count_get_preset,
 463                 .write = stm32_count_set_preset
 464         },
 465         IIO_ENUM("count_direction", IIO_SEPARATE, &stm32_count_direction_enum),
 466         IIO_ENUM_AVAILABLE("count_direction", &stm32_count_direction_enum),
 467         IIO_ENUM("quadrature_mode", IIO_SEPARATE, &stm32_quadrature_mode_enum),
 468         IIO_ENUM_AVAILABLE("quadrature_mode", &stm32_quadrature_mode_enum),
 469         {}
 470 };
 471
 472 static const struct iio_chan_spec stm32_trigger_channel = {
 473         .type = IIO_COUNT,
 474         .channel = 0,
 475         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
 476         .ext_info = stm32_trigger_count_info,
 477         .indexed = 1
 478 };
 479
 480 static struct stm32_timer_trigger *stm32_setup_counter_device(struct device *dev)
 481 {
 482         struct iio_dev *indio_dev;
 483         int ret;
 484
 485         indio_dev = devm_iio_device_alloc(dev,
 486                                           sizeof(struct stm32_timer_trigger));
 487         if (!indio_dev)
 488                 return NULL;
 489
 490         indio_dev->name = dev_name(dev);
 491         indio_dev->dev.parent = dev;
 492         indio_dev->info = &stm32_trigger_info;
 493         indio_dev->num_channels = 1;
 494         indio_dev->channels = &stm32_trigger_channel;
 495         indio_dev->dev.of_node = dev->of_node;
 496
 497         ret = devm_iio_device_register(dev, indio_dev);
 498         if (ret)
 499                 return NULL;
 500
 501         return iio_priv(indio_dev);
 502 }
 503
 504 /**
 505  * is_stm32_timer_trigger
 506  * @trig: trigger to be checked
 507  *
 508  * return true if the trigger is a valid stm32 iio timer trigger
 509  * either return false
 510  */
 511 bool is_stm32_timer_trigger(struct iio_trigger *trig)
 512 {
 513         return (trig->ops == &timer_trigger_ops);
 514 }
 515 EXPORT_SYMBOL(is_stm32_timer_trigger);
 516
 517 static int stm32_timer_trigger_probe(struct platform_device *pdev)
 518 {
 519         struct device *dev = &pdev->dev;
 520         struct stm32_timer_trigger *priv;
 521         struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
 522         unsigned int index;
 523         int ret;
 524
 525         if (of_property_read_u32(dev->of_node, "reg", &index))
 526                 return -EINVAL;
 527
 528         if (index >= ARRAY_SIZE(triggers_table) ||
 529             index >= ARRAY_SIZE(valids_table))
 530                 return -EINVAL;
 531
 532         /* Create an IIO device only if we have triggers to be validated */
 533         if (*valids_table[index])
 534                 priv = stm32_setup_counter_device(dev);
 535         else
 536                 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 537
 538         if (!priv)
 539                 return -ENOMEM;
 540
 541         priv->dev = dev;
 542         priv->regmap = ddata->regmap;
 543         priv->clk = ddata->clk;
 544         priv->max_arr = ddata->max_arr;
 545         priv->triggers = triggers_table[index];
 546         priv->valids = valids_table[index];
 547
 548         ret = stm32_setup_iio_triggers(priv);
 549         if (ret)
 550                 return ret;
 551
 552         platform_set_drvdata(pdev, priv);
 553
 554         return 0;
 555 }
 556
 557 static const struct of_device_id stm32_trig_of_match[] = {
 558         { .compatible = "st,stm32-timer-trigger", },
 559         { /* end node */ },
 560 };
 561 MODULE_DEVICE_TABLE(of, stm32_trig_of_match);
 562
 563 static struct platform_driver stm32_timer_trigger_driver = {
 564         .probe = stm32_timer_trigger_probe,
 565         .driver = {
 566                 .name = "stm32-timer-trigger",
 567                 .of_match_table = stm32_trig_of_match,
 568         },
 569 };
 570 module_platform_driver(stm32_timer_trigger_driver);
 571
 572 MODULE_ALIAS("platform: stm32-timer-trigger");
 573 MODULE_DESCRIPTION("STMicroelectronics STM32 Timer Trigger driver");
 574 MODULE_LICENSE("GPL v2");