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IB/bnxt_re: Fix frame stack compilation warning
[mirror_ubuntu-bionic-kernel.git] / drivers / infiniband / hw / bnxt_re / ib_verbs.c
1 /*
2 * Broadcom NetXtreme-E RoCE driver.
3 *
4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
5 * Broadcom refers to Broadcom Limited and/or its subsidiaries.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 *
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the
22 * distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 *
36 * Description: IB Verbs interpreter
37 */
38
39 #include <linux/interrupt.h>
40 #include <linux/types.h>
41 #include <linux/pci.h>
42 #include <linux/netdevice.h>
43 #include <linux/if_ether.h>
44
45 #include <rdma/ib_verbs.h>
46 #include <rdma/ib_user_verbs.h>
47 #include <rdma/ib_umem.h>
48 #include <rdma/ib_addr.h>
49 #include <rdma/ib_mad.h>
50 #include <rdma/ib_cache.h>
51
52 #include "bnxt_ulp.h"
53
54 #include "roce_hsi.h"
55 #include "qplib_res.h"
56 #include "qplib_sp.h"
57 #include "qplib_fp.h"
58 #include "qplib_rcfw.h"
59
60 #include "bnxt_re.h"
61 #include "ib_verbs.h"
62 #include <rdma/bnxt_re-abi.h>
63
64 static int __from_ib_access_flags(int iflags)
65 {
66 int qflags = 0;
67
68 if (iflags & IB_ACCESS_LOCAL_WRITE)
69 qflags |= BNXT_QPLIB_ACCESS_LOCAL_WRITE;
70 if (iflags & IB_ACCESS_REMOTE_READ)
71 qflags |= BNXT_QPLIB_ACCESS_REMOTE_READ;
72 if (iflags & IB_ACCESS_REMOTE_WRITE)
73 qflags |= BNXT_QPLIB_ACCESS_REMOTE_WRITE;
74 if (iflags & IB_ACCESS_REMOTE_ATOMIC)
75 qflags |= BNXT_QPLIB_ACCESS_REMOTE_ATOMIC;
76 if (iflags & IB_ACCESS_MW_BIND)
77 qflags |= BNXT_QPLIB_ACCESS_MW_BIND;
78 if (iflags & IB_ZERO_BASED)
79 qflags |= BNXT_QPLIB_ACCESS_ZERO_BASED;
80 if (iflags & IB_ACCESS_ON_DEMAND)
81 qflags |= BNXT_QPLIB_ACCESS_ON_DEMAND;
82 return qflags;
83 };
84
85 static enum ib_access_flags __to_ib_access_flags(int qflags)
86 {
87 enum ib_access_flags iflags = 0;
88
89 if (qflags & BNXT_QPLIB_ACCESS_LOCAL_WRITE)
90 iflags |= IB_ACCESS_LOCAL_WRITE;
91 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_WRITE)
92 iflags |= IB_ACCESS_REMOTE_WRITE;
93 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_READ)
94 iflags |= IB_ACCESS_REMOTE_READ;
95 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_ATOMIC)
96 iflags |= IB_ACCESS_REMOTE_ATOMIC;
97 if (qflags & BNXT_QPLIB_ACCESS_MW_BIND)
98 iflags |= IB_ACCESS_MW_BIND;
99 if (qflags & BNXT_QPLIB_ACCESS_ZERO_BASED)
100 iflags |= IB_ZERO_BASED;
101 if (qflags & BNXT_QPLIB_ACCESS_ON_DEMAND)
102 iflags |= IB_ACCESS_ON_DEMAND;
103 return iflags;
104 };
105
106 static int bnxt_re_build_sgl(struct ib_sge *ib_sg_list,
107 struct bnxt_qplib_sge *sg_list, int num)
108 {
109 int i, total = 0;
110
111 for (i = 0; i < num; i++) {
112 sg_list[i].addr = ib_sg_list[i].addr;
113 sg_list[i].lkey = ib_sg_list[i].lkey;
114 sg_list[i].size = ib_sg_list[i].length;
115 total += sg_list[i].size;
116 }
117 return total;
118 }
119
120 /* Device */
121 struct net_device *bnxt_re_get_netdev(struct ib_device *ibdev, u8 port_num)
122 {
123 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
124 struct net_device *netdev = NULL;
125
126 rcu_read_lock();
127 if (rdev)
128 netdev = rdev->netdev;
129 if (netdev)
130 dev_hold(netdev);
131
132 rcu_read_unlock();
133 return netdev;
134 }
135
136 int bnxt_re_query_device(struct ib_device *ibdev,
137 struct ib_device_attr *ib_attr,
138 struct ib_udata *udata)
139 {
140 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
141 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
142
143 memset(ib_attr, 0, sizeof(*ib_attr));
144
145 ib_attr->fw_ver = (u64)(unsigned long)(dev_attr->fw_ver);
146 bnxt_qplib_get_guid(rdev->netdev->dev_addr,
147 (u8 *)&ib_attr->sys_image_guid);
148 ib_attr->max_mr_size = BNXT_RE_MAX_MR_SIZE;
149 ib_attr->page_size_cap = BNXT_RE_PAGE_SIZE_4K;
150
151 ib_attr->vendor_id = rdev->en_dev->pdev->vendor;
152 ib_attr->vendor_part_id = rdev->en_dev->pdev->device;
153 ib_attr->hw_ver = rdev->en_dev->pdev->subsystem_device;
154 ib_attr->max_qp = dev_attr->max_qp;
155 ib_attr->max_qp_wr = dev_attr->max_qp_wqes;
156 ib_attr->device_cap_flags =
157 IB_DEVICE_CURR_QP_STATE_MOD
158 | IB_DEVICE_RC_RNR_NAK_GEN
159 | IB_DEVICE_SHUTDOWN_PORT
160 | IB_DEVICE_SYS_IMAGE_GUID
161 | IB_DEVICE_LOCAL_DMA_LKEY
162 | IB_DEVICE_RESIZE_MAX_WR
163 | IB_DEVICE_PORT_ACTIVE_EVENT
164 | IB_DEVICE_N_NOTIFY_CQ
165 | IB_DEVICE_MEM_WINDOW
166 | IB_DEVICE_MEM_WINDOW_TYPE_2B
167 | IB_DEVICE_MEM_MGT_EXTENSIONS;
168 ib_attr->max_sge = dev_attr->max_qp_sges;
169 ib_attr->max_sge_rd = dev_attr->max_qp_sges;
170 ib_attr->max_cq = dev_attr->max_cq;
171 ib_attr->max_cqe = dev_attr->max_cq_wqes;
172 ib_attr->max_mr = dev_attr->max_mr;
173 ib_attr->max_pd = dev_attr->max_pd;
174 ib_attr->max_qp_rd_atom = dev_attr->max_qp_rd_atom;
175 ib_attr->max_qp_init_rd_atom = dev_attr->max_qp_init_rd_atom;
176 if (dev_attr->is_atomic) {
177 ib_attr->atomic_cap = IB_ATOMIC_HCA;
178 ib_attr->masked_atomic_cap = IB_ATOMIC_HCA;
179 }
180
181 ib_attr->max_ee_rd_atom = 0;
182 ib_attr->max_res_rd_atom = 0;
183 ib_attr->max_ee_init_rd_atom = 0;
184 ib_attr->max_ee = 0;
185 ib_attr->max_rdd = 0;
186 ib_attr->max_mw = dev_attr->max_mw;
187 ib_attr->max_raw_ipv6_qp = 0;
188 ib_attr->max_raw_ethy_qp = dev_attr->max_raw_ethy_qp;
189 ib_attr->max_mcast_grp = 0;
190 ib_attr->max_mcast_qp_attach = 0;
191 ib_attr->max_total_mcast_qp_attach = 0;
192 ib_attr->max_ah = dev_attr->max_ah;
193
194 ib_attr->max_fmr = 0;
195 ib_attr->max_map_per_fmr = 0;
196
197 ib_attr->max_srq = dev_attr->max_srq;
198 ib_attr->max_srq_wr = dev_attr->max_srq_wqes;
199 ib_attr->max_srq_sge = dev_attr->max_srq_sges;
200
201 ib_attr->max_fast_reg_page_list_len = MAX_PBL_LVL_1_PGS;
202
203 ib_attr->max_pkeys = 1;
204 ib_attr->local_ca_ack_delay = BNXT_RE_DEFAULT_ACK_DELAY;
205 return 0;
206 }
207
208 int bnxt_re_modify_device(struct ib_device *ibdev,
209 int device_modify_mask,
210 struct ib_device_modify *device_modify)
211 {
212 switch (device_modify_mask) {
213 case IB_DEVICE_MODIFY_SYS_IMAGE_GUID:
214 /* Modify the GUID requires the modification of the GID table */
215 /* GUID should be made as READ-ONLY */
216 break;
217 case IB_DEVICE_MODIFY_NODE_DESC:
218 /* Node Desc should be made as READ-ONLY */
219 break;
220 default:
221 break;
222 }
223 return 0;
224 }
225
226 /* Port */
227 int bnxt_re_query_port(struct ib_device *ibdev, u8 port_num,
228 struct ib_port_attr *port_attr)
229 {
230 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
231 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
232
233 memset(port_attr, 0, sizeof(*port_attr));
234
235 if (netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev)) {
236 port_attr->state = IB_PORT_ACTIVE;
237 port_attr->phys_state = 5;
238 } else {
239 port_attr->state = IB_PORT_DOWN;
240 port_attr->phys_state = 3;
241 }
242 port_attr->max_mtu = IB_MTU_4096;
243 port_attr->active_mtu = iboe_get_mtu(rdev->netdev->mtu);
244 port_attr->gid_tbl_len = dev_attr->max_sgid;
245 port_attr->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
246 IB_PORT_DEVICE_MGMT_SUP |
247 IB_PORT_VENDOR_CLASS_SUP |
248 IB_PORT_IP_BASED_GIDS;
249
250 /* Max MSG size set to 2G for now */
251 port_attr->max_msg_sz = 0x80000000;
252 port_attr->bad_pkey_cntr = 0;
253 port_attr->qkey_viol_cntr = 0;
254 port_attr->pkey_tbl_len = dev_attr->max_pkey;
255 port_attr->lid = 0;
256 port_attr->sm_lid = 0;
257 port_attr->lmc = 0;
258 port_attr->max_vl_num = 4;
259 port_attr->sm_sl = 0;
260 port_attr->subnet_timeout = 0;
261 port_attr->init_type_reply = 0;
262 /* call the underlying netdev's ethtool hooks to query speed settings
263 * for which we acquire rtnl_lock _only_ if it's registered with
264 * IB stack to avoid race in the NETDEV_UNREG path
265 */
266 if (test_bit(BNXT_RE_FLAG_IBDEV_REGISTERED, &rdev->flags))
267 if (ib_get_eth_speed(ibdev, port_num, &port_attr->active_speed,
268 &port_attr->active_width))
269 return -EINVAL;
270 return 0;
271 }
272
273 int bnxt_re_get_port_immutable(struct ib_device *ibdev, u8 port_num,
274 struct ib_port_immutable *immutable)
275 {
276 struct ib_port_attr port_attr;
277
278 if (bnxt_re_query_port(ibdev, port_num, &port_attr))
279 return -EINVAL;
280
281 immutable->pkey_tbl_len = port_attr.pkey_tbl_len;
282 immutable->gid_tbl_len = port_attr.gid_tbl_len;
283 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
284 immutable->core_cap_flags |= RDMA_CORE_CAP_PROT_ROCE_UDP_ENCAP;
285 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
286 return 0;
287 }
288
289 int bnxt_re_query_pkey(struct ib_device *ibdev, u8 port_num,
290 u16 index, u16 *pkey)
291 {
292 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
293
294 /* Ignore port_num */
295
296 memset(pkey, 0, sizeof(*pkey));
297 return bnxt_qplib_get_pkey(&rdev->qplib_res,
298 &rdev->qplib_res.pkey_tbl, index, pkey);
299 }
300
301 int bnxt_re_query_gid(struct ib_device *ibdev, u8 port_num,
302 int index, union ib_gid *gid)
303 {
304 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
305 int rc = 0;
306
307 /* Ignore port_num */
308 memset(gid, 0, sizeof(*gid));
309 rc = bnxt_qplib_get_sgid(&rdev->qplib_res,
310 &rdev->qplib_res.sgid_tbl, index,
311 (struct bnxt_qplib_gid *)gid);
312 return rc;
313 }
314
315 int bnxt_re_del_gid(struct ib_device *ibdev, u8 port_num,
316 unsigned int index, void **context)
317 {
318 int rc = 0;
319 struct bnxt_re_gid_ctx *ctx, **ctx_tbl;
320 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
321 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
322
323 /* Delete the entry from the hardware */
324 ctx = *context;
325 if (!ctx)
326 return -EINVAL;
327
328 if (sgid_tbl && sgid_tbl->active) {
329 if (ctx->idx >= sgid_tbl->max)
330 return -EINVAL;
331 ctx->refcnt--;
332 if (!ctx->refcnt) {
333 rc = bnxt_qplib_del_sgid(sgid_tbl,
334 &sgid_tbl->tbl[ctx->idx],
335 true);
336 if (rc) {
337 dev_err(rdev_to_dev(rdev),
338 "Failed to remove GID: %#x", rc);
339 } else {
340 ctx_tbl = sgid_tbl->ctx;
341 ctx_tbl[ctx->idx] = NULL;
342 kfree(ctx);
343 }
344 }
345 } else {
346 return -EINVAL;
347 }
348 return rc;
349 }
350
351 int bnxt_re_add_gid(struct ib_device *ibdev, u8 port_num,
352 unsigned int index, const union ib_gid *gid,
353 const struct ib_gid_attr *attr, void **context)
354 {
355 int rc;
356 u32 tbl_idx = 0;
357 u16 vlan_id = 0xFFFF;
358 struct bnxt_re_gid_ctx *ctx, **ctx_tbl;
359 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
360 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
361
362 if ((attr->ndev) && is_vlan_dev(attr->ndev))
363 vlan_id = vlan_dev_vlan_id(attr->ndev);
364
365 rc = bnxt_qplib_add_sgid(sgid_tbl, (struct bnxt_qplib_gid *)gid,
366 rdev->qplib_res.netdev->dev_addr,
367 vlan_id, true, &tbl_idx);
368 if (rc == -EALREADY) {
369 ctx_tbl = sgid_tbl->ctx;
370 ctx_tbl[tbl_idx]->refcnt++;
371 *context = ctx_tbl[tbl_idx];
372 return 0;
373 }
374
375 if (rc < 0) {
376 dev_err(rdev_to_dev(rdev), "Failed to add GID: %#x", rc);
377 return rc;
378 }
379
380 ctx = kmalloc(sizeof(*ctx), GFP_KERNEL);
381 if (!ctx)
382 return -ENOMEM;
383 ctx_tbl = sgid_tbl->ctx;
384 ctx->idx = tbl_idx;
385 ctx->refcnt = 1;
386 ctx_tbl[tbl_idx] = ctx;
387
388 return rc;
389 }
390
391 enum rdma_link_layer bnxt_re_get_link_layer(struct ib_device *ibdev,
392 u8 port_num)
393 {
394 return IB_LINK_LAYER_ETHERNET;
395 }
396
397 #define BNXT_RE_FENCE_PBL_SIZE DIV_ROUND_UP(BNXT_RE_FENCE_BYTES, PAGE_SIZE)
398
399 static void bnxt_re_create_fence_wqe(struct bnxt_re_pd *pd)
400 {
401 struct bnxt_re_fence_data *fence = &pd->fence;
402 struct ib_mr *ib_mr = &fence->mr->ib_mr;
403 struct bnxt_qplib_swqe *wqe = &fence->bind_wqe;
404
405 memset(wqe, 0, sizeof(*wqe));
406 wqe->type = BNXT_QPLIB_SWQE_TYPE_BIND_MW;
407 wqe->wr_id = BNXT_QPLIB_FENCE_WRID;
408 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
409 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
410 wqe->bind.zero_based = false;
411 wqe->bind.parent_l_key = ib_mr->lkey;
412 wqe->bind.va = (u64)(unsigned long)fence->va;
413 wqe->bind.length = fence->size;
414 wqe->bind.access_cntl = __from_ib_access_flags(IB_ACCESS_REMOTE_READ);
415 wqe->bind.mw_type = SQ_BIND_MW_TYPE_TYPE1;
416
417 /* Save the initial rkey in fence structure for now;
418 * wqe->bind.r_key will be set at (re)bind time.
419 */
420 fence->bind_rkey = ib_inc_rkey(fence->mw->rkey);
421 }
422
423 static int bnxt_re_bind_fence_mw(struct bnxt_qplib_qp *qplib_qp)
424 {
425 struct bnxt_re_qp *qp = container_of(qplib_qp, struct bnxt_re_qp,
426 qplib_qp);
427 struct ib_pd *ib_pd = qp->ib_qp.pd;
428 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
429 struct bnxt_re_fence_data *fence = &pd->fence;
430 struct bnxt_qplib_swqe *fence_wqe = &fence->bind_wqe;
431 struct bnxt_qplib_swqe wqe;
432 int rc;
433
434 memcpy(&wqe, fence_wqe, sizeof(wqe));
435 wqe.bind.r_key = fence->bind_rkey;
436 fence->bind_rkey = ib_inc_rkey(fence->bind_rkey);
437
438 dev_dbg(rdev_to_dev(qp->rdev),
439 "Posting bind fence-WQE: rkey: %#x QP: %d PD: %p\n",
440 wqe.bind.r_key, qp->qplib_qp.id, pd);
441 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
442 if (rc) {
443 dev_err(rdev_to_dev(qp->rdev), "Failed to bind fence-WQE\n");
444 return rc;
445 }
446 bnxt_qplib_post_send_db(&qp->qplib_qp);
447
448 return rc;
449 }
450
451 static void bnxt_re_destroy_fence_mr(struct bnxt_re_pd *pd)
452 {
453 struct bnxt_re_fence_data *fence = &pd->fence;
454 struct bnxt_re_dev *rdev = pd->rdev;
455 struct device *dev = &rdev->en_dev->pdev->dev;
456 struct bnxt_re_mr *mr = fence->mr;
457
458 if (fence->mw) {
459 bnxt_re_dealloc_mw(fence->mw);
460 fence->mw = NULL;
461 }
462 if (mr) {
463 if (mr->ib_mr.rkey)
464 bnxt_qplib_dereg_mrw(&rdev->qplib_res, &mr->qplib_mr,
465 true);
466 if (mr->ib_mr.lkey)
467 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
468 kfree(mr);
469 fence->mr = NULL;
470 }
471 if (fence->dma_addr) {
472 dma_unmap_single(dev, fence->dma_addr, BNXT_RE_FENCE_BYTES,
473 DMA_BIDIRECTIONAL);
474 fence->dma_addr = 0;
475 }
476 }
477
478 static int bnxt_re_create_fence_mr(struct bnxt_re_pd *pd)
479 {
480 int mr_access_flags = IB_ACCESS_LOCAL_WRITE | IB_ACCESS_MW_BIND;
481 struct bnxt_re_fence_data *fence = &pd->fence;
482 struct bnxt_re_dev *rdev = pd->rdev;
483 struct device *dev = &rdev->en_dev->pdev->dev;
484 struct bnxt_re_mr *mr = NULL;
485 dma_addr_t dma_addr = 0;
486 struct ib_mw *mw;
487 u64 pbl_tbl;
488 int rc;
489
490 dma_addr = dma_map_single(dev, fence->va, BNXT_RE_FENCE_BYTES,
491 DMA_BIDIRECTIONAL);
492 rc = dma_mapping_error(dev, dma_addr);
493 if (rc) {
494 dev_err(rdev_to_dev(rdev), "Failed to dma-map fence-MR-mem\n");
495 rc = -EIO;
496 fence->dma_addr = 0;
497 goto fail;
498 }
499 fence->dma_addr = dma_addr;
500
501 /* Allocate a MR */
502 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
503 if (!mr) {
504 rc = -ENOMEM;
505 goto fail;
506 }
507 fence->mr = mr;
508 mr->rdev = rdev;
509 mr->qplib_mr.pd = &pd->qplib_pd;
510 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
511 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags);
512 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
513 if (rc) {
514 dev_err(rdev_to_dev(rdev), "Failed to alloc fence-HW-MR\n");
515 goto fail;
516 }
517
518 /* Register MR */
519 mr->ib_mr.lkey = mr->qplib_mr.lkey;
520 mr->qplib_mr.va = (u64)(unsigned long)fence->va;
521 mr->qplib_mr.total_size = BNXT_RE_FENCE_BYTES;
522 pbl_tbl = dma_addr;
523 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, &pbl_tbl,
524 BNXT_RE_FENCE_PBL_SIZE, false);
525 if (rc) {
526 dev_err(rdev_to_dev(rdev), "Failed to register fence-MR\n");
527 goto fail;
528 }
529 mr->ib_mr.rkey = mr->qplib_mr.rkey;
530
531 /* Create a fence MW only for kernel consumers */
532 mw = bnxt_re_alloc_mw(&pd->ib_pd, IB_MW_TYPE_1, NULL);
533 if (IS_ERR(mw)) {
534 dev_err(rdev_to_dev(rdev),
535 "Failed to create fence-MW for PD: %p\n", pd);
536 rc = PTR_ERR(mw);
537 goto fail;
538 }
539 fence->mw = mw;
540
541 bnxt_re_create_fence_wqe(pd);
542 return 0;
543
544 fail:
545 bnxt_re_destroy_fence_mr(pd);
546 return rc;
547 }
548
549 /* Protection Domains */
550 int bnxt_re_dealloc_pd(struct ib_pd *ib_pd)
551 {
552 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
553 struct bnxt_re_dev *rdev = pd->rdev;
554 int rc;
555
556 bnxt_re_destroy_fence_mr(pd);
557
558 if (pd->qplib_pd.id) {
559 rc = bnxt_qplib_dealloc_pd(&rdev->qplib_res,
560 &rdev->qplib_res.pd_tbl,
561 &pd->qplib_pd);
562 if (rc)
563 dev_err(rdev_to_dev(rdev), "Failed to deallocate HW PD");
564 }
565
566 kfree(pd);
567 return 0;
568 }
569
570 struct ib_pd *bnxt_re_alloc_pd(struct ib_device *ibdev,
571 struct ib_ucontext *ucontext,
572 struct ib_udata *udata)
573 {
574 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
575 struct bnxt_re_ucontext *ucntx = container_of(ucontext,
576 struct bnxt_re_ucontext,
577 ib_uctx);
578 struct bnxt_re_pd *pd;
579 int rc;
580
581 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
582 if (!pd)
583 return ERR_PTR(-ENOMEM);
584
585 pd->rdev = rdev;
586 if (bnxt_qplib_alloc_pd(&rdev->qplib_res.pd_tbl, &pd->qplib_pd)) {
587 dev_err(rdev_to_dev(rdev), "Failed to allocate HW PD");
588 rc = -ENOMEM;
589 goto fail;
590 }
591
592 if (udata) {
593 struct bnxt_re_pd_resp resp;
594
595 if (!ucntx->dpi.dbr) {
596 /* Allocate DPI in alloc_pd to avoid failing of
597 * ibv_devinfo and family of application when DPIs
598 * are depleted.
599 */
600 if (bnxt_qplib_alloc_dpi(&rdev->qplib_res.dpi_tbl,
601 &ucntx->dpi, ucntx)) {
602 rc = -ENOMEM;
603 goto dbfail;
604 }
605 }
606
607 resp.pdid = pd->qplib_pd.id;
608 /* Still allow mapping this DBR to the new user PD. */
609 resp.dpi = ucntx->dpi.dpi;
610 resp.dbr = (u64)ucntx->dpi.umdbr;
611
612 rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
613 if (rc) {
614 dev_err(rdev_to_dev(rdev),
615 "Failed to copy user response\n");
616 goto dbfail;
617 }
618 }
619
620 if (!udata)
621 if (bnxt_re_create_fence_mr(pd))
622 dev_warn(rdev_to_dev(rdev),
623 "Failed to create Fence-MR\n");
624 return &pd->ib_pd;
625 dbfail:
626 (void)bnxt_qplib_dealloc_pd(&rdev->qplib_res, &rdev->qplib_res.pd_tbl,
627 &pd->qplib_pd);
628 fail:
629 kfree(pd);
630 return ERR_PTR(rc);
631 }
632
633 /* Address Handles */
634 int bnxt_re_destroy_ah(struct ib_ah *ib_ah)
635 {
636 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
637 struct bnxt_re_dev *rdev = ah->rdev;
638 int rc;
639
640 rc = bnxt_qplib_destroy_ah(&rdev->qplib_res, &ah->qplib_ah);
641 if (rc) {
642 dev_err(rdev_to_dev(rdev), "Failed to destroy HW AH");
643 return rc;
644 }
645 kfree(ah);
646 return 0;
647 }
648
649 struct ib_ah *bnxt_re_create_ah(struct ib_pd *ib_pd,
650 struct rdma_ah_attr *ah_attr,
651 struct ib_udata *udata)
652 {
653 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
654 struct bnxt_re_dev *rdev = pd->rdev;
655 struct bnxt_re_ah *ah;
656 const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr);
657 int rc;
658 u16 vlan_tag;
659 u8 nw_type;
660
661 struct ib_gid_attr sgid_attr;
662
663 if (!(rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH)) {
664 dev_err(rdev_to_dev(rdev), "Failed to alloc AH: GRH not set");
665 return ERR_PTR(-EINVAL);
666 }
667 ah = kzalloc(sizeof(*ah), GFP_ATOMIC);
668 if (!ah)
669 return ERR_PTR(-ENOMEM);
670
671 ah->rdev = rdev;
672 ah->qplib_ah.pd = &pd->qplib_pd;
673
674 /* Supply the configuration for the HW */
675 memcpy(ah->qplib_ah.dgid.data, grh->dgid.raw,
676 sizeof(union ib_gid));
677 /*
678 * If RoCE V2 is enabled, stack will have two entries for
679 * each GID entry. Avoiding this duplicte entry in HW. Dividing
680 * the GID index by 2 for RoCE V2
681 */
682 ah->qplib_ah.sgid_index = grh->sgid_index / 2;
683 ah->qplib_ah.host_sgid_index = grh->sgid_index;
684 ah->qplib_ah.traffic_class = grh->traffic_class;
685 ah->qplib_ah.flow_label = grh->flow_label;
686 ah->qplib_ah.hop_limit = grh->hop_limit;
687 ah->qplib_ah.sl = rdma_ah_get_sl(ah_attr);
688 if (ib_pd->uobject &&
689 !rdma_is_multicast_addr((struct in6_addr *)
690 grh->dgid.raw) &&
691 !rdma_link_local_addr((struct in6_addr *)
692 grh->dgid.raw)) {
693 union ib_gid sgid;
694
695 rc = ib_get_cached_gid(&rdev->ibdev, 1,
696 grh->sgid_index, &sgid,
697 &sgid_attr);
698 if (rc) {
699 dev_err(rdev_to_dev(rdev),
700 "Failed to query gid at index %d",
701 grh->sgid_index);
702 goto fail;
703 }
704 if (sgid_attr.ndev) {
705 if (is_vlan_dev(sgid_attr.ndev))
706 vlan_tag = vlan_dev_vlan_id(sgid_attr.ndev);
707 dev_put(sgid_attr.ndev);
708 }
709 /* Get network header type for this GID */
710 nw_type = ib_gid_to_network_type(sgid_attr.gid_type, &sgid);
711 switch (nw_type) {
712 case RDMA_NETWORK_IPV4:
713 ah->qplib_ah.nw_type = CMDQ_CREATE_AH_TYPE_V2IPV4;
714 break;
715 case RDMA_NETWORK_IPV6:
716 ah->qplib_ah.nw_type = CMDQ_CREATE_AH_TYPE_V2IPV6;
717 break;
718 default:
719 ah->qplib_ah.nw_type = CMDQ_CREATE_AH_TYPE_V1;
720 break;
721 }
722 rc = rdma_addr_find_l2_eth_by_grh(&sgid, &grh->dgid,
723 ah_attr->roce.dmac, &vlan_tag,
724 &sgid_attr.ndev->ifindex,
725 NULL);
726 if (rc) {
727 dev_err(rdev_to_dev(rdev), "Failed to get dmac\n");
728 goto fail;
729 }
730 }
731
732 memcpy(ah->qplib_ah.dmac, ah_attr->roce.dmac, ETH_ALEN);
733 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah);
734 if (rc) {
735 dev_err(rdev_to_dev(rdev), "Failed to allocate HW AH");
736 goto fail;
737 }
738
739 /* Write AVID to shared page. */
740 if (ib_pd->uobject) {
741 struct ib_ucontext *ib_uctx = ib_pd->uobject->context;
742 struct bnxt_re_ucontext *uctx;
743 unsigned long flag;
744 u32 *wrptr;
745
746 uctx = container_of(ib_uctx, struct bnxt_re_ucontext, ib_uctx);
747 spin_lock_irqsave(&uctx->sh_lock, flag);
748 wrptr = (u32 *)(uctx->shpg + BNXT_RE_AVID_OFFT);
749 *wrptr = ah->qplib_ah.id;
750 wmb(); /* make sure cache is updated. */
751 spin_unlock_irqrestore(&uctx->sh_lock, flag);
752 }
753
754 return &ah->ib_ah;
755
756 fail:
757 kfree(ah);
758 return ERR_PTR(rc);
759 }
760
761 int bnxt_re_modify_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr)
762 {
763 return 0;
764 }
765
766 int bnxt_re_query_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr)
767 {
768 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
769
770 ah_attr->type = ib_ah->type;
771 rdma_ah_set_sl(ah_attr, ah->qplib_ah.sl);
772 memcpy(ah_attr->roce.dmac, ah->qplib_ah.dmac, ETH_ALEN);
773 rdma_ah_set_grh(ah_attr, NULL, 0,
774 ah->qplib_ah.host_sgid_index,
775 0, ah->qplib_ah.traffic_class);
776 rdma_ah_set_dgid_raw(ah_attr, ah->qplib_ah.dgid.data);
777 rdma_ah_set_port_num(ah_attr, 1);
778 rdma_ah_set_static_rate(ah_attr, 0);
779 return 0;
780 }
781
782 /* Queue Pairs */
783 int bnxt_re_destroy_qp(struct ib_qp *ib_qp)
784 {
785 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
786 struct bnxt_re_dev *rdev = qp->rdev;
787 int rc;
788
789 bnxt_qplib_del_flush_qp(&qp->qplib_qp);
790 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp);
791 if (rc) {
792 dev_err(rdev_to_dev(rdev), "Failed to destroy HW QP");
793 return rc;
794 }
795 if (ib_qp->qp_type == IB_QPT_GSI && rdev->qp1_sqp) {
796 rc = bnxt_qplib_destroy_ah(&rdev->qplib_res,
797 &rdev->sqp_ah->qplib_ah);
798 if (rc) {
799 dev_err(rdev_to_dev(rdev),
800 "Failed to destroy HW AH for shadow QP");
801 return rc;
802 }
803
804 bnxt_qplib_del_flush_qp(&qp->qplib_qp);
805 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res,
806 &rdev->qp1_sqp->qplib_qp);
807 if (rc) {
808 dev_err(rdev_to_dev(rdev),
809 "Failed to destroy Shadow QP");
810 return rc;
811 }
812 mutex_lock(&rdev->qp_lock);
813 list_del(&rdev->qp1_sqp->list);
814 atomic_dec(&rdev->qp_count);
815 mutex_unlock(&rdev->qp_lock);
816
817 kfree(rdev->sqp_ah);
818 kfree(rdev->qp1_sqp);
819 }
820
821 if (!IS_ERR_OR_NULL(qp->rumem))
822 ib_umem_release(qp->rumem);
823 if (!IS_ERR_OR_NULL(qp->sumem))
824 ib_umem_release(qp->sumem);
825
826 mutex_lock(&rdev->qp_lock);
827 list_del(&qp->list);
828 atomic_dec(&rdev->qp_count);
829 mutex_unlock(&rdev->qp_lock);
830 kfree(qp);
831 return 0;
832 }
833
834 static u8 __from_ib_qp_type(enum ib_qp_type type)
835 {
836 switch (type) {
837 case IB_QPT_GSI:
838 return CMDQ_CREATE_QP1_TYPE_GSI;
839 case IB_QPT_RC:
840 return CMDQ_CREATE_QP_TYPE_RC;
841 case IB_QPT_UD:
842 return CMDQ_CREATE_QP_TYPE_UD;
843 default:
844 return IB_QPT_MAX;
845 }
846 }
847
848 static int bnxt_re_init_user_qp(struct bnxt_re_dev *rdev, struct bnxt_re_pd *pd,
849 struct bnxt_re_qp *qp, struct ib_udata *udata)
850 {
851 struct bnxt_re_qp_req ureq;
852 struct bnxt_qplib_qp *qplib_qp = &qp->qplib_qp;
853 struct ib_umem *umem;
854 int bytes = 0;
855 struct ib_ucontext *context = pd->ib_pd.uobject->context;
856 struct bnxt_re_ucontext *cntx = container_of(context,
857 struct bnxt_re_ucontext,
858 ib_uctx);
859 if (ib_copy_from_udata(&ureq, udata, sizeof(ureq)))
860 return -EFAULT;
861
862 bytes = (qplib_qp->sq.max_wqe * BNXT_QPLIB_MAX_SQE_ENTRY_SIZE);
863 /* Consider mapping PSN search memory only for RC QPs. */
864 if (qplib_qp->type == CMDQ_CREATE_QP_TYPE_RC)
865 bytes += (qplib_qp->sq.max_wqe * sizeof(struct sq_psn_search));
866 bytes = PAGE_ALIGN(bytes);
867 umem = ib_umem_get(context, ureq.qpsva, bytes,
868 IB_ACCESS_LOCAL_WRITE, 1);
869 if (IS_ERR(umem))
870 return PTR_ERR(umem);
871
872 qp->sumem = umem;
873 qplib_qp->sq.sglist = umem->sg_head.sgl;
874 qplib_qp->sq.nmap = umem->nmap;
875 qplib_qp->qp_handle = ureq.qp_handle;
876
877 if (!qp->qplib_qp.srq) {
878 bytes = (qplib_qp->rq.max_wqe * BNXT_QPLIB_MAX_RQE_ENTRY_SIZE);
879 bytes = PAGE_ALIGN(bytes);
880 umem = ib_umem_get(context, ureq.qprva, bytes,
881 IB_ACCESS_LOCAL_WRITE, 1);
882 if (IS_ERR(umem))
883 goto rqfail;
884 qp->rumem = umem;
885 qplib_qp->rq.sglist = umem->sg_head.sgl;
886 qplib_qp->rq.nmap = umem->nmap;
887 }
888
889 qplib_qp->dpi = &cntx->dpi;
890 return 0;
891 rqfail:
892 ib_umem_release(qp->sumem);
893 qp->sumem = NULL;
894 qplib_qp->sq.sglist = NULL;
895 qplib_qp->sq.nmap = 0;
896
897 return PTR_ERR(umem);
898 }
899
900 static struct bnxt_re_ah *bnxt_re_create_shadow_qp_ah
901 (struct bnxt_re_pd *pd,
902 struct bnxt_qplib_res *qp1_res,
903 struct bnxt_qplib_qp *qp1_qp)
904 {
905 struct bnxt_re_dev *rdev = pd->rdev;
906 struct bnxt_re_ah *ah;
907 union ib_gid sgid;
908 int rc;
909
910 ah = kzalloc(sizeof(*ah), GFP_KERNEL);
911 if (!ah)
912 return NULL;
913
914 ah->rdev = rdev;
915 ah->qplib_ah.pd = &pd->qplib_pd;
916
917 rc = bnxt_re_query_gid(&rdev->ibdev, 1, 0, &sgid);
918 if (rc)
919 goto fail;
920
921 /* supply the dgid data same as sgid */
922 memcpy(ah->qplib_ah.dgid.data, &sgid.raw,
923 sizeof(union ib_gid));
924 ah->qplib_ah.sgid_index = 0;
925
926 ah->qplib_ah.traffic_class = 0;
927 ah->qplib_ah.flow_label = 0;
928 ah->qplib_ah.hop_limit = 1;
929 ah->qplib_ah.sl = 0;
930 /* Have DMAC same as SMAC */
931 ether_addr_copy(ah->qplib_ah.dmac, rdev->netdev->dev_addr);
932
933 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah);
934 if (rc) {
935 dev_err(rdev_to_dev(rdev),
936 "Failed to allocate HW AH for Shadow QP");
937 goto fail;
938 }
939
940 return ah;
941
942 fail:
943 kfree(ah);
944 return NULL;
945 }
946
947 static struct bnxt_re_qp *bnxt_re_create_shadow_qp
948 (struct bnxt_re_pd *pd,
949 struct bnxt_qplib_res *qp1_res,
950 struct bnxt_qplib_qp *qp1_qp)
951 {
952 struct bnxt_re_dev *rdev = pd->rdev;
953 struct bnxt_re_qp *qp;
954 int rc;
955
956 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
957 if (!qp)
958 return NULL;
959
960 qp->rdev = rdev;
961
962 /* Initialize the shadow QP structure from the QP1 values */
963 ether_addr_copy(qp->qplib_qp.smac, rdev->netdev->dev_addr);
964
965 qp->qplib_qp.pd = &pd->qplib_pd;
966 qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp);
967 qp->qplib_qp.type = IB_QPT_UD;
968
969 qp->qplib_qp.max_inline_data = 0;
970 qp->qplib_qp.sig_type = true;
971
972 /* Shadow QP SQ depth should be same as QP1 RQ depth */
973 qp->qplib_qp.sq.max_wqe = qp1_qp->rq.max_wqe;
974 qp->qplib_qp.sq.max_sge = 2;
975 /* Q full delta can be 1 since it is internal QP */
976 qp->qplib_qp.sq.q_full_delta = 1;
977
978 qp->qplib_qp.scq = qp1_qp->scq;
979 qp->qplib_qp.rcq = qp1_qp->rcq;
980
981 qp->qplib_qp.rq.max_wqe = qp1_qp->rq.max_wqe;
982 qp->qplib_qp.rq.max_sge = qp1_qp->rq.max_sge;
983 /* Q full delta can be 1 since it is internal QP */
984 qp->qplib_qp.rq.q_full_delta = 1;
985
986 qp->qplib_qp.mtu = qp1_qp->mtu;
987
988 qp->qplib_qp.sq_hdr_buf_size = 0;
989 qp->qplib_qp.rq_hdr_buf_size = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6;
990 qp->qplib_qp.dpi = &rdev->dpi_privileged;
991
992 rc = bnxt_qplib_create_qp(qp1_res, &qp->qplib_qp);
993 if (rc)
994 goto fail;
995
996 rdev->sqp_id = qp->qplib_qp.id;
997
998 spin_lock_init(&qp->sq_lock);
999 INIT_LIST_HEAD(&qp->list);
1000 mutex_lock(&rdev->qp_lock);
1001 list_add_tail(&qp->list, &rdev->qp_list);
1002 atomic_inc(&rdev->qp_count);
1003 mutex_unlock(&rdev->qp_lock);
1004 return qp;
1005 fail:
1006 kfree(qp);
1007 return NULL;
1008 }
1009
1010 struct ib_qp *bnxt_re_create_qp(struct ib_pd *ib_pd,
1011 struct ib_qp_init_attr *qp_init_attr,
1012 struct ib_udata *udata)
1013 {
1014 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
1015 struct bnxt_re_dev *rdev = pd->rdev;
1016 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
1017 struct bnxt_re_qp *qp;
1018 struct bnxt_re_cq *cq;
1019 int rc, entries;
1020
1021 if ((qp_init_attr->cap.max_send_wr > dev_attr->max_qp_wqes) ||
1022 (qp_init_attr->cap.max_recv_wr > dev_attr->max_qp_wqes) ||
1023 (qp_init_attr->cap.max_send_sge > dev_attr->max_qp_sges) ||
1024 (qp_init_attr->cap.max_recv_sge > dev_attr->max_qp_sges) ||
1025 (qp_init_attr->cap.max_inline_data > dev_attr->max_inline_data))
1026 return ERR_PTR(-EINVAL);
1027
1028 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
1029 if (!qp)
1030 return ERR_PTR(-ENOMEM);
1031
1032 qp->rdev = rdev;
1033 ether_addr_copy(qp->qplib_qp.smac, rdev->netdev->dev_addr);
1034 qp->qplib_qp.pd = &pd->qplib_pd;
1035 qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp);
1036 qp->qplib_qp.type = __from_ib_qp_type(qp_init_attr->qp_type);
1037 if (qp->qplib_qp.type == IB_QPT_MAX) {
1038 dev_err(rdev_to_dev(rdev), "QP type 0x%x not supported",
1039 qp->qplib_qp.type);
1040 rc = -EINVAL;
1041 goto fail;
1042 }
1043 qp->qplib_qp.max_inline_data = qp_init_attr->cap.max_inline_data;
1044 qp->qplib_qp.sig_type = ((qp_init_attr->sq_sig_type ==
1045 IB_SIGNAL_ALL_WR) ? true : false);
1046
1047 qp->qplib_qp.sq.max_sge = qp_init_attr->cap.max_send_sge;
1048 if (qp->qplib_qp.sq.max_sge > dev_attr->max_qp_sges)
1049 qp->qplib_qp.sq.max_sge = dev_attr->max_qp_sges;
1050
1051 if (qp_init_attr->send_cq) {
1052 cq = container_of(qp_init_attr->send_cq, struct bnxt_re_cq,
1053 ib_cq);
1054 if (!cq) {
1055 dev_err(rdev_to_dev(rdev), "Send CQ not found");
1056 rc = -EINVAL;
1057 goto fail;
1058 }
1059 qp->qplib_qp.scq = &cq->qplib_cq;
1060 }
1061
1062 if (qp_init_attr->recv_cq) {
1063 cq = container_of(qp_init_attr->recv_cq, struct bnxt_re_cq,
1064 ib_cq);
1065 if (!cq) {
1066 dev_err(rdev_to_dev(rdev), "Receive CQ not found");
1067 rc = -EINVAL;
1068 goto fail;
1069 }
1070 qp->qplib_qp.rcq = &cq->qplib_cq;
1071 }
1072
1073 if (qp_init_attr->srq) {
1074 dev_err(rdev_to_dev(rdev), "SRQ not supported");
1075 rc = -ENOTSUPP;
1076 goto fail;
1077 } else {
1078 /* Allocate 1 more than what's provided so posting max doesn't
1079 * mean empty
1080 */
1081 entries = roundup_pow_of_two(qp_init_attr->cap.max_recv_wr + 1);
1082 qp->qplib_qp.rq.max_wqe = min_t(u32, entries,
1083 dev_attr->max_qp_wqes + 1);
1084
1085 qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe -
1086 qp_init_attr->cap.max_recv_wr;
1087
1088 qp->qplib_qp.rq.max_sge = qp_init_attr->cap.max_recv_sge;
1089 if (qp->qplib_qp.rq.max_sge > dev_attr->max_qp_sges)
1090 qp->qplib_qp.rq.max_sge = dev_attr->max_qp_sges;
1091 }
1092
1093 qp->qplib_qp.mtu = ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu));
1094
1095 if (qp_init_attr->qp_type == IB_QPT_GSI) {
1096 /* Allocate 1 more than what's provided */
1097 entries = roundup_pow_of_two(qp_init_attr->cap.max_send_wr + 1);
1098 qp->qplib_qp.sq.max_wqe = min_t(u32, entries,
1099 dev_attr->max_qp_wqes + 1);
1100 qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe -
1101 qp_init_attr->cap.max_send_wr;
1102 qp->qplib_qp.rq.max_sge = dev_attr->max_qp_sges;
1103 if (qp->qplib_qp.rq.max_sge > dev_attr->max_qp_sges)
1104 qp->qplib_qp.rq.max_sge = dev_attr->max_qp_sges;
1105 qp->qplib_qp.sq.max_sge++;
1106 if (qp->qplib_qp.sq.max_sge > dev_attr->max_qp_sges)
1107 qp->qplib_qp.sq.max_sge = dev_attr->max_qp_sges;
1108
1109 qp->qplib_qp.rq_hdr_buf_size =
1110 BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2;
1111
1112 qp->qplib_qp.sq_hdr_buf_size =
1113 BNXT_QPLIB_MAX_QP1_SQ_HDR_SIZE_V2;
1114 qp->qplib_qp.dpi = &rdev->dpi_privileged;
1115 rc = bnxt_qplib_create_qp1(&rdev->qplib_res, &qp->qplib_qp);
1116 if (rc) {
1117 dev_err(rdev_to_dev(rdev), "Failed to create HW QP1");
1118 goto fail;
1119 }
1120 /* Create a shadow QP to handle the QP1 traffic */
1121 rdev->qp1_sqp = bnxt_re_create_shadow_qp(pd, &rdev->qplib_res,
1122 &qp->qplib_qp);
1123 if (!rdev->qp1_sqp) {
1124 rc = -EINVAL;
1125 dev_err(rdev_to_dev(rdev),
1126 "Failed to create Shadow QP for QP1");
1127 goto qp_destroy;
1128 }
1129 rdev->sqp_ah = bnxt_re_create_shadow_qp_ah(pd, &rdev->qplib_res,
1130 &qp->qplib_qp);
1131 if (!rdev->sqp_ah) {
1132 bnxt_qplib_destroy_qp(&rdev->qplib_res,
1133 &rdev->qp1_sqp->qplib_qp);
1134 rc = -EINVAL;
1135 dev_err(rdev_to_dev(rdev),
1136 "Failed to create AH entry for ShadowQP");
1137 goto qp_destroy;
1138 }
1139
1140 } else {
1141 /* Allocate 128 + 1 more than what's provided */
1142 entries = roundup_pow_of_two(qp_init_attr->cap.max_send_wr +
1143 BNXT_QPLIB_RESERVED_QP_WRS + 1);
1144 qp->qplib_qp.sq.max_wqe = min_t(u32, entries,
1145 dev_attr->max_qp_wqes +
1146 BNXT_QPLIB_RESERVED_QP_WRS + 1);
1147 qp->qplib_qp.sq.q_full_delta = BNXT_QPLIB_RESERVED_QP_WRS + 1;
1148
1149 /*
1150 * Reserving one slot for Phantom WQE. Application can
1151 * post one extra entry in this case. But allowing this to avoid
1152 * unexpected Queue full condition
1153 */
1154
1155 qp->qplib_qp.sq.q_full_delta -= 1;
1156
1157 qp->qplib_qp.max_rd_atomic = dev_attr->max_qp_rd_atom;
1158 qp->qplib_qp.max_dest_rd_atomic = dev_attr->max_qp_init_rd_atom;
1159 if (udata) {
1160 rc = bnxt_re_init_user_qp(rdev, pd, qp, udata);
1161 if (rc)
1162 goto fail;
1163 } else {
1164 qp->qplib_qp.dpi = &rdev->dpi_privileged;
1165 }
1166
1167 rc = bnxt_qplib_create_qp(&rdev->qplib_res, &qp->qplib_qp);
1168 if (rc) {
1169 dev_err(rdev_to_dev(rdev), "Failed to create HW QP");
1170 goto fail;
1171 }
1172 }
1173
1174 qp->ib_qp.qp_num = qp->qplib_qp.id;
1175 spin_lock_init(&qp->sq_lock);
1176 spin_lock_init(&qp->rq_lock);
1177
1178 if (udata) {
1179 struct bnxt_re_qp_resp resp;
1180
1181 resp.qpid = qp->ib_qp.qp_num;
1182 resp.rsvd = 0;
1183 rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
1184 if (rc) {
1185 dev_err(rdev_to_dev(rdev), "Failed to copy QP udata");
1186 goto qp_destroy;
1187 }
1188 }
1189 INIT_LIST_HEAD(&qp->list);
1190 mutex_lock(&rdev->qp_lock);
1191 list_add_tail(&qp->list, &rdev->qp_list);
1192 atomic_inc(&rdev->qp_count);
1193 mutex_unlock(&rdev->qp_lock);
1194
1195 return &qp->ib_qp;
1196 qp_destroy:
1197 bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp);
1198 fail:
1199 kfree(qp);
1200 return ERR_PTR(rc);
1201 }
1202
1203 static u8 __from_ib_qp_state(enum ib_qp_state state)
1204 {
1205 switch (state) {
1206 case IB_QPS_RESET:
1207 return CMDQ_MODIFY_QP_NEW_STATE_RESET;
1208 case IB_QPS_INIT:
1209 return CMDQ_MODIFY_QP_NEW_STATE_INIT;
1210 case IB_QPS_RTR:
1211 return CMDQ_MODIFY_QP_NEW_STATE_RTR;
1212 case IB_QPS_RTS:
1213 return CMDQ_MODIFY_QP_NEW_STATE_RTS;
1214 case IB_QPS_SQD:
1215 return CMDQ_MODIFY_QP_NEW_STATE_SQD;
1216 case IB_QPS_SQE:
1217 return CMDQ_MODIFY_QP_NEW_STATE_SQE;
1218 case IB_QPS_ERR:
1219 default:
1220 return CMDQ_MODIFY_QP_NEW_STATE_ERR;
1221 }
1222 }
1223
1224 static enum ib_qp_state __to_ib_qp_state(u8 state)
1225 {
1226 switch (state) {
1227 case CMDQ_MODIFY_QP_NEW_STATE_RESET:
1228 return IB_QPS_RESET;
1229 case CMDQ_MODIFY_QP_NEW_STATE_INIT:
1230 return IB_QPS_INIT;
1231 case CMDQ_MODIFY_QP_NEW_STATE_RTR:
1232 return IB_QPS_RTR;
1233 case CMDQ_MODIFY_QP_NEW_STATE_RTS:
1234 return IB_QPS_RTS;
1235 case CMDQ_MODIFY_QP_NEW_STATE_SQD:
1236 return IB_QPS_SQD;
1237 case CMDQ_MODIFY_QP_NEW_STATE_SQE:
1238 return IB_QPS_SQE;
1239 case CMDQ_MODIFY_QP_NEW_STATE_ERR:
1240 default:
1241 return IB_QPS_ERR;
1242 }
1243 }
1244
1245 static u32 __from_ib_mtu(enum ib_mtu mtu)
1246 {
1247 switch (mtu) {
1248 case IB_MTU_256:
1249 return CMDQ_MODIFY_QP_PATH_MTU_MTU_256;
1250 case IB_MTU_512:
1251 return CMDQ_MODIFY_QP_PATH_MTU_MTU_512;
1252 case IB_MTU_1024:
1253 return CMDQ_MODIFY_QP_PATH_MTU_MTU_1024;
1254 case IB_MTU_2048:
1255 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048;
1256 case IB_MTU_4096:
1257 return CMDQ_MODIFY_QP_PATH_MTU_MTU_4096;
1258 default:
1259 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048;
1260 }
1261 }
1262
1263 static enum ib_mtu __to_ib_mtu(u32 mtu)
1264 {
1265 switch (mtu & CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK) {
1266 case CMDQ_MODIFY_QP_PATH_MTU_MTU_256:
1267 return IB_MTU_256;
1268 case CMDQ_MODIFY_QP_PATH_MTU_MTU_512:
1269 return IB_MTU_512;
1270 case CMDQ_MODIFY_QP_PATH_MTU_MTU_1024:
1271 return IB_MTU_1024;
1272 case CMDQ_MODIFY_QP_PATH_MTU_MTU_2048:
1273 return IB_MTU_2048;
1274 case CMDQ_MODIFY_QP_PATH_MTU_MTU_4096:
1275 return IB_MTU_4096;
1276 default:
1277 return IB_MTU_2048;
1278 }
1279 }
1280
1281 static int bnxt_re_modify_shadow_qp(struct bnxt_re_dev *rdev,
1282 struct bnxt_re_qp *qp1_qp,
1283 int qp_attr_mask)
1284 {
1285 struct bnxt_re_qp *qp = rdev->qp1_sqp;
1286 int rc = 0;
1287
1288 if (qp_attr_mask & IB_QP_STATE) {
1289 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE;
1290 qp->qplib_qp.state = qp1_qp->qplib_qp.state;
1291 }
1292 if (qp_attr_mask & IB_QP_PKEY_INDEX) {
1293 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY;
1294 qp->qplib_qp.pkey_index = qp1_qp->qplib_qp.pkey_index;
1295 }
1296
1297 if (qp_attr_mask & IB_QP_QKEY) {
1298 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY;
1299 /* Using a Random QKEY */
1300 qp->qplib_qp.qkey = 0x81818181;
1301 }
1302 if (qp_attr_mask & IB_QP_SQ_PSN) {
1303 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN;
1304 qp->qplib_qp.sq.psn = qp1_qp->qplib_qp.sq.psn;
1305 }
1306
1307 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp);
1308 if (rc)
1309 dev_err(rdev_to_dev(rdev),
1310 "Failed to modify Shadow QP for QP1");
1311 return rc;
1312 }
1313
1314 int bnxt_re_modify_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr,
1315 int qp_attr_mask, struct ib_udata *udata)
1316 {
1317 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
1318 struct bnxt_re_dev *rdev = qp->rdev;
1319 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
1320 enum ib_qp_state curr_qp_state, new_qp_state;
1321 int rc, entries;
1322 int status;
1323 union ib_gid sgid;
1324 struct ib_gid_attr sgid_attr;
1325 u8 nw_type;
1326
1327 qp->qplib_qp.modify_flags = 0;
1328 if (qp_attr_mask & IB_QP_STATE) {
1329 curr_qp_state = __to_ib_qp_state(qp->qplib_qp.cur_qp_state);
1330 new_qp_state = qp_attr->qp_state;
1331 if (!ib_modify_qp_is_ok(curr_qp_state, new_qp_state,
1332 ib_qp->qp_type, qp_attr_mask,
1333 IB_LINK_LAYER_ETHERNET)) {
1334 dev_err(rdev_to_dev(rdev),
1335 "Invalid attribute mask: %#x specified ",
1336 qp_attr_mask);
1337 dev_err(rdev_to_dev(rdev),
1338 "for qpn: %#x type: %#x",
1339 ib_qp->qp_num, ib_qp->qp_type);
1340 dev_err(rdev_to_dev(rdev),
1341 "curr_qp_state=0x%x, new_qp_state=0x%x\n",
1342 curr_qp_state, new_qp_state);
1343 return -EINVAL;
1344 }
1345 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE;
1346 qp->qplib_qp.state = __from_ib_qp_state(qp_attr->qp_state);
1347
1348 if (!qp->sumem &&
1349 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR) {
1350 dev_dbg(rdev_to_dev(rdev),
1351 "Move QP = %p to flush list\n",
1352 qp);
1353 bnxt_qplib_add_flush_qp(&qp->qplib_qp);
1354 }
1355 if (!qp->sumem &&
1356 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_RESET) {
1357 dev_dbg(rdev_to_dev(rdev),
1358 "Move QP = %p out of flush list\n",
1359 qp);
1360 bnxt_qplib_del_flush_qp(&qp->qplib_qp);
1361 }
1362 }
1363 if (qp_attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) {
1364 qp->qplib_qp.modify_flags |=
1365 CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY;
1366 qp->qplib_qp.en_sqd_async_notify = true;
1367 }
1368 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
1369 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS;
1370 qp->qplib_qp.access =
1371 __from_ib_access_flags(qp_attr->qp_access_flags);
1372 /* LOCAL_WRITE access must be set to allow RC receive */
1373 qp->qplib_qp.access |= BNXT_QPLIB_ACCESS_LOCAL_WRITE;
1374 }
1375 if (qp_attr_mask & IB_QP_PKEY_INDEX) {
1376 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY;
1377 qp->qplib_qp.pkey_index = qp_attr->pkey_index;
1378 }
1379 if (qp_attr_mask & IB_QP_QKEY) {
1380 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY;
1381 qp->qplib_qp.qkey = qp_attr->qkey;
1382 }
1383 if (qp_attr_mask & IB_QP_AV) {
1384 const struct ib_global_route *grh =
1385 rdma_ah_read_grh(&qp_attr->ah_attr);
1386
1387 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_DGID |
1388 CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL |
1389 CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX |
1390 CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT |
1391 CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS |
1392 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC |
1393 CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID;
1394 memcpy(qp->qplib_qp.ah.dgid.data, grh->dgid.raw,
1395 sizeof(qp->qplib_qp.ah.dgid.data));
1396 qp->qplib_qp.ah.flow_label = grh->flow_label;
1397 /* If RoCE V2 is enabled, stack will have two entries for
1398 * each GID entry. Avoiding this duplicte entry in HW. Dividing
1399 * the GID index by 2 for RoCE V2
1400 */
1401 qp->qplib_qp.ah.sgid_index = grh->sgid_index / 2;
1402 qp->qplib_qp.ah.host_sgid_index = grh->sgid_index;
1403 qp->qplib_qp.ah.hop_limit = grh->hop_limit;
1404 qp->qplib_qp.ah.traffic_class = grh->traffic_class;
1405 qp->qplib_qp.ah.sl = rdma_ah_get_sl(&qp_attr->ah_attr);
1406 ether_addr_copy(qp->qplib_qp.ah.dmac,
1407 qp_attr->ah_attr.roce.dmac);
1408
1409 status = ib_get_cached_gid(&rdev->ibdev, 1,
1410 grh->sgid_index,
1411 &sgid, &sgid_attr);
1412 if (!status && sgid_attr.ndev) {
1413 memcpy(qp->qplib_qp.smac, sgid_attr.ndev->dev_addr,
1414 ETH_ALEN);
1415 dev_put(sgid_attr.ndev);
1416 nw_type = ib_gid_to_network_type(sgid_attr.gid_type,
1417 &sgid);
1418 switch (nw_type) {
1419 case RDMA_NETWORK_IPV4:
1420 qp->qplib_qp.nw_type =
1421 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4;
1422 break;
1423 case RDMA_NETWORK_IPV6:
1424 qp->qplib_qp.nw_type =
1425 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6;
1426 break;
1427 default:
1428 qp->qplib_qp.nw_type =
1429 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1;
1430 break;
1431 }
1432 }
1433 }
1434
1435 if (qp_attr_mask & IB_QP_PATH_MTU) {
1436 qp->qplib_qp.modify_flags |=
1437 CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU;
1438 qp->qplib_qp.path_mtu = __from_ib_mtu(qp_attr->path_mtu);
1439 } else if (qp_attr->qp_state == IB_QPS_RTR) {
1440 qp->qplib_qp.modify_flags |=
1441 CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU;
1442 qp->qplib_qp.path_mtu =
1443 __from_ib_mtu(iboe_get_mtu(rdev->netdev->mtu));
1444 }
1445
1446 if (qp_attr_mask & IB_QP_TIMEOUT) {
1447 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT;
1448 qp->qplib_qp.timeout = qp_attr->timeout;
1449 }
1450 if (qp_attr_mask & IB_QP_RETRY_CNT) {
1451 qp->qplib_qp.modify_flags |=
1452 CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT;
1453 qp->qplib_qp.retry_cnt = qp_attr->retry_cnt;
1454 }
1455 if (qp_attr_mask & IB_QP_RNR_RETRY) {
1456 qp->qplib_qp.modify_flags |=
1457 CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY;
1458 qp->qplib_qp.rnr_retry = qp_attr->rnr_retry;
1459 }
1460 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) {
1461 qp->qplib_qp.modify_flags |=
1462 CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER;
1463 qp->qplib_qp.min_rnr_timer = qp_attr->min_rnr_timer;
1464 }
1465 if (qp_attr_mask & IB_QP_RQ_PSN) {
1466 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN;
1467 qp->qplib_qp.rq.psn = qp_attr->rq_psn;
1468 }
1469 if (qp_attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1470 qp->qplib_qp.modify_flags |=
1471 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC;
1472 /* Cap the max_rd_atomic to device max */
1473 qp->qplib_qp.max_rd_atomic = min_t(u32, qp_attr->max_rd_atomic,
1474 dev_attr->max_qp_rd_atom);
1475 }
1476 if (qp_attr_mask & IB_QP_SQ_PSN) {
1477 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN;
1478 qp->qplib_qp.sq.psn = qp_attr->sq_psn;
1479 }
1480 if (qp_attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1481 if (qp_attr->max_dest_rd_atomic >
1482 dev_attr->max_qp_init_rd_atom) {
1483 dev_err(rdev_to_dev(rdev),
1484 "max_dest_rd_atomic requested%d is > dev_max%d",
1485 qp_attr->max_dest_rd_atomic,
1486 dev_attr->max_qp_init_rd_atom);
1487 return -EINVAL;
1488 }
1489
1490 qp->qplib_qp.modify_flags |=
1491 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC;
1492 qp->qplib_qp.max_dest_rd_atomic = qp_attr->max_dest_rd_atomic;
1493 }
1494 if (qp_attr_mask & IB_QP_CAP) {
1495 qp->qplib_qp.modify_flags |=
1496 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE |
1497 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE |
1498 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE |
1499 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE |
1500 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA;
1501 if ((qp_attr->cap.max_send_wr >= dev_attr->max_qp_wqes) ||
1502 (qp_attr->cap.max_recv_wr >= dev_attr->max_qp_wqes) ||
1503 (qp_attr->cap.max_send_sge >= dev_attr->max_qp_sges) ||
1504 (qp_attr->cap.max_recv_sge >= dev_attr->max_qp_sges) ||
1505 (qp_attr->cap.max_inline_data >=
1506 dev_attr->max_inline_data)) {
1507 dev_err(rdev_to_dev(rdev),
1508 "Create QP failed - max exceeded");
1509 return -EINVAL;
1510 }
1511 entries = roundup_pow_of_two(qp_attr->cap.max_send_wr);
1512 qp->qplib_qp.sq.max_wqe = min_t(u32, entries,
1513 dev_attr->max_qp_wqes + 1);
1514 qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe -
1515 qp_attr->cap.max_send_wr;
1516 /*
1517 * Reserving one slot for Phantom WQE. Some application can
1518 * post one extra entry in this case. Allowing this to avoid
1519 * unexpected Queue full condition
1520 */
1521 qp->qplib_qp.sq.q_full_delta -= 1;
1522 qp->qplib_qp.sq.max_sge = qp_attr->cap.max_send_sge;
1523 if (qp->qplib_qp.rq.max_wqe) {
1524 entries = roundup_pow_of_two(qp_attr->cap.max_recv_wr);
1525 qp->qplib_qp.rq.max_wqe =
1526 min_t(u32, entries, dev_attr->max_qp_wqes + 1);
1527 qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe -
1528 qp_attr->cap.max_recv_wr;
1529 qp->qplib_qp.rq.max_sge = qp_attr->cap.max_recv_sge;
1530 } else {
1531 /* SRQ was used prior, just ignore the RQ caps */
1532 }
1533 }
1534 if (qp_attr_mask & IB_QP_DEST_QPN) {
1535 qp->qplib_qp.modify_flags |=
1536 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID;
1537 qp->qplib_qp.dest_qpn = qp_attr->dest_qp_num;
1538 }
1539 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp);
1540 if (rc) {
1541 dev_err(rdev_to_dev(rdev), "Failed to modify HW QP");
1542 return rc;
1543 }
1544 if (ib_qp->qp_type == IB_QPT_GSI && rdev->qp1_sqp)
1545 rc = bnxt_re_modify_shadow_qp(rdev, qp, qp_attr_mask);
1546 return rc;
1547 }
1548
1549 int bnxt_re_query_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr,
1550 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
1551 {
1552 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
1553 struct bnxt_re_dev *rdev = qp->rdev;
1554 struct bnxt_qplib_qp *qplib_qp;
1555 int rc;
1556
1557 qplib_qp = kzalloc(sizeof(*qplib_qp), GFP_KERNEL);
1558 if (!qplib_qp)
1559 return -ENOMEM;
1560
1561 qplib_qp->id = qp->qplib_qp.id;
1562 qplib_qp->ah.host_sgid_index = qp->qplib_qp.ah.host_sgid_index;
1563
1564 rc = bnxt_qplib_query_qp(&rdev->qplib_res, qplib_qp);
1565 if (rc) {
1566 dev_err(rdev_to_dev(rdev), "Failed to query HW QP");
1567 goto out;
1568 }
1569 qp_attr->qp_state = __to_ib_qp_state(qplib_qp->state);
1570 qp_attr->en_sqd_async_notify = qplib_qp->en_sqd_async_notify ? 1 : 0;
1571 qp_attr->qp_access_flags = __to_ib_access_flags(qplib_qp->access);
1572 qp_attr->pkey_index = qplib_qp->pkey_index;
1573 qp_attr->qkey = qplib_qp->qkey;
1574 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
1575 rdma_ah_set_grh(&qp_attr->ah_attr, NULL, qplib_qp->ah.flow_label,
1576 qplib_qp->ah.host_sgid_index,
1577 qplib_qp->ah.hop_limit,
1578 qplib_qp->ah.traffic_class);
1579 rdma_ah_set_dgid_raw(&qp_attr->ah_attr, qplib_qp->ah.dgid.data);
1580 rdma_ah_set_sl(&qp_attr->ah_attr, qplib_qp->ah.sl);
1581 ether_addr_copy(qp_attr->ah_attr.roce.dmac, qplib_qp->ah.dmac);
1582 qp_attr->path_mtu = __to_ib_mtu(qplib_qp->path_mtu);
1583 qp_attr->timeout = qplib_qp->timeout;
1584 qp_attr->retry_cnt = qplib_qp->retry_cnt;
1585 qp_attr->rnr_retry = qplib_qp->rnr_retry;
1586 qp_attr->min_rnr_timer = qplib_qp->min_rnr_timer;
1587 qp_attr->rq_psn = qplib_qp->rq.psn;
1588 qp_attr->max_rd_atomic = qplib_qp->max_rd_atomic;
1589 qp_attr->sq_psn = qplib_qp->sq.psn;
1590 qp_attr->max_dest_rd_atomic = qplib_qp->max_dest_rd_atomic;
1591 qp_init_attr->sq_sig_type = qplib_qp->sig_type ? IB_SIGNAL_ALL_WR :
1592 IB_SIGNAL_REQ_WR;
1593 qp_attr->dest_qp_num = qplib_qp->dest_qpn;
1594
1595 qp_attr->cap.max_send_wr = qp->qplib_qp.sq.max_wqe;
1596 qp_attr->cap.max_send_sge = qp->qplib_qp.sq.max_sge;
1597 qp_attr->cap.max_recv_wr = qp->qplib_qp.rq.max_wqe;
1598 qp_attr->cap.max_recv_sge = qp->qplib_qp.rq.max_sge;
1599 qp_attr->cap.max_inline_data = qp->qplib_qp.max_inline_data;
1600 qp_init_attr->cap = qp_attr->cap;
1601
1602 out:
1603 kfree(qplib_qp);
1604 return rc;
1605 }
1606
1607 /* Routine for sending QP1 packets for RoCE V1 an V2
1608 */
1609 static int bnxt_re_build_qp1_send_v2(struct bnxt_re_qp *qp,
1610 struct ib_send_wr *wr,
1611 struct bnxt_qplib_swqe *wqe,
1612 int payload_size)
1613 {
1614 struct ib_device *ibdev = &qp->rdev->ibdev;
1615 struct bnxt_re_ah *ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah,
1616 ib_ah);
1617 struct bnxt_qplib_ah *qplib_ah = &ah->qplib_ah;
1618 struct bnxt_qplib_sge sge;
1619 union ib_gid sgid;
1620 u8 nw_type;
1621 u16 ether_type;
1622 struct ib_gid_attr sgid_attr;
1623 union ib_gid dgid;
1624 bool is_eth = false;
1625 bool is_vlan = false;
1626 bool is_grh = false;
1627 bool is_udp = false;
1628 u8 ip_version = 0;
1629 u16 vlan_id = 0xFFFF;
1630 void *buf;
1631 int i, rc = 0, size;
1632
1633 memset(&qp->qp1_hdr, 0, sizeof(qp->qp1_hdr));
1634
1635 rc = ib_get_cached_gid(ibdev, 1,
1636 qplib_ah->host_sgid_index, &sgid,
1637 &sgid_attr);
1638 if (rc) {
1639 dev_err(rdev_to_dev(qp->rdev),
1640 "Failed to query gid at index %d",
1641 qplib_ah->host_sgid_index);
1642 return rc;
1643 }
1644 if (sgid_attr.ndev) {
1645 if (is_vlan_dev(sgid_attr.ndev))
1646 vlan_id = vlan_dev_vlan_id(sgid_attr.ndev);
1647 dev_put(sgid_attr.ndev);
1648 }
1649 /* Get network header type for this GID */
1650 nw_type = ib_gid_to_network_type(sgid_attr.gid_type, &sgid);
1651 switch (nw_type) {
1652 case RDMA_NETWORK_IPV4:
1653 nw_type = BNXT_RE_ROCEV2_IPV4_PACKET;
1654 break;
1655 case RDMA_NETWORK_IPV6:
1656 nw_type = BNXT_RE_ROCEV2_IPV6_PACKET;
1657 break;
1658 default:
1659 nw_type = BNXT_RE_ROCE_V1_PACKET;
1660 break;
1661 }
1662 memcpy(&dgid.raw, &qplib_ah->dgid, 16);
1663 is_udp = sgid_attr.gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP;
1664 if (is_udp) {
1665 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid)) {
1666 ip_version = 4;
1667 ether_type = ETH_P_IP;
1668 } else {
1669 ip_version = 6;
1670 ether_type = ETH_P_IPV6;
1671 }
1672 is_grh = false;
1673 } else {
1674 ether_type = ETH_P_IBOE;
1675 is_grh = true;
1676 }
1677
1678 is_eth = true;
1679 is_vlan = (vlan_id && (vlan_id < 0x1000)) ? true : false;
1680
1681 ib_ud_header_init(payload_size, !is_eth, is_eth, is_vlan, is_grh,
1682 ip_version, is_udp, 0, &qp->qp1_hdr);
1683
1684 /* ETH */
1685 ether_addr_copy(qp->qp1_hdr.eth.dmac_h, ah->qplib_ah.dmac);
1686 ether_addr_copy(qp->qp1_hdr.eth.smac_h, qp->qplib_qp.smac);
1687
1688 /* For vlan, check the sgid for vlan existence */
1689
1690 if (!is_vlan) {
1691 qp->qp1_hdr.eth.type = cpu_to_be16(ether_type);
1692 } else {
1693 qp->qp1_hdr.vlan.type = cpu_to_be16(ether_type);
1694 qp->qp1_hdr.vlan.tag = cpu_to_be16(vlan_id);
1695 }
1696
1697 if (is_grh || (ip_version == 6)) {
1698 memcpy(qp->qp1_hdr.grh.source_gid.raw, sgid.raw, sizeof(sgid));
1699 memcpy(qp->qp1_hdr.grh.destination_gid.raw, qplib_ah->dgid.data,
1700 sizeof(sgid));
1701 qp->qp1_hdr.grh.hop_limit = qplib_ah->hop_limit;
1702 }
1703
1704 if (ip_version == 4) {
1705 qp->qp1_hdr.ip4.tos = 0;
1706 qp->qp1_hdr.ip4.id = 0;
1707 qp->qp1_hdr.ip4.frag_off = htons(IP_DF);
1708 qp->qp1_hdr.ip4.ttl = qplib_ah->hop_limit;
1709
1710 memcpy(&qp->qp1_hdr.ip4.saddr, sgid.raw + 12, 4);
1711 memcpy(&qp->qp1_hdr.ip4.daddr, qplib_ah->dgid.data + 12, 4);
1712 qp->qp1_hdr.ip4.check = ib_ud_ip4_csum(&qp->qp1_hdr);
1713 }
1714
1715 if (is_udp) {
1716 qp->qp1_hdr.udp.dport = htons(ROCE_V2_UDP_DPORT);
1717 qp->qp1_hdr.udp.sport = htons(0x8CD1);
1718 qp->qp1_hdr.udp.csum = 0;
1719 }
1720
1721 /* BTH */
1722 if (wr->opcode == IB_WR_SEND_WITH_IMM) {
1723 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1724 qp->qp1_hdr.immediate_present = 1;
1725 } else {
1726 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1727 }
1728 if (wr->send_flags & IB_SEND_SOLICITED)
1729 qp->qp1_hdr.bth.solicited_event = 1;
1730 /* pad_count */
1731 qp->qp1_hdr.bth.pad_count = (4 - payload_size) & 3;
1732
1733 /* P_key for QP1 is for all members */
1734 qp->qp1_hdr.bth.pkey = cpu_to_be16(0xFFFF);
1735 qp->qp1_hdr.bth.destination_qpn = IB_QP1;
1736 qp->qp1_hdr.bth.ack_req = 0;
1737 qp->send_psn++;
1738 qp->send_psn &= BTH_PSN_MASK;
1739 qp->qp1_hdr.bth.psn = cpu_to_be32(qp->send_psn);
1740 /* DETH */
1741 /* Use the priviledged Q_Key for QP1 */
1742 qp->qp1_hdr.deth.qkey = cpu_to_be32(IB_QP1_QKEY);
1743 qp->qp1_hdr.deth.source_qpn = IB_QP1;
1744
1745 /* Pack the QP1 to the transmit buffer */
1746 buf = bnxt_qplib_get_qp1_sq_buf(&qp->qplib_qp, &sge);
1747 if (buf) {
1748 size = ib_ud_header_pack(&qp->qp1_hdr, buf);
1749 for (i = wqe->num_sge; i; i--) {
1750 wqe->sg_list[i].addr = wqe->sg_list[i - 1].addr;
1751 wqe->sg_list[i].lkey = wqe->sg_list[i - 1].lkey;
1752 wqe->sg_list[i].size = wqe->sg_list[i - 1].size;
1753 }
1754
1755 /*
1756 * Max Header buf size for IPV6 RoCE V2 is 86,
1757 * which is same as the QP1 SQ header buffer.
1758 * Header buf size for IPV4 RoCE V2 can be 66.
1759 * ETH(14) + VLAN(4)+ IP(20) + UDP (8) + BTH(20).
1760 * Subtract 20 bytes from QP1 SQ header buf size
1761 */
1762 if (is_udp && ip_version == 4)
1763 sge.size -= 20;
1764 /*
1765 * Max Header buf size for RoCE V1 is 78.
1766 * ETH(14) + VLAN(4) + GRH(40) + BTH(20).
1767 * Subtract 8 bytes from QP1 SQ header buf size
1768 */
1769 if (!is_udp)
1770 sge.size -= 8;
1771
1772 /* Subtract 4 bytes for non vlan packets */
1773 if (!is_vlan)
1774 sge.size -= 4;
1775
1776 wqe->sg_list[0].addr = sge.addr;
1777 wqe->sg_list[0].lkey = sge.lkey;
1778 wqe->sg_list[0].size = sge.size;
1779 wqe->num_sge++;
1780
1781 } else {
1782 dev_err(rdev_to_dev(qp->rdev), "QP1 buffer is empty!");
1783 rc = -ENOMEM;
1784 }
1785 return rc;
1786 }
1787
1788 /* For the MAD layer, it only provides the recv SGE the size of
1789 * ib_grh + MAD datagram. No Ethernet headers, Ethertype, BTH, DETH,
1790 * nor RoCE iCRC. The Cu+ solution must provide buffer for the entire
1791 * receive packet (334 bytes) with no VLAN and then copy the GRH
1792 * and the MAD datagram out to the provided SGE.
1793 */
1794 static int bnxt_re_build_qp1_shadow_qp_recv(struct bnxt_re_qp *qp,
1795 struct ib_recv_wr *wr,
1796 struct bnxt_qplib_swqe *wqe,
1797 int payload_size)
1798 {
1799 struct bnxt_qplib_sge ref, sge;
1800 u32 rq_prod_index;
1801 struct bnxt_re_sqp_entries *sqp_entry;
1802
1803 rq_prod_index = bnxt_qplib_get_rq_prod_index(&qp->qplib_qp);
1804
1805 if (!bnxt_qplib_get_qp1_rq_buf(&qp->qplib_qp, &sge))
1806 return -ENOMEM;
1807
1808 /* Create 1 SGE to receive the entire
1809 * ethernet packet
1810 */
1811 /* Save the reference from ULP */
1812 ref.addr = wqe->sg_list[0].addr;
1813 ref.lkey = wqe->sg_list[0].lkey;
1814 ref.size = wqe->sg_list[0].size;
1815
1816 sqp_entry = &qp->rdev->sqp_tbl[rq_prod_index];
1817
1818 /* SGE 1 */
1819 wqe->sg_list[0].addr = sge.addr;
1820 wqe->sg_list[0].lkey = sge.lkey;
1821 wqe->sg_list[0].size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2;
1822 sge.size -= wqe->sg_list[0].size;
1823
1824 sqp_entry->sge.addr = ref.addr;
1825 sqp_entry->sge.lkey = ref.lkey;
1826 sqp_entry->sge.size = ref.size;
1827 /* Store the wrid for reporting completion */
1828 sqp_entry->wrid = wqe->wr_id;
1829 /* change the wqe->wrid to table index */
1830 wqe->wr_id = rq_prod_index;
1831 return 0;
1832 }
1833
1834 static int is_ud_qp(struct bnxt_re_qp *qp)
1835 {
1836 return qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD;
1837 }
1838
1839 static int bnxt_re_build_send_wqe(struct bnxt_re_qp *qp,
1840 struct ib_send_wr *wr,
1841 struct bnxt_qplib_swqe *wqe)
1842 {
1843 struct bnxt_re_ah *ah = NULL;
1844
1845 if (is_ud_qp(qp)) {
1846 ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, ib_ah);
1847 wqe->send.q_key = ud_wr(wr)->remote_qkey;
1848 wqe->send.dst_qp = ud_wr(wr)->remote_qpn;
1849 wqe->send.avid = ah->qplib_ah.id;
1850 }
1851 switch (wr->opcode) {
1852 case IB_WR_SEND:
1853 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND;
1854 break;
1855 case IB_WR_SEND_WITH_IMM:
1856 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM;
1857 wqe->send.imm_data = wr->ex.imm_data;
1858 break;
1859 case IB_WR_SEND_WITH_INV:
1860 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV;
1861 wqe->send.inv_key = wr->ex.invalidate_rkey;
1862 break;
1863 default:
1864 return -EINVAL;
1865 }
1866 if (wr->send_flags & IB_SEND_SIGNALED)
1867 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
1868 if (wr->send_flags & IB_SEND_FENCE)
1869 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
1870 if (wr->send_flags & IB_SEND_SOLICITED)
1871 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
1872 if (wr->send_flags & IB_SEND_INLINE)
1873 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE;
1874
1875 return 0;
1876 }
1877
1878 static int bnxt_re_build_rdma_wqe(struct ib_send_wr *wr,
1879 struct bnxt_qplib_swqe *wqe)
1880 {
1881 switch (wr->opcode) {
1882 case IB_WR_RDMA_WRITE:
1883 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE;
1884 break;
1885 case IB_WR_RDMA_WRITE_WITH_IMM:
1886 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM;
1887 wqe->rdma.imm_data = wr->ex.imm_data;
1888 break;
1889 case IB_WR_RDMA_READ:
1890 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_READ;
1891 wqe->rdma.inv_key = wr->ex.invalidate_rkey;
1892 break;
1893 default:
1894 return -EINVAL;
1895 }
1896 wqe->rdma.remote_va = rdma_wr(wr)->remote_addr;
1897 wqe->rdma.r_key = rdma_wr(wr)->rkey;
1898 if (wr->send_flags & IB_SEND_SIGNALED)
1899 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
1900 if (wr->send_flags & IB_SEND_FENCE)
1901 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
1902 if (wr->send_flags & IB_SEND_SOLICITED)
1903 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
1904 if (wr->send_flags & IB_SEND_INLINE)
1905 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE;
1906
1907 return 0;
1908 }
1909
1910 static int bnxt_re_build_atomic_wqe(struct ib_send_wr *wr,
1911 struct bnxt_qplib_swqe *wqe)
1912 {
1913 switch (wr->opcode) {
1914 case IB_WR_ATOMIC_CMP_AND_SWP:
1915 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP;
1916 wqe->atomic.swap_data = atomic_wr(wr)->swap;
1917 break;
1918 case IB_WR_ATOMIC_FETCH_AND_ADD:
1919 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD;
1920 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add;
1921 break;
1922 default:
1923 return -EINVAL;
1924 }
1925 wqe->atomic.remote_va = atomic_wr(wr)->remote_addr;
1926 wqe->atomic.r_key = atomic_wr(wr)->rkey;
1927 if (wr->send_flags & IB_SEND_SIGNALED)
1928 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
1929 if (wr->send_flags & IB_SEND_FENCE)
1930 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
1931 if (wr->send_flags & IB_SEND_SOLICITED)
1932 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
1933 return 0;
1934 }
1935
1936 static int bnxt_re_build_inv_wqe(struct ib_send_wr *wr,
1937 struct bnxt_qplib_swqe *wqe)
1938 {
1939 wqe->type = BNXT_QPLIB_SWQE_TYPE_LOCAL_INV;
1940 wqe->local_inv.inv_l_key = wr->ex.invalidate_rkey;
1941
1942 if (wr->send_flags & IB_SEND_SIGNALED)
1943 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
1944 if (wr->send_flags & IB_SEND_FENCE)
1945 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
1946 if (wr->send_flags & IB_SEND_SOLICITED)
1947 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
1948
1949 return 0;
1950 }
1951
1952 static int bnxt_re_build_reg_wqe(struct ib_reg_wr *wr,
1953 struct bnxt_qplib_swqe *wqe)
1954 {
1955 struct bnxt_re_mr *mr = container_of(wr->mr, struct bnxt_re_mr, ib_mr);
1956 struct bnxt_qplib_frpl *qplib_frpl = &mr->qplib_frpl;
1957 int access = wr->access;
1958
1959 wqe->frmr.pbl_ptr = (__le64 *)qplib_frpl->hwq.pbl_ptr[0];
1960 wqe->frmr.pbl_dma_ptr = qplib_frpl->hwq.pbl_dma_ptr[0];
1961 wqe->frmr.page_list = mr->pages;
1962 wqe->frmr.page_list_len = mr->npages;
1963 wqe->frmr.levels = qplib_frpl->hwq.level + 1;
1964 wqe->type = BNXT_QPLIB_SWQE_TYPE_REG_MR;
1965
1966 if (wr->wr.send_flags & IB_SEND_FENCE)
1967 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
1968 if (wr->wr.send_flags & IB_SEND_SIGNALED)
1969 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
1970
1971 if (access & IB_ACCESS_LOCAL_WRITE)
1972 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE;
1973 if (access & IB_ACCESS_REMOTE_READ)
1974 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ;
1975 if (access & IB_ACCESS_REMOTE_WRITE)
1976 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE;
1977 if (access & IB_ACCESS_REMOTE_ATOMIC)
1978 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC;
1979 if (access & IB_ACCESS_MW_BIND)
1980 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND;
1981
1982 wqe->frmr.l_key = wr->key;
1983 wqe->frmr.length = wr->mr->length;
1984 wqe->frmr.pbl_pg_sz_log = (wr->mr->page_size >> PAGE_SHIFT_4K) - 1;
1985 wqe->frmr.va = wr->mr->iova;
1986 return 0;
1987 }
1988
1989 static int bnxt_re_copy_inline_data(struct bnxt_re_dev *rdev,
1990 struct ib_send_wr *wr,
1991 struct bnxt_qplib_swqe *wqe)
1992 {
1993 /* Copy the inline data to the data field */
1994 u8 *in_data;
1995 u32 i, sge_len;
1996 void *sge_addr;
1997
1998 in_data = wqe->inline_data;
1999 for (i = 0; i < wr->num_sge; i++) {
2000 sge_addr = (void *)(unsigned long)
2001 wr->sg_list[i].addr;
2002 sge_len = wr->sg_list[i].length;
2003
2004 if ((sge_len + wqe->inline_len) >
2005 BNXT_QPLIB_SWQE_MAX_INLINE_LENGTH) {
2006 dev_err(rdev_to_dev(rdev),
2007 "Inline data size requested > supported value");
2008 return -EINVAL;
2009 }
2010 sge_len = wr->sg_list[i].length;
2011
2012 memcpy(in_data, sge_addr, sge_len);
2013 in_data += wr->sg_list[i].length;
2014 wqe->inline_len += wr->sg_list[i].length;
2015 }
2016 return wqe->inline_len;
2017 }
2018
2019 static int bnxt_re_copy_wr_payload(struct bnxt_re_dev *rdev,
2020 struct ib_send_wr *wr,
2021 struct bnxt_qplib_swqe *wqe)
2022 {
2023 int payload_sz = 0;
2024
2025 if (wr->send_flags & IB_SEND_INLINE)
2026 payload_sz = bnxt_re_copy_inline_data(rdev, wr, wqe);
2027 else
2028 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe->sg_list,
2029 wqe->num_sge);
2030
2031 return payload_sz;
2032 }
2033
2034 static void bnxt_ud_qp_hw_stall_workaround(struct bnxt_re_qp *qp)
2035 {
2036 if ((qp->ib_qp.qp_type == IB_QPT_UD ||
2037 qp->ib_qp.qp_type == IB_QPT_GSI ||
2038 qp->ib_qp.qp_type == IB_QPT_RAW_ETHERTYPE) &&
2039 qp->qplib_qp.wqe_cnt == BNXT_RE_UD_QP_HW_STALL) {
2040 int qp_attr_mask;
2041 struct ib_qp_attr qp_attr;
2042
2043 qp_attr_mask = IB_QP_STATE;
2044 qp_attr.qp_state = IB_QPS_RTS;
2045 bnxt_re_modify_qp(&qp->ib_qp, &qp_attr, qp_attr_mask, NULL);
2046 qp->qplib_qp.wqe_cnt = 0;
2047 }
2048 }
2049
2050 static int bnxt_re_post_send_shadow_qp(struct bnxt_re_dev *rdev,
2051 struct bnxt_re_qp *qp,
2052 struct ib_send_wr *wr)
2053 {
2054 struct bnxt_qplib_swqe wqe;
2055 int rc = 0, payload_sz = 0;
2056 unsigned long flags;
2057
2058 spin_lock_irqsave(&qp->sq_lock, flags);
2059 memset(&wqe, 0, sizeof(wqe));
2060 while (wr) {
2061 /* House keeping */
2062 memset(&wqe, 0, sizeof(wqe));
2063
2064 /* Common */
2065 wqe.num_sge = wr->num_sge;
2066 if (wr->num_sge > qp->qplib_qp.sq.max_sge) {
2067 dev_err(rdev_to_dev(rdev),
2068 "Limit exceeded for Send SGEs");
2069 rc = -EINVAL;
2070 goto bad;
2071 }
2072
2073 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe);
2074 if (payload_sz < 0) {
2075 rc = -EINVAL;
2076 goto bad;
2077 }
2078 wqe.wr_id = wr->wr_id;
2079
2080 wqe.type = BNXT_QPLIB_SWQE_TYPE_SEND;
2081
2082 rc = bnxt_re_build_send_wqe(qp, wr, &wqe);
2083 if (!rc)
2084 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
2085 bad:
2086 if (rc) {
2087 dev_err(rdev_to_dev(rdev),
2088 "Post send failed opcode = %#x rc = %d",
2089 wr->opcode, rc);
2090 break;
2091 }
2092 wr = wr->next;
2093 }
2094 bnxt_qplib_post_send_db(&qp->qplib_qp);
2095 bnxt_ud_qp_hw_stall_workaround(qp);
2096 spin_unlock_irqrestore(&qp->sq_lock, flags);
2097 return rc;
2098 }
2099
2100 int bnxt_re_post_send(struct ib_qp *ib_qp, struct ib_send_wr *wr,
2101 struct ib_send_wr **bad_wr)
2102 {
2103 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
2104 struct bnxt_qplib_swqe wqe;
2105 int rc = 0, payload_sz = 0;
2106 unsigned long flags;
2107
2108 spin_lock_irqsave(&qp->sq_lock, flags);
2109 while (wr) {
2110 /* House keeping */
2111 memset(&wqe, 0, sizeof(wqe));
2112
2113 /* Common */
2114 wqe.num_sge = wr->num_sge;
2115 if (wr->num_sge > qp->qplib_qp.sq.max_sge) {
2116 dev_err(rdev_to_dev(qp->rdev),
2117 "Limit exceeded for Send SGEs");
2118 rc = -EINVAL;
2119 goto bad;
2120 }
2121
2122 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe);
2123 if (payload_sz < 0) {
2124 rc = -EINVAL;
2125 goto bad;
2126 }
2127 wqe.wr_id = wr->wr_id;
2128
2129 switch (wr->opcode) {
2130 case IB_WR_SEND:
2131 case IB_WR_SEND_WITH_IMM:
2132 if (ib_qp->qp_type == IB_QPT_GSI) {
2133 rc = bnxt_re_build_qp1_send_v2(qp, wr, &wqe,
2134 payload_sz);
2135 if (rc)
2136 goto bad;
2137 wqe.rawqp1.lflags |=
2138 SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC;
2139 }
2140 switch (wr->send_flags) {
2141 case IB_SEND_IP_CSUM:
2142 wqe.rawqp1.lflags |=
2143 SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM;
2144 break;
2145 default:
2146 break;
2147 }
2148 /* Fall thru to build the wqe */
2149 case IB_WR_SEND_WITH_INV:
2150 rc = bnxt_re_build_send_wqe(qp, wr, &wqe);
2151 break;
2152 case IB_WR_RDMA_WRITE:
2153 case IB_WR_RDMA_WRITE_WITH_IMM:
2154 case IB_WR_RDMA_READ:
2155 rc = bnxt_re_build_rdma_wqe(wr, &wqe);
2156 break;
2157 case IB_WR_ATOMIC_CMP_AND_SWP:
2158 case IB_WR_ATOMIC_FETCH_AND_ADD:
2159 rc = bnxt_re_build_atomic_wqe(wr, &wqe);
2160 break;
2161 case IB_WR_RDMA_READ_WITH_INV:
2162 dev_err(rdev_to_dev(qp->rdev),
2163 "RDMA Read with Invalidate is not supported");
2164 rc = -EINVAL;
2165 goto bad;
2166 case IB_WR_LOCAL_INV:
2167 rc = bnxt_re_build_inv_wqe(wr, &wqe);
2168 break;
2169 case IB_WR_REG_MR:
2170 rc = bnxt_re_build_reg_wqe(reg_wr(wr), &wqe);
2171 break;
2172 default:
2173 /* Unsupported WRs */
2174 dev_err(rdev_to_dev(qp->rdev),
2175 "WR (%#x) is not supported", wr->opcode);
2176 rc = -EINVAL;
2177 goto bad;
2178 }
2179 if (!rc)
2180 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
2181 bad:
2182 if (rc) {
2183 dev_err(rdev_to_dev(qp->rdev),
2184 "post_send failed op:%#x qps = %#x rc = %d\n",
2185 wr->opcode, qp->qplib_qp.state, rc);
2186 *bad_wr = wr;
2187 break;
2188 }
2189 wr = wr->next;
2190 }
2191 bnxt_qplib_post_send_db(&qp->qplib_qp);
2192 bnxt_ud_qp_hw_stall_workaround(qp);
2193 spin_unlock_irqrestore(&qp->sq_lock, flags);
2194
2195 return rc;
2196 }
2197
2198 static int bnxt_re_post_recv_shadow_qp(struct bnxt_re_dev *rdev,
2199 struct bnxt_re_qp *qp,
2200 struct ib_recv_wr *wr)
2201 {
2202 struct bnxt_qplib_swqe wqe;
2203 int rc = 0, payload_sz = 0;
2204
2205 memset(&wqe, 0, sizeof(wqe));
2206 while (wr) {
2207 /* House keeping */
2208 memset(&wqe, 0, sizeof(wqe));
2209
2210 /* Common */
2211 wqe.num_sge = wr->num_sge;
2212 if (wr->num_sge > qp->qplib_qp.rq.max_sge) {
2213 dev_err(rdev_to_dev(rdev),
2214 "Limit exceeded for Receive SGEs");
2215 rc = -EINVAL;
2216 break;
2217 }
2218 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe.sg_list,
2219 wr->num_sge);
2220 wqe.wr_id = wr->wr_id;
2221 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
2222
2223 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe);
2224 if (rc)
2225 break;
2226
2227 wr = wr->next;
2228 }
2229 if (!rc)
2230 bnxt_qplib_post_recv_db(&qp->qplib_qp);
2231 return rc;
2232 }
2233
2234 int bnxt_re_post_recv(struct ib_qp *ib_qp, struct ib_recv_wr *wr,
2235 struct ib_recv_wr **bad_wr)
2236 {
2237 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
2238 struct bnxt_qplib_swqe wqe;
2239 int rc = 0, payload_sz = 0;
2240 unsigned long flags;
2241 u32 count = 0;
2242
2243 spin_lock_irqsave(&qp->rq_lock, flags);
2244 while (wr) {
2245 /* House keeping */
2246 memset(&wqe, 0, sizeof(wqe));
2247
2248 /* Common */
2249 wqe.num_sge = wr->num_sge;
2250 if (wr->num_sge > qp->qplib_qp.rq.max_sge) {
2251 dev_err(rdev_to_dev(qp->rdev),
2252 "Limit exceeded for Receive SGEs");
2253 rc = -EINVAL;
2254 *bad_wr = wr;
2255 break;
2256 }
2257
2258 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe.sg_list,
2259 wr->num_sge);
2260 wqe.wr_id = wr->wr_id;
2261 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
2262
2263 if (ib_qp->qp_type == IB_QPT_GSI)
2264 rc = bnxt_re_build_qp1_shadow_qp_recv(qp, wr, &wqe,
2265 payload_sz);
2266 if (!rc)
2267 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe);
2268 if (rc) {
2269 *bad_wr = wr;
2270 break;
2271 }
2272
2273 /* Ring DB if the RQEs posted reaches a threshold value */
2274 if (++count >= BNXT_RE_RQ_WQE_THRESHOLD) {
2275 bnxt_qplib_post_recv_db(&qp->qplib_qp);
2276 count = 0;
2277 }
2278
2279 wr = wr->next;
2280 }
2281
2282 if (count)
2283 bnxt_qplib_post_recv_db(&qp->qplib_qp);
2284
2285 spin_unlock_irqrestore(&qp->rq_lock, flags);
2286
2287 return rc;
2288 }
2289
2290 /* Completion Queues */
2291 int bnxt_re_destroy_cq(struct ib_cq *ib_cq)
2292 {
2293 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
2294 struct bnxt_re_dev *rdev = cq->rdev;
2295 int rc;
2296 struct bnxt_qplib_nq *nq = cq->qplib_cq.nq;
2297
2298 rc = bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq);
2299 if (rc) {
2300 dev_err(rdev_to_dev(rdev), "Failed to destroy HW CQ");
2301 return rc;
2302 }
2303 if (!IS_ERR_OR_NULL(cq->umem))
2304 ib_umem_release(cq->umem);
2305
2306 if (cq) {
2307 kfree(cq->cql);
2308 kfree(cq);
2309 }
2310 atomic_dec(&rdev->cq_count);
2311 nq->budget--;
2312 return 0;
2313 }
2314
2315 struct ib_cq *bnxt_re_create_cq(struct ib_device *ibdev,
2316 const struct ib_cq_init_attr *attr,
2317 struct ib_ucontext *context,
2318 struct ib_udata *udata)
2319 {
2320 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
2321 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
2322 struct bnxt_re_cq *cq = NULL;
2323 int rc, entries;
2324 int cqe = attr->cqe;
2325 struct bnxt_qplib_nq *nq = NULL;
2326 unsigned int nq_alloc_cnt;
2327
2328 /* Validate CQ fields */
2329 if (cqe < 1 || cqe > dev_attr->max_cq_wqes) {
2330 dev_err(rdev_to_dev(rdev), "Failed to create CQ -max exceeded");
2331 return ERR_PTR(-EINVAL);
2332 }
2333 cq = kzalloc(sizeof(*cq), GFP_KERNEL);
2334 if (!cq)
2335 return ERR_PTR(-ENOMEM);
2336
2337 cq->rdev = rdev;
2338 cq->qplib_cq.cq_handle = (u64)(unsigned long)(&cq->qplib_cq);
2339
2340 entries = roundup_pow_of_two(cqe + 1);
2341 if (entries > dev_attr->max_cq_wqes + 1)
2342 entries = dev_attr->max_cq_wqes + 1;
2343
2344 if (context) {
2345 struct bnxt_re_cq_req req;
2346 struct bnxt_re_ucontext *uctx = container_of
2347 (context,
2348 struct bnxt_re_ucontext,
2349 ib_uctx);
2350 if (ib_copy_from_udata(&req, udata, sizeof(req))) {
2351 rc = -EFAULT;
2352 goto fail;
2353 }
2354
2355 cq->umem = ib_umem_get(context, req.cq_va,
2356 entries * sizeof(struct cq_base),
2357 IB_ACCESS_LOCAL_WRITE, 1);
2358 if (IS_ERR(cq->umem)) {
2359 rc = PTR_ERR(cq->umem);
2360 goto fail;
2361 }
2362 cq->qplib_cq.sghead = cq->umem->sg_head.sgl;
2363 cq->qplib_cq.nmap = cq->umem->nmap;
2364 cq->qplib_cq.dpi = &uctx->dpi;
2365 } else {
2366 cq->max_cql = min_t(u32, entries, MAX_CQL_PER_POLL);
2367 cq->cql = kcalloc(cq->max_cql, sizeof(struct bnxt_qplib_cqe),
2368 GFP_KERNEL);
2369 if (!cq->cql) {
2370 rc = -ENOMEM;
2371 goto fail;
2372 }
2373
2374 cq->qplib_cq.dpi = &rdev->dpi_privileged;
2375 cq->qplib_cq.sghead = NULL;
2376 cq->qplib_cq.nmap = 0;
2377 }
2378 /*
2379 * Allocating the NQ in a round robin fashion. nq_alloc_cnt is a
2380 * used for getting the NQ index.
2381 */
2382 nq_alloc_cnt = atomic_inc_return(&rdev->nq_alloc_cnt);
2383 nq = &rdev->nq[nq_alloc_cnt % (rdev->num_msix - 1)];
2384 cq->qplib_cq.max_wqe = entries;
2385 cq->qplib_cq.cnq_hw_ring_id = nq->ring_id;
2386 cq->qplib_cq.nq = nq;
2387
2388 rc = bnxt_qplib_create_cq(&rdev->qplib_res, &cq->qplib_cq);
2389 if (rc) {
2390 dev_err(rdev_to_dev(rdev), "Failed to create HW CQ");
2391 goto fail;
2392 }
2393
2394 cq->ib_cq.cqe = entries;
2395 cq->cq_period = cq->qplib_cq.period;
2396 nq->budget++;
2397
2398 atomic_inc(&rdev->cq_count);
2399
2400 if (context) {
2401 struct bnxt_re_cq_resp resp;
2402
2403 resp.cqid = cq->qplib_cq.id;
2404 resp.tail = cq->qplib_cq.hwq.cons;
2405 resp.phase = cq->qplib_cq.period;
2406 resp.rsvd = 0;
2407 rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
2408 if (rc) {
2409 dev_err(rdev_to_dev(rdev), "Failed to copy CQ udata");
2410 bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq);
2411 goto c2fail;
2412 }
2413 }
2414
2415 return &cq->ib_cq;
2416
2417 c2fail:
2418 if (context)
2419 ib_umem_release(cq->umem);
2420 fail:
2421 kfree(cq->cql);
2422 kfree(cq);
2423 return ERR_PTR(rc);
2424 }
2425
2426 static u8 __req_to_ib_wc_status(u8 qstatus)
2427 {
2428 switch (qstatus) {
2429 case CQ_REQ_STATUS_OK:
2430 return IB_WC_SUCCESS;
2431 case CQ_REQ_STATUS_BAD_RESPONSE_ERR:
2432 return IB_WC_BAD_RESP_ERR;
2433 case CQ_REQ_STATUS_LOCAL_LENGTH_ERR:
2434 return IB_WC_LOC_LEN_ERR;
2435 case CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR:
2436 return IB_WC_LOC_QP_OP_ERR;
2437 case CQ_REQ_STATUS_LOCAL_PROTECTION_ERR:
2438 return IB_WC_LOC_PROT_ERR;
2439 case CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR:
2440 return IB_WC_GENERAL_ERR;
2441 case CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR:
2442 return IB_WC_REM_INV_REQ_ERR;
2443 case CQ_REQ_STATUS_REMOTE_ACCESS_ERR:
2444 return IB_WC_REM_ACCESS_ERR;
2445 case CQ_REQ_STATUS_REMOTE_OPERATION_ERR:
2446 return IB_WC_REM_OP_ERR;
2447 case CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR:
2448 return IB_WC_RNR_RETRY_EXC_ERR;
2449 case CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR:
2450 return IB_WC_RETRY_EXC_ERR;
2451 case CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR:
2452 return IB_WC_WR_FLUSH_ERR;
2453 default:
2454 return IB_WC_GENERAL_ERR;
2455 }
2456 return 0;
2457 }
2458
2459 static u8 __rawqp1_to_ib_wc_status(u8 qstatus)
2460 {
2461 switch (qstatus) {
2462 case CQ_RES_RAWETH_QP1_STATUS_OK:
2463 return IB_WC_SUCCESS;
2464 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR:
2465 return IB_WC_LOC_ACCESS_ERR;
2466 case CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR:
2467 return IB_WC_LOC_LEN_ERR;
2468 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR:
2469 return IB_WC_LOC_PROT_ERR;
2470 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR:
2471 return IB_WC_LOC_QP_OP_ERR;
2472 case CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR:
2473 return IB_WC_GENERAL_ERR;
2474 case CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR:
2475 return IB_WC_WR_FLUSH_ERR;
2476 case CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR:
2477 return IB_WC_WR_FLUSH_ERR;
2478 default:
2479 return IB_WC_GENERAL_ERR;
2480 }
2481 }
2482
2483 static u8 __rc_to_ib_wc_status(u8 qstatus)
2484 {
2485 switch (qstatus) {
2486 case CQ_RES_RC_STATUS_OK:
2487 return IB_WC_SUCCESS;
2488 case CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR:
2489 return IB_WC_LOC_ACCESS_ERR;
2490 case CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR:
2491 return IB_WC_LOC_LEN_ERR;
2492 case CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR:
2493 return IB_WC_LOC_PROT_ERR;
2494 case CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR:
2495 return IB_WC_LOC_QP_OP_ERR;
2496 case CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR:
2497 return IB_WC_GENERAL_ERR;
2498 case CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR:
2499 return IB_WC_REM_INV_REQ_ERR;
2500 case CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR:
2501 return IB_WC_WR_FLUSH_ERR;
2502 case CQ_RES_RC_STATUS_HW_FLUSH_ERR:
2503 return IB_WC_WR_FLUSH_ERR;
2504 default:
2505 return IB_WC_GENERAL_ERR;
2506 }
2507 }
2508
2509 static void bnxt_re_process_req_wc(struct ib_wc *wc, struct bnxt_qplib_cqe *cqe)
2510 {
2511 switch (cqe->type) {
2512 case BNXT_QPLIB_SWQE_TYPE_SEND:
2513 wc->opcode = IB_WC_SEND;
2514 break;
2515 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM:
2516 wc->opcode = IB_WC_SEND;
2517 wc->wc_flags |= IB_WC_WITH_IMM;
2518 break;
2519 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV:
2520 wc->opcode = IB_WC_SEND;
2521 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
2522 break;
2523 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE:
2524 wc->opcode = IB_WC_RDMA_WRITE;
2525 break;
2526 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM:
2527 wc->opcode = IB_WC_RDMA_WRITE;
2528 wc->wc_flags |= IB_WC_WITH_IMM;
2529 break;
2530 case BNXT_QPLIB_SWQE_TYPE_RDMA_READ:
2531 wc->opcode = IB_WC_RDMA_READ;
2532 break;
2533 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP:
2534 wc->opcode = IB_WC_COMP_SWAP;
2535 break;
2536 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD:
2537 wc->opcode = IB_WC_FETCH_ADD;
2538 break;
2539 case BNXT_QPLIB_SWQE_TYPE_LOCAL_INV:
2540 wc->opcode = IB_WC_LOCAL_INV;
2541 break;
2542 case BNXT_QPLIB_SWQE_TYPE_REG_MR:
2543 wc->opcode = IB_WC_REG_MR;
2544 break;
2545 default:
2546 wc->opcode = IB_WC_SEND;
2547 break;
2548 }
2549
2550 wc->status = __req_to_ib_wc_status(cqe->status);
2551 }
2552
2553 static int bnxt_re_check_packet_type(u16 raweth_qp1_flags,
2554 u16 raweth_qp1_flags2)
2555 {
2556 bool is_udp = false, is_ipv6 = false, is_ipv4 = false;
2557
2558 /* raweth_qp1_flags Bit 9-6 indicates itype */
2559 if ((raweth_qp1_flags & CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE)
2560 != CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE)
2561 return -1;
2562
2563 if (raweth_qp1_flags2 &
2564 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC &&
2565 raweth_qp1_flags2 &
2566 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC) {
2567 is_udp = true;
2568 /* raweth_qp1_flags2 Bit 8 indicates ip_type. 0-v4 1 - v6 */
2569 (raweth_qp1_flags2 &
2570 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE) ?
2571 (is_ipv6 = true) : (is_ipv4 = true);
2572 return ((is_ipv6) ?
2573 BNXT_RE_ROCEV2_IPV6_PACKET :
2574 BNXT_RE_ROCEV2_IPV4_PACKET);
2575 } else {
2576 return BNXT_RE_ROCE_V1_PACKET;
2577 }
2578 }
2579
2580 static int bnxt_re_to_ib_nw_type(int nw_type)
2581 {
2582 u8 nw_hdr_type = 0xFF;
2583
2584 switch (nw_type) {
2585 case BNXT_RE_ROCE_V1_PACKET:
2586 nw_hdr_type = RDMA_NETWORK_ROCE_V1;
2587 break;
2588 case BNXT_RE_ROCEV2_IPV4_PACKET:
2589 nw_hdr_type = RDMA_NETWORK_IPV4;
2590 break;
2591 case BNXT_RE_ROCEV2_IPV6_PACKET:
2592 nw_hdr_type = RDMA_NETWORK_IPV6;
2593 break;
2594 }
2595 return nw_hdr_type;
2596 }
2597
2598 static bool bnxt_re_is_loopback_packet(struct bnxt_re_dev *rdev,
2599 void *rq_hdr_buf)
2600 {
2601 u8 *tmp_buf = NULL;
2602 struct ethhdr *eth_hdr;
2603 u16 eth_type;
2604 bool rc = false;
2605
2606 tmp_buf = (u8 *)rq_hdr_buf;
2607 /*
2608 * If dest mac is not same as I/F mac, this could be a
2609 * loopback address or multicast address, check whether
2610 * it is a loopback packet
2611 */
2612 if (!ether_addr_equal(tmp_buf, rdev->netdev->dev_addr)) {
2613 tmp_buf += 4;
2614 /* Check the ether type */
2615 eth_hdr = (struct ethhdr *)tmp_buf;
2616 eth_type = ntohs(eth_hdr->h_proto);
2617 switch (eth_type) {
2618 case ETH_P_IBOE:
2619 rc = true;
2620 break;
2621 case ETH_P_IP:
2622 case ETH_P_IPV6: {
2623 u32 len;
2624 struct udphdr *udp_hdr;
2625
2626 len = (eth_type == ETH_P_IP ? sizeof(struct iphdr) :
2627 sizeof(struct ipv6hdr));
2628 tmp_buf += sizeof(struct ethhdr) + len;
2629 udp_hdr = (struct udphdr *)tmp_buf;
2630 if (ntohs(udp_hdr->dest) ==
2631 ROCE_V2_UDP_DPORT)
2632 rc = true;
2633 break;
2634 }
2635 default:
2636 break;
2637 }
2638 }
2639
2640 return rc;
2641 }
2642
2643 static int bnxt_re_process_raw_qp_pkt_rx(struct bnxt_re_qp *qp1_qp,
2644 struct bnxt_qplib_cqe *cqe)
2645 {
2646 struct bnxt_re_dev *rdev = qp1_qp->rdev;
2647 struct bnxt_re_sqp_entries *sqp_entry = NULL;
2648 struct bnxt_re_qp *qp = rdev->qp1_sqp;
2649 struct ib_send_wr *swr;
2650 struct ib_ud_wr udwr;
2651 struct ib_recv_wr rwr;
2652 int pkt_type = 0;
2653 u32 tbl_idx;
2654 void *rq_hdr_buf;
2655 dma_addr_t rq_hdr_buf_map;
2656 dma_addr_t shrq_hdr_buf_map;
2657 u32 offset = 0;
2658 u32 skip_bytes = 0;
2659 struct ib_sge s_sge[2];
2660 struct ib_sge r_sge[2];
2661 int rc;
2662
2663 memset(&udwr, 0, sizeof(udwr));
2664 memset(&rwr, 0, sizeof(rwr));
2665 memset(&s_sge, 0, sizeof(s_sge));
2666 memset(&r_sge, 0, sizeof(r_sge));
2667
2668 swr = &udwr.wr;
2669 tbl_idx = cqe->wr_id;
2670
2671 rq_hdr_buf = qp1_qp->qplib_qp.rq_hdr_buf +
2672 (tbl_idx * qp1_qp->qplib_qp.rq_hdr_buf_size);
2673 rq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&qp1_qp->qplib_qp,
2674 tbl_idx);
2675
2676 /* Shadow QP header buffer */
2677 shrq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&qp->qplib_qp,
2678 tbl_idx);
2679 sqp_entry = &rdev->sqp_tbl[tbl_idx];
2680
2681 /* Store this cqe */
2682 memcpy(&sqp_entry->cqe, cqe, sizeof(struct bnxt_qplib_cqe));
2683 sqp_entry->qp1_qp = qp1_qp;
2684
2685 /* Find packet type from the cqe */
2686
2687 pkt_type = bnxt_re_check_packet_type(cqe->raweth_qp1_flags,
2688 cqe->raweth_qp1_flags2);
2689 if (pkt_type < 0) {
2690 dev_err(rdev_to_dev(rdev), "Invalid packet\n");
2691 return -EINVAL;
2692 }
2693
2694 /* Adjust the offset for the user buffer and post in the rq */
2695
2696 if (pkt_type == BNXT_RE_ROCEV2_IPV4_PACKET)
2697 offset = 20;
2698
2699 /*
2700 * QP1 loopback packet has 4 bytes of internal header before
2701 * ether header. Skip these four bytes.
2702 */
2703 if (bnxt_re_is_loopback_packet(rdev, rq_hdr_buf))
2704 skip_bytes = 4;
2705
2706 /* First send SGE . Skip the ether header*/
2707 s_sge[0].addr = rq_hdr_buf_map + BNXT_QPLIB_MAX_QP1_RQ_ETH_HDR_SIZE
2708 + skip_bytes;
2709 s_sge[0].lkey = 0xFFFFFFFF;
2710 s_sge[0].length = offset ? BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV4 :
2711 BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6;
2712
2713 /* Second Send SGE */
2714 s_sge[1].addr = s_sge[0].addr + s_sge[0].length +
2715 BNXT_QPLIB_MAX_QP1_RQ_BDETH_HDR_SIZE;
2716 if (pkt_type != BNXT_RE_ROCE_V1_PACKET)
2717 s_sge[1].addr += 8;
2718 s_sge[1].lkey = 0xFFFFFFFF;
2719 s_sge[1].length = 256;
2720
2721 /* First recv SGE */
2722
2723 r_sge[0].addr = shrq_hdr_buf_map;
2724 r_sge[0].lkey = 0xFFFFFFFF;
2725 r_sge[0].length = 40;
2726
2727 r_sge[1].addr = sqp_entry->sge.addr + offset;
2728 r_sge[1].lkey = sqp_entry->sge.lkey;
2729 r_sge[1].length = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6 + 256 - offset;
2730
2731 /* Create receive work request */
2732 rwr.num_sge = 2;
2733 rwr.sg_list = r_sge;
2734 rwr.wr_id = tbl_idx;
2735 rwr.next = NULL;
2736
2737 rc = bnxt_re_post_recv_shadow_qp(rdev, qp, &rwr);
2738 if (rc) {
2739 dev_err(rdev_to_dev(rdev),
2740 "Failed to post Rx buffers to shadow QP");
2741 return -ENOMEM;
2742 }
2743
2744 swr->num_sge = 2;
2745 swr->sg_list = s_sge;
2746 swr->wr_id = tbl_idx;
2747 swr->opcode = IB_WR_SEND;
2748 swr->next = NULL;
2749
2750 udwr.ah = &rdev->sqp_ah->ib_ah;
2751 udwr.remote_qpn = rdev->qp1_sqp->qplib_qp.id;
2752 udwr.remote_qkey = rdev->qp1_sqp->qplib_qp.qkey;
2753
2754 /* post data received in the send queue */
2755 rc = bnxt_re_post_send_shadow_qp(rdev, qp, swr);
2756
2757 return 0;
2758 }
2759
2760 static void bnxt_re_process_res_rawqp1_wc(struct ib_wc *wc,
2761 struct bnxt_qplib_cqe *cqe)
2762 {
2763 wc->opcode = IB_WC_RECV;
2764 wc->status = __rawqp1_to_ib_wc_status(cqe->status);
2765 wc->wc_flags |= IB_WC_GRH;
2766 }
2767
2768 static void bnxt_re_process_res_rc_wc(struct ib_wc *wc,
2769 struct bnxt_qplib_cqe *cqe)
2770 {
2771 wc->opcode = IB_WC_RECV;
2772 wc->status = __rc_to_ib_wc_status(cqe->status);
2773
2774 if (cqe->flags & CQ_RES_RC_FLAGS_IMM)
2775 wc->wc_flags |= IB_WC_WITH_IMM;
2776 if (cqe->flags & CQ_RES_RC_FLAGS_INV)
2777 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
2778 if ((cqe->flags & (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) ==
2779 (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM))
2780 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
2781 }
2782
2783 static void bnxt_re_process_res_shadow_qp_wc(struct bnxt_re_qp *qp,
2784 struct ib_wc *wc,
2785 struct bnxt_qplib_cqe *cqe)
2786 {
2787 u32 tbl_idx;
2788 struct bnxt_re_dev *rdev = qp->rdev;
2789 struct bnxt_re_qp *qp1_qp = NULL;
2790 struct bnxt_qplib_cqe *orig_cqe = NULL;
2791 struct bnxt_re_sqp_entries *sqp_entry = NULL;
2792 int nw_type;
2793
2794 tbl_idx = cqe->wr_id;
2795
2796 sqp_entry = &rdev->sqp_tbl[tbl_idx];
2797 qp1_qp = sqp_entry->qp1_qp;
2798 orig_cqe = &sqp_entry->cqe;
2799
2800 wc->wr_id = sqp_entry->wrid;
2801 wc->byte_len = orig_cqe->length;
2802 wc->qp = &qp1_qp->ib_qp;
2803
2804 wc->ex.imm_data = orig_cqe->immdata;
2805 wc->src_qp = orig_cqe->src_qp;
2806 memcpy(wc->smac, orig_cqe->smac, ETH_ALEN);
2807 wc->port_num = 1;
2808 wc->vendor_err = orig_cqe->status;
2809
2810 wc->opcode = IB_WC_RECV;
2811 wc->status = __rawqp1_to_ib_wc_status(orig_cqe->status);
2812 wc->wc_flags |= IB_WC_GRH;
2813
2814 nw_type = bnxt_re_check_packet_type(orig_cqe->raweth_qp1_flags,
2815 orig_cqe->raweth_qp1_flags2);
2816 if (nw_type >= 0) {
2817 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type);
2818 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
2819 }
2820 }
2821
2822 static void bnxt_re_process_res_ud_wc(struct ib_wc *wc,
2823 struct bnxt_qplib_cqe *cqe)
2824 {
2825 wc->opcode = IB_WC_RECV;
2826 wc->status = __rc_to_ib_wc_status(cqe->status);
2827
2828 if (cqe->flags & CQ_RES_RC_FLAGS_IMM)
2829 wc->wc_flags |= IB_WC_WITH_IMM;
2830 if (cqe->flags & CQ_RES_RC_FLAGS_INV)
2831 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
2832 if ((cqe->flags & (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) ==
2833 (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM))
2834 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
2835 }
2836
2837 static int send_phantom_wqe(struct bnxt_re_qp *qp)
2838 {
2839 struct bnxt_qplib_qp *lib_qp = &qp->qplib_qp;
2840 unsigned long flags;
2841 int rc = 0;
2842
2843 spin_lock_irqsave(&qp->sq_lock, flags);
2844
2845 rc = bnxt_re_bind_fence_mw(lib_qp);
2846 if (!rc) {
2847 lib_qp->sq.phantom_wqe_cnt++;
2848 dev_dbg(&lib_qp->sq.hwq.pdev->dev,
2849 "qp %#x sq->prod %#x sw_prod %#x phantom_wqe_cnt %d\n",
2850 lib_qp->id, lib_qp->sq.hwq.prod,
2851 HWQ_CMP(lib_qp->sq.hwq.prod, &lib_qp->sq.hwq),
2852 lib_qp->sq.phantom_wqe_cnt);
2853 }
2854
2855 spin_unlock_irqrestore(&qp->sq_lock, flags);
2856 return rc;
2857 }
2858
2859 int bnxt_re_poll_cq(struct ib_cq *ib_cq, int num_entries, struct ib_wc *wc)
2860 {
2861 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
2862 struct bnxt_re_qp *qp;
2863 struct bnxt_qplib_cqe *cqe;
2864 int i, ncqe, budget;
2865 struct bnxt_qplib_q *sq;
2866 struct bnxt_qplib_qp *lib_qp;
2867 u32 tbl_idx;
2868 struct bnxt_re_sqp_entries *sqp_entry = NULL;
2869 unsigned long flags;
2870
2871 spin_lock_irqsave(&cq->cq_lock, flags);
2872 budget = min_t(u32, num_entries, cq->max_cql);
2873 num_entries = budget;
2874 if (!cq->cql) {
2875 dev_err(rdev_to_dev(cq->rdev), "POLL CQ : no CQL to use");
2876 goto exit;
2877 }
2878 cqe = &cq->cql[0];
2879 while (budget) {
2880 lib_qp = NULL;
2881 ncqe = bnxt_qplib_poll_cq(&cq->qplib_cq, cqe, budget, &lib_qp);
2882 if (lib_qp) {
2883 sq = &lib_qp->sq;
2884 if (sq->send_phantom) {
2885 qp = container_of(lib_qp,
2886 struct bnxt_re_qp, qplib_qp);
2887 if (send_phantom_wqe(qp) == -ENOMEM)
2888 dev_err(rdev_to_dev(cq->rdev),
2889 "Phantom failed! Scheduled to send again\n");
2890 else
2891 sq->send_phantom = false;
2892 }
2893 }
2894 if (ncqe < budget)
2895 ncqe += bnxt_qplib_process_flush_list(&cq->qplib_cq,
2896 cqe + ncqe,
2897 budget - ncqe);
2898
2899 if (!ncqe)
2900 break;
2901
2902 for (i = 0; i < ncqe; i++, cqe++) {
2903 /* Transcribe each qplib_wqe back to ib_wc */
2904 memset(wc, 0, sizeof(*wc));
2905
2906 wc->wr_id = cqe->wr_id;
2907 wc->byte_len = cqe->length;
2908 qp = container_of
2909 ((struct bnxt_qplib_qp *)
2910 (unsigned long)(cqe->qp_handle),
2911 struct bnxt_re_qp, qplib_qp);
2912 if (!qp) {
2913 dev_err(rdev_to_dev(cq->rdev),
2914 "POLL CQ : bad QP handle");
2915 continue;
2916 }
2917 wc->qp = &qp->ib_qp;
2918 wc->ex.imm_data = cqe->immdata;
2919 wc->src_qp = cqe->src_qp;
2920 memcpy(wc->smac, cqe->smac, ETH_ALEN);
2921 wc->port_num = 1;
2922 wc->vendor_err = cqe->status;
2923
2924 switch (cqe->opcode) {
2925 case CQ_BASE_CQE_TYPE_REQ:
2926 if (qp->qplib_qp.id ==
2927 qp->rdev->qp1_sqp->qplib_qp.id) {
2928 /* Handle this completion with
2929 * the stored completion
2930 */
2931 memset(wc, 0, sizeof(*wc));
2932 continue;
2933 }
2934 bnxt_re_process_req_wc(wc, cqe);
2935 break;
2936 case CQ_BASE_CQE_TYPE_RES_RAWETH_QP1:
2937 if (!cqe->status) {
2938 int rc = 0;
2939
2940 rc = bnxt_re_process_raw_qp_pkt_rx
2941 (qp, cqe);
2942 if (!rc) {
2943 memset(wc, 0, sizeof(*wc));
2944 continue;
2945 }
2946 cqe->status = -1;
2947 }
2948 /* Errors need not be looped back.
2949 * But change the wr_id to the one
2950 * stored in the table
2951 */
2952 tbl_idx = cqe->wr_id;
2953 sqp_entry = &cq->rdev->sqp_tbl[tbl_idx];
2954 wc->wr_id = sqp_entry->wrid;
2955 bnxt_re_process_res_rawqp1_wc(wc, cqe);
2956 break;
2957 case CQ_BASE_CQE_TYPE_RES_RC:
2958 bnxt_re_process_res_rc_wc(wc, cqe);
2959 break;
2960 case CQ_BASE_CQE_TYPE_RES_UD:
2961 if (qp->qplib_qp.id ==
2962 qp->rdev->qp1_sqp->qplib_qp.id) {
2963 /* Handle this completion with
2964 * the stored completion
2965 */
2966 if (cqe->status) {
2967 continue;
2968 } else {
2969 bnxt_re_process_res_shadow_qp_wc
2970 (qp, wc, cqe);
2971 break;
2972 }
2973 }
2974 bnxt_re_process_res_ud_wc(wc, cqe);
2975 break;
2976 default:
2977 dev_err(rdev_to_dev(cq->rdev),
2978 "POLL CQ : type 0x%x not handled",
2979 cqe->opcode);
2980 continue;
2981 }
2982 wc++;
2983 budget--;
2984 }
2985 }
2986 exit:
2987 spin_unlock_irqrestore(&cq->cq_lock, flags);
2988 return num_entries - budget;
2989 }
2990
2991 int bnxt_re_req_notify_cq(struct ib_cq *ib_cq,
2992 enum ib_cq_notify_flags ib_cqn_flags)
2993 {
2994 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
2995 int type = 0;
2996
2997 /* Trigger on the very next completion */
2998 if (ib_cqn_flags & IB_CQ_NEXT_COMP)
2999 type = DBR_DBR_TYPE_CQ_ARMALL;
3000 /* Trigger on the next solicited completion */
3001 else if (ib_cqn_flags & IB_CQ_SOLICITED)
3002 type = DBR_DBR_TYPE_CQ_ARMSE;
3003
3004 /* Poll to see if there are missed events */
3005 if ((ib_cqn_flags & IB_CQ_REPORT_MISSED_EVENTS) &&
3006 !(bnxt_qplib_is_cq_empty(&cq->qplib_cq)))
3007 return 1;
3008
3009 bnxt_qplib_req_notify_cq(&cq->qplib_cq, type);
3010
3011 return 0;
3012 }
3013
3014 /* Memory Regions */
3015 struct ib_mr *bnxt_re_get_dma_mr(struct ib_pd *ib_pd, int mr_access_flags)
3016 {
3017 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3018 struct bnxt_re_dev *rdev = pd->rdev;
3019 struct bnxt_re_mr *mr;
3020 u64 pbl = 0;
3021 int rc;
3022
3023 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
3024 if (!mr)
3025 return ERR_PTR(-ENOMEM);
3026
3027 mr->rdev = rdev;
3028 mr->qplib_mr.pd = &pd->qplib_pd;
3029 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags);
3030 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
3031
3032 /* Allocate and register 0 as the address */
3033 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
3034 if (rc)
3035 goto fail;
3036
3037 mr->qplib_mr.hwq.level = PBL_LVL_MAX;
3038 mr->qplib_mr.total_size = -1; /* Infinte length */
3039 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, &pbl, 0, false);
3040 if (rc)
3041 goto fail_mr;
3042
3043 mr->ib_mr.lkey = mr->qplib_mr.lkey;
3044 if (mr_access_flags & (IB_ACCESS_REMOTE_WRITE | IB_ACCESS_REMOTE_READ |
3045 IB_ACCESS_REMOTE_ATOMIC))
3046 mr->ib_mr.rkey = mr->ib_mr.lkey;
3047 atomic_inc(&rdev->mr_count);
3048
3049 return &mr->ib_mr;
3050
3051 fail_mr:
3052 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3053 fail:
3054 kfree(mr);
3055 return ERR_PTR(rc);
3056 }
3057
3058 int bnxt_re_dereg_mr(struct ib_mr *ib_mr)
3059 {
3060 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
3061 struct bnxt_re_dev *rdev = mr->rdev;
3062 int rc;
3063
3064 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3065 if (rc) {
3066 dev_err(rdev_to_dev(rdev), "Dereg MR failed: %#x\n", rc);
3067 return rc;
3068 }
3069
3070 if (mr->npages && mr->pages) {
3071 rc = bnxt_qplib_free_fast_reg_page_list(&rdev->qplib_res,
3072 &mr->qplib_frpl);
3073 kfree(mr->pages);
3074 mr->npages = 0;
3075 mr->pages = NULL;
3076 }
3077 if (!IS_ERR_OR_NULL(mr->ib_umem))
3078 ib_umem_release(mr->ib_umem);
3079
3080 kfree(mr);
3081 atomic_dec(&rdev->mr_count);
3082 return rc;
3083 }
3084
3085 static int bnxt_re_set_page(struct ib_mr *ib_mr, u64 addr)
3086 {
3087 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
3088
3089 if (unlikely(mr->npages == mr->qplib_frpl.max_pg_ptrs))
3090 return -ENOMEM;
3091
3092 mr->pages[mr->npages++] = addr;
3093 return 0;
3094 }
3095
3096 int bnxt_re_map_mr_sg(struct ib_mr *ib_mr, struct scatterlist *sg, int sg_nents,
3097 unsigned int *sg_offset)
3098 {
3099 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
3100
3101 mr->npages = 0;
3102 return ib_sg_to_pages(ib_mr, sg, sg_nents, sg_offset, bnxt_re_set_page);
3103 }
3104
3105 struct ib_mr *bnxt_re_alloc_mr(struct ib_pd *ib_pd, enum ib_mr_type type,
3106 u32 max_num_sg)
3107 {
3108 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3109 struct bnxt_re_dev *rdev = pd->rdev;
3110 struct bnxt_re_mr *mr = NULL;
3111 int rc;
3112
3113 if (type != IB_MR_TYPE_MEM_REG) {
3114 dev_dbg(rdev_to_dev(rdev), "MR type 0x%x not supported", type);
3115 return ERR_PTR(-EINVAL);
3116 }
3117 if (max_num_sg > MAX_PBL_LVL_1_PGS)
3118 return ERR_PTR(-EINVAL);
3119
3120 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
3121 if (!mr)
3122 return ERR_PTR(-ENOMEM);
3123
3124 mr->rdev = rdev;
3125 mr->qplib_mr.pd = &pd->qplib_pd;
3126 mr->qplib_mr.flags = BNXT_QPLIB_FR_PMR;
3127 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
3128
3129 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
3130 if (rc)
3131 goto fail;
3132
3133 mr->ib_mr.lkey = mr->qplib_mr.lkey;
3134 mr->ib_mr.rkey = mr->ib_mr.lkey;
3135
3136 mr->pages = kcalloc(max_num_sg, sizeof(u64), GFP_KERNEL);
3137 if (!mr->pages) {
3138 rc = -ENOMEM;
3139 goto fail;
3140 }
3141 rc = bnxt_qplib_alloc_fast_reg_page_list(&rdev->qplib_res,
3142 &mr->qplib_frpl, max_num_sg);
3143 if (rc) {
3144 dev_err(rdev_to_dev(rdev),
3145 "Failed to allocate HW FR page list");
3146 goto fail_mr;
3147 }
3148
3149 atomic_inc(&rdev->mr_count);
3150 return &mr->ib_mr;
3151
3152 fail_mr:
3153 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3154 fail:
3155 kfree(mr->pages);
3156 kfree(mr);
3157 return ERR_PTR(rc);
3158 }
3159
3160 struct ib_mw *bnxt_re_alloc_mw(struct ib_pd *ib_pd, enum ib_mw_type type,
3161 struct ib_udata *udata)
3162 {
3163 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3164 struct bnxt_re_dev *rdev = pd->rdev;
3165 struct bnxt_re_mw *mw;
3166 int rc;
3167
3168 mw = kzalloc(sizeof(*mw), GFP_KERNEL);
3169 if (!mw)
3170 return ERR_PTR(-ENOMEM);
3171 mw->rdev = rdev;
3172 mw->qplib_mw.pd = &pd->qplib_pd;
3173
3174 mw->qplib_mw.type = (type == IB_MW_TYPE_1 ?
3175 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 :
3176 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B);
3177 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mw->qplib_mw);
3178 if (rc) {
3179 dev_err(rdev_to_dev(rdev), "Allocate MW failed!");
3180 goto fail;
3181 }
3182 mw->ib_mw.rkey = mw->qplib_mw.rkey;
3183
3184 atomic_inc(&rdev->mw_count);
3185 return &mw->ib_mw;
3186
3187 fail:
3188 kfree(mw);
3189 return ERR_PTR(rc);
3190 }
3191
3192 int bnxt_re_dealloc_mw(struct ib_mw *ib_mw)
3193 {
3194 struct bnxt_re_mw *mw = container_of(ib_mw, struct bnxt_re_mw, ib_mw);
3195 struct bnxt_re_dev *rdev = mw->rdev;
3196 int rc;
3197
3198 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mw->qplib_mw);
3199 if (rc) {
3200 dev_err(rdev_to_dev(rdev), "Free MW failed: %#x\n", rc);
3201 return rc;
3202 }
3203
3204 kfree(mw);
3205 atomic_dec(&rdev->mw_count);
3206 return rc;
3207 }
3208
3209 /* uverbs */
3210 struct ib_mr *bnxt_re_reg_user_mr(struct ib_pd *ib_pd, u64 start, u64 length,
3211 u64 virt_addr, int mr_access_flags,
3212 struct ib_udata *udata)
3213 {
3214 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3215 struct bnxt_re_dev *rdev = pd->rdev;
3216 struct bnxt_re_mr *mr;
3217 struct ib_umem *umem;
3218 u64 *pbl_tbl, *pbl_tbl_orig;
3219 int i, umem_pgs, pages, rc;
3220 struct scatterlist *sg;
3221 int entry;
3222
3223 if (length > BNXT_RE_MAX_MR_SIZE) {
3224 dev_err(rdev_to_dev(rdev), "MR Size: %lld > Max supported:%ld\n",
3225 length, BNXT_RE_MAX_MR_SIZE);
3226 return ERR_PTR(-ENOMEM);
3227 }
3228
3229 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
3230 if (!mr)
3231 return ERR_PTR(-ENOMEM);
3232
3233 mr->rdev = rdev;
3234 mr->qplib_mr.pd = &pd->qplib_pd;
3235 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags);
3236 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR;
3237
3238 umem = ib_umem_get(ib_pd->uobject->context, start, length,
3239 mr_access_flags, 0);
3240 if (IS_ERR(umem)) {
3241 dev_err(rdev_to_dev(rdev), "Failed to get umem");
3242 rc = -EFAULT;
3243 goto free_mr;
3244 }
3245 mr->ib_umem = umem;
3246
3247 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
3248 if (rc) {
3249 dev_err(rdev_to_dev(rdev), "Failed to allocate MR");
3250 goto release_umem;
3251 }
3252 /* The fixed portion of the rkey is the same as the lkey */
3253 mr->ib_mr.rkey = mr->qplib_mr.rkey;
3254
3255 mr->qplib_mr.va = virt_addr;
3256 umem_pgs = ib_umem_page_count(umem);
3257 if (!umem_pgs) {
3258 dev_err(rdev_to_dev(rdev), "umem is invalid!");
3259 rc = -EINVAL;
3260 goto free_mrw;
3261 }
3262 mr->qplib_mr.total_size = length;
3263
3264 pbl_tbl = kcalloc(umem_pgs, sizeof(u64 *), GFP_KERNEL);
3265 if (!pbl_tbl) {
3266 rc = -EINVAL;
3267 goto free_mrw;
3268 }
3269 pbl_tbl_orig = pbl_tbl;
3270
3271 if (umem->hugetlb) {
3272 dev_err(rdev_to_dev(rdev), "umem hugetlb not supported!");
3273 rc = -EFAULT;
3274 goto fail;
3275 }
3276
3277 if (umem->page_shift != PAGE_SHIFT) {
3278 dev_err(rdev_to_dev(rdev), "umem page shift unsupported!");
3279 rc = -EFAULT;
3280 goto fail;
3281 }
3282 /* Map umem buf ptrs to the PBL */
3283 for_each_sg(umem->sg_head.sgl, sg, umem->nmap, entry) {
3284 pages = sg_dma_len(sg) >> umem->page_shift;
3285 for (i = 0; i < pages; i++, pbl_tbl++)
3286 *pbl_tbl = sg_dma_address(sg) + (i << umem->page_shift);
3287 }
3288 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, pbl_tbl_orig,
3289 umem_pgs, false);
3290 if (rc) {
3291 dev_err(rdev_to_dev(rdev), "Failed to register user MR");
3292 goto fail;
3293 }
3294
3295 kfree(pbl_tbl_orig);
3296
3297 mr->ib_mr.lkey = mr->qplib_mr.lkey;
3298 mr->ib_mr.rkey = mr->qplib_mr.lkey;
3299 atomic_inc(&rdev->mr_count);
3300
3301 return &mr->ib_mr;
3302 fail:
3303 kfree(pbl_tbl_orig);
3304 free_mrw:
3305 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3306 release_umem:
3307 ib_umem_release(umem);
3308 free_mr:
3309 kfree(mr);
3310 return ERR_PTR(rc);
3311 }
3312
3313 struct ib_ucontext *bnxt_re_alloc_ucontext(struct ib_device *ibdev,
3314 struct ib_udata *udata)
3315 {
3316 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
3317 struct bnxt_re_uctx_resp resp;
3318 struct bnxt_re_ucontext *uctx;
3319 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
3320 int rc;
3321
3322 dev_dbg(rdev_to_dev(rdev), "ABI version requested %d",
3323 ibdev->uverbs_abi_ver);
3324
3325 if (ibdev->uverbs_abi_ver != BNXT_RE_ABI_VERSION) {
3326 dev_dbg(rdev_to_dev(rdev), " is different from the device %d ",
3327 BNXT_RE_ABI_VERSION);
3328 return ERR_PTR(-EPERM);
3329 }
3330
3331 uctx = kzalloc(sizeof(*uctx), GFP_KERNEL);
3332 if (!uctx)
3333 return ERR_PTR(-ENOMEM);
3334
3335 uctx->rdev = rdev;
3336
3337 uctx->shpg = (void *)__get_free_page(GFP_KERNEL);
3338 if (!uctx->shpg) {
3339 rc = -ENOMEM;
3340 goto fail;
3341 }
3342 spin_lock_init(&uctx->sh_lock);
3343
3344 resp.dev_id = rdev->en_dev->pdev->devfn; /*Temp, Use idr_alloc instead*/
3345 resp.max_qp = rdev->qplib_ctx.qpc_count;
3346 resp.pg_size = PAGE_SIZE;
3347 resp.cqe_sz = sizeof(struct cq_base);
3348 resp.max_cqd = dev_attr->max_cq_wqes;
3349 resp.rsvd = 0;
3350
3351 rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
3352 if (rc) {
3353 dev_err(rdev_to_dev(rdev), "Failed to copy user context");
3354 rc = -EFAULT;
3355 goto cfail;
3356 }
3357
3358 return &uctx->ib_uctx;
3359 cfail:
3360 free_page((unsigned long)uctx->shpg);
3361 uctx->shpg = NULL;
3362 fail:
3363 kfree(uctx);
3364 return ERR_PTR(rc);
3365 }
3366
3367 int bnxt_re_dealloc_ucontext(struct ib_ucontext *ib_uctx)
3368 {
3369 struct bnxt_re_ucontext *uctx = container_of(ib_uctx,
3370 struct bnxt_re_ucontext,
3371 ib_uctx);
3372
3373 struct bnxt_re_dev *rdev = uctx->rdev;
3374 int rc = 0;
3375
3376 if (uctx->shpg)
3377 free_page((unsigned long)uctx->shpg);
3378
3379 if (uctx->dpi.dbr) {
3380 /* Free DPI only if this is the first PD allocated by the
3381 * application and mark the context dpi as NULL
3382 */
3383 rc = bnxt_qplib_dealloc_dpi(&rdev->qplib_res,
3384 &rdev->qplib_res.dpi_tbl,
3385 &uctx->dpi);
3386 if (rc)
3387 dev_err(rdev_to_dev(rdev), "Deallocate HW DPI failed!");
3388 /* Don't fail, continue*/
3389 uctx->dpi.dbr = NULL;
3390 }
3391
3392 kfree(uctx);
3393 return 0;
3394 }
3395
3396 /* Helper function to mmap the virtual memory from user app */
3397 int bnxt_re_mmap(struct ib_ucontext *ib_uctx, struct vm_area_struct *vma)
3398 {
3399 struct bnxt_re_ucontext *uctx = container_of(ib_uctx,
3400 struct bnxt_re_ucontext,
3401 ib_uctx);
3402 struct bnxt_re_dev *rdev = uctx->rdev;
3403 u64 pfn;
3404
3405 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
3406 return -EINVAL;
3407
3408 if (vma->vm_pgoff) {
3409 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
3410 if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
3411 PAGE_SIZE, vma->vm_page_prot)) {
3412 dev_err(rdev_to_dev(rdev), "Failed to map DPI");
3413 return -EAGAIN;
3414 }
3415 } else {
3416 pfn = virt_to_phys(uctx->shpg) >> PAGE_SHIFT;
3417 if (remap_pfn_range(vma, vma->vm_start,
3418 pfn, PAGE_SIZE, vma->vm_page_prot)) {
3419 dev_err(rdev_to_dev(rdev),
3420 "Failed to map shared page");
3421 return -EAGAIN;
3422 }
3423 }
3424
3425 return 0;
3426 }
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