drivers/infiniband/hw/bnxt_re/qplib_rcfw.h

   1 /*
   2  * Broadcom NetXtreme-E RoCE driver.
   3  *
   4  * Copyright (c) 2016 - 2017, Broadcom. All rights reserved.  The term
   5  * Broadcom refers to Broadcom Limited and/or its subsidiaries.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * BSD license below:
  12  *
  13  * Redistribution and use in source and binary forms, with or without
  14  * modification, are permitted provided that the following conditions
  15  * are met:
  16  *
  17  * 1. Redistributions of source code must retain the above copyright
  18  *    notice, this list of conditions and the following disclaimer.
  19  * 2. Redistributions in binary form must reproduce the above copyright
  20  *    notice, this list of conditions and the following disclaimer in
  21  *    the documentation and/or other materials provided with the
  22  *    distribution.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
  25  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
  28  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  29  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  30  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  31  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  32  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  33  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  34  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  *
  36  * Description: RDMA Controller HW interface (header)
  37  */
  38
  39 #ifndef __BNXT_QPLIB_RCFW_H__
  40 #define __BNXT_QPLIB_RCFW_H__
  41
  42 #define RCFW_CMDQ_TRIG_VAL              1
  43 #define RCFW_COMM_PCI_BAR_REGION        0
  44 #define RCFW_COMM_CONS_PCI_BAR_REGION   2
  45 #define RCFW_COMM_BASE_OFFSET           0x600
  46 #define RCFW_PF_COMM_PROD_OFFSET        0xc
  47 #define RCFW_VF_COMM_PROD_OFFSET        0xc
  48 #define RCFW_COMM_TRIG_OFFSET           0x100
  49 #define RCFW_COMM_SIZE                  0x104
  50
  51 #define RCFW_DBR_PCI_BAR_REGION         2
  52
  53 #define RCFW_CMD_PREP(req, CMD, cmd_flags)                              \
  54         do {                                                            \
  55                 memset(&(req), 0, sizeof((req)));                       \
  56                 (req).opcode = CMDQ_BASE_OPCODE_##CMD;                  \
  57                 (req).cmd_size = (sizeof((req)) +                       \
  58                                 BNXT_QPLIB_CMDQE_UNITS - 1) /           \
  59                                 BNXT_QPLIB_CMDQE_UNITS;                 \
  60                 (req).flags = cpu_to_le16(cmd_flags);                   \
  61         } while (0)
  62
  63 #define RCFW_CMD_WAIT_TIME_MS           20000 /* 20 Seconds timeout */
  64
  65 /* CMDQ elements */
  66 #define BNXT_QPLIB_CMDQE_MAX_CNT        256
  67 #define BNXT_QPLIB_CMDQE_UNITS          sizeof(struct bnxt_qplib_cmdqe)
  68 #define BNXT_QPLIB_CMDQE_CNT_PER_PG     (PAGE_SIZE / BNXT_QPLIB_CMDQE_UNITS)
  69
  70 #define MAX_CMDQ_IDX                    (BNXT_QPLIB_CMDQE_MAX_CNT - 1)
  71 #define MAX_CMDQ_IDX_PER_PG             (BNXT_QPLIB_CMDQE_CNT_PER_PG - 1)
  72
  73 #define RCFW_MAX_OUTSTANDING_CMD        BNXT_QPLIB_CMDQE_MAX_CNT
  74 #define RCFW_MAX_COOKIE_VALUE           0x7FFF
  75 #define RCFW_CMD_IS_BLOCKING            0x8000
  76 #define RCFW_BLOCKED_CMD_WAIT_COUNT     0x4E20
  77
  78 /* Cmdq contains a fix number of a 16-Byte slots */
  79 struct bnxt_qplib_cmdqe {
  80         u8              data[16];
  81 };
  82
  83 static inline u32 get_cmdq_pg(u32 val)
  84 {
  85         return (val & ~MAX_CMDQ_IDX_PER_PG) / BNXT_QPLIB_CMDQE_CNT_PER_PG;
  86 }
  87
  88 static inline u32 get_cmdq_idx(u32 val)
  89 {
  90         return val & MAX_CMDQ_IDX_PER_PG;
  91 }
  92
  93 /* Crsq buf is 1024-Byte */
  94 struct bnxt_qplib_crsbe {
  95         u8                      data[1024];
  96 };
  97
  98 /* CREQ */
  99 /* Allocate 1 per QP for async error notification for now */
 100 #define BNXT_QPLIB_CREQE_MAX_CNT        (64 * 1024)
 101 #define BNXT_QPLIB_CREQE_UNITS          16      /* 16-Bytes per prod unit */
 102 #define BNXT_QPLIB_CREQE_CNT_PER_PG     (PAGE_SIZE / BNXT_QPLIB_CREQE_UNITS)
 103
 104 #define MAX_CREQ_IDX                    (BNXT_QPLIB_CREQE_MAX_CNT - 1)
 105 #define MAX_CREQ_IDX_PER_PG             (BNXT_QPLIB_CREQE_CNT_PER_PG - 1)
 106
 107 static inline u32 get_creq_pg(u32 val)
 108 {
 109         return (val & ~MAX_CREQ_IDX_PER_PG) / BNXT_QPLIB_CREQE_CNT_PER_PG;
 110 }
 111
 112 static inline u32 get_creq_idx(u32 val)
 113 {
 114         return val & MAX_CREQ_IDX_PER_PG;
 115 }
 116
 117 #define BNXT_QPLIB_CREQE_PER_PG (PAGE_SIZE / sizeof(struct creq_base))
 118
 119 #define CREQ_CMP_VALID(hdr, raw_cons, cp_bit)                   \
 120         (!!((hdr)->v & CREQ_BASE_V) ==                          \
 121            !((raw_cons) & (cp_bit)))
 122
 123 #define CREQ_DB_KEY_CP                  (0x2 << CMPL_DOORBELL_KEY_SFT)
 124 #define CREQ_DB_IDX_VALID               CMPL_DOORBELL_IDX_VALID
 125 #define CREQ_DB_IRQ_DIS                 CMPL_DOORBELL_MASK
 126 #define CREQ_DB_CP_FLAGS_REARM          (CREQ_DB_KEY_CP |       \
 127                                          CREQ_DB_IDX_VALID)
 128 #define CREQ_DB_CP_FLAGS                (CREQ_DB_KEY_CP |       \
 129                                          CREQ_DB_IDX_VALID |    \
 130                                          CREQ_DB_IRQ_DIS)
 131 #define CREQ_DB_REARM(db, raw_cons, cp_bit)                     \
 132         writel(CREQ_DB_CP_FLAGS_REARM | ((raw_cons) & ((cp_bit) - 1)), db)
 133 #define CREQ_DB(db, raw_cons, cp_bit)                           \
 134         writel(CREQ_DB_CP_FLAGS | ((raw_cons) & ((cp_bit) - 1)), db)
 135
 136 #define CREQ_ENTRY_POLL_BUDGET          0x100
 137
 138 /* HWQ */
 139
 140 struct bnxt_qplib_crsq {
 141         struct creq_qp_event    *resp;
 142         u32                     req_size;
 143 };
 144
 145 struct bnxt_qplib_rcfw_sbuf {
 146         void *sb;
 147         dma_addr_t dma_addr;
 148         u32 size;
 149 };
 150
 151 struct bnxt_qplib_qp_node {
 152         u32 qp_id;              /* QP id */
 153         void *qp_handle;        /* ptr to qplib_qp */
 154 };
 155
 156 /* RCFW Communication Channels */
 157 struct bnxt_qplib_rcfw {
 158         struct pci_dev          *pdev;
 159         int                     vector;
 160         struct tasklet_struct   worker;
 161         bool                    requested;
 162         unsigned long           *cmdq_bitmap;
 163         u32                     bmap_size;
 164         unsigned long           flags;
 165 #define FIRMWARE_INITIALIZED_FLAG       BIT(0)
 166 #define FIRMWARE_FIRST_FLAG             BIT(31)
 167 #define FIRMWARE_TIMED_OUT              BIT(3)
 168         wait_queue_head_t       waitq;
 169         int                     (*aeq_handler)(struct bnxt_qplib_rcfw *,
 170                                                struct creq_func_event *);
 171         u32                     seq_num;
 172
 173         /* Bar region info */
 174         void __iomem            *cmdq_bar_reg_iomem;
 175         u16                     cmdq_bar_reg;
 176         u16                     cmdq_bar_reg_prod_off;
 177         u16                     cmdq_bar_reg_trig_off;
 178         u16                     creq_ring_id;
 179         u16                     creq_bar_reg;
 180         void __iomem            *creq_bar_reg_iomem;
 181
 182         /* Cmd-Resp and Async Event notification queue */
 183         struct bnxt_qplib_hwq   creq;
 184         u64                     creq_qp_event_processed;
 185         u64                     creq_func_event_processed;
 186
 187         /* Actual Cmd and Resp Queues */
 188         struct bnxt_qplib_hwq   cmdq;
 189         struct bnxt_qplib_crsq  *crsqe_tbl;
 190         int qp_tbl_size;
 191         struct bnxt_qplib_qp_node *qp_tbl;
 192 };
 193
 194 void bnxt_qplib_free_rcfw_channel(struct bnxt_qplib_rcfw *rcfw);
 195 int bnxt_qplib_alloc_rcfw_channel(struct pci_dev *pdev,
 196                                   struct bnxt_qplib_rcfw *rcfw, int qp_tbl_sz);
 197 void bnxt_qplib_disable_rcfw_channel(struct bnxt_qplib_rcfw *rcfw);
 198 int bnxt_qplib_enable_rcfw_channel(struct pci_dev *pdev,
 199                                    struct bnxt_qplib_rcfw *rcfw,
 200                                    int msix_vector,
 201                                    int cp_bar_reg_off, int virt_fn,
 202                                    int (*aeq_handler)
 203                                         (struct bnxt_qplib_rcfw *,
 204                                          struct creq_func_event *));
 205
 206 struct bnxt_qplib_rcfw_sbuf *bnxt_qplib_rcfw_alloc_sbuf(
 207                                 struct bnxt_qplib_rcfw *rcfw,
 208                                 u32 size);
 209 void bnxt_qplib_rcfw_free_sbuf(struct bnxt_qplib_rcfw *rcfw,
 210                                struct bnxt_qplib_rcfw_sbuf *sbuf);
 211 int bnxt_qplib_rcfw_send_message(struct bnxt_qplib_rcfw *rcfw,
 212                                  struct cmdq_base *req, struct creq_base *resp,
 213                                  void *sbuf, u8 is_block);
 214
 215 int bnxt_qplib_deinit_rcfw(struct bnxt_qplib_rcfw *rcfw);
 216 int bnxt_qplib_init_rcfw(struct bnxt_qplib_rcfw *rcfw,
 217                          struct bnxt_qplib_ctx *ctx, int is_virtfn);
 218 void bnxt_qplib_mark_qp_error(void *qp_handle);
 219 #endif /* __BNXT_QPLIB_RCFW_H__ */