drivers/infiniband/hw/bnxt_re/qplib_res.h

   1 /*
   2  * Broadcom NetXtreme-E RoCE driver.
   3  *
   4  * Copyright (c) 2016 - 2017, Broadcom. All rights reserved.  The term
   5  * Broadcom refers to Broadcom Limited and/or its subsidiaries.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * BSD license below:
  12  *
  13  * Redistribution and use in source and binary forms, with or without
  14  * modification, are permitted provided that the following conditions
  15  * are met:
  16  *
  17  * 1. Redistributions of source code must retain the above copyright
  18  *    notice, this list of conditions and the following disclaimer.
  19  * 2. Redistributions in binary form must reproduce the above copyright
  20  *    notice, this list of conditions and the following disclaimer in
  21  *    the documentation and/or other materials provided with the
  22  *    distribution.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
  25  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
  28  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  29  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  30  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  31  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  32  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  33  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  34  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  *
  36  * Description: QPLib resource manager (header)
  37  */
  38
  39 #ifndef __BNXT_QPLIB_RES_H__
  40 #define __BNXT_QPLIB_RES_H__
  41
  42 extern const struct bnxt_qplib_gid bnxt_qplib_gid_zero;
  43
  44 #define PTR_CNT_PER_PG          (PAGE_SIZE / sizeof(void *))
  45 #define PTR_MAX_IDX_PER_PG      (PTR_CNT_PER_PG - 1)
  46 #define PTR_PG(x)               (((x) & ~PTR_MAX_IDX_PER_PG) / PTR_CNT_PER_PG)
  47 #define PTR_IDX(x)              ((x) & PTR_MAX_IDX_PER_PG)
  48
  49 #define HWQ_CMP(idx, hwq)       ((idx) & ((hwq)->max_elements - 1))
  50
  51 enum bnxt_qplib_hwq_type {
  52         HWQ_TYPE_CTX,
  53         HWQ_TYPE_QUEUE,
  54         HWQ_TYPE_L2_CMPL
  55 };
  56
  57 #define MAX_PBL_LVL_0_PGS               1
  58 #define MAX_PBL_LVL_1_PGS               512
  59 #define MAX_PBL_LVL_1_PGS_SHIFT         9
  60 #define MAX_PBL_LVL_1_PGS_FOR_LVL_2     256
  61 #define MAX_PBL_LVL_2_PGS               (256 * 512)
  62
  63 enum bnxt_qplib_pbl_lvl {
  64         PBL_LVL_0,
  65         PBL_LVL_1,
  66         PBL_LVL_2,
  67         PBL_LVL_MAX
  68 };
  69
  70 #define ROCE_PG_SIZE_4K         (4 * 1024)
  71 #define ROCE_PG_SIZE_8K         (8 * 1024)
  72 #define ROCE_PG_SIZE_64K        (64 * 1024)
  73 #define ROCE_PG_SIZE_2M         (2 * 1024 * 1024)
  74 #define ROCE_PG_SIZE_8M         (8 * 1024 * 1024)
  75 #define ROCE_PG_SIZE_1G         (1024 * 1024 * 1024)
  76
  77 struct bnxt_qplib_pbl {
  78         u32                             pg_count;
  79         u32                             pg_size;
  80         void                            **pg_arr;
  81         dma_addr_t                      *pg_map_arr;
  82 };
  83
  84 struct bnxt_qplib_hwq {
  85         struct pci_dev                  *pdev;
  86         /* lock to protect qplib_hwq */
  87         spinlock_t                      lock;
  88         struct bnxt_qplib_pbl           pbl[PBL_LVL_MAX];
  89         enum bnxt_qplib_pbl_lvl         level;          /* 0, 1, or 2 */
  90         /* ptr for easy access to the PBL entries */
  91         void                            **pbl_ptr;
  92         /* ptr for easy access to the dma_addr */
  93         dma_addr_t                      *pbl_dma_ptr;
  94         u32                             max_elements;
  95         u16                             element_size;   /* Size of each entry */
  96
  97         u32                             prod;           /* raw */
  98         u32                             cons;           /* raw */
  99         u8                              cp_bit;
 100         u8                              is_user;
 101 };
 102
 103 /* Tables */
 104 struct bnxt_qplib_pd_tbl {
 105         unsigned long                   *tbl;
 106         u32                             max;
 107 };
 108
 109 struct bnxt_qplib_sgid_tbl {
 110         struct bnxt_qplib_gid           *tbl;
 111         u16                             *hw_id;
 112         u16                             max;
 113         u16                             active;
 114         void                            *ctx;
 115 };
 116
 117 struct bnxt_qplib_pkey_tbl {
 118         u16                             *tbl;
 119         u16                             max;
 120         u16                             active;
 121 };
 122
 123 struct bnxt_qplib_dpi {
 124         u32                             dpi;
 125         void __iomem                    *dbr;
 126         u64                             umdbr;
 127 };
 128
 129 struct bnxt_qplib_dpi_tbl {
 130         void                            **app_tbl;
 131         unsigned long                   *tbl;
 132         u16                             max;
 133         void __iomem                    *dbr_bar_reg_iomem;
 134         u64                             unmapped_dbr;
 135 };
 136
 137 struct bnxt_qplib_stats {
 138         dma_addr_t                      dma_map;
 139         void                            *dma;
 140         u32                             size;
 141         u32                             fw_id;
 142 };
 143
 144 struct bnxt_qplib_vf_res {
 145         u32 max_qp_per_vf;
 146         u32 max_mrw_per_vf;
 147         u32 max_srq_per_vf;
 148         u32 max_cq_per_vf;
 149         u32 max_gid_per_vf;
 150 };
 151
 152 #define BNXT_QPLIB_MAX_QP_CTX_ENTRY_SIZE        448
 153 #define BNXT_QPLIB_MAX_SRQ_CTX_ENTRY_SIZE       64
 154 #define BNXT_QPLIB_MAX_CQ_CTX_ENTRY_SIZE        64
 155 #define BNXT_QPLIB_MAX_MRW_CTX_ENTRY_SIZE       128
 156
 157 struct bnxt_qplib_ctx {
 158         u32                             qpc_count;
 159         struct bnxt_qplib_hwq           qpc_tbl;
 160         u32                             mrw_count;
 161         struct bnxt_qplib_hwq           mrw_tbl;
 162         u32                             srqc_count;
 163         struct bnxt_qplib_hwq           srqc_tbl;
 164         u32                             cq_count;
 165         struct bnxt_qplib_hwq           cq_tbl;
 166         struct bnxt_qplib_hwq           tim_tbl;
 167 #define MAX_TQM_ALLOC_REQ               32
 168 #define MAX_TQM_ALLOC_BLK_SIZE          8
 169         u8                              tqm_count[MAX_TQM_ALLOC_REQ];
 170         struct bnxt_qplib_hwq           tqm_pde;
 171         u32                             tqm_pde_level;
 172         struct bnxt_qplib_hwq           tqm_tbl[MAX_TQM_ALLOC_REQ];
 173         struct bnxt_qplib_stats         stats;
 174         struct bnxt_qplib_vf_res        vf_res;
 175 };
 176
 177 struct bnxt_qplib_res {
 178         struct pci_dev                  *pdev;
 179         struct net_device               *netdev;
 180
 181         struct bnxt_qplib_rcfw          *rcfw;
 182
 183         struct bnxt_qplib_pd_tbl        pd_tbl;
 184         struct bnxt_qplib_sgid_tbl      sgid_tbl;
 185         struct bnxt_qplib_pkey_tbl      pkey_tbl;
 186         struct bnxt_qplib_dpi_tbl       dpi_tbl;
 187 };
 188
 189 #define to_bnxt_qplib(ptr, type, member)        \
 190         container_of(ptr, type, member)
 191
 192 struct bnxt_qplib_pd;
 193 struct bnxt_qplib_dev_attr;
 194
 195 void bnxt_qplib_free_hwq(struct pci_dev *pdev, struct bnxt_qplib_hwq *hwq);
 196 int bnxt_qplib_alloc_init_hwq(struct pci_dev *pdev, struct bnxt_qplib_hwq *hwq,
 197                               struct scatterlist *sl, int nmap, u32 *elements,
 198                               u32 elements_per_page, u32 aux, u32 pg_size,
 199                               enum bnxt_qplib_hwq_type hwq_type);
 200 void bnxt_qplib_get_guid(u8 *dev_addr, u8 *guid);
 201 int bnxt_qplib_alloc_pd(struct bnxt_qplib_pd_tbl *pd_tbl,
 202                         struct bnxt_qplib_pd *pd);
 203 int bnxt_qplib_dealloc_pd(struct bnxt_qplib_res *res,
 204                           struct bnxt_qplib_pd_tbl *pd_tbl,
 205                           struct bnxt_qplib_pd *pd);
 206 int bnxt_qplib_alloc_dpi(struct bnxt_qplib_dpi_tbl *dpit,
 207                          struct bnxt_qplib_dpi     *dpi,
 208                          void                      *app);
 209 int bnxt_qplib_dealloc_dpi(struct bnxt_qplib_res *res,
 210                            struct bnxt_qplib_dpi_tbl *dpi_tbl,
 211                            struct bnxt_qplib_dpi *dpi);
 212 void bnxt_qplib_cleanup_res(struct bnxt_qplib_res *res);
 213 int bnxt_qplib_init_res(struct bnxt_qplib_res *res);
 214 void bnxt_qplib_free_res(struct bnxt_qplib_res *res);
 215 int bnxt_qplib_alloc_res(struct bnxt_qplib_res *res, struct pci_dev *pdev,
 216                          struct net_device *netdev,
 217                          struct bnxt_qplib_dev_attr *dev_attr);
 218 void bnxt_qplib_free_ctx(struct pci_dev *pdev,
 219                          struct bnxt_qplib_ctx *ctx);
 220 int bnxt_qplib_alloc_ctx(struct pci_dev *pdev,
 221                          struct bnxt_qplib_ctx *ctx,
 222                          bool virt_fn);
 223 #endif /* __BNXT_QPLIB_RES_H__ */