]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - drivers/infiniband/hw/cxgb3/cxio_hal.c
projects / mirror_ubuntu-artful-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
networking: make skb_put & friends return void pointers
[mirror_ubuntu-artful-kernel.git] / drivers / infiniband / hw / cxgb3 / cxio_hal.c
1 /*
2 * Copyright (c) 2006 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32 #include <asm/delay.h>
33
34 #include <linux/mutex.h>
35 #include <linux/netdevice.h>
36 #include <linux/sched.h>
37 #include <linux/spinlock.h>
38 #include <linux/pci.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/slab.h>
41 #include <net/net_namespace.h>
42
43 #include "cxio_resource.h"
44 #include "cxio_hal.h"
45 #include "cxgb3_offload.h"
46 #include "sge_defs.h"
47
48 static LIST_HEAD(rdev_list);
49 static cxio_hal_ev_callback_func_t cxio_ev_cb = NULL;
50
51 static struct cxio_rdev *cxio_hal_find_rdev_by_name(char *dev_name)
52 {
53 struct cxio_rdev *rdev;
54
55 list_for_each_entry(rdev, &rdev_list, entry)
56 if (!strcmp(rdev->dev_name, dev_name))
57 return rdev;
58 return NULL;
59 }
60
61 static struct cxio_rdev *cxio_hal_find_rdev_by_t3cdev(struct t3cdev *tdev)
62 {
63 struct cxio_rdev *rdev;
64
65 list_for_each_entry(rdev, &rdev_list, entry)
66 if (rdev->t3cdev_p == tdev)
67 return rdev;
68 return NULL;
69 }
70
71 int cxio_hal_cq_op(struct cxio_rdev *rdev_p, struct t3_cq *cq,
72 enum t3_cq_opcode op, u32 credit)
73 {
74 int ret;
75 struct t3_cqe *cqe;
76 u32 rptr;
77
78 struct rdma_cq_op setup;
79 setup.id = cq->cqid;
80 setup.credits = (op == CQ_CREDIT_UPDATE) ? credit : 0;
81 setup.op = op;
82 ret = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_OP, &setup);
83
84 if ((ret < 0) || (op == CQ_CREDIT_UPDATE))
85 return ret;
86
87 /*
88 * If the rearm returned an index other than our current index,
89 * then there might be CQE's in flight (being DMA'd). We must wait
90 * here for them to complete or the consumer can miss a notification.
91 */
92 if (Q_PTR2IDX((cq->rptr), cq->size_log2) != ret) {
93 int i=0;
94
95 rptr = cq->rptr;
96
97 /*
98 * Keep the generation correct by bumping rptr until it
99 * matches the index returned by the rearm - 1.
100 */
101 while (Q_PTR2IDX((rptr+1), cq->size_log2) != ret)
102 rptr++;
103
104 /*
105 * Now rptr is the index for the (last) cqe that was
106 * in-flight at the time the HW rearmed the CQ. We
107 * spin until that CQE is valid.
108 */
109 cqe = cq->queue + Q_PTR2IDX(rptr, cq->size_log2);
110 while (!CQ_VLD_ENTRY(rptr, cq->size_log2, cqe)) {
111 udelay(1);
112 if (i++ > 1000000) {
113 pr_err("%s: stalled rnic\n", rdev_p->dev_name);
114 return -EIO;
115 }
116 }
117
118 return 1;
119 }
120
121 return 0;
122 }
123
124 static int cxio_hal_clear_cq_ctx(struct cxio_rdev *rdev_p, u32 cqid)
125 {
126 struct rdma_cq_setup setup;
127 setup.id = cqid;
128 setup.base_addr = 0; /* NULL address */
129 setup.size = 0; /* disaable the CQ */
130 setup.credits = 0;
131 setup.credit_thres = 0;
132 setup.ovfl_mode = 0;
133 return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
134 }
135
136 static int cxio_hal_clear_qp_ctx(struct cxio_rdev *rdev_p, u32 qpid)
137 {
138 u64 sge_cmd;
139 struct t3_modify_qp_wr *wqe;
140 struct sk_buff *skb = alloc_skb(sizeof(*wqe), GFP_KERNEL);
141 if (!skb) {
142 pr_debug("%s alloc_skb failed\n", __func__);
143 return -ENOMEM;
144 }
145 wqe = skb_put_zero(skb, sizeof(*wqe));
146 build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_QP_MOD,
147 T3_COMPLETION_FLAG | T3_NOTIFY_FLAG, 0, qpid, 7,
148 T3_SOPEOP);
149 wqe->flags = cpu_to_be32(MODQP_WRITE_EC);
150 sge_cmd = qpid << 8 | 3;
151 wqe->sge_cmd = cpu_to_be64(sge_cmd);
152 skb->priority = CPL_PRIORITY_CONTROL;
153 return iwch_cxgb3_ofld_send(rdev_p->t3cdev_p, skb);
154 }
155
156 int cxio_create_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq, int kernel)
157 {
158 struct rdma_cq_setup setup;
159 int size = (1UL << (cq->size_log2)) * sizeof(struct t3_cqe);
160
161 size += 1; /* one extra page for storing cq-in-err state */
162 cq->cqid = cxio_hal_get_cqid(rdev_p->rscp);
163 if (!cq->cqid)
164 return -ENOMEM;
165 if (kernel) {
166 cq->sw_queue = kzalloc(size, GFP_KERNEL);
167 if (!cq->sw_queue)
168 return -ENOMEM;
169 }
170 cq->queue = dma_alloc_coherent(&(rdev_p->rnic_info.pdev->dev), size,
171 &(cq->dma_addr), GFP_KERNEL);
172 if (!cq->queue) {
173 kfree(cq->sw_queue);
174 return -ENOMEM;
175 }
176 dma_unmap_addr_set(cq, mapping, cq->dma_addr);
177 memset(cq->queue, 0, size);
178 setup.id = cq->cqid;
179 setup.base_addr = (u64) (cq->dma_addr);
180 setup.size = 1UL << cq->size_log2;
181 setup.credits = 65535;
182 setup.credit_thres = 1;
183 if (rdev_p->t3cdev_p->type != T3A)
184 setup.ovfl_mode = 0;
185 else
186 setup.ovfl_mode = 1;
187 return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
188 }
189
190 #ifdef notyet
191 int cxio_resize_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq)
192 {
193 struct rdma_cq_setup setup;
194 setup.id = cq->cqid;
195 setup.base_addr = (u64) (cq->dma_addr);
196 setup.size = 1UL << cq->size_log2;
197 setup.credits = setup.size;
198 setup.credit_thres = setup.size; /* TBD: overflow recovery */
199 setup.ovfl_mode = 1;
200 return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
201 }
202 #endif
203
204 static u32 get_qpid(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx)
205 {
206 struct cxio_qpid_list *entry;
207 u32 qpid;
208 int i;
209
210 mutex_lock(&uctx->lock);
211 if (!list_empty(&uctx->qpids)) {
212 entry = list_entry(uctx->qpids.next, struct cxio_qpid_list,
213 entry);
214 list_del(&entry->entry);
215 qpid = entry->qpid;
216 kfree(entry);
217 } else {
218 qpid = cxio_hal_get_qpid(rdev_p->rscp);
219 if (!qpid)
220 goto out;
221 for (i = qpid+1; i & rdev_p->qpmask; i++) {
222 entry = kmalloc(sizeof *entry, GFP_KERNEL);
223 if (!entry)
224 break;
225 entry->qpid = i;
226 list_add_tail(&entry->entry, &uctx->qpids);
227 }
228 }
229 out:
230 mutex_unlock(&uctx->lock);
231 pr_debug("%s qpid 0x%x\n", __func__, qpid);
232 return qpid;
233 }
234
235 static void put_qpid(struct cxio_rdev *rdev_p, u32 qpid,
236 struct cxio_ucontext *uctx)
237 {
238 struct cxio_qpid_list *entry;
239
240 entry = kmalloc(sizeof *entry, GFP_KERNEL);
241 if (!entry)
242 return;
243 pr_debug("%s qpid 0x%x\n", __func__, qpid);
244 entry->qpid = qpid;
245 mutex_lock(&uctx->lock);
246 list_add_tail(&entry->entry, &uctx->qpids);
247 mutex_unlock(&uctx->lock);
248 }
249
250 void cxio_release_ucontext(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx)
251 {
252 struct list_head *pos, *nxt;
253 struct cxio_qpid_list *entry;
254
255 mutex_lock(&uctx->lock);
256 list_for_each_safe(pos, nxt, &uctx->qpids) {
257 entry = list_entry(pos, struct cxio_qpid_list, entry);
258 list_del_init(&entry->entry);
259 if (!(entry->qpid & rdev_p->qpmask))
260 cxio_hal_put_qpid(rdev_p->rscp, entry->qpid);
261 kfree(entry);
262 }
263 mutex_unlock(&uctx->lock);
264 }
265
266 void cxio_init_ucontext(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx)
267 {
268 INIT_LIST_HEAD(&uctx->qpids);
269 mutex_init(&uctx->lock);
270 }
271
272 int cxio_create_qp(struct cxio_rdev *rdev_p, u32 kernel_domain,
273 struct t3_wq *wq, struct cxio_ucontext *uctx)
274 {
275 int depth = 1UL << wq->size_log2;
276 int rqsize = 1UL << wq->rq_size_log2;
277
278 wq->qpid = get_qpid(rdev_p, uctx);
279 if (!wq->qpid)
280 return -ENOMEM;
281
282 wq->rq = kzalloc(depth * sizeof(struct t3_swrq), GFP_KERNEL);
283 if (!wq->rq)
284 goto err1;
285
286 wq->rq_addr = cxio_hal_rqtpool_alloc(rdev_p, rqsize);
287 if (!wq->rq_addr)
288 goto err2;
289
290 wq->sq = kzalloc(depth * sizeof(struct t3_swsq), GFP_KERNEL);
291 if (!wq->sq)
292 goto err3;
293
294 wq->queue = dma_alloc_coherent(&(rdev_p->rnic_info.pdev->dev),
295 depth * sizeof(union t3_wr),
296 &(wq->dma_addr), GFP_KERNEL);
297 if (!wq->queue)
298 goto err4;
299
300 memset(wq->queue, 0, depth * sizeof(union t3_wr));
301 dma_unmap_addr_set(wq, mapping, wq->dma_addr);
302 wq->doorbell = (void __iomem *)rdev_p->rnic_info.kdb_addr;
303 if (!kernel_domain)
304 wq->udb = (u64)rdev_p->rnic_info.udbell_physbase +
305 (wq->qpid << rdev_p->qpshift);
306 wq->rdev = rdev_p;
307 pr_debug("%s qpid 0x%x doorbell 0x%p udb 0x%llx\n",
308 __func__, wq->qpid, wq->doorbell, (unsigned long long)wq->udb);
309 return 0;
310 err4:
311 kfree(wq->sq);
312 err3:
313 cxio_hal_rqtpool_free(rdev_p, wq->rq_addr, rqsize);
314 err2:
315 kfree(wq->rq);
316 err1:
317 put_qpid(rdev_p, wq->qpid, uctx);
318 return -ENOMEM;
319 }
320
321 int cxio_destroy_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq)
322 {
323 int err;
324 err = cxio_hal_clear_cq_ctx(rdev_p, cq->cqid);
325 kfree(cq->sw_queue);
326 dma_free_coherent(&(rdev_p->rnic_info.pdev->dev),
327 (1UL << (cq->size_log2))
328 * sizeof(struct t3_cqe) + 1, cq->queue,
329 dma_unmap_addr(cq, mapping));
330 cxio_hal_put_cqid(rdev_p->rscp, cq->cqid);
331 return err;
332 }
333
334 int cxio_destroy_qp(struct cxio_rdev *rdev_p, struct t3_wq *wq,
335 struct cxio_ucontext *uctx)
336 {
337 dma_free_coherent(&(rdev_p->rnic_info.pdev->dev),
338 (1UL << (wq->size_log2))
339 * sizeof(union t3_wr), wq->queue,
340 dma_unmap_addr(wq, mapping));
341 kfree(wq->sq);
342 cxio_hal_rqtpool_free(rdev_p, wq->rq_addr, (1UL << wq->rq_size_log2));
343 kfree(wq->rq);
344 put_qpid(rdev_p, wq->qpid, uctx);
345 return 0;
346 }
347
348 static void insert_recv_cqe(struct t3_wq *wq, struct t3_cq *cq)
349 {
350 struct t3_cqe cqe;
351
352 pr_debug("%s wq %p cq %p sw_rptr 0x%x sw_wptr 0x%x\n", __func__,
353 wq, cq, cq->sw_rptr, cq->sw_wptr);
354 memset(&cqe, 0, sizeof(cqe));
355 cqe.header = cpu_to_be32(V_CQE_STATUS(TPT_ERR_SWFLUSH) |
356 V_CQE_OPCODE(T3_SEND) |
357 V_CQE_TYPE(0) |
358 V_CQE_SWCQE(1) |
359 V_CQE_QPID(wq->qpid) |
360 V_CQE_GENBIT(Q_GENBIT(cq->sw_wptr,
361 cq->size_log2)));
362 *(cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2)) = cqe;
363 cq->sw_wptr++;
364 }
365
366 int cxio_flush_rq(struct t3_wq *wq, struct t3_cq *cq, int count)
367 {
368 u32 ptr;
369 int flushed = 0;
370
371 pr_debug("%s wq %p cq %p\n", __func__, wq, cq);
372
373 /* flush RQ */
374 pr_debug("%s rq_rptr %u rq_wptr %u skip count %u\n", __func__,
375 wq->rq_rptr, wq->rq_wptr, count);
376 ptr = wq->rq_rptr + count;
377 while (ptr++ != wq->rq_wptr) {
378 insert_recv_cqe(wq, cq);
379 flushed++;
380 }
381 return flushed;
382 }
383
384 static void insert_sq_cqe(struct t3_wq *wq, struct t3_cq *cq,
385 struct t3_swsq *sqp)
386 {
387 struct t3_cqe cqe;
388
389 pr_debug("%s wq %p cq %p sw_rptr 0x%x sw_wptr 0x%x\n", __func__,
390 wq, cq, cq->sw_rptr, cq->sw_wptr);
391 memset(&cqe, 0, sizeof(cqe));
392 cqe.header = cpu_to_be32(V_CQE_STATUS(TPT_ERR_SWFLUSH) |
393 V_CQE_OPCODE(sqp->opcode) |
394 V_CQE_TYPE(1) |
395 V_CQE_SWCQE(1) |
396 V_CQE_QPID(wq->qpid) |
397 V_CQE_GENBIT(Q_GENBIT(cq->sw_wptr,
398 cq->size_log2)));
399 cqe.u.scqe.wrid_hi = sqp->sq_wptr;
400
401 *(cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2)) = cqe;
402 cq->sw_wptr++;
403 }
404
405 int cxio_flush_sq(struct t3_wq *wq, struct t3_cq *cq, int count)
406 {
407 __u32 ptr;
408 int flushed = 0;
409 struct t3_swsq *sqp = wq->sq + Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2);
410
411 ptr = wq->sq_rptr + count;
412 sqp = wq->sq + Q_PTR2IDX(ptr, wq->sq_size_log2);
413 while (ptr != wq->sq_wptr) {
414 sqp->signaled = 0;
415 insert_sq_cqe(wq, cq, sqp);
416 ptr++;
417 sqp = wq->sq + Q_PTR2IDX(ptr, wq->sq_size_log2);
418 flushed++;
419 }
420 return flushed;
421 }
422
423 /*
424 * Move all CQEs from the HWCQ into the SWCQ.
425 */
426 void cxio_flush_hw_cq(struct t3_cq *cq)
427 {
428 struct t3_cqe *cqe, *swcqe;
429
430 pr_debug("%s cq %p cqid 0x%x\n", __func__, cq, cq->cqid);
431 cqe = cxio_next_hw_cqe(cq);
432 while (cqe) {
433 pr_debug("%s flushing hwcq rptr 0x%x to swcq wptr 0x%x\n",
434 __func__, cq->rptr, cq->sw_wptr);
435 swcqe = cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2);
436 *swcqe = *cqe;
437 swcqe->header |= cpu_to_be32(V_CQE_SWCQE(1));
438 cq->sw_wptr++;
439 cq->rptr++;
440 cqe = cxio_next_hw_cqe(cq);
441 }
442 }
443
444 static int cqe_completes_wr(struct t3_cqe *cqe, struct t3_wq *wq)
445 {
446 if (CQE_OPCODE(*cqe) == T3_TERMINATE)
447 return 0;
448
449 if ((CQE_OPCODE(*cqe) == T3_RDMA_WRITE) && RQ_TYPE(*cqe))
450 return 0;
451
452 if ((CQE_OPCODE(*cqe) == T3_READ_RESP) && SQ_TYPE(*cqe))
453 return 0;
454
455 if (CQE_SEND_OPCODE(*cqe) && RQ_TYPE(*cqe) &&
456 Q_EMPTY(wq->rq_rptr, wq->rq_wptr))
457 return 0;
458
459 return 1;
460 }
461
462 void cxio_count_scqes(struct t3_cq *cq, struct t3_wq *wq, int *count)
463 {
464 struct t3_cqe *cqe;
465 u32 ptr;
466
467 *count = 0;
468 ptr = cq->sw_rptr;
469 while (!Q_EMPTY(ptr, cq->sw_wptr)) {
470 cqe = cq->sw_queue + (Q_PTR2IDX(ptr, cq->size_log2));
471 if ((SQ_TYPE(*cqe) ||
472 ((CQE_OPCODE(*cqe) == T3_READ_RESP) && wq->oldest_read)) &&
473 (CQE_QPID(*cqe) == wq->qpid))
474 (*count)++;
475 ptr++;
476 }
477 pr_debug("%s cq %p count %d\n", __func__, cq, *count);
478 }
479
480 void cxio_count_rcqes(struct t3_cq *cq, struct t3_wq *wq, int *count)
481 {
482 struct t3_cqe *cqe;
483 u32 ptr;
484
485 *count = 0;
486 pr_debug("%s count zero %d\n", __func__, *count);
487 ptr = cq->sw_rptr;
488 while (!Q_EMPTY(ptr, cq->sw_wptr)) {
489 cqe = cq->sw_queue + (Q_PTR2IDX(ptr, cq->size_log2));
490 if (RQ_TYPE(*cqe) && (CQE_OPCODE(*cqe) != T3_READ_RESP) &&
491 (CQE_QPID(*cqe) == wq->qpid) && cqe_completes_wr(cqe, wq))
492 (*count)++;
493 ptr++;
494 }
495 pr_debug("%s cq %p count %d\n", __func__, cq, *count);
496 }
497
498 static int cxio_hal_init_ctrl_cq(struct cxio_rdev *rdev_p)
499 {
500 struct rdma_cq_setup setup;
501 setup.id = 0;
502 setup.base_addr = 0; /* NULL address */
503 setup.size = 1; /* enable the CQ */
504 setup.credits = 0;
505
506 /* force SGE to redirect to RspQ and interrupt */
507 setup.credit_thres = 0;
508 setup.ovfl_mode = 1;
509 return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
510 }
511
512 static int cxio_hal_init_ctrl_qp(struct cxio_rdev *rdev_p)
513 {
514 int err;
515 u64 sge_cmd, ctx0, ctx1;
516 u64 base_addr;
517 struct t3_modify_qp_wr *wqe;
518 struct sk_buff *skb;
519
520 skb = alloc_skb(sizeof(*wqe), GFP_KERNEL);
521 if (!skb) {
522 pr_debug("%s alloc_skb failed\n", __func__);
523 return -ENOMEM;
524 }
525 err = cxio_hal_init_ctrl_cq(rdev_p);
526 if (err) {
527 pr_debug("%s err %d initializing ctrl_cq\n", __func__, err);
528 goto err;
529 }
530 rdev_p->ctrl_qp.workq = dma_alloc_coherent(
531 &(rdev_p->rnic_info.pdev->dev),
532 (1 << T3_CTRL_QP_SIZE_LOG2) *
533 sizeof(union t3_wr),
534 &(rdev_p->ctrl_qp.dma_addr),
535 GFP_KERNEL);
536 if (!rdev_p->ctrl_qp.workq) {
537 pr_debug("%s dma_alloc_coherent failed\n", __func__);
538 err = -ENOMEM;
539 goto err;
540 }
541 dma_unmap_addr_set(&rdev_p->ctrl_qp, mapping,
542 rdev_p->ctrl_qp.dma_addr);
543 rdev_p->ctrl_qp.doorbell = (void __iomem *)rdev_p->rnic_info.kdb_addr;
544 memset(rdev_p->ctrl_qp.workq, 0,
545 (1 << T3_CTRL_QP_SIZE_LOG2) * sizeof(union t3_wr));
546
547 mutex_init(&rdev_p->ctrl_qp.lock);
548 init_waitqueue_head(&rdev_p->ctrl_qp.waitq);
549
550 /* update HW Ctrl QP context */
551 base_addr = rdev_p->ctrl_qp.dma_addr;
552 base_addr >>= 12;
553 ctx0 = (V_EC_SIZE((1 << T3_CTRL_QP_SIZE_LOG2)) |
554 V_EC_BASE_LO((u32) base_addr & 0xffff));
555 ctx0 <<= 32;
556 ctx0 |= V_EC_CREDITS(FW_WR_NUM);
557 base_addr >>= 16;
558 ctx1 = (u32) base_addr;
559 base_addr >>= 32;
560 ctx1 |= ((u64) (V_EC_BASE_HI((u32) base_addr & 0xf) | V_EC_RESPQ(0) |
561 V_EC_TYPE(0) | V_EC_GEN(1) |
562 V_EC_UP_TOKEN(T3_CTL_QP_TID) | F_EC_VALID)) << 32;
563 wqe = skb_put_zero(skb, sizeof(*wqe));
564 build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_QP_MOD, 0, 0,
565 T3_CTL_QP_TID, 7, T3_SOPEOP);
566 wqe->flags = cpu_to_be32(MODQP_WRITE_EC);
567 sge_cmd = (3ULL << 56) | FW_RI_SGEEC_START << 8 | 3;
568 wqe->sge_cmd = cpu_to_be64(sge_cmd);
569 wqe->ctx1 = cpu_to_be64(ctx1);
570 wqe->ctx0 = cpu_to_be64(ctx0);
571 pr_debug("CtrlQP dma_addr 0x%llx workq %p size %d\n",
572 (unsigned long long)rdev_p->ctrl_qp.dma_addr,
573 rdev_p->ctrl_qp.workq, 1 << T3_CTRL_QP_SIZE_LOG2);
574 skb->priority = CPL_PRIORITY_CONTROL;
575 return iwch_cxgb3_ofld_send(rdev_p->t3cdev_p, skb);
576 err:
577 kfree_skb(skb);
578 return err;
579 }
580
581 static int cxio_hal_destroy_ctrl_qp(struct cxio_rdev *rdev_p)
582 {
583 dma_free_coherent(&(rdev_p->rnic_info.pdev->dev),
584 (1UL << T3_CTRL_QP_SIZE_LOG2)
585 * sizeof(union t3_wr), rdev_p->ctrl_qp.workq,
586 dma_unmap_addr(&rdev_p->ctrl_qp, mapping));
587 return cxio_hal_clear_qp_ctx(rdev_p, T3_CTRL_QP_ID);
588 }
589
590 /* write len bytes of data into addr (32B aligned address)
591 * If data is NULL, clear len byte of memory to zero.
592 * caller acquires the ctrl_qp lock before the call
593 */
594 static int cxio_hal_ctrl_qp_write_mem(struct cxio_rdev *rdev_p, u32 addr,
595 u32 len, void *data)
596 {
597 u32 i, nr_wqe, copy_len;
598 u8 *copy_data;
599 u8 wr_len, utx_len; /* length in 8 byte flit */
600 enum t3_wr_flags flag;
601 __be64 *wqe;
602 u64 utx_cmd;
603 addr &= 0x7FFFFFF;
604 nr_wqe = len % 96 ? len / 96 + 1 : len / 96; /* 96B max per WQE */
605 pr_debug("%s wptr 0x%x rptr 0x%x len %d, nr_wqe %d data %p addr 0x%0x\n",
606 __func__, rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, len,
607 nr_wqe, data, addr);
608 utx_len = 3; /* in 32B unit */
609 for (i = 0; i < nr_wqe; i++) {
610 if (Q_FULL(rdev_p->ctrl_qp.rptr, rdev_p->ctrl_qp.wptr,
611 T3_CTRL_QP_SIZE_LOG2)) {
612 pr_debug("%s ctrl_qp full wtpr 0x%0x rptr 0x%0x, wait for more space i %d\n",
613 __func__,
614 rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, i);
615 if (wait_event_interruptible(rdev_p->ctrl_qp.waitq,
616 !Q_FULL(rdev_p->ctrl_qp.rptr,
617 rdev_p->ctrl_qp.wptr,
618 T3_CTRL_QP_SIZE_LOG2))) {
619 pr_debug("%s ctrl_qp workq interrupted\n",
620 __func__);
621 return -ERESTARTSYS;
622 }
623 pr_debug("%s ctrl_qp wakeup, continue posting work request i %d\n",
624 __func__, i);
625 }
626 wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr %
627 (1 << T3_CTRL_QP_SIZE_LOG2)));
628 flag = 0;
629 if (i == (nr_wqe - 1)) {
630 /* last WQE */
631 flag = T3_COMPLETION_FLAG;
632 if (len % 32)
633 utx_len = len / 32 + 1;
634 else
635 utx_len = len / 32;
636 }
637
638 /*
639 * Force a CQE to return the credit to the workq in case
640 * we posted more than half the max QP size of WRs
641 */
642 if ((i != 0) &&
643 (i % (((1 << T3_CTRL_QP_SIZE_LOG2)) >> 1) == 0)) {
644 flag = T3_COMPLETION_FLAG;
645 pr_debug("%s force completion at i %d\n", __func__, i);
646 }
647
648 /* build the utx mem command */
649 wqe += (sizeof(struct t3_bypass_wr) >> 3);
650 utx_cmd = (T3_UTX_MEM_WRITE << 28) | (addr + i * 3);
651 utx_cmd <<= 32;
652 utx_cmd |= (utx_len << 28) | ((utx_len << 2) + 1);
653 *wqe = cpu_to_be64(utx_cmd);
654 wqe++;
655 copy_data = (u8 *) data + i * 96;
656 copy_len = len > 96 ? 96 : len;
657
658 /* clear memory content if data is NULL */
659 if (data)
660 memcpy(wqe, copy_data, copy_len);
661 else
662 memset(wqe, 0, copy_len);
663 if (copy_len % 32)
664 memset(((u8 *) wqe) + copy_len, 0,
665 32 - (copy_len % 32));
666 wr_len = ((sizeof(struct t3_bypass_wr)) >> 3) + 1 +
667 (utx_len << 2);
668 wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr %
669 (1 << T3_CTRL_QP_SIZE_LOG2)));
670
671 /* wptr in the WRID[31:0] */
672 ((union t3_wrid *)(wqe+1))->id0.low = rdev_p->ctrl_qp.wptr;
673
674 /*
675 * This must be the last write with a memory barrier
676 * for the genbit
677 */
678 build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_BP, flag,
679 Q_GENBIT(rdev_p->ctrl_qp.wptr,
680 T3_CTRL_QP_SIZE_LOG2), T3_CTRL_QP_ID,
681 wr_len, T3_SOPEOP);
682 if (flag == T3_COMPLETION_FLAG)
683 ring_doorbell(rdev_p->ctrl_qp.doorbell, T3_CTRL_QP_ID);
684 len -= 96;
685 rdev_p->ctrl_qp.wptr++;
686 }
687 return 0;
688 }
689
690 /* IN: stag key, pdid, perm, zbva, to, len, page_size, pbl_size and pbl_addr
691 * OUT: stag index
692 * TBD: shared memory region support
693 */
694 static int __cxio_tpt_op(struct cxio_rdev *rdev_p, u32 reset_tpt_entry,
695 u32 *stag, u8 stag_state, u32 pdid,
696 enum tpt_mem_type type, enum tpt_mem_perm perm,
697 u32 zbva, u64 to, u32 len, u8 page_size,
698 u32 pbl_size, u32 pbl_addr)
699 {
700 int err;
701 struct tpt_entry tpt;
702 u32 stag_idx;
703 u32 wptr;
704
705 if (cxio_fatal_error(rdev_p))
706 return -EIO;
707
708 stag_state = stag_state > 0;
709 stag_idx = (*stag) >> 8;
710
711 if ((!reset_tpt_entry) && !(*stag != T3_STAG_UNSET)) {
712 stag_idx = cxio_hal_get_stag(rdev_p->rscp);
713 if (!stag_idx)
714 return -ENOMEM;
715 *stag = (stag_idx << 8) | ((*stag) & 0xFF);
716 }
717 pr_debug("%s stag_state 0x%0x type 0x%0x pdid 0x%0x, stag_idx 0x%x\n",
718 __func__, stag_state, type, pdid, stag_idx);
719
720 mutex_lock(&rdev_p->ctrl_qp.lock);
721
722 /* write TPT entry */
723 if (reset_tpt_entry)
724 memset(&tpt, 0, sizeof(tpt));
725 else {
726 tpt.valid_stag_pdid = cpu_to_be32(F_TPT_VALID |
727 V_TPT_STAG_KEY((*stag) & M_TPT_STAG_KEY) |
728 V_TPT_STAG_STATE(stag_state) |
729 V_TPT_STAG_TYPE(type) | V_TPT_PDID(pdid));
730 BUG_ON(page_size >= 28);
731 tpt.flags_pagesize_qpid = cpu_to_be32(V_TPT_PERM(perm) |
732 ((perm & TPT_MW_BIND) ? F_TPT_MW_BIND_ENABLE : 0) |
733 V_TPT_ADDR_TYPE((zbva ? TPT_ZBTO : TPT_VATO)) |
734 V_TPT_PAGE_SIZE(page_size));
735 tpt.rsvd_pbl_addr = cpu_to_be32(V_TPT_PBL_ADDR(PBL_OFF(rdev_p, pbl_addr)>>3));
736 tpt.len = cpu_to_be32(len);
737 tpt.va_hi = cpu_to_be32((u32) (to >> 32));
738 tpt.va_low_or_fbo = cpu_to_be32((u32) (to & 0xFFFFFFFFULL));
739 tpt.rsvd_bind_cnt_or_pstag = 0;
740 tpt.rsvd_pbl_size = cpu_to_be32(V_TPT_PBL_SIZE(pbl_size >> 2));
741 }
742 err = cxio_hal_ctrl_qp_write_mem(rdev_p,
743 stag_idx +
744 (rdev_p->rnic_info.tpt_base >> 5),
745 sizeof(tpt), &tpt);
746
747 /* release the stag index to free pool */
748 if (reset_tpt_entry)
749 cxio_hal_put_stag(rdev_p->rscp, stag_idx);
750
751 wptr = rdev_p->ctrl_qp.wptr;
752 mutex_unlock(&rdev_p->ctrl_qp.lock);
753 if (!err)
754 if (wait_event_interruptible(rdev_p->ctrl_qp.waitq,
755 SEQ32_GE(rdev_p->ctrl_qp.rptr,
756 wptr)))
757 return -ERESTARTSYS;
758 return err;
759 }
760
761 int cxio_write_pbl(struct cxio_rdev *rdev_p, __be64 *pbl,
762 u32 pbl_addr, u32 pbl_size)
763 {
764 u32 wptr;
765 int err;
766
767 pr_debug("%s *pdb_addr 0x%x, pbl_base 0x%x, pbl_size %d\n",
768 __func__, pbl_addr, rdev_p->rnic_info.pbl_base,
769 pbl_size);
770
771 mutex_lock(&rdev_p->ctrl_qp.lock);
772 err = cxio_hal_ctrl_qp_write_mem(rdev_p, pbl_addr >> 5, pbl_size << 3,
773 pbl);
774 wptr = rdev_p->ctrl_qp.wptr;
775 mutex_unlock(&rdev_p->ctrl_qp.lock);
776 if (err)
777 return err;
778
779 if (wait_event_interruptible(rdev_p->ctrl_qp.waitq,
780 SEQ32_GE(rdev_p->ctrl_qp.rptr,
781 wptr)))
782 return -ERESTARTSYS;
783
784 return 0;
785 }
786
787 int cxio_register_phys_mem(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid,
788 enum tpt_mem_perm perm, u32 zbva, u64 to, u32 len,
789 u8 page_size, u32 pbl_size, u32 pbl_addr)
790 {
791 *stag = T3_STAG_UNSET;
792 return __cxio_tpt_op(rdev_p, 0, stag, 1, pdid, TPT_NON_SHARED_MR, perm,
793 zbva, to, len, page_size, pbl_size, pbl_addr);
794 }
795
796 int cxio_reregister_phys_mem(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid,
797 enum tpt_mem_perm perm, u32 zbva, u64 to, u32 len,
798 u8 page_size, u32 pbl_size, u32 pbl_addr)
799 {
800 return __cxio_tpt_op(rdev_p, 0, stag, 1, pdid, TPT_NON_SHARED_MR, perm,
801 zbva, to, len, page_size, pbl_size, pbl_addr);
802 }
803
804 int cxio_dereg_mem(struct cxio_rdev *rdev_p, u32 stag, u32 pbl_size,
805 u32 pbl_addr)
806 {
807 return __cxio_tpt_op(rdev_p, 1, &stag, 0, 0, 0, 0, 0, 0ULL, 0, 0,
808 pbl_size, pbl_addr);
809 }
810
811 int cxio_allocate_window(struct cxio_rdev *rdev_p, u32 * stag, u32 pdid)
812 {
813 *stag = T3_STAG_UNSET;
814 return __cxio_tpt_op(rdev_p, 0, stag, 0, pdid, TPT_MW, 0, 0, 0ULL, 0, 0,
815 0, 0);
816 }
817
818 int cxio_deallocate_window(struct cxio_rdev *rdev_p, u32 stag)
819 {
820 return __cxio_tpt_op(rdev_p, 1, &stag, 0, 0, 0, 0, 0, 0ULL, 0, 0,
821 0, 0);
822 }
823
824 int cxio_allocate_stag(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid, u32 pbl_size, u32 pbl_addr)
825 {
826 *stag = T3_STAG_UNSET;
827 return __cxio_tpt_op(rdev_p, 0, stag, 0, pdid, TPT_NON_SHARED_MR,
828 0, 0, 0ULL, 0, 0, pbl_size, pbl_addr);
829 }
830
831 int cxio_rdma_init(struct cxio_rdev *rdev_p, struct t3_rdma_init_attr *attr)
832 {
833 struct t3_rdma_init_wr *wqe;
834 struct sk_buff *skb = alloc_skb(sizeof(*wqe), GFP_ATOMIC);
835 if (!skb)
836 return -ENOMEM;
837 pr_debug("%s rdev_p %p\n", __func__, rdev_p);
838 wqe = __skb_put(skb, sizeof(*wqe));
839 wqe->wrh.op_seop_flags = cpu_to_be32(V_FW_RIWR_OP(T3_WR_INIT));
840 wqe->wrh.gen_tid_len = cpu_to_be32(V_FW_RIWR_TID(attr->tid) |
841 V_FW_RIWR_LEN(sizeof(*wqe) >> 3));
842 wqe->wrid.id1 = 0;
843 wqe->qpid = cpu_to_be32(attr->qpid);
844 wqe->pdid = cpu_to_be32(attr->pdid);
845 wqe->scqid = cpu_to_be32(attr->scqid);
846 wqe->rcqid = cpu_to_be32(attr->rcqid);
847 wqe->rq_addr = cpu_to_be32(attr->rq_addr - rdev_p->rnic_info.rqt_base);
848 wqe->rq_size = cpu_to_be32(attr->rq_size);
849 wqe->mpaattrs = attr->mpaattrs;
850 wqe->qpcaps = attr->qpcaps;
851 wqe->ulpdu_size = cpu_to_be16(attr->tcp_emss);
852 wqe->rqe_count = cpu_to_be16(attr->rqe_count);
853 wqe->flags_rtr_type = cpu_to_be16(attr->flags |
854 V_RTR_TYPE(attr->rtr_type) |
855 V_CHAN(attr->chan));
856 wqe->ord = cpu_to_be32(attr->ord);
857 wqe->ird = cpu_to_be32(attr->ird);
858 wqe->qp_dma_addr = cpu_to_be64(attr->qp_dma_addr);
859 wqe->qp_dma_size = cpu_to_be32(attr->qp_dma_size);
860 wqe->irs = cpu_to_be32(attr->irs);
861 skb->priority = 0; /* 0=>ToeQ; 1=>CtrlQ */
862 return iwch_cxgb3_ofld_send(rdev_p->t3cdev_p, skb);
863 }
864
865 void cxio_register_ev_cb(cxio_hal_ev_callback_func_t ev_cb)
866 {
867 cxio_ev_cb = ev_cb;
868 }
869
870 void cxio_unregister_ev_cb(cxio_hal_ev_callback_func_t ev_cb)
871 {
872 cxio_ev_cb = NULL;
873 }
874
875 static int cxio_hal_ev_handler(struct t3cdev *t3cdev_p, struct sk_buff *skb)
876 {
877 static int cnt;
878 struct cxio_rdev *rdev_p = NULL;
879 struct respQ_msg_t *rsp_msg = (struct respQ_msg_t *) skb->data;
880 pr_debug("%d: %s cq_id 0x%x cq_ptr 0x%x genbit %0x overflow %0x an %0x se %0x notify %0x cqbranch %0x creditth %0x\n",
881 cnt, __func__, RSPQ_CQID(rsp_msg), RSPQ_CQPTR(rsp_msg),
882 RSPQ_GENBIT(rsp_msg), RSPQ_OVERFLOW(rsp_msg), RSPQ_AN(rsp_msg),
883 RSPQ_SE(rsp_msg), RSPQ_NOTIFY(rsp_msg), RSPQ_CQBRANCH(rsp_msg),
884 RSPQ_CREDIT_THRESH(rsp_msg));
885 pr_debug("CQE: QPID 0x%0x genbit %0x type 0x%0x status 0x%0x opcode %d len 0x%0x wrid_hi_stag 0x%x wrid_low_msn 0x%x\n",
886 CQE_QPID(rsp_msg->cqe), CQE_GENBIT(rsp_msg->cqe),
887 CQE_TYPE(rsp_msg->cqe), CQE_STATUS(rsp_msg->cqe),
888 CQE_OPCODE(rsp_msg->cqe), CQE_LEN(rsp_msg->cqe),
889 CQE_WRID_HI(rsp_msg->cqe), CQE_WRID_LOW(rsp_msg->cqe));
890 rdev_p = (struct cxio_rdev *)t3cdev_p->ulp;
891 if (!rdev_p) {
892 pr_debug("%s called by t3cdev %p with null ulp\n", __func__,
893 t3cdev_p);
894 return 0;
895 }
896 if (CQE_QPID(rsp_msg->cqe) == T3_CTRL_QP_ID) {
897 rdev_p->ctrl_qp.rptr = CQE_WRID_LOW(rsp_msg->cqe) + 1;
898 wake_up_interruptible(&rdev_p->ctrl_qp.waitq);
899 dev_kfree_skb_irq(skb);
900 } else if (CQE_QPID(rsp_msg->cqe) == 0xfff8)
901 dev_kfree_skb_irq(skb);
902 else if (cxio_ev_cb)
903 (*cxio_ev_cb) (rdev_p, skb);
904 else
905 dev_kfree_skb_irq(skb);
906 cnt++;
907 return 0;
908 }
909
910 /* Caller takes care of locking if needed */
911 int cxio_rdev_open(struct cxio_rdev *rdev_p)
912 {
913 struct net_device *netdev_p = NULL;
914 int err = 0;
915 if (strlen(rdev_p->dev_name)) {
916 if (cxio_hal_find_rdev_by_name(rdev_p->dev_name)) {
917 return -EBUSY;
918 }
919 netdev_p = dev_get_by_name(&init_net, rdev_p->dev_name);
920 if (!netdev_p) {
921 return -EINVAL;
922 }
923 dev_put(netdev_p);
924 } else if (rdev_p->t3cdev_p) {
925 if (cxio_hal_find_rdev_by_t3cdev(rdev_p->t3cdev_p)) {
926 return -EBUSY;
927 }
928 netdev_p = rdev_p->t3cdev_p->lldev;
929 strncpy(rdev_p->dev_name, rdev_p->t3cdev_p->name,
930 T3_MAX_DEV_NAME_LEN);
931 } else {
932 pr_debug("%s t3cdev_p or dev_name must be set\n", __func__);
933 return -EINVAL;
934 }
935
936 list_add_tail(&rdev_p->entry, &rdev_list);
937
938 pr_debug("%s opening rnic dev %s\n", __func__, rdev_p->dev_name);
939 memset(&rdev_p->ctrl_qp, 0, sizeof(rdev_p->ctrl_qp));
940 if (!rdev_p->t3cdev_p)
941 rdev_p->t3cdev_p = dev2t3cdev(netdev_p);
942 rdev_p->t3cdev_p->ulp = (void *) rdev_p;
943
944 err = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, GET_EMBEDDED_INFO,
945 &(rdev_p->fw_info));
946 if (err) {
947 pr_err("%s t3cdev_p(%p)->ctl returned error %d\n",
948 __func__, rdev_p->t3cdev_p, err);
949 goto err1;
950 }
951 if (G_FW_VERSION_MAJOR(rdev_p->fw_info.fw_vers) != CXIO_FW_MAJ) {
952 pr_err("fatal firmware version mismatch: need version %u but adapter has version %u\n",
953 CXIO_FW_MAJ,
954 G_FW_VERSION_MAJOR(rdev_p->fw_info.fw_vers));
955 err = -EINVAL;
956 goto err1;
957 }
958
959 err = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_GET_PARAMS,
960 &(rdev_p->rnic_info));
961 if (err) {
962 pr_err("%s t3cdev_p(%p)->ctl returned error %d\n",
963 __func__, rdev_p->t3cdev_p, err);
964 goto err1;
965 }
966 err = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, GET_PORTS,
967 &(rdev_p->port_info));
968 if (err) {
969 pr_err("%s t3cdev_p(%p)->ctl returned error %d\n",
970 __func__, rdev_p->t3cdev_p, err);
971 goto err1;
972 }
973
974 /*
975 * qpshift is the number of bits to shift the qpid left in order
976 * to get the correct address of the doorbell for that qp.
977 */
978 cxio_init_ucontext(rdev_p, &rdev_p->uctx);
979 rdev_p->qpshift = PAGE_SHIFT -
980 ilog2(65536 >>
981 ilog2(rdev_p->rnic_info.udbell_len >>
982 PAGE_SHIFT));
983 rdev_p->qpnr = rdev_p->rnic_info.udbell_len >> PAGE_SHIFT;
984 rdev_p->qpmask = (65536 >> ilog2(rdev_p->qpnr)) - 1;
985 pr_debug("%s rnic %s info: tpt_base 0x%0x tpt_top 0x%0x num stags %d pbl_base 0x%0x pbl_top 0x%0x rqt_base 0x%0x, rqt_top 0x%0x\n",
986 __func__, rdev_p->dev_name, rdev_p->rnic_info.tpt_base,
987 rdev_p->rnic_info.tpt_top, cxio_num_stags(rdev_p),
988 rdev_p->rnic_info.pbl_base,
989 rdev_p->rnic_info.pbl_top, rdev_p->rnic_info.rqt_base,
990 rdev_p->rnic_info.rqt_top);
991 pr_debug("udbell_len 0x%0x udbell_physbase 0x%lx kdb_addr %p qpshift %lu qpnr %d qpmask 0x%x\n",
992 rdev_p->rnic_info.udbell_len,
993 rdev_p->rnic_info.udbell_physbase, rdev_p->rnic_info.kdb_addr,
994 rdev_p->qpshift, rdev_p->qpnr, rdev_p->qpmask);
995
996 err = cxio_hal_init_ctrl_qp(rdev_p);
997 if (err) {
998 pr_err("%s error %d initializing ctrl_qp\n", __func__, err);
999 goto err1;
1000 }
1001 err = cxio_hal_init_resource(rdev_p, cxio_num_stags(rdev_p), 0,
1002 0, T3_MAX_NUM_QP, T3_MAX_NUM_CQ,
1003 T3_MAX_NUM_PD);
1004 if (err) {
1005 pr_err("%s error %d initializing hal resources\n",
1006 __func__, err);
1007 goto err2;
1008 }
1009 err = cxio_hal_pblpool_create(rdev_p);
1010 if (err) {
1011 pr_err("%s error %d initializing pbl mem pool\n",
1012 __func__, err);
1013 goto err3;
1014 }
1015 err = cxio_hal_rqtpool_create(rdev_p);
1016 if (err) {
1017 pr_err("%s error %d initializing rqt mem pool\n",
1018 __func__, err);
1019 goto err4;
1020 }
1021 return 0;
1022 err4:
1023 cxio_hal_pblpool_destroy(rdev_p);
1024 err3:
1025 cxio_hal_destroy_resource(rdev_p->rscp);
1026 err2:
1027 cxio_hal_destroy_ctrl_qp(rdev_p);
1028 err1:
1029 rdev_p->t3cdev_p->ulp = NULL;
1030 list_del(&rdev_p->entry);
1031 return err;
1032 }
1033
1034 void cxio_rdev_close(struct cxio_rdev *rdev_p)
1035 {
1036 if (rdev_p) {
1037 cxio_hal_pblpool_destroy(rdev_p);
1038 cxio_hal_rqtpool_destroy(rdev_p);
1039 list_del(&rdev_p->entry);
1040 cxio_hal_destroy_ctrl_qp(rdev_p);
1041 cxio_hal_destroy_resource(rdev_p->rscp);
1042 rdev_p->t3cdev_p->ulp = NULL;
1043 }
1044 }
1045
1046 int __init cxio_hal_init(void)
1047 {
1048 if (cxio_hal_init_rhdl_resource(T3_MAX_NUM_RI))
1049 return -ENOMEM;
1050 t3_register_cpl_handler(CPL_ASYNC_NOTIF, cxio_hal_ev_handler);
1051 return 0;
1052 }
1053
1054 void __exit cxio_hal_exit(void)
1055 {
1056 struct cxio_rdev *rdev, *tmp;
1057
1058 t3_register_cpl_handler(CPL_ASYNC_NOTIF, NULL);
1059 list_for_each_entry_safe(rdev, tmp, &rdev_list, entry)
1060 cxio_rdev_close(rdev);
1061 cxio_hal_destroy_rhdl_resource();
1062 }
1063
1064 static void flush_completed_wrs(struct t3_wq *wq, struct t3_cq *cq)
1065 {
1066 struct t3_swsq *sqp;
1067 __u32 ptr = wq->sq_rptr;
1068 int count = Q_COUNT(wq->sq_rptr, wq->sq_wptr);
1069
1070 sqp = wq->sq + Q_PTR2IDX(ptr, wq->sq_size_log2);
1071 while (count--)
1072 if (!sqp->signaled) {
1073 ptr++;
1074 sqp = wq->sq + Q_PTR2IDX(ptr, wq->sq_size_log2);
1075 } else if (sqp->complete) {
1076
1077 /*
1078 * Insert this completed cqe into the swcq.
1079 */
1080 pr_debug("%s moving cqe into swcq sq idx %ld cq idx %ld\n",
1081 __func__, Q_PTR2IDX(ptr, wq->sq_size_log2),
1082 Q_PTR2IDX(cq->sw_wptr, cq->size_log2));
1083 sqp->cqe.header |= htonl(V_CQE_SWCQE(1));
1084 *(cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2))
1085 = sqp->cqe;
1086 cq->sw_wptr++;
1087 sqp->signaled = 0;
1088 break;
1089 } else
1090 break;
1091 }
1092
1093 static void create_read_req_cqe(struct t3_wq *wq, struct t3_cqe *hw_cqe,
1094 struct t3_cqe *read_cqe)
1095 {
1096 read_cqe->u.scqe.wrid_hi = wq->oldest_read->sq_wptr;
1097 read_cqe->len = wq->oldest_read->read_len;
1098 read_cqe->header = htonl(V_CQE_QPID(CQE_QPID(*hw_cqe)) |
1099 V_CQE_SWCQE(SW_CQE(*hw_cqe)) |
1100 V_CQE_OPCODE(T3_READ_REQ) |
1101 V_CQE_TYPE(1));
1102 }
1103
1104 /*
1105 * Return a ptr to the next read wr in the SWSQ or NULL.
1106 */
1107 static void advance_oldest_read(struct t3_wq *wq)
1108 {
1109
1110 u32 rptr = wq->oldest_read - wq->sq + 1;
1111 u32 wptr = Q_PTR2IDX(wq->sq_wptr, wq->sq_size_log2);
1112
1113 while (Q_PTR2IDX(rptr, wq->sq_size_log2) != wptr) {
1114 wq->oldest_read = wq->sq + Q_PTR2IDX(rptr, wq->sq_size_log2);
1115
1116 if (wq->oldest_read->opcode == T3_READ_REQ)
1117 return;
1118 rptr++;
1119 }
1120 wq->oldest_read = NULL;
1121 }
1122
1123 /*
1124 * cxio_poll_cq
1125 *
1126 * Caller must:
1127 * check the validity of the first CQE,
1128 * supply the wq assicated with the qpid.
1129 *
1130 * credit: cq credit to return to sge.
1131 * cqe_flushed: 1 iff the CQE is flushed.
1132 * cqe: copy of the polled CQE.
1133 *
1134 * return value:
1135 * 0 CQE returned,
1136 * -1 CQE skipped, try again.
1137 */
1138 int cxio_poll_cq(struct t3_wq *wq, struct t3_cq *cq, struct t3_cqe *cqe,
1139 u8 *cqe_flushed, u64 *cookie, u32 *credit)
1140 {
1141 int ret = 0;
1142 struct t3_cqe *hw_cqe, read_cqe;
1143
1144 *cqe_flushed = 0;
1145 *credit = 0;
1146 hw_cqe = cxio_next_cqe(cq);
1147
1148 pr_debug("%s CQE OOO %d qpid 0x%0x genbit %d type %d status 0x%0x opcode 0x%0x len 0x%0x wrid_hi_stag 0x%x wrid_low_msn 0x%x\n",
1149 __func__, CQE_OOO(*hw_cqe), CQE_QPID(*hw_cqe),
1150 CQE_GENBIT(*hw_cqe), CQE_TYPE(*hw_cqe), CQE_STATUS(*hw_cqe),
1151 CQE_OPCODE(*hw_cqe), CQE_LEN(*hw_cqe), CQE_WRID_HI(*hw_cqe),
1152 CQE_WRID_LOW(*hw_cqe));
1153
1154 /*
1155 * skip cqe's not affiliated with a QP.
1156 */
1157 if (wq == NULL) {
1158 ret = -1;
1159 goto skip_cqe;
1160 }
1161
1162 /*
1163 * Gotta tweak READ completions:
1164 * 1) the cqe doesn't contain the sq_wptr from the wr.
1165 * 2) opcode not reflected from the wr.
1166 * 3) read_len not reflected from the wr.
1167 * 4) cq_type is RQ_TYPE not SQ_TYPE.
1168 */
1169 if (RQ_TYPE(*hw_cqe) && (CQE_OPCODE(*hw_cqe) == T3_READ_RESP)) {
1170
1171 /*
1172 * If this is an unsolicited read response, then the read
1173 * was generated by the kernel driver as part of peer-2-peer
1174 * connection setup. So ignore the completion.
1175 */
1176 if (!wq->oldest_read) {
1177 if (CQE_STATUS(*hw_cqe))
1178 wq->error = 1;
1179 ret = -1;
1180 goto skip_cqe;
1181 }
1182
1183 /*
1184 * Don't write to the HWCQ, so create a new read req CQE
1185 * in local memory.
1186 */
1187 create_read_req_cqe(wq, hw_cqe, &read_cqe);
1188 hw_cqe = &read_cqe;
1189 advance_oldest_read(wq);
1190 }
1191
1192 /*
1193 * T3A: Discard TERMINATE CQEs.
1194 */
1195 if (CQE_OPCODE(*hw_cqe) == T3_TERMINATE) {
1196 ret = -1;
1197 wq->error = 1;
1198 goto skip_cqe;
1199 }
1200
1201 if (CQE_STATUS(*hw_cqe) || wq->error) {
1202 *cqe_flushed = wq->error;
1203 wq->error = 1;
1204
1205 /*
1206 * T3A inserts errors into the CQE. We cannot return
1207 * these as work completions.
1208 */
1209 /* incoming write failures */
1210 if ((CQE_OPCODE(*hw_cqe) == T3_RDMA_WRITE)
1211 && RQ_TYPE(*hw_cqe)) {
1212 ret = -1;
1213 goto skip_cqe;
1214 }
1215 /* incoming read request failures */
1216 if ((CQE_OPCODE(*hw_cqe) == T3_READ_RESP) && SQ_TYPE(*hw_cqe)) {
1217 ret = -1;
1218 goto skip_cqe;
1219 }
1220
1221 /* incoming SEND with no receive posted failures */
1222 if (CQE_SEND_OPCODE(*hw_cqe) && RQ_TYPE(*hw_cqe) &&
1223 Q_EMPTY(wq->rq_rptr, wq->rq_wptr)) {
1224 ret = -1;
1225 goto skip_cqe;
1226 }
1227 BUG_ON((*cqe_flushed == 0) && !SW_CQE(*hw_cqe));
1228 goto proc_cqe;
1229 }
1230
1231 /*
1232 * RECV completion.
1233 */
1234 if (RQ_TYPE(*hw_cqe)) {
1235
1236 /*
1237 * HW only validates 4 bits of MSN. So we must validate that
1238 * the MSN in the SEND is the next expected MSN. If its not,
1239 * then we complete this with TPT_ERR_MSN and mark the wq in
1240 * error.
1241 */
1242
1243 if (Q_EMPTY(wq->rq_rptr, wq->rq_wptr)) {
1244 wq->error = 1;
1245 ret = -1;
1246 goto skip_cqe;
1247 }
1248
1249 if (unlikely((CQE_WRID_MSN(*hw_cqe) != (wq->rq_rptr + 1)))) {
1250 wq->error = 1;
1251 hw_cqe->header |= htonl(V_CQE_STATUS(TPT_ERR_MSN));
1252 goto proc_cqe;
1253 }
1254 goto proc_cqe;
1255 }
1256
1257 /*
1258 * If we get here its a send completion.
1259 *
1260 * Handle out of order completion. These get stuffed
1261 * in the SW SQ. Then the SW SQ is walked to move any
1262 * now in-order completions into the SW CQ. This handles
1263 * 2 cases:
1264 * 1) reaping unsignaled WRs when the first subsequent
1265 * signaled WR is completed.
1266 * 2) out of order read completions.
1267 */
1268 if (!SW_CQE(*hw_cqe) && (CQE_WRID_SQ_WPTR(*hw_cqe) != wq->sq_rptr)) {
1269 struct t3_swsq *sqp;
1270
1271 pr_debug("%s out of order completion going in swsq at idx %ld\n",
1272 __func__,
1273 Q_PTR2IDX(CQE_WRID_SQ_WPTR(*hw_cqe),
1274 wq->sq_size_log2));
1275 sqp = wq->sq +
1276 Q_PTR2IDX(CQE_WRID_SQ_WPTR(*hw_cqe), wq->sq_size_log2);
1277 sqp->cqe = *hw_cqe;
1278 sqp->complete = 1;
1279 ret = -1;
1280 goto flush_wq;
1281 }
1282
1283 proc_cqe:
1284 *cqe = *hw_cqe;
1285
1286 /*
1287 * Reap the associated WR(s) that are freed up with this
1288 * completion.
1289 */
1290 if (SQ_TYPE(*hw_cqe)) {
1291 wq->sq_rptr = CQE_WRID_SQ_WPTR(*hw_cqe);
1292 pr_debug("%s completing sq idx %ld\n", __func__,
1293 Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2));
1294 *cookie = wq->sq[Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2)].wr_id;
1295 wq->sq_rptr++;
1296 } else {
1297 pr_debug("%s completing rq idx %ld\n", __func__,
1298 Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2));
1299 *cookie = wq->rq[Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2)].wr_id;
1300 if (wq->rq[Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2)].pbl_addr)
1301 cxio_hal_pblpool_free(wq->rdev,
1302 wq->rq[Q_PTR2IDX(wq->rq_rptr,
1303 wq->rq_size_log2)].pbl_addr, T3_STAG0_PBL_SIZE);
1304 BUG_ON(Q_EMPTY(wq->rq_rptr, wq->rq_wptr));
1305 wq->rq_rptr++;
1306 }
1307
1308 flush_wq:
1309 /*
1310 * Flush any completed cqes that are now in-order.
1311 */
1312 flush_completed_wrs(wq, cq);
1313
1314 skip_cqe:
1315 if (SW_CQE(*hw_cqe)) {
1316 pr_debug("%s cq %p cqid 0x%x skip sw cqe sw_rptr 0x%x\n",
1317 __func__, cq, cq->cqid, cq->sw_rptr);
1318 ++cq->sw_rptr;
1319 } else {
1320 pr_debug("%s cq %p cqid 0x%x skip hw cqe rptr 0x%x\n",
1321 __func__, cq, cq->cqid, cq->rptr);
1322 ++cq->rptr;
1323
1324 /*
1325 * T3A: compute credits.
1326 */
1327 if (((cq->rptr - cq->wptr) > (1 << (cq->size_log2 - 1)))
1328 || ((cq->rptr - cq->wptr) >= 128)) {
1329 *credit = cq->rptr - cq->wptr;
1330 cq->wptr = cq->rptr;
1331 }
1332 }
1333 return ret;
1334 }
Ubuntu Artful kernel mirror