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cxgb3: Convert PDBG to pr_debug
[mirror_ubuntu-bionic-kernel.git] / drivers / infiniband / hw / cxgb3 / cxio_hal.c
1 /*
2 * Copyright (c) 2006 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32 #include <asm/delay.h>
33
34 #include <linux/mutex.h>
35 #include <linux/netdevice.h>
36 #include <linux/sched.h>
37 #include <linux/spinlock.h>
38 #include <linux/pci.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/slab.h>
41 #include <net/net_namespace.h>
42
43 #include "cxio_resource.h"
44 #include "cxio_hal.h"
45 #include "cxgb3_offload.h"
46 #include "sge_defs.h"
47
48 static LIST_HEAD(rdev_list);
49 static cxio_hal_ev_callback_func_t cxio_ev_cb = NULL;
50
51 static struct cxio_rdev *cxio_hal_find_rdev_by_name(char *dev_name)
52 {
53 struct cxio_rdev *rdev;
54
55 list_for_each_entry(rdev, &rdev_list, entry)
56 if (!strcmp(rdev->dev_name, dev_name))
57 return rdev;
58 return NULL;
59 }
60
61 static struct cxio_rdev *cxio_hal_find_rdev_by_t3cdev(struct t3cdev *tdev)
62 {
63 struct cxio_rdev *rdev;
64
65 list_for_each_entry(rdev, &rdev_list, entry)
66 if (rdev->t3cdev_p == tdev)
67 return rdev;
68 return NULL;
69 }
70
71 int cxio_hal_cq_op(struct cxio_rdev *rdev_p, struct t3_cq *cq,
72 enum t3_cq_opcode op, u32 credit)
73 {
74 int ret;
75 struct t3_cqe *cqe;
76 u32 rptr;
77
78 struct rdma_cq_op setup;
79 setup.id = cq->cqid;
80 setup.credits = (op == CQ_CREDIT_UPDATE) ? credit : 0;
81 setup.op = op;
82 ret = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_OP, &setup);
83
84 if ((ret < 0) || (op == CQ_CREDIT_UPDATE))
85 return ret;
86
87 /*
88 * If the rearm returned an index other than our current index,
89 * then there might be CQE's in flight (being DMA'd). We must wait
90 * here for them to complete or the consumer can miss a notification.
91 */
92 if (Q_PTR2IDX((cq->rptr), cq->size_log2) != ret) {
93 int i=0;
94
95 rptr = cq->rptr;
96
97 /*
98 * Keep the generation correct by bumping rptr until it
99 * matches the index returned by the rearm - 1.
100 */
101 while (Q_PTR2IDX((rptr+1), cq->size_log2) != ret)
102 rptr++;
103
104 /*
105 * Now rptr is the index for the (last) cqe that was
106 * in-flight at the time the HW rearmed the CQ. We
107 * spin until that CQE is valid.
108 */
109 cqe = cq->queue + Q_PTR2IDX(rptr, cq->size_log2);
110 while (!CQ_VLD_ENTRY(rptr, cq->size_log2, cqe)) {
111 udelay(1);
112 if (i++ > 1000000) {
113 pr_err("%s: stalled rnic\n", rdev_p->dev_name);
114 return -EIO;
115 }
116 }
117
118 return 1;
119 }
120
121 return 0;
122 }
123
124 static int cxio_hal_clear_cq_ctx(struct cxio_rdev *rdev_p, u32 cqid)
125 {
126 struct rdma_cq_setup setup;
127 setup.id = cqid;
128 setup.base_addr = 0; /* NULL address */
129 setup.size = 0; /* disaable the CQ */
130 setup.credits = 0;
131 setup.credit_thres = 0;
132 setup.ovfl_mode = 0;
133 return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
134 }
135
136 static int cxio_hal_clear_qp_ctx(struct cxio_rdev *rdev_p, u32 qpid)
137 {
138 u64 sge_cmd;
139 struct t3_modify_qp_wr *wqe;
140 struct sk_buff *skb = alloc_skb(sizeof(*wqe), GFP_KERNEL);
141 if (!skb) {
142 pr_debug("%s alloc_skb failed\n", __func__);
143 return -ENOMEM;
144 }
145 wqe = (struct t3_modify_qp_wr *) skb_put(skb, sizeof(*wqe));
146 memset(wqe, 0, sizeof(*wqe));
147 build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_QP_MOD,
148 T3_COMPLETION_FLAG | T3_NOTIFY_FLAG, 0, qpid, 7,
149 T3_SOPEOP);
150 wqe->flags = cpu_to_be32(MODQP_WRITE_EC);
151 sge_cmd = qpid << 8 | 3;
152 wqe->sge_cmd = cpu_to_be64(sge_cmd);
153 skb->priority = CPL_PRIORITY_CONTROL;
154 return iwch_cxgb3_ofld_send(rdev_p->t3cdev_p, skb);
155 }
156
157 int cxio_create_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq, int kernel)
158 {
159 struct rdma_cq_setup setup;
160 int size = (1UL << (cq->size_log2)) * sizeof(struct t3_cqe);
161
162 size += 1; /* one extra page for storing cq-in-err state */
163 cq->cqid = cxio_hal_get_cqid(rdev_p->rscp);
164 if (!cq->cqid)
165 return -ENOMEM;
166 if (kernel) {
167 cq->sw_queue = kzalloc(size, GFP_KERNEL);
168 if (!cq->sw_queue)
169 return -ENOMEM;
170 }
171 cq->queue = dma_alloc_coherent(&(rdev_p->rnic_info.pdev->dev), size,
172 &(cq->dma_addr), GFP_KERNEL);
173 if (!cq->queue) {
174 kfree(cq->sw_queue);
175 return -ENOMEM;
176 }
177 dma_unmap_addr_set(cq, mapping, cq->dma_addr);
178 memset(cq->queue, 0, size);
179 setup.id = cq->cqid;
180 setup.base_addr = (u64) (cq->dma_addr);
181 setup.size = 1UL << cq->size_log2;
182 setup.credits = 65535;
183 setup.credit_thres = 1;
184 if (rdev_p->t3cdev_p->type != T3A)
185 setup.ovfl_mode = 0;
186 else
187 setup.ovfl_mode = 1;
188 return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
189 }
190
191 #ifdef notyet
192 int cxio_resize_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq)
193 {
194 struct rdma_cq_setup setup;
195 setup.id = cq->cqid;
196 setup.base_addr = (u64) (cq->dma_addr);
197 setup.size = 1UL << cq->size_log2;
198 setup.credits = setup.size;
199 setup.credit_thres = setup.size; /* TBD: overflow recovery */
200 setup.ovfl_mode = 1;
201 return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
202 }
203 #endif
204
205 static u32 get_qpid(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx)
206 {
207 struct cxio_qpid_list *entry;
208 u32 qpid;
209 int i;
210
211 mutex_lock(&uctx->lock);
212 if (!list_empty(&uctx->qpids)) {
213 entry = list_entry(uctx->qpids.next, struct cxio_qpid_list,
214 entry);
215 list_del(&entry->entry);
216 qpid = entry->qpid;
217 kfree(entry);
218 } else {
219 qpid = cxio_hal_get_qpid(rdev_p->rscp);
220 if (!qpid)
221 goto out;
222 for (i = qpid+1; i & rdev_p->qpmask; i++) {
223 entry = kmalloc(sizeof *entry, GFP_KERNEL);
224 if (!entry)
225 break;
226 entry->qpid = i;
227 list_add_tail(&entry->entry, &uctx->qpids);
228 }
229 }
230 out:
231 mutex_unlock(&uctx->lock);
232 pr_debug("%s qpid 0x%x\n", __func__, qpid);
233 return qpid;
234 }
235
236 static void put_qpid(struct cxio_rdev *rdev_p, u32 qpid,
237 struct cxio_ucontext *uctx)
238 {
239 struct cxio_qpid_list *entry;
240
241 entry = kmalloc(sizeof *entry, GFP_KERNEL);
242 if (!entry)
243 return;
244 pr_debug("%s qpid 0x%x\n", __func__, qpid);
245 entry->qpid = qpid;
246 mutex_lock(&uctx->lock);
247 list_add_tail(&entry->entry, &uctx->qpids);
248 mutex_unlock(&uctx->lock);
249 }
250
251 void cxio_release_ucontext(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx)
252 {
253 struct list_head *pos, *nxt;
254 struct cxio_qpid_list *entry;
255
256 mutex_lock(&uctx->lock);
257 list_for_each_safe(pos, nxt, &uctx->qpids) {
258 entry = list_entry(pos, struct cxio_qpid_list, entry);
259 list_del_init(&entry->entry);
260 if (!(entry->qpid & rdev_p->qpmask))
261 cxio_hal_put_qpid(rdev_p->rscp, entry->qpid);
262 kfree(entry);
263 }
264 mutex_unlock(&uctx->lock);
265 }
266
267 void cxio_init_ucontext(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx)
268 {
269 INIT_LIST_HEAD(&uctx->qpids);
270 mutex_init(&uctx->lock);
271 }
272
273 int cxio_create_qp(struct cxio_rdev *rdev_p, u32 kernel_domain,
274 struct t3_wq *wq, struct cxio_ucontext *uctx)
275 {
276 int depth = 1UL << wq->size_log2;
277 int rqsize = 1UL << wq->rq_size_log2;
278
279 wq->qpid = get_qpid(rdev_p, uctx);
280 if (!wq->qpid)
281 return -ENOMEM;
282
283 wq->rq = kzalloc(depth * sizeof(struct t3_swrq), GFP_KERNEL);
284 if (!wq->rq)
285 goto err1;
286
287 wq->rq_addr = cxio_hal_rqtpool_alloc(rdev_p, rqsize);
288 if (!wq->rq_addr)
289 goto err2;
290
291 wq->sq = kzalloc(depth * sizeof(struct t3_swsq), GFP_KERNEL);
292 if (!wq->sq)
293 goto err3;
294
295 wq->queue = dma_alloc_coherent(&(rdev_p->rnic_info.pdev->dev),
296 depth * sizeof(union t3_wr),
297 &(wq->dma_addr), GFP_KERNEL);
298 if (!wq->queue)
299 goto err4;
300
301 memset(wq->queue, 0, depth * sizeof(union t3_wr));
302 dma_unmap_addr_set(wq, mapping, wq->dma_addr);
303 wq->doorbell = (void __iomem *)rdev_p->rnic_info.kdb_addr;
304 if (!kernel_domain)
305 wq->udb = (u64)rdev_p->rnic_info.udbell_physbase +
306 (wq->qpid << rdev_p->qpshift);
307 wq->rdev = rdev_p;
308 pr_debug("%s qpid 0x%x doorbell 0x%p udb 0x%llx\n",
309 __func__, wq->qpid, wq->doorbell, (unsigned long long)wq->udb);
310 return 0;
311 err4:
312 kfree(wq->sq);
313 err3:
314 cxio_hal_rqtpool_free(rdev_p, wq->rq_addr, rqsize);
315 err2:
316 kfree(wq->rq);
317 err1:
318 put_qpid(rdev_p, wq->qpid, uctx);
319 return -ENOMEM;
320 }
321
322 int cxio_destroy_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq)
323 {
324 int err;
325 err = cxio_hal_clear_cq_ctx(rdev_p, cq->cqid);
326 kfree(cq->sw_queue);
327 dma_free_coherent(&(rdev_p->rnic_info.pdev->dev),
328 (1UL << (cq->size_log2))
329 * sizeof(struct t3_cqe) + 1, cq->queue,
330 dma_unmap_addr(cq, mapping));
331 cxio_hal_put_cqid(rdev_p->rscp, cq->cqid);
332 return err;
333 }
334
335 int cxio_destroy_qp(struct cxio_rdev *rdev_p, struct t3_wq *wq,
336 struct cxio_ucontext *uctx)
337 {
338 dma_free_coherent(&(rdev_p->rnic_info.pdev->dev),
339 (1UL << (wq->size_log2))
340 * sizeof(union t3_wr), wq->queue,
341 dma_unmap_addr(wq, mapping));
342 kfree(wq->sq);
343 cxio_hal_rqtpool_free(rdev_p, wq->rq_addr, (1UL << wq->rq_size_log2));
344 kfree(wq->rq);
345 put_qpid(rdev_p, wq->qpid, uctx);
346 return 0;
347 }
348
349 static void insert_recv_cqe(struct t3_wq *wq, struct t3_cq *cq)
350 {
351 struct t3_cqe cqe;
352
353 pr_debug("%s wq %p cq %p sw_rptr 0x%x sw_wptr 0x%x\n", __func__,
354 wq, cq, cq->sw_rptr, cq->sw_wptr);
355 memset(&cqe, 0, sizeof(cqe));
356 cqe.header = cpu_to_be32(V_CQE_STATUS(TPT_ERR_SWFLUSH) |
357 V_CQE_OPCODE(T3_SEND) |
358 V_CQE_TYPE(0) |
359 V_CQE_SWCQE(1) |
360 V_CQE_QPID(wq->qpid) |
361 V_CQE_GENBIT(Q_GENBIT(cq->sw_wptr,
362 cq->size_log2)));
363 *(cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2)) = cqe;
364 cq->sw_wptr++;
365 }
366
367 int cxio_flush_rq(struct t3_wq *wq, struct t3_cq *cq, int count)
368 {
369 u32 ptr;
370 int flushed = 0;
371
372 pr_debug("%s wq %p cq %p\n", __func__, wq, cq);
373
374 /* flush RQ */
375 pr_debug("%s rq_rptr %u rq_wptr %u skip count %u\n", __func__,
376 wq->rq_rptr, wq->rq_wptr, count);
377 ptr = wq->rq_rptr + count;
378 while (ptr++ != wq->rq_wptr) {
379 insert_recv_cqe(wq, cq);
380 flushed++;
381 }
382 return flushed;
383 }
384
385 static void insert_sq_cqe(struct t3_wq *wq, struct t3_cq *cq,
386 struct t3_swsq *sqp)
387 {
388 struct t3_cqe cqe;
389
390 pr_debug("%s wq %p cq %p sw_rptr 0x%x sw_wptr 0x%x\n", __func__,
391 wq, cq, cq->sw_rptr, cq->sw_wptr);
392 memset(&cqe, 0, sizeof(cqe));
393 cqe.header = cpu_to_be32(V_CQE_STATUS(TPT_ERR_SWFLUSH) |
394 V_CQE_OPCODE(sqp->opcode) |
395 V_CQE_TYPE(1) |
396 V_CQE_SWCQE(1) |
397 V_CQE_QPID(wq->qpid) |
398 V_CQE_GENBIT(Q_GENBIT(cq->sw_wptr,
399 cq->size_log2)));
400 cqe.u.scqe.wrid_hi = sqp->sq_wptr;
401
402 *(cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2)) = cqe;
403 cq->sw_wptr++;
404 }
405
406 int cxio_flush_sq(struct t3_wq *wq, struct t3_cq *cq, int count)
407 {
408 __u32 ptr;
409 int flushed = 0;
410 struct t3_swsq *sqp = wq->sq + Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2);
411
412 ptr = wq->sq_rptr + count;
413 sqp = wq->sq + Q_PTR2IDX(ptr, wq->sq_size_log2);
414 while (ptr != wq->sq_wptr) {
415 sqp->signaled = 0;
416 insert_sq_cqe(wq, cq, sqp);
417 ptr++;
418 sqp = wq->sq + Q_PTR2IDX(ptr, wq->sq_size_log2);
419 flushed++;
420 }
421 return flushed;
422 }
423
424 /*
425 * Move all CQEs from the HWCQ into the SWCQ.
426 */
427 void cxio_flush_hw_cq(struct t3_cq *cq)
428 {
429 struct t3_cqe *cqe, *swcqe;
430
431 pr_debug("%s cq %p cqid 0x%x\n", __func__, cq, cq->cqid);
432 cqe = cxio_next_hw_cqe(cq);
433 while (cqe) {
434 pr_debug("%s flushing hwcq rptr 0x%x to swcq wptr 0x%x\n",
435 __func__, cq->rptr, cq->sw_wptr);
436 swcqe = cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2);
437 *swcqe = *cqe;
438 swcqe->header |= cpu_to_be32(V_CQE_SWCQE(1));
439 cq->sw_wptr++;
440 cq->rptr++;
441 cqe = cxio_next_hw_cqe(cq);
442 }
443 }
444
445 static int cqe_completes_wr(struct t3_cqe *cqe, struct t3_wq *wq)
446 {
447 if (CQE_OPCODE(*cqe) == T3_TERMINATE)
448 return 0;
449
450 if ((CQE_OPCODE(*cqe) == T3_RDMA_WRITE) && RQ_TYPE(*cqe))
451 return 0;
452
453 if ((CQE_OPCODE(*cqe) == T3_READ_RESP) && SQ_TYPE(*cqe))
454 return 0;
455
456 if (CQE_SEND_OPCODE(*cqe) && RQ_TYPE(*cqe) &&
457 Q_EMPTY(wq->rq_rptr, wq->rq_wptr))
458 return 0;
459
460 return 1;
461 }
462
463 void cxio_count_scqes(struct t3_cq *cq, struct t3_wq *wq, int *count)
464 {
465 struct t3_cqe *cqe;
466 u32 ptr;
467
468 *count = 0;
469 ptr = cq->sw_rptr;
470 while (!Q_EMPTY(ptr, cq->sw_wptr)) {
471 cqe = cq->sw_queue + (Q_PTR2IDX(ptr, cq->size_log2));
472 if ((SQ_TYPE(*cqe) ||
473 ((CQE_OPCODE(*cqe) == T3_READ_RESP) && wq->oldest_read)) &&
474 (CQE_QPID(*cqe) == wq->qpid))
475 (*count)++;
476 ptr++;
477 }
478 pr_debug("%s cq %p count %d\n", __func__, cq, *count);
479 }
480
481 void cxio_count_rcqes(struct t3_cq *cq, struct t3_wq *wq, int *count)
482 {
483 struct t3_cqe *cqe;
484 u32 ptr;
485
486 *count = 0;
487 pr_debug("%s count zero %d\n", __func__, *count);
488 ptr = cq->sw_rptr;
489 while (!Q_EMPTY(ptr, cq->sw_wptr)) {
490 cqe = cq->sw_queue + (Q_PTR2IDX(ptr, cq->size_log2));
491 if (RQ_TYPE(*cqe) && (CQE_OPCODE(*cqe) != T3_READ_RESP) &&
492 (CQE_QPID(*cqe) == wq->qpid) && cqe_completes_wr(cqe, wq))
493 (*count)++;
494 ptr++;
495 }
496 pr_debug("%s cq %p count %d\n", __func__, cq, *count);
497 }
498
499 static int cxio_hal_init_ctrl_cq(struct cxio_rdev *rdev_p)
500 {
501 struct rdma_cq_setup setup;
502 setup.id = 0;
503 setup.base_addr = 0; /* NULL address */
504 setup.size = 1; /* enable the CQ */
505 setup.credits = 0;
506
507 /* force SGE to redirect to RspQ and interrupt */
508 setup.credit_thres = 0;
509 setup.ovfl_mode = 1;
510 return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
511 }
512
513 static int cxio_hal_init_ctrl_qp(struct cxio_rdev *rdev_p)
514 {
515 int err;
516 u64 sge_cmd, ctx0, ctx1;
517 u64 base_addr;
518 struct t3_modify_qp_wr *wqe;
519 struct sk_buff *skb;
520
521 skb = alloc_skb(sizeof(*wqe), GFP_KERNEL);
522 if (!skb) {
523 pr_debug("%s alloc_skb failed\n", __func__);
524 return -ENOMEM;
525 }
526 err = cxio_hal_init_ctrl_cq(rdev_p);
527 if (err) {
528 pr_debug("%s err %d initializing ctrl_cq\n", __func__, err);
529 goto err;
530 }
531 rdev_p->ctrl_qp.workq = dma_alloc_coherent(
532 &(rdev_p->rnic_info.pdev->dev),
533 (1 << T3_CTRL_QP_SIZE_LOG2) *
534 sizeof(union t3_wr),
535 &(rdev_p->ctrl_qp.dma_addr),
536 GFP_KERNEL);
537 if (!rdev_p->ctrl_qp.workq) {
538 pr_debug("%s dma_alloc_coherent failed\n", __func__);
539 err = -ENOMEM;
540 goto err;
541 }
542 dma_unmap_addr_set(&rdev_p->ctrl_qp, mapping,
543 rdev_p->ctrl_qp.dma_addr);
544 rdev_p->ctrl_qp.doorbell = (void __iomem *)rdev_p->rnic_info.kdb_addr;
545 memset(rdev_p->ctrl_qp.workq, 0,
546 (1 << T3_CTRL_QP_SIZE_LOG2) * sizeof(union t3_wr));
547
548 mutex_init(&rdev_p->ctrl_qp.lock);
549 init_waitqueue_head(&rdev_p->ctrl_qp.waitq);
550
551 /* update HW Ctrl QP context */
552 base_addr = rdev_p->ctrl_qp.dma_addr;
553 base_addr >>= 12;
554 ctx0 = (V_EC_SIZE((1 << T3_CTRL_QP_SIZE_LOG2)) |
555 V_EC_BASE_LO((u32) base_addr & 0xffff));
556 ctx0 <<= 32;
557 ctx0 |= V_EC_CREDITS(FW_WR_NUM);
558 base_addr >>= 16;
559 ctx1 = (u32) base_addr;
560 base_addr >>= 32;
561 ctx1 |= ((u64) (V_EC_BASE_HI((u32) base_addr & 0xf) | V_EC_RESPQ(0) |
562 V_EC_TYPE(0) | V_EC_GEN(1) |
563 V_EC_UP_TOKEN(T3_CTL_QP_TID) | F_EC_VALID)) << 32;
564 wqe = (struct t3_modify_qp_wr *) skb_put(skb, sizeof(*wqe));
565 memset(wqe, 0, sizeof(*wqe));
566 build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_QP_MOD, 0, 0,
567 T3_CTL_QP_TID, 7, T3_SOPEOP);
568 wqe->flags = cpu_to_be32(MODQP_WRITE_EC);
569 sge_cmd = (3ULL << 56) | FW_RI_SGEEC_START << 8 | 3;
570 wqe->sge_cmd = cpu_to_be64(sge_cmd);
571 wqe->ctx1 = cpu_to_be64(ctx1);
572 wqe->ctx0 = cpu_to_be64(ctx0);
573 pr_debug("CtrlQP dma_addr 0x%llx workq %p size %d\n",
574 (unsigned long long)rdev_p->ctrl_qp.dma_addr,
575 rdev_p->ctrl_qp.workq, 1 << T3_CTRL_QP_SIZE_LOG2);
576 skb->priority = CPL_PRIORITY_CONTROL;
577 return iwch_cxgb3_ofld_send(rdev_p->t3cdev_p, skb);
578 err:
579 kfree_skb(skb);
580 return err;
581 }
582
583 static int cxio_hal_destroy_ctrl_qp(struct cxio_rdev *rdev_p)
584 {
585 dma_free_coherent(&(rdev_p->rnic_info.pdev->dev),
586 (1UL << T3_CTRL_QP_SIZE_LOG2)
587 * sizeof(union t3_wr), rdev_p->ctrl_qp.workq,
588 dma_unmap_addr(&rdev_p->ctrl_qp, mapping));
589 return cxio_hal_clear_qp_ctx(rdev_p, T3_CTRL_QP_ID);
590 }
591
592 /* write len bytes of data into addr (32B aligned address)
593 * If data is NULL, clear len byte of memory to zero.
594 * caller acquires the ctrl_qp lock before the call
595 */
596 static int cxio_hal_ctrl_qp_write_mem(struct cxio_rdev *rdev_p, u32 addr,
597 u32 len, void *data)
598 {
599 u32 i, nr_wqe, copy_len;
600 u8 *copy_data;
601 u8 wr_len, utx_len; /* length in 8 byte flit */
602 enum t3_wr_flags flag;
603 __be64 *wqe;
604 u64 utx_cmd;
605 addr &= 0x7FFFFFF;
606 nr_wqe = len % 96 ? len / 96 + 1 : len / 96; /* 96B max per WQE */
607 pr_debug("%s wptr 0x%x rptr 0x%x len %d, nr_wqe %d data %p addr 0x%0x\n",
608 __func__, rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, len,
609 nr_wqe, data, addr);
610 utx_len = 3; /* in 32B unit */
611 for (i = 0; i < nr_wqe; i++) {
612 if (Q_FULL(rdev_p->ctrl_qp.rptr, rdev_p->ctrl_qp.wptr,
613 T3_CTRL_QP_SIZE_LOG2)) {
614 pr_debug("%s ctrl_qp full wtpr 0x%0x rptr 0x%0x, wait for more space i %d\n",
615 __func__,
616 rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, i);
617 if (wait_event_interruptible(rdev_p->ctrl_qp.waitq,
618 !Q_FULL(rdev_p->ctrl_qp.rptr,
619 rdev_p->ctrl_qp.wptr,
620 T3_CTRL_QP_SIZE_LOG2))) {
621 pr_debug("%s ctrl_qp workq interrupted\n",
622 __func__);
623 return -ERESTARTSYS;
624 }
625 pr_debug("%s ctrl_qp wakeup, continue posting work request i %d\n",
626 __func__, i);
627 }
628 wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr %
629 (1 << T3_CTRL_QP_SIZE_LOG2)));
630 flag = 0;
631 if (i == (nr_wqe - 1)) {
632 /* last WQE */
633 flag = T3_COMPLETION_FLAG;
634 if (len % 32)
635 utx_len = len / 32 + 1;
636 else
637 utx_len = len / 32;
638 }
639
640 /*
641 * Force a CQE to return the credit to the workq in case
642 * we posted more than half the max QP size of WRs
643 */
644 if ((i != 0) &&
645 (i % (((1 << T3_CTRL_QP_SIZE_LOG2)) >> 1) == 0)) {
646 flag = T3_COMPLETION_FLAG;
647 pr_debug("%s force completion at i %d\n", __func__, i);
648 }
649
650 /* build the utx mem command */
651 wqe += (sizeof(struct t3_bypass_wr) >> 3);
652 utx_cmd = (T3_UTX_MEM_WRITE << 28) | (addr + i * 3);
653 utx_cmd <<= 32;
654 utx_cmd |= (utx_len << 28) | ((utx_len << 2) + 1);
655 *wqe = cpu_to_be64(utx_cmd);
656 wqe++;
657 copy_data = (u8 *) data + i * 96;
658 copy_len = len > 96 ? 96 : len;
659
660 /* clear memory content if data is NULL */
661 if (data)
662 memcpy(wqe, copy_data, copy_len);
663 else
664 memset(wqe, 0, copy_len);
665 if (copy_len % 32)
666 memset(((u8 *) wqe) + copy_len, 0,
667 32 - (copy_len % 32));
668 wr_len = ((sizeof(struct t3_bypass_wr)) >> 3) + 1 +
669 (utx_len << 2);
670 wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr %
671 (1 << T3_CTRL_QP_SIZE_LOG2)));
672
673 /* wptr in the WRID[31:0] */
674 ((union t3_wrid *)(wqe+1))->id0.low = rdev_p->ctrl_qp.wptr;
675
676 /*
677 * This must be the last write with a memory barrier
678 * for the genbit
679 */
680 build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_BP, flag,
681 Q_GENBIT(rdev_p->ctrl_qp.wptr,
682 T3_CTRL_QP_SIZE_LOG2), T3_CTRL_QP_ID,
683 wr_len, T3_SOPEOP);
684 if (flag == T3_COMPLETION_FLAG)
685 ring_doorbell(rdev_p->ctrl_qp.doorbell, T3_CTRL_QP_ID);
686 len -= 96;
687 rdev_p->ctrl_qp.wptr++;
688 }
689 return 0;
690 }
691
692 /* IN: stag key, pdid, perm, zbva, to, len, page_size, pbl_size and pbl_addr
693 * OUT: stag index
694 * TBD: shared memory region support
695 */
696 static int __cxio_tpt_op(struct cxio_rdev *rdev_p, u32 reset_tpt_entry,
697 u32 *stag, u8 stag_state, u32 pdid,
698 enum tpt_mem_type type, enum tpt_mem_perm perm,
699 u32 zbva, u64 to, u32 len, u8 page_size,
700 u32 pbl_size, u32 pbl_addr)
701 {
702 int err;
703 struct tpt_entry tpt;
704 u32 stag_idx;
705 u32 wptr;
706
707 if (cxio_fatal_error(rdev_p))
708 return -EIO;
709
710 stag_state = stag_state > 0;
711 stag_idx = (*stag) >> 8;
712
713 if ((!reset_tpt_entry) && !(*stag != T3_STAG_UNSET)) {
714 stag_idx = cxio_hal_get_stag(rdev_p->rscp);
715 if (!stag_idx)
716 return -ENOMEM;
717 *stag = (stag_idx << 8) | ((*stag) & 0xFF);
718 }
719 pr_debug("%s stag_state 0x%0x type 0x%0x pdid 0x%0x, stag_idx 0x%x\n",
720 __func__, stag_state, type, pdid, stag_idx);
721
722 mutex_lock(&rdev_p->ctrl_qp.lock);
723
724 /* write TPT entry */
725 if (reset_tpt_entry)
726 memset(&tpt, 0, sizeof(tpt));
727 else {
728 tpt.valid_stag_pdid = cpu_to_be32(F_TPT_VALID |
729 V_TPT_STAG_KEY((*stag) & M_TPT_STAG_KEY) |
730 V_TPT_STAG_STATE(stag_state) |
731 V_TPT_STAG_TYPE(type) | V_TPT_PDID(pdid));
732 BUG_ON(page_size >= 28);
733 tpt.flags_pagesize_qpid = cpu_to_be32(V_TPT_PERM(perm) |
734 ((perm & TPT_MW_BIND) ? F_TPT_MW_BIND_ENABLE : 0) |
735 V_TPT_ADDR_TYPE((zbva ? TPT_ZBTO : TPT_VATO)) |
736 V_TPT_PAGE_SIZE(page_size));
737 tpt.rsvd_pbl_addr = cpu_to_be32(V_TPT_PBL_ADDR(PBL_OFF(rdev_p, pbl_addr)>>3));
738 tpt.len = cpu_to_be32(len);
739 tpt.va_hi = cpu_to_be32((u32) (to >> 32));
740 tpt.va_low_or_fbo = cpu_to_be32((u32) (to & 0xFFFFFFFFULL));
741 tpt.rsvd_bind_cnt_or_pstag = 0;
742 tpt.rsvd_pbl_size = cpu_to_be32(V_TPT_PBL_SIZE(pbl_size >> 2));
743 }
744 err = cxio_hal_ctrl_qp_write_mem(rdev_p,
745 stag_idx +
746 (rdev_p->rnic_info.tpt_base >> 5),
747 sizeof(tpt), &tpt);
748
749 /* release the stag index to free pool */
750 if (reset_tpt_entry)
751 cxio_hal_put_stag(rdev_p->rscp, stag_idx);
752
753 wptr = rdev_p->ctrl_qp.wptr;
754 mutex_unlock(&rdev_p->ctrl_qp.lock);
755 if (!err)
756 if (wait_event_interruptible(rdev_p->ctrl_qp.waitq,
757 SEQ32_GE(rdev_p->ctrl_qp.rptr,
758 wptr)))
759 return -ERESTARTSYS;
760 return err;
761 }
762
763 int cxio_write_pbl(struct cxio_rdev *rdev_p, __be64 *pbl,
764 u32 pbl_addr, u32 pbl_size)
765 {
766 u32 wptr;
767 int err;
768
769 pr_debug("%s *pdb_addr 0x%x, pbl_base 0x%x, pbl_size %d\n",
770 __func__, pbl_addr, rdev_p->rnic_info.pbl_base,
771 pbl_size);
772
773 mutex_lock(&rdev_p->ctrl_qp.lock);
774 err = cxio_hal_ctrl_qp_write_mem(rdev_p, pbl_addr >> 5, pbl_size << 3,
775 pbl);
776 wptr = rdev_p->ctrl_qp.wptr;
777 mutex_unlock(&rdev_p->ctrl_qp.lock);
778 if (err)
779 return err;
780
781 if (wait_event_interruptible(rdev_p->ctrl_qp.waitq,
782 SEQ32_GE(rdev_p->ctrl_qp.rptr,
783 wptr)))
784 return -ERESTARTSYS;
785
786 return 0;
787 }
788
789 int cxio_register_phys_mem(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid,
790 enum tpt_mem_perm perm, u32 zbva, u64 to, u32 len,
791 u8 page_size, u32 pbl_size, u32 pbl_addr)
792 {
793 *stag = T3_STAG_UNSET;
794 return __cxio_tpt_op(rdev_p, 0, stag, 1, pdid, TPT_NON_SHARED_MR, perm,
795 zbva, to, len, page_size, pbl_size, pbl_addr);
796 }
797
798 int cxio_reregister_phys_mem(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid,
799 enum tpt_mem_perm perm, u32 zbva, u64 to, u32 len,
800 u8 page_size, u32 pbl_size, u32 pbl_addr)
801 {
802 return __cxio_tpt_op(rdev_p, 0, stag, 1, pdid, TPT_NON_SHARED_MR, perm,
803 zbva, to, len, page_size, pbl_size, pbl_addr);
804 }
805
806 int cxio_dereg_mem(struct cxio_rdev *rdev_p, u32 stag, u32 pbl_size,
807 u32 pbl_addr)
808 {
809 return __cxio_tpt_op(rdev_p, 1, &stag, 0, 0, 0, 0, 0, 0ULL, 0, 0,
810 pbl_size, pbl_addr);
811 }
812
813 int cxio_allocate_window(struct cxio_rdev *rdev_p, u32 * stag, u32 pdid)
814 {
815 *stag = T3_STAG_UNSET;
816 return __cxio_tpt_op(rdev_p, 0, stag, 0, pdid, TPT_MW, 0, 0, 0ULL, 0, 0,
817 0, 0);
818 }
819
820 int cxio_deallocate_window(struct cxio_rdev *rdev_p, u32 stag)
821 {
822 return __cxio_tpt_op(rdev_p, 1, &stag, 0, 0, 0, 0, 0, 0ULL, 0, 0,
823 0, 0);
824 }
825
826 int cxio_allocate_stag(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid, u32 pbl_size, u32 pbl_addr)
827 {
828 *stag = T3_STAG_UNSET;
829 return __cxio_tpt_op(rdev_p, 0, stag, 0, pdid, TPT_NON_SHARED_MR,
830 0, 0, 0ULL, 0, 0, pbl_size, pbl_addr);
831 }
832
833 int cxio_rdma_init(struct cxio_rdev *rdev_p, struct t3_rdma_init_attr *attr)
834 {
835 struct t3_rdma_init_wr *wqe;
836 struct sk_buff *skb = alloc_skb(sizeof(*wqe), GFP_ATOMIC);
837 if (!skb)
838 return -ENOMEM;
839 pr_debug("%s rdev_p %p\n", __func__, rdev_p);
840 wqe = (struct t3_rdma_init_wr *) __skb_put(skb, sizeof(*wqe));
841 wqe->wrh.op_seop_flags = cpu_to_be32(V_FW_RIWR_OP(T3_WR_INIT));
842 wqe->wrh.gen_tid_len = cpu_to_be32(V_FW_RIWR_TID(attr->tid) |
843 V_FW_RIWR_LEN(sizeof(*wqe) >> 3));
844 wqe->wrid.id1 = 0;
845 wqe->qpid = cpu_to_be32(attr->qpid);
846 wqe->pdid = cpu_to_be32(attr->pdid);
847 wqe->scqid = cpu_to_be32(attr->scqid);
848 wqe->rcqid = cpu_to_be32(attr->rcqid);
849 wqe->rq_addr = cpu_to_be32(attr->rq_addr - rdev_p->rnic_info.rqt_base);
850 wqe->rq_size = cpu_to_be32(attr->rq_size);
851 wqe->mpaattrs = attr->mpaattrs;
852 wqe->qpcaps = attr->qpcaps;
853 wqe->ulpdu_size = cpu_to_be16(attr->tcp_emss);
854 wqe->rqe_count = cpu_to_be16(attr->rqe_count);
855 wqe->flags_rtr_type = cpu_to_be16(attr->flags |
856 V_RTR_TYPE(attr->rtr_type) |
857 V_CHAN(attr->chan));
858 wqe->ord = cpu_to_be32(attr->ord);
859 wqe->ird = cpu_to_be32(attr->ird);
860 wqe->qp_dma_addr = cpu_to_be64(attr->qp_dma_addr);
861 wqe->qp_dma_size = cpu_to_be32(attr->qp_dma_size);
862 wqe->irs = cpu_to_be32(attr->irs);
863 skb->priority = 0; /* 0=>ToeQ; 1=>CtrlQ */
864 return iwch_cxgb3_ofld_send(rdev_p->t3cdev_p, skb);
865 }
866
867 void cxio_register_ev_cb(cxio_hal_ev_callback_func_t ev_cb)
868 {
869 cxio_ev_cb = ev_cb;
870 }
871
872 void cxio_unregister_ev_cb(cxio_hal_ev_callback_func_t ev_cb)
873 {
874 cxio_ev_cb = NULL;
875 }
876
877 static int cxio_hal_ev_handler(struct t3cdev *t3cdev_p, struct sk_buff *skb)
878 {
879 static int cnt;
880 struct cxio_rdev *rdev_p = NULL;
881 struct respQ_msg_t *rsp_msg = (struct respQ_msg_t *) skb->data;
882 pr_debug("%d: %s cq_id 0x%x cq_ptr 0x%x genbit %0x overflow %0x an %0x se %0x notify %0x cqbranch %0x creditth %0x\n",
883 cnt, __func__, RSPQ_CQID(rsp_msg), RSPQ_CQPTR(rsp_msg),
884 RSPQ_GENBIT(rsp_msg), RSPQ_OVERFLOW(rsp_msg), RSPQ_AN(rsp_msg),
885 RSPQ_SE(rsp_msg), RSPQ_NOTIFY(rsp_msg), RSPQ_CQBRANCH(rsp_msg),
886 RSPQ_CREDIT_THRESH(rsp_msg));
887 pr_debug("CQE: QPID 0x%0x genbit %0x type 0x%0x status 0x%0x opcode %d len 0x%0x wrid_hi_stag 0x%x wrid_low_msn 0x%x\n",
888 CQE_QPID(rsp_msg->cqe), CQE_GENBIT(rsp_msg->cqe),
889 CQE_TYPE(rsp_msg->cqe), CQE_STATUS(rsp_msg->cqe),
890 CQE_OPCODE(rsp_msg->cqe), CQE_LEN(rsp_msg->cqe),
891 CQE_WRID_HI(rsp_msg->cqe), CQE_WRID_LOW(rsp_msg->cqe));
892 rdev_p = (struct cxio_rdev *)t3cdev_p->ulp;
893 if (!rdev_p) {
894 pr_debug("%s called by t3cdev %p with null ulp\n", __func__,
895 t3cdev_p);
896 return 0;
897 }
898 if (CQE_QPID(rsp_msg->cqe) == T3_CTRL_QP_ID) {
899 rdev_p->ctrl_qp.rptr = CQE_WRID_LOW(rsp_msg->cqe) + 1;
900 wake_up_interruptible(&rdev_p->ctrl_qp.waitq);
901 dev_kfree_skb_irq(skb);
902 } else if (CQE_QPID(rsp_msg->cqe) == 0xfff8)
903 dev_kfree_skb_irq(skb);
904 else if (cxio_ev_cb)
905 (*cxio_ev_cb) (rdev_p, skb);
906 else
907 dev_kfree_skb_irq(skb);
908 cnt++;
909 return 0;
910 }
911
912 /* Caller takes care of locking if needed */
913 int cxio_rdev_open(struct cxio_rdev *rdev_p)
914 {
915 struct net_device *netdev_p = NULL;
916 int err = 0;
917 if (strlen(rdev_p->dev_name)) {
918 if (cxio_hal_find_rdev_by_name(rdev_p->dev_name)) {
919 return -EBUSY;
920 }
921 netdev_p = dev_get_by_name(&init_net, rdev_p->dev_name);
922 if (!netdev_p) {
923 return -EINVAL;
924 }
925 dev_put(netdev_p);
926 } else if (rdev_p->t3cdev_p) {
927 if (cxio_hal_find_rdev_by_t3cdev(rdev_p->t3cdev_p)) {
928 return -EBUSY;
929 }
930 netdev_p = rdev_p->t3cdev_p->lldev;
931 strncpy(rdev_p->dev_name, rdev_p->t3cdev_p->name,
932 T3_MAX_DEV_NAME_LEN);
933 } else {
934 pr_debug("%s t3cdev_p or dev_name must be set\n", __func__);
935 return -EINVAL;
936 }
937
938 list_add_tail(&rdev_p->entry, &rdev_list);
939
940 pr_debug("%s opening rnic dev %s\n", __func__, rdev_p->dev_name);
941 memset(&rdev_p->ctrl_qp, 0, sizeof(rdev_p->ctrl_qp));
942 if (!rdev_p->t3cdev_p)
943 rdev_p->t3cdev_p = dev2t3cdev(netdev_p);
944 rdev_p->t3cdev_p->ulp = (void *) rdev_p;
945
946 err = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, GET_EMBEDDED_INFO,
947 &(rdev_p->fw_info));
948 if (err) {
949 pr_err("%s t3cdev_p(%p)->ctl returned error %d\n",
950 __func__, rdev_p->t3cdev_p, err);
951 goto err1;
952 }
953 if (G_FW_VERSION_MAJOR(rdev_p->fw_info.fw_vers) != CXIO_FW_MAJ) {
954 pr_err("fatal firmware version mismatch: need version %u but adapter has version %u\n",
955 CXIO_FW_MAJ,
956 G_FW_VERSION_MAJOR(rdev_p->fw_info.fw_vers));
957 err = -EINVAL;
958 goto err1;
959 }
960
961 err = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_GET_PARAMS,
962 &(rdev_p->rnic_info));
963 if (err) {
964 pr_err("%s t3cdev_p(%p)->ctl returned error %d\n",
965 __func__, rdev_p->t3cdev_p, err);
966 goto err1;
967 }
968 err = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, GET_PORTS,
969 &(rdev_p->port_info));
970 if (err) {
971 pr_err("%s t3cdev_p(%p)->ctl returned error %d\n",
972 __func__, rdev_p->t3cdev_p, err);
973 goto err1;
974 }
975
976 /*
977 * qpshift is the number of bits to shift the qpid left in order
978 * to get the correct address of the doorbell for that qp.
979 */
980 cxio_init_ucontext(rdev_p, &rdev_p->uctx);
981 rdev_p->qpshift = PAGE_SHIFT -
982 ilog2(65536 >>
983 ilog2(rdev_p->rnic_info.udbell_len >>
984 PAGE_SHIFT));
985 rdev_p->qpnr = rdev_p->rnic_info.udbell_len >> PAGE_SHIFT;
986 rdev_p->qpmask = (65536 >> ilog2(rdev_p->qpnr)) - 1;
987 pr_debug("%s rnic %s info: tpt_base 0x%0x tpt_top 0x%0x num stags %d pbl_base 0x%0x pbl_top 0x%0x rqt_base 0x%0x, rqt_top 0x%0x\n",
988 __func__, rdev_p->dev_name, rdev_p->rnic_info.tpt_base,
989 rdev_p->rnic_info.tpt_top, cxio_num_stags(rdev_p),
990 rdev_p->rnic_info.pbl_base,
991 rdev_p->rnic_info.pbl_top, rdev_p->rnic_info.rqt_base,
992 rdev_p->rnic_info.rqt_top);
993 pr_debug("udbell_len 0x%0x udbell_physbase 0x%lx kdb_addr %p qpshift %lu qpnr %d qpmask 0x%x\n",
994 rdev_p->rnic_info.udbell_len,
995 rdev_p->rnic_info.udbell_physbase, rdev_p->rnic_info.kdb_addr,
996 rdev_p->qpshift, rdev_p->qpnr, rdev_p->qpmask);
997
998 err = cxio_hal_init_ctrl_qp(rdev_p);
999 if (err) {
1000 pr_err("%s error %d initializing ctrl_qp\n", __func__, err);
1001 goto err1;
1002 }
1003 err = cxio_hal_init_resource(rdev_p, cxio_num_stags(rdev_p), 0,
1004 0, T3_MAX_NUM_QP, T3_MAX_NUM_CQ,
1005 T3_MAX_NUM_PD);
1006 if (err) {
1007 pr_err("%s error %d initializing hal resources\n",
1008 __func__, err);
1009 goto err2;
1010 }
1011 err = cxio_hal_pblpool_create(rdev_p);
1012 if (err) {
1013 pr_err("%s error %d initializing pbl mem pool\n",
1014 __func__, err);
1015 goto err3;
1016 }
1017 err = cxio_hal_rqtpool_create(rdev_p);
1018 if (err) {
1019 pr_err("%s error %d initializing rqt mem pool\n",
1020 __func__, err);
1021 goto err4;
1022 }
1023 return 0;
1024 err4:
1025 cxio_hal_pblpool_destroy(rdev_p);
1026 err3:
1027 cxio_hal_destroy_resource(rdev_p->rscp);
1028 err2:
1029 cxio_hal_destroy_ctrl_qp(rdev_p);
1030 err1:
1031 rdev_p->t3cdev_p->ulp = NULL;
1032 list_del(&rdev_p->entry);
1033 return err;
1034 }
1035
1036 void cxio_rdev_close(struct cxio_rdev *rdev_p)
1037 {
1038 if (rdev_p) {
1039 cxio_hal_pblpool_destroy(rdev_p);
1040 cxio_hal_rqtpool_destroy(rdev_p);
1041 list_del(&rdev_p->entry);
1042 cxio_hal_destroy_ctrl_qp(rdev_p);
1043 cxio_hal_destroy_resource(rdev_p->rscp);
1044 rdev_p->t3cdev_p->ulp = NULL;
1045 }
1046 }
1047
1048 int __init cxio_hal_init(void)
1049 {
1050 if (cxio_hal_init_rhdl_resource(T3_MAX_NUM_RI))
1051 return -ENOMEM;
1052 t3_register_cpl_handler(CPL_ASYNC_NOTIF, cxio_hal_ev_handler);
1053 return 0;
1054 }
1055
1056 void __exit cxio_hal_exit(void)
1057 {
1058 struct cxio_rdev *rdev, *tmp;
1059
1060 t3_register_cpl_handler(CPL_ASYNC_NOTIF, NULL);
1061 list_for_each_entry_safe(rdev, tmp, &rdev_list, entry)
1062 cxio_rdev_close(rdev);
1063 cxio_hal_destroy_rhdl_resource();
1064 }
1065
1066 static void flush_completed_wrs(struct t3_wq *wq, struct t3_cq *cq)
1067 {
1068 struct t3_swsq *sqp;
1069 __u32 ptr = wq->sq_rptr;
1070 int count = Q_COUNT(wq->sq_rptr, wq->sq_wptr);
1071
1072 sqp = wq->sq + Q_PTR2IDX(ptr, wq->sq_size_log2);
1073 while (count--)
1074 if (!sqp->signaled) {
1075 ptr++;
1076 sqp = wq->sq + Q_PTR2IDX(ptr, wq->sq_size_log2);
1077 } else if (sqp->complete) {
1078
1079 /*
1080 * Insert this completed cqe into the swcq.
1081 */
1082 pr_debug("%s moving cqe into swcq sq idx %ld cq idx %ld\n",
1083 __func__, Q_PTR2IDX(ptr, wq->sq_size_log2),
1084 Q_PTR2IDX(cq->sw_wptr, cq->size_log2));
1085 sqp->cqe.header |= htonl(V_CQE_SWCQE(1));
1086 *(cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2))
1087 = sqp->cqe;
1088 cq->sw_wptr++;
1089 sqp->signaled = 0;
1090 break;
1091 } else
1092 break;
1093 }
1094
1095 static void create_read_req_cqe(struct t3_wq *wq, struct t3_cqe *hw_cqe,
1096 struct t3_cqe *read_cqe)
1097 {
1098 read_cqe->u.scqe.wrid_hi = wq->oldest_read->sq_wptr;
1099 read_cqe->len = wq->oldest_read->read_len;
1100 read_cqe->header = htonl(V_CQE_QPID(CQE_QPID(*hw_cqe)) |
1101 V_CQE_SWCQE(SW_CQE(*hw_cqe)) |
1102 V_CQE_OPCODE(T3_READ_REQ) |
1103 V_CQE_TYPE(1));
1104 }
1105
1106 /*
1107 * Return a ptr to the next read wr in the SWSQ or NULL.
1108 */
1109 static void advance_oldest_read(struct t3_wq *wq)
1110 {
1111
1112 u32 rptr = wq->oldest_read - wq->sq + 1;
1113 u32 wptr = Q_PTR2IDX(wq->sq_wptr, wq->sq_size_log2);
1114
1115 while (Q_PTR2IDX(rptr, wq->sq_size_log2) != wptr) {
1116 wq->oldest_read = wq->sq + Q_PTR2IDX(rptr, wq->sq_size_log2);
1117
1118 if (wq->oldest_read->opcode == T3_READ_REQ)
1119 return;
1120 rptr++;
1121 }
1122 wq->oldest_read = NULL;
1123 }
1124
1125 /*
1126 * cxio_poll_cq
1127 *
1128 * Caller must:
1129 * check the validity of the first CQE,
1130 * supply the wq assicated with the qpid.
1131 *
1132 * credit: cq credit to return to sge.
1133 * cqe_flushed: 1 iff the CQE is flushed.
1134 * cqe: copy of the polled CQE.
1135 *
1136 * return value:
1137 * 0 CQE returned,
1138 * -1 CQE skipped, try again.
1139 */
1140 int cxio_poll_cq(struct t3_wq *wq, struct t3_cq *cq, struct t3_cqe *cqe,
1141 u8 *cqe_flushed, u64 *cookie, u32 *credit)
1142 {
1143 int ret = 0;
1144 struct t3_cqe *hw_cqe, read_cqe;
1145
1146 *cqe_flushed = 0;
1147 *credit = 0;
1148 hw_cqe = cxio_next_cqe(cq);
1149
1150 pr_debug("%s CQE OOO %d qpid 0x%0x genbit %d type %d status 0x%0x opcode 0x%0x len 0x%0x wrid_hi_stag 0x%x wrid_low_msn 0x%x\n",
1151 __func__, CQE_OOO(*hw_cqe), CQE_QPID(*hw_cqe),
1152 CQE_GENBIT(*hw_cqe), CQE_TYPE(*hw_cqe), CQE_STATUS(*hw_cqe),
1153 CQE_OPCODE(*hw_cqe), CQE_LEN(*hw_cqe), CQE_WRID_HI(*hw_cqe),
1154 CQE_WRID_LOW(*hw_cqe));
1155
1156 /*
1157 * skip cqe's not affiliated with a QP.
1158 */
1159 if (wq == NULL) {
1160 ret = -1;
1161 goto skip_cqe;
1162 }
1163
1164 /*
1165 * Gotta tweak READ completions:
1166 * 1) the cqe doesn't contain the sq_wptr from the wr.
1167 * 2) opcode not reflected from the wr.
1168 * 3) read_len not reflected from the wr.
1169 * 4) cq_type is RQ_TYPE not SQ_TYPE.
1170 */
1171 if (RQ_TYPE(*hw_cqe) && (CQE_OPCODE(*hw_cqe) == T3_READ_RESP)) {
1172
1173 /*
1174 * If this is an unsolicited read response, then the read
1175 * was generated by the kernel driver as part of peer-2-peer
1176 * connection setup. So ignore the completion.
1177 */
1178 if (!wq->oldest_read) {
1179 if (CQE_STATUS(*hw_cqe))
1180 wq->error = 1;
1181 ret = -1;
1182 goto skip_cqe;
1183 }
1184
1185 /*
1186 * Don't write to the HWCQ, so create a new read req CQE
1187 * in local memory.
1188 */
1189 create_read_req_cqe(wq, hw_cqe, &read_cqe);
1190 hw_cqe = &read_cqe;
1191 advance_oldest_read(wq);
1192 }
1193
1194 /*
1195 * T3A: Discard TERMINATE CQEs.
1196 */
1197 if (CQE_OPCODE(*hw_cqe) == T3_TERMINATE) {
1198 ret = -1;
1199 wq->error = 1;
1200 goto skip_cqe;
1201 }
1202
1203 if (CQE_STATUS(*hw_cqe) || wq->error) {
1204 *cqe_flushed = wq->error;
1205 wq->error = 1;
1206
1207 /*
1208 * T3A inserts errors into the CQE. We cannot return
1209 * these as work completions.
1210 */
1211 /* incoming write failures */
1212 if ((CQE_OPCODE(*hw_cqe) == T3_RDMA_WRITE)
1213 && RQ_TYPE(*hw_cqe)) {
1214 ret = -1;
1215 goto skip_cqe;
1216 }
1217 /* incoming read request failures */
1218 if ((CQE_OPCODE(*hw_cqe) == T3_READ_RESP) && SQ_TYPE(*hw_cqe)) {
1219 ret = -1;
1220 goto skip_cqe;
1221 }
1222
1223 /* incoming SEND with no receive posted failures */
1224 if (CQE_SEND_OPCODE(*hw_cqe) && RQ_TYPE(*hw_cqe) &&
1225 Q_EMPTY(wq->rq_rptr, wq->rq_wptr)) {
1226 ret = -1;
1227 goto skip_cqe;
1228 }
1229 BUG_ON((*cqe_flushed == 0) && !SW_CQE(*hw_cqe));
1230 goto proc_cqe;
1231 }
1232
1233 /*
1234 * RECV completion.
1235 */
1236 if (RQ_TYPE(*hw_cqe)) {
1237
1238 /*
1239 * HW only validates 4 bits of MSN. So we must validate that
1240 * the MSN in the SEND is the next expected MSN. If its not,
1241 * then we complete this with TPT_ERR_MSN and mark the wq in
1242 * error.
1243 */
1244
1245 if (Q_EMPTY(wq->rq_rptr, wq->rq_wptr)) {
1246 wq->error = 1;
1247 ret = -1;
1248 goto skip_cqe;
1249 }
1250
1251 if (unlikely((CQE_WRID_MSN(*hw_cqe) != (wq->rq_rptr + 1)))) {
1252 wq->error = 1;
1253 hw_cqe->header |= htonl(V_CQE_STATUS(TPT_ERR_MSN));
1254 goto proc_cqe;
1255 }
1256 goto proc_cqe;
1257 }
1258
1259 /*
1260 * If we get here its a send completion.
1261 *
1262 * Handle out of order completion. These get stuffed
1263 * in the SW SQ. Then the SW SQ is walked to move any
1264 * now in-order completions into the SW CQ. This handles
1265 * 2 cases:
1266 * 1) reaping unsignaled WRs when the first subsequent
1267 * signaled WR is completed.
1268 * 2) out of order read completions.
1269 */
1270 if (!SW_CQE(*hw_cqe) && (CQE_WRID_SQ_WPTR(*hw_cqe) != wq->sq_rptr)) {
1271 struct t3_swsq *sqp;
1272
1273 pr_debug("%s out of order completion going in swsq at idx %ld\n",
1274 __func__,
1275 Q_PTR2IDX(CQE_WRID_SQ_WPTR(*hw_cqe),
1276 wq->sq_size_log2));
1277 sqp = wq->sq +
1278 Q_PTR2IDX(CQE_WRID_SQ_WPTR(*hw_cqe), wq->sq_size_log2);
1279 sqp->cqe = *hw_cqe;
1280 sqp->complete = 1;
1281 ret = -1;
1282 goto flush_wq;
1283 }
1284
1285 proc_cqe:
1286 *cqe = *hw_cqe;
1287
1288 /*
1289 * Reap the associated WR(s) that are freed up with this
1290 * completion.
1291 */
1292 if (SQ_TYPE(*hw_cqe)) {
1293 wq->sq_rptr = CQE_WRID_SQ_WPTR(*hw_cqe);
1294 pr_debug("%s completing sq idx %ld\n", __func__,
1295 Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2));
1296 *cookie = wq->sq[Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2)].wr_id;
1297 wq->sq_rptr++;
1298 } else {
1299 pr_debug("%s completing rq idx %ld\n", __func__,
1300 Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2));
1301 *cookie = wq->rq[Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2)].wr_id;
1302 if (wq->rq[Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2)].pbl_addr)
1303 cxio_hal_pblpool_free(wq->rdev,
1304 wq->rq[Q_PTR2IDX(wq->rq_rptr,
1305 wq->rq_size_log2)].pbl_addr, T3_STAG0_PBL_SIZE);
1306 BUG_ON(Q_EMPTY(wq->rq_rptr, wq->rq_wptr));
1307 wq->rq_rptr++;
1308 }
1309
1310 flush_wq:
1311 /*
1312 * Flush any completed cqes that are now in-order.
1313 */
1314 flush_completed_wrs(wq, cq);
1315
1316 skip_cqe:
1317 if (SW_CQE(*hw_cqe)) {
1318 pr_debug("%s cq %p cqid 0x%x skip sw cqe sw_rptr 0x%x\n",
1319 __func__, cq, cq->cqid, cq->sw_rptr);
1320 ++cq->sw_rptr;
1321 } else {
1322 pr_debug("%s cq %p cqid 0x%x skip hw cqe rptr 0x%x\n",
1323 __func__, cq, cq->cqid, cq->rptr);
1324 ++cq->rptr;
1325
1326 /*
1327 * T3A: compute credits.
1328 */
1329 if (((cq->rptr - cq->wptr) > (1 << (cq->size_log2 - 1)))
1330 || ((cq->rptr - cq->wptr) >= 128)) {
1331 *credit = cq->rptr - cq->wptr;
1332 cq->wptr = cq->rptr;
1333 }
1334 }
1335 return ret;
1336 }
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