drivers/infiniband/hw/cxgb4/iw_cxgb4.h

   1 /*
   2  * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *      - Redistributions in binary form must reproduce the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer in the documentation and/or other materials
  20  *        provided with the distribution.
  21  *
  22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  23  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  24  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  25  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  26  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  27  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  28  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  29  * SOFTWARE.
  30  */
  31 #ifndef __IW_CXGB4_H__
  32 #define __IW_CXGB4_H__
  33
  34 #include <linux/mutex.h>
  35 #include <linux/list.h>
  36 #include <linux/spinlock.h>
  37 #include <linux/idr.h>
  38 #include <linux/completion.h>
  39 #include <linux/netdevice.h>
  40 #include <linux/sched.h>
  41 #include <linux/pci.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/inet.h>
  44 #include <linux/wait.h>
  45 #include <linux/kref.h>
  46 #include <linux/timer.h>
  47 #include <linux/io.h>
  48
  49 #include <asm/byteorder.h>
  50
  51 #include <net/net_namespace.h>
  52
  53 #include <rdma/ib_verbs.h>
  54 #include <rdma/iw_cm.h>
  55 #include <rdma/rdma_netlink.h>
  56 #include <rdma/iw_portmap.h>
  57
  58 #include "cxgb4.h"
  59 #include "cxgb4_uld.h"
  60 #include "l2t.h"
  61 #include "user.h"
  62
  63 #define DRV_NAME "iw_cxgb4"
  64 #define MOD DRV_NAME ":"
  65
  66 extern int c4iw_debug;
  67 #define PDBG(fmt, args...) \
  68 do { \
  69         if (c4iw_debug) \
  70                 printk(MOD fmt, ## args); \
  71 } while (0)
  72
  73 #include "t4.h"
  74
  75 #define PBL_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->pbl.start)
  76 #define RQT_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->rq.start)
  77
  78 static inline void *cplhdr(struct sk_buff *skb)
  79 {
  80         return skb->data;
  81 }
  82
  83 #define C4IW_ID_TABLE_F_RANDOM 1       /* Pseudo-randomize the id's returned */
  84 #define C4IW_ID_TABLE_F_EMPTY  2       /* Table is initially empty */
  85
  86 struct c4iw_id_table {
  87         u32 flags;
  88         u32 start;              /* logical minimal id */
  89         u32 last;               /* hint for find */
  90         u32 max;
  91         spinlock_t lock;
  92         unsigned long *table;
  93 };
  94
  95 struct c4iw_resource {
  96         struct c4iw_id_table tpt_table;
  97         struct c4iw_id_table qid_table;
  98         struct c4iw_id_table pdid_table;
  99 };
 100
 101 struct c4iw_qid_list {
 102         struct list_head entry;
 103         u32 qid;
 104 };
 105
 106 struct c4iw_dev_ucontext {
 107         struct list_head qpids;
 108         struct list_head cqids;
 109         struct mutex lock;
 110 };
 111
 112 enum c4iw_rdev_flags {
 113         T4_FATAL_ERROR = (1<<0),
 114         T4_STATUS_PAGE_DISABLED = (1<<1),
 115 };
 116
 117 struct c4iw_stat {
 118         u64 total;
 119         u64 cur;
 120         u64 max;
 121         u64 fail;
 122 };
 123
 124 struct c4iw_stats {
 125         struct mutex lock;
 126         struct c4iw_stat qid;
 127         struct c4iw_stat pd;
 128         struct c4iw_stat stag;
 129         struct c4iw_stat pbl;
 130         struct c4iw_stat rqt;
 131         struct c4iw_stat ocqp;
 132         u64  db_full;
 133         u64  db_empty;
 134         u64  db_drop;
 135         u64  db_state_transitions;
 136         u64  db_fc_interruptions;
 137         u64  tcam_full;
 138         u64  act_ofld_conn_fails;
 139         u64  pas_ofld_conn_fails;
 140         u64  neg_adv;
 141 };
 142
 143 struct c4iw_hw_queue {
 144         int t4_eq_status_entries;
 145         int t4_max_eq_size;
 146         int t4_max_iq_size;
 147         int t4_max_rq_size;
 148         int t4_max_sq_size;
 149         int t4_max_qp_depth;
 150         int t4_max_cq_depth;
 151         int t4_stat_len;
 152 };
 153
 154 struct wr_log_entry {
 155         struct timespec post_host_ts;
 156         struct timespec poll_host_ts;
 157         u64 post_sge_ts;
 158         u64 cqe_sge_ts;
 159         u64 poll_sge_ts;
 160         u16 qid;
 161         u16 wr_id;
 162         u8 opcode;
 163         u8 valid;
 164 };
 165
 166 struct c4iw_rdev {
 167         struct c4iw_resource resource;
 168         u32 qpmask;
 169         u32 cqmask;
 170         struct c4iw_dev_ucontext uctx;
 171         struct gen_pool *pbl_pool;
 172         struct gen_pool *rqt_pool;
 173         struct gen_pool *ocqp_pool;
 174         u32 flags;
 175         struct cxgb4_lld_info lldi;
 176         unsigned long bar2_pa;
 177         void __iomem *bar2_kva;
 178         unsigned long oc_mw_pa;
 179         void __iomem *oc_mw_kva;
 180         struct c4iw_stats stats;
 181         struct c4iw_hw_queue hw_queue;
 182         struct t4_dev_status_page *status_page;
 183         atomic_t wr_log_idx;
 184         struct wr_log_entry *wr_log;
 185         int wr_log_size;
 186 };
 187
 188 static inline int c4iw_fatal_error(struct c4iw_rdev *rdev)
 189 {
 190         return rdev->flags & T4_FATAL_ERROR;
 191 }
 192
 193 static inline int c4iw_num_stags(struct c4iw_rdev *rdev)
 194 {
 195         return (int)(rdev->lldi.vr->stag.size >> 5);
 196 }
 197
 198 #define C4IW_WR_TO (60*HZ)
 199
 200 struct c4iw_wr_wait {
 201         struct completion completion;
 202         int ret;
 203 };
 204
 205 static inline void c4iw_init_wr_wait(struct c4iw_wr_wait *wr_waitp)
 206 {
 207         wr_waitp->ret = 0;
 208         init_completion(&wr_waitp->completion);
 209 }
 210
 211 static inline void c4iw_wake_up(struct c4iw_wr_wait *wr_waitp, int ret)
 212 {
 213         wr_waitp->ret = ret;
 214         complete(&wr_waitp->completion);
 215 }
 216
 217 static inline int c4iw_wait_for_reply(struct c4iw_rdev *rdev,
 218                                  struct c4iw_wr_wait *wr_waitp,
 219                                  u32 hwtid, u32 qpid,
 220                                  const char *func)
 221 {
 222         int ret;
 223
 224         if (c4iw_fatal_error(rdev)) {
 225                 wr_waitp->ret = -EIO;
 226                 goto out;
 227         }
 228
 229         ret = wait_for_completion_timeout(&wr_waitp->completion, C4IW_WR_TO);
 230         if (!ret) {
 231                 PDBG("%s - Device %s not responding (disabling device) - tid %u qpid %u\n",
 232                      func, pci_name(rdev->lldi.pdev), hwtid, qpid);
 233                 rdev->flags |= T4_FATAL_ERROR;
 234                 wr_waitp->ret = -EIO;
 235         }
 236 out:
 237         if (wr_waitp->ret)
 238                 PDBG("%s: FW reply %d tid %u qpid %u\n",
 239                      pci_name(rdev->lldi.pdev), wr_waitp->ret, hwtid, qpid);
 240         return wr_waitp->ret;
 241 }
 242
 243 enum db_state {
 244         NORMAL = 0,
 245         FLOW_CONTROL = 1,
 246         RECOVERY = 2,
 247         STOPPED = 3
 248 };
 249
 250 struct c4iw_dev {
 251         struct ib_device ibdev;
 252         struct c4iw_rdev rdev;
 253         u32 device_cap_flags;
 254         struct idr cqidr;
 255         struct idr qpidr;
 256         struct idr mmidr;
 257         spinlock_t lock;
 258         struct mutex db_mutex;
 259         struct dentry *debugfs_root;
 260         enum db_state db_state;
 261         struct idr hwtid_idr;
 262         struct idr atid_idr;
 263         struct idr stid_idr;
 264         struct list_head db_fc_list;
 265         u32 avail_ird;
 266 };
 267
 268 static inline struct c4iw_dev *to_c4iw_dev(struct ib_device *ibdev)
 269 {
 270         return container_of(ibdev, struct c4iw_dev, ibdev);
 271 }
 272
 273 static inline struct c4iw_dev *rdev_to_c4iw_dev(struct c4iw_rdev *rdev)
 274 {
 275         return container_of(rdev, struct c4iw_dev, rdev);
 276 }
 277
 278 static inline struct c4iw_cq *get_chp(struct c4iw_dev *rhp, u32 cqid)
 279 {
 280         return idr_find(&rhp->cqidr, cqid);
 281 }
 282
 283 static inline struct c4iw_qp *get_qhp(struct c4iw_dev *rhp, u32 qpid)
 284 {
 285         return idr_find(&rhp->qpidr, qpid);
 286 }
 287
 288 static inline struct c4iw_mr *get_mhp(struct c4iw_dev *rhp, u32 mmid)
 289 {
 290         return idr_find(&rhp->mmidr, mmid);
 291 }
 292
 293 static inline int _insert_handle(struct c4iw_dev *rhp, struct idr *idr,
 294                                  void *handle, u32 id, int lock)
 295 {
 296         int ret;
 297
 298         if (lock) {
 299                 idr_preload(GFP_KERNEL);
 300                 spin_lock_irq(&rhp->lock);
 301         }
 302
 303         ret = idr_alloc(idr, handle, id, id + 1, GFP_ATOMIC);
 304
 305         if (lock) {
 306                 spin_unlock_irq(&rhp->lock);
 307                 idr_preload_end();
 308         }
 309
 310         BUG_ON(ret == -ENOSPC);
 311         return ret < 0 ? ret : 0;
 312 }
 313
 314 static inline int insert_handle(struct c4iw_dev *rhp, struct idr *idr,
 315                                 void *handle, u32 id)
 316 {
 317         return _insert_handle(rhp, idr, handle, id, 1);
 318 }
 319
 320 static inline int insert_handle_nolock(struct c4iw_dev *rhp, struct idr *idr,
 321                                        void *handle, u32 id)
 322 {
 323         return _insert_handle(rhp, idr, handle, id, 0);
 324 }
 325
 326 static inline void _remove_handle(struct c4iw_dev *rhp, struct idr *idr,
 327                                    u32 id, int lock)
 328 {
 329         if (lock)
 330                 spin_lock_irq(&rhp->lock);
 331         idr_remove(idr, id);
 332         if (lock)
 333                 spin_unlock_irq(&rhp->lock);
 334 }
 335
 336 static inline void remove_handle(struct c4iw_dev *rhp, struct idr *idr, u32 id)
 337 {
 338         _remove_handle(rhp, idr, id, 1);
 339 }
 340
 341 static inline void remove_handle_nolock(struct c4iw_dev *rhp,
 342                                          struct idr *idr, u32 id)
 343 {
 344         _remove_handle(rhp, idr, id, 0);
 345 }
 346
 347 extern uint c4iw_max_read_depth;
 348
 349 static inline int cur_max_read_depth(struct c4iw_dev *dev)
 350 {
 351         return min(dev->rdev.lldi.max_ordird_qp, c4iw_max_read_depth);
 352 }
 353
 354 struct c4iw_pd {
 355         struct ib_pd ibpd;
 356         u32 pdid;
 357         struct c4iw_dev *rhp;
 358 };
 359
 360 static inline struct c4iw_pd *to_c4iw_pd(struct ib_pd *ibpd)
 361 {
 362         return container_of(ibpd, struct c4iw_pd, ibpd);
 363 }
 364
 365 struct tpt_attributes {
 366         u64 len;
 367         u64 va_fbo;
 368         enum fw_ri_mem_perms perms;
 369         u32 stag;
 370         u32 pdid;
 371         u32 qpid;
 372         u32 pbl_addr;
 373         u32 pbl_size;
 374         u32 state:1;
 375         u32 type:2;
 376         u32 rsvd:1;
 377         u32 remote_invaliate_disable:1;
 378         u32 zbva:1;
 379         u32 mw_bind_enable:1;
 380         u32 page_size:5;
 381 };
 382
 383 struct c4iw_mr {
 384         struct ib_mr ibmr;
 385         struct ib_umem *umem;
 386         struct c4iw_dev *rhp;
 387         u64 kva;
 388         struct tpt_attributes attr;
 389 };
 390
 391 static inline struct c4iw_mr *to_c4iw_mr(struct ib_mr *ibmr)
 392 {
 393         return container_of(ibmr, struct c4iw_mr, ibmr);
 394 }
 395
 396 struct c4iw_mw {
 397         struct ib_mw ibmw;
 398         struct c4iw_dev *rhp;
 399         u64 kva;
 400         struct tpt_attributes attr;
 401 };
 402
 403 static inline struct c4iw_mw *to_c4iw_mw(struct ib_mw *ibmw)
 404 {
 405         return container_of(ibmw, struct c4iw_mw, ibmw);
 406 }
 407
 408 struct c4iw_fr_page_list {
 409         struct ib_fast_reg_page_list ibpl;
 410         DEFINE_DMA_UNMAP_ADDR(mapping);
 411         dma_addr_t dma_addr;
 412         struct c4iw_dev *dev;
 413         int pll_len;
 414 };
 415
 416 static inline struct c4iw_fr_page_list *to_c4iw_fr_page_list(
 417                                         struct ib_fast_reg_page_list *ibpl)
 418 {
 419         return container_of(ibpl, struct c4iw_fr_page_list, ibpl);
 420 }
 421
 422 struct c4iw_cq {
 423         struct ib_cq ibcq;
 424         struct c4iw_dev *rhp;
 425         struct t4_cq cq;
 426         spinlock_t lock;
 427         spinlock_t comp_handler_lock;
 428         atomic_t refcnt;
 429         wait_queue_head_t wait;
 430 };
 431
 432 static inline struct c4iw_cq *to_c4iw_cq(struct ib_cq *ibcq)
 433 {
 434         return container_of(ibcq, struct c4iw_cq, ibcq);
 435 }
 436
 437 struct c4iw_mpa_attributes {
 438         u8 initiator;
 439         u8 recv_marker_enabled;
 440         u8 xmit_marker_enabled;
 441         u8 crc_enabled;
 442         u8 enhanced_rdma_conn;
 443         u8 version;
 444         u8 p2p_type;
 445 };
 446
 447 struct c4iw_qp_attributes {
 448         u32 scq;
 449         u32 rcq;
 450         u32 sq_num_entries;
 451         u32 rq_num_entries;
 452         u32 sq_max_sges;
 453         u32 sq_max_sges_rdma_write;
 454         u32 rq_max_sges;
 455         u32 state;
 456         u8 enable_rdma_read;
 457         u8 enable_rdma_write;
 458         u8 enable_bind;
 459         u8 enable_mmid0_fastreg;
 460         u32 max_ord;
 461         u32 max_ird;
 462         u32 pd;
 463         u32 next_state;
 464         char terminate_buffer[52];
 465         u32 terminate_msg_len;
 466         u8 is_terminate_local;
 467         struct c4iw_mpa_attributes mpa_attr;
 468         struct c4iw_ep *llp_stream_handle;
 469         u8 layer_etype;
 470         u8 ecode;
 471         u16 sq_db_inc;
 472         u16 rq_db_inc;
 473         u8 send_term;
 474 };
 475
 476 struct c4iw_qp {
 477         struct ib_qp ibqp;
 478         struct list_head db_fc_entry;
 479         struct c4iw_dev *rhp;
 480         struct c4iw_ep *ep;
 481         struct c4iw_qp_attributes attr;
 482         struct t4_wq wq;
 483         spinlock_t lock;
 484         struct mutex mutex;
 485         atomic_t refcnt;
 486         wait_queue_head_t wait;
 487         struct timer_list timer;
 488         int sq_sig_all;
 489 };
 490
 491 static inline struct c4iw_qp *to_c4iw_qp(struct ib_qp *ibqp)
 492 {
 493         return container_of(ibqp, struct c4iw_qp, ibqp);
 494 }
 495
 496 struct c4iw_ucontext {
 497         struct ib_ucontext ibucontext;
 498         struct c4iw_dev_ucontext uctx;
 499         u32 key;
 500         spinlock_t mmap_lock;
 501         struct list_head mmaps;
 502 };
 503
 504 static inline struct c4iw_ucontext *to_c4iw_ucontext(struct ib_ucontext *c)
 505 {
 506         return container_of(c, struct c4iw_ucontext, ibucontext);
 507 }
 508
 509 struct c4iw_mm_entry {
 510         struct list_head entry;
 511         u64 addr;
 512         u32 key;
 513         unsigned len;
 514 };
 515
 516 static inline struct c4iw_mm_entry *remove_mmap(struct c4iw_ucontext *ucontext,
 517                                                 u32 key, unsigned len)
 518 {
 519         struct list_head *pos, *nxt;
 520         struct c4iw_mm_entry *mm;
 521
 522         spin_lock(&ucontext->mmap_lock);
 523         list_for_each_safe(pos, nxt, &ucontext->mmaps) {
 524
 525                 mm = list_entry(pos, struct c4iw_mm_entry, entry);
 526                 if (mm->key == key && mm->len == len) {
 527                         list_del_init(&mm->entry);
 528                         spin_unlock(&ucontext->mmap_lock);
 529                         PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__,
 530                              key, (unsigned long long) mm->addr, mm->len);
 531                         return mm;
 532                 }
 533         }
 534         spin_unlock(&ucontext->mmap_lock);
 535         return NULL;
 536 }
 537
 538 static inline void insert_mmap(struct c4iw_ucontext *ucontext,
 539                                struct c4iw_mm_entry *mm)
 540 {
 541         spin_lock(&ucontext->mmap_lock);
 542         PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__,
 543              mm->key, (unsigned long long) mm->addr, mm->len);
 544         list_add_tail(&mm->entry, &ucontext->mmaps);
 545         spin_unlock(&ucontext->mmap_lock);
 546 }
 547
 548 enum c4iw_qp_attr_mask {
 549         C4IW_QP_ATTR_NEXT_STATE = 1 << 0,
 550         C4IW_QP_ATTR_SQ_DB = 1<<1,
 551         C4IW_QP_ATTR_RQ_DB = 1<<2,
 552         C4IW_QP_ATTR_ENABLE_RDMA_READ = 1 << 7,
 553         C4IW_QP_ATTR_ENABLE_RDMA_WRITE = 1 << 8,
 554         C4IW_QP_ATTR_ENABLE_RDMA_BIND = 1 << 9,
 555         C4IW_QP_ATTR_MAX_ORD = 1 << 11,
 556         C4IW_QP_ATTR_MAX_IRD = 1 << 12,
 557         C4IW_QP_ATTR_LLP_STREAM_HANDLE = 1 << 22,
 558         C4IW_QP_ATTR_STREAM_MSG_BUFFER = 1 << 23,
 559         C4IW_QP_ATTR_MPA_ATTR = 1 << 24,
 560         C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE = 1 << 25,
 561         C4IW_QP_ATTR_VALID_MODIFY = (C4IW_QP_ATTR_ENABLE_RDMA_READ |
 562                                      C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
 563                                      C4IW_QP_ATTR_MAX_ORD |
 564                                      C4IW_QP_ATTR_MAX_IRD |
 565                                      C4IW_QP_ATTR_LLP_STREAM_HANDLE |
 566                                      C4IW_QP_ATTR_STREAM_MSG_BUFFER |
 567                                      C4IW_QP_ATTR_MPA_ATTR |
 568                                      C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE)
 569 };
 570
 571 int c4iw_modify_qp(struct c4iw_dev *rhp,
 572                                 struct c4iw_qp *qhp,
 573                                 enum c4iw_qp_attr_mask mask,
 574                                 struct c4iw_qp_attributes *attrs,
 575                                 int internal);
 576
 577 enum c4iw_qp_state {
 578         C4IW_QP_STATE_IDLE,
 579         C4IW_QP_STATE_RTS,
 580         C4IW_QP_STATE_ERROR,
 581         C4IW_QP_STATE_TERMINATE,
 582         C4IW_QP_STATE_CLOSING,
 583         C4IW_QP_STATE_TOT
 584 };
 585
 586 static inline int c4iw_convert_state(enum ib_qp_state ib_state)
 587 {
 588         switch (ib_state) {
 589         case IB_QPS_RESET:
 590         case IB_QPS_INIT:
 591                 return C4IW_QP_STATE_IDLE;
 592         case IB_QPS_RTS:
 593                 return C4IW_QP_STATE_RTS;
 594         case IB_QPS_SQD:
 595                 return C4IW_QP_STATE_CLOSING;
 596         case IB_QPS_SQE:
 597                 return C4IW_QP_STATE_TERMINATE;
 598         case IB_QPS_ERR:
 599                 return C4IW_QP_STATE_ERROR;
 600         default:
 601                 return -1;
 602         }
 603 }
 604
 605 static inline int to_ib_qp_state(int c4iw_qp_state)
 606 {
 607         switch (c4iw_qp_state) {
 608         case C4IW_QP_STATE_IDLE:
 609                 return IB_QPS_INIT;
 610         case C4IW_QP_STATE_RTS:
 611                 return IB_QPS_RTS;
 612         case C4IW_QP_STATE_CLOSING:
 613                 return IB_QPS_SQD;
 614         case C4IW_QP_STATE_TERMINATE:
 615                 return IB_QPS_SQE;
 616         case C4IW_QP_STATE_ERROR:
 617                 return IB_QPS_ERR;
 618         }
 619         return IB_QPS_ERR;
 620 }
 621
 622 static inline u32 c4iw_ib_to_tpt_access(int a)
 623 {
 624         return (a & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
 625                (a & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0) |
 626                (a & IB_ACCESS_LOCAL_WRITE ? FW_RI_MEM_ACCESS_LOCAL_WRITE : 0) |
 627                FW_RI_MEM_ACCESS_LOCAL_READ;
 628 }
 629
 630 static inline u32 c4iw_ib_to_tpt_bind_access(int acc)
 631 {
 632         return (acc & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
 633                (acc & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0);
 634 }
 635
 636 enum c4iw_mmid_state {
 637         C4IW_STAG_STATE_VALID,
 638         C4IW_STAG_STATE_INVALID
 639 };
 640
 641 #define C4IW_NODE_DESC "cxgb4 Chelsio Communications"
 642
 643 #define MPA_KEY_REQ "MPA ID Req Frame"
 644 #define MPA_KEY_REP "MPA ID Rep Frame"
 645
 646 #define MPA_MAX_PRIVATE_DATA    256
 647 #define MPA_ENHANCED_RDMA_CONN  0x10
 648 #define MPA_REJECT              0x20
 649 #define MPA_CRC                 0x40
 650 #define MPA_MARKERS             0x80
 651 #define MPA_FLAGS_MASK          0xE0
 652
 653 #define MPA_V2_PEER2PEER_MODEL          0x8000
 654 #define MPA_V2_ZERO_LEN_FPDU_RTR        0x4000
 655 #define MPA_V2_RDMA_WRITE_RTR           0x8000
 656 #define MPA_V2_RDMA_READ_RTR            0x4000
 657 #define MPA_V2_IRD_ORD_MASK             0x3FFF
 658
 659 #define c4iw_put_ep(ep) { \
 660         PDBG("put_ep (via %s:%u) ep %p refcnt %d\n", __func__, __LINE__,  \
 661              ep, atomic_read(&((ep)->kref.refcount))); \
 662         WARN_ON(atomic_read(&((ep)->kref.refcount)) < 1); \
 663         kref_put(&((ep)->kref), _c4iw_free_ep); \
 664 }
 665
 666 #define c4iw_get_ep(ep) { \
 667         PDBG("get_ep (via %s:%u) ep %p, refcnt %d\n", __func__, __LINE__, \
 668              ep, atomic_read(&((ep)->kref.refcount))); \
 669         kref_get(&((ep)->kref));  \
 670 }
 671 void _c4iw_free_ep(struct kref *kref);
 672
 673 struct mpa_message {
 674         u8 key[16];
 675         u8 flags;
 676         u8 revision;
 677         __be16 private_data_size;
 678         u8 private_data[0];
 679 };
 680
 681 struct mpa_v2_conn_params {
 682         __be16 ird;
 683         __be16 ord;
 684 };
 685
 686 struct terminate_message {
 687         u8 layer_etype;
 688         u8 ecode;
 689         __be16 hdrct_rsvd;
 690         u8 len_hdrs[0];
 691 };
 692
 693 #define TERM_MAX_LENGTH (sizeof(struct terminate_message) + 2 + 18 + 28)
 694
 695 enum c4iw_layers_types {
 696         LAYER_RDMAP             = 0x00,
 697         LAYER_DDP               = 0x10,
 698         LAYER_MPA               = 0x20,
 699         RDMAP_LOCAL_CATA        = 0x00,
 700         RDMAP_REMOTE_PROT       = 0x01,
 701         RDMAP_REMOTE_OP         = 0x02,
 702         DDP_LOCAL_CATA          = 0x00,
 703         DDP_TAGGED_ERR          = 0x01,
 704         DDP_UNTAGGED_ERR        = 0x02,
 705         DDP_LLP                 = 0x03
 706 };
 707
 708 enum c4iw_rdma_ecodes {
 709         RDMAP_INV_STAG          = 0x00,
 710         RDMAP_BASE_BOUNDS       = 0x01,
 711         RDMAP_ACC_VIOL          = 0x02,
 712         RDMAP_STAG_NOT_ASSOC    = 0x03,
 713         RDMAP_TO_WRAP           = 0x04,
 714         RDMAP_INV_VERS          = 0x05,
 715         RDMAP_INV_OPCODE        = 0x06,
 716         RDMAP_STREAM_CATA       = 0x07,
 717         RDMAP_GLOBAL_CATA       = 0x08,
 718         RDMAP_CANT_INV_STAG     = 0x09,
 719         RDMAP_UNSPECIFIED       = 0xff
 720 };
 721
 722 enum c4iw_ddp_ecodes {
 723         DDPT_INV_STAG           = 0x00,
 724         DDPT_BASE_BOUNDS        = 0x01,
 725         DDPT_STAG_NOT_ASSOC     = 0x02,
 726         DDPT_TO_WRAP            = 0x03,
 727         DDPT_INV_VERS           = 0x04,
 728         DDPU_INV_QN             = 0x01,
 729         DDPU_INV_MSN_NOBUF      = 0x02,
 730         DDPU_INV_MSN_RANGE      = 0x03,
 731         DDPU_INV_MO             = 0x04,
 732         DDPU_MSG_TOOBIG         = 0x05,
 733         DDPU_INV_VERS           = 0x06
 734 };
 735
 736 enum c4iw_mpa_ecodes {
 737         MPA_CRC_ERR             = 0x02,
 738         MPA_MARKER_ERR          = 0x03,
 739         MPA_LOCAL_CATA          = 0x05,
 740         MPA_INSUFF_IRD          = 0x06,
 741         MPA_NOMATCH_RTR         = 0x07,
 742 };
 743
 744 enum c4iw_ep_state {
 745         IDLE = 0,
 746         LISTEN,
 747         CONNECTING,
 748         MPA_REQ_WAIT,
 749         MPA_REQ_SENT,
 750         MPA_REQ_RCVD,
 751         MPA_REP_SENT,
 752         FPDU_MODE,
 753         ABORTING,
 754         CLOSING,
 755         MORIBUND,
 756         DEAD,
 757 };
 758
 759 enum c4iw_ep_flags {
 760         PEER_ABORT_IN_PROGRESS  = 0,
 761         ABORT_REQ_IN_PROGRESS   = 1,
 762         RELEASE_RESOURCES       = 2,
 763         CLOSE_SENT              = 3,
 764         TIMEOUT                 = 4,
 765         QP_REFERENCED           = 5,
 766         RELEASE_MAPINFO         = 6,
 767 };
 768
 769 enum c4iw_ep_history {
 770         ACT_OPEN_REQ            = 0,
 771         ACT_OFLD_CONN           = 1,
 772         ACT_OPEN_RPL            = 2,
 773         ACT_ESTAB               = 3,
 774         PASS_ACCEPT_REQ         = 4,
 775         PASS_ESTAB              = 5,
 776         ABORT_UPCALL            = 6,
 777         ESTAB_UPCALL            = 7,
 778         CLOSE_UPCALL            = 8,
 779         ULP_ACCEPT              = 9,
 780         ULP_REJECT              = 10,
 781         TIMEDOUT                = 11,
 782         PEER_ABORT              = 12,
 783         PEER_CLOSE              = 13,
 784         CONNREQ_UPCALL          = 14,
 785         ABORT_CONN              = 15,
 786         DISCONN_UPCALL          = 16,
 787         EP_DISC_CLOSE           = 17,
 788         EP_DISC_ABORT           = 18,
 789         CONN_RPL_UPCALL         = 19,
 790         ACT_RETRY_NOMEM         = 20,
 791         ACT_RETRY_INUSE         = 21
 792 };
 793
 794 struct c4iw_ep_common {
 795         struct iw_cm_id *cm_id;
 796         struct c4iw_qp *qp;
 797         struct c4iw_dev *dev;
 798         enum c4iw_ep_state state;
 799         struct kref kref;
 800         struct mutex mutex;
 801         struct sockaddr_storage local_addr;
 802         struct sockaddr_storage remote_addr;
 803         struct sockaddr_storage mapped_local_addr;
 804         struct sockaddr_storage mapped_remote_addr;
 805         struct c4iw_wr_wait wr_wait;
 806         unsigned long flags;
 807         unsigned long history;
 808 };
 809
 810 struct c4iw_listen_ep {
 811         struct c4iw_ep_common com;
 812         unsigned int stid;
 813         int backlog;
 814 };
 815
 816 struct c4iw_ep_stats {
 817         unsigned connect_neg_adv;
 818         unsigned abort_neg_adv;
 819 };
 820
 821 struct c4iw_ep {
 822         struct c4iw_ep_common com;
 823         struct c4iw_ep *parent_ep;
 824         struct timer_list timer;
 825         struct list_head entry;
 826         unsigned int atid;
 827         u32 hwtid;
 828         u32 snd_seq;
 829         u32 rcv_seq;
 830         struct l2t_entry *l2t;
 831         struct dst_entry *dst;
 832         struct sk_buff *mpa_skb;
 833         struct c4iw_mpa_attributes mpa_attr;
 834         u8 mpa_pkt[sizeof(struct mpa_message) + MPA_MAX_PRIVATE_DATA];
 835         unsigned int mpa_pkt_len;
 836         u32 ird;
 837         u32 ord;
 838         u32 smac_idx;
 839         u32 tx_chan;
 840         u32 mtu;
 841         u16 mss;
 842         u16 emss;
 843         u16 plen;
 844         u16 rss_qid;
 845         u16 txq_idx;
 846         u16 ctrlq_idx;
 847         u8 tos;
 848         u8 retry_with_mpa_v1;
 849         u8 tried_with_mpa_v1;
 850         unsigned int retry_count;
 851         int snd_win;
 852         int rcv_win;
 853         struct c4iw_ep_stats stats;
 854 };
 855
 856 static inline void print_addr(struct c4iw_ep_common *epc, const char *func,
 857                               const char *msg)
 858 {
 859
 860 #define SINA(a) (&(((struct sockaddr_in *)(a))->sin_addr.s_addr))
 861 #define SINP(a) ntohs(((struct sockaddr_in *)(a))->sin_port)
 862 #define SIN6A(a) (&(((struct sockaddr_in6 *)(a))->sin6_addr))
 863 #define SIN6P(a) ntohs(((struct sockaddr_in6 *)(a))->sin6_port)
 864
 865         if (c4iw_debug) {
 866                 switch (epc->local_addr.ss_family) {
 867                 case AF_INET:
 868                         PDBG("%s %s %pI4:%u/%u <-> %pI4:%u/%u\n",
 869                              func, msg, SINA(&epc->local_addr),
 870                              SINP(&epc->local_addr),
 871                              SINP(&epc->mapped_local_addr),
 872                              SINA(&epc->remote_addr),
 873                              SINP(&epc->remote_addr),
 874                              SINP(&epc->mapped_remote_addr));
 875                         break;
 876                 case AF_INET6:
 877                         PDBG("%s %s %pI6:%u/%u <-> %pI6:%u/%u\n",
 878                              func, msg, SIN6A(&epc->local_addr),
 879                              SIN6P(&epc->local_addr),
 880                              SIN6P(&epc->mapped_local_addr),
 881                              SIN6A(&epc->remote_addr),
 882                              SIN6P(&epc->remote_addr),
 883                              SIN6P(&epc->mapped_remote_addr));
 884                         break;
 885                 default:
 886                         break;
 887                 }
 888         }
 889 #undef SINA
 890 #undef SINP
 891 #undef SIN6A
 892 #undef SIN6P
 893 }
 894
 895 static inline struct c4iw_ep *to_ep(struct iw_cm_id *cm_id)
 896 {
 897         return cm_id->provider_data;
 898 }
 899
 900 static inline struct c4iw_listen_ep *to_listen_ep(struct iw_cm_id *cm_id)
 901 {
 902         return cm_id->provider_data;
 903 }
 904
 905 static inline int compute_wscale(int win)
 906 {
 907         int wscale = 0;
 908
 909         while (wscale < 14 && (65535<<wscale) < win)
 910                 wscale++;
 911         return wscale;
 912 }
 913
 914 static inline int ocqp_supported(const struct cxgb4_lld_info *infop)
 915 {
 916 #if defined(__i386__) || defined(__x86_64__) || defined(CONFIG_PPC64)
 917         return infop->vr->ocq.size > 0;
 918 #else
 919         return 0;
 920 #endif
 921 }
 922
 923 u32 c4iw_id_alloc(struct c4iw_id_table *alloc);
 924 void c4iw_id_free(struct c4iw_id_table *alloc, u32 obj);
 925 int c4iw_id_table_alloc(struct c4iw_id_table *alloc, u32 start, u32 num,
 926                         u32 reserved, u32 flags);
 927 void c4iw_id_table_free(struct c4iw_id_table *alloc);
 928
 929 typedef int (*c4iw_handler_func)(struct c4iw_dev *dev, struct sk_buff *skb);
 930
 931 int c4iw_ep_redirect(void *ctx, struct dst_entry *old, struct dst_entry *new,
 932                      struct l2t_entry *l2t);
 933 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qpid,
 934                    struct c4iw_dev_ucontext *uctx);
 935 u32 c4iw_get_resource(struct c4iw_id_table *id_table);
 936 void c4iw_put_resource(struct c4iw_id_table *id_table, u32 entry);
 937 int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_tpt, u32 nr_pdid);
 938 int c4iw_init_ctrl_qp(struct c4iw_rdev *rdev);
 939 int c4iw_pblpool_create(struct c4iw_rdev *rdev);
 940 int c4iw_rqtpool_create(struct c4iw_rdev *rdev);
 941 int c4iw_ocqp_pool_create(struct c4iw_rdev *rdev);
 942 void c4iw_pblpool_destroy(struct c4iw_rdev *rdev);
 943 void c4iw_rqtpool_destroy(struct c4iw_rdev *rdev);
 944 void c4iw_ocqp_pool_destroy(struct c4iw_rdev *rdev);
 945 void c4iw_destroy_resource(struct c4iw_resource *rscp);
 946 int c4iw_destroy_ctrl_qp(struct c4iw_rdev *rdev);
 947 int c4iw_register_device(struct c4iw_dev *dev);
 948 void c4iw_unregister_device(struct c4iw_dev *dev);
 949 int __init c4iw_cm_init(void);
 950 void c4iw_cm_term(void);
 951 void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
 952                                struct c4iw_dev_ucontext *uctx);
 953 void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
 954                             struct c4iw_dev_ucontext *uctx);
 955 int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
 956 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
 957                       struct ib_send_wr **bad_wr);
 958 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
 959                       struct ib_recv_wr **bad_wr);
 960 int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw,
 961                  struct ib_mw_bind *mw_bind);
 962 int c4iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
 963 int c4iw_create_listen(struct iw_cm_id *cm_id, int backlog);
 964 int c4iw_destroy_listen(struct iw_cm_id *cm_id);
 965 int c4iw_accept_cr(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
 966 int c4iw_reject_cr(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len);
 967 void c4iw_qp_add_ref(struct ib_qp *qp);
 968 void c4iw_qp_rem_ref(struct ib_qp *qp);
 969 void c4iw_free_fastreg_pbl(struct ib_fast_reg_page_list *page_list);
 970 struct ib_fast_reg_page_list *c4iw_alloc_fastreg_pbl(
 971                                         struct ib_device *device,
 972                                         int page_list_len);
 973 struct ib_mr *c4iw_alloc_mr(struct ib_pd *pd,
 974                             enum ib_mr_type mr_type,
 975                             u32 max_num_sg);
 976 int c4iw_dealloc_mw(struct ib_mw *mw);
 977 struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd, enum ib_mw_type type);
 978 struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start,
 979                                            u64 length, u64 virt, int acc,
 980                                            struct ib_udata *udata);
 981 struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc);
 982 struct ib_mr *c4iw_register_phys_mem(struct ib_pd *pd,
 983                                         struct ib_phys_buf *buffer_list,
 984                                         int num_phys_buf,
 985                                         int acc,
 986                                         u64 *iova_start);
 987 int c4iw_reregister_phys_mem(struct ib_mr *mr,
 988                                      int mr_rereg_mask,
 989                                      struct ib_pd *pd,
 990                                      struct ib_phys_buf *buffer_list,
 991                                      int num_phys_buf,
 992                                      int acc, u64 *iova_start);
 993 int c4iw_dereg_mr(struct ib_mr *ib_mr);
 994 int c4iw_destroy_cq(struct ib_cq *ib_cq);
 995 struct ib_cq *c4iw_create_cq(struct ib_device *ibdev,
 996                              const struct ib_cq_init_attr *attr,
 997                              struct ib_ucontext *ib_context,
 998                              struct ib_udata *udata);
 999 int c4iw_resize_cq(struct ib_cq *cq, int cqe, struct ib_udata *udata);
1000 int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
1001 int c4iw_destroy_qp(struct ib_qp *ib_qp);
1002 struct ib_qp *c4iw_create_qp(struct ib_pd *pd,
1003                              struct ib_qp_init_attr *attrs,
1004                              struct ib_udata *udata);
1005 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1006                                  int attr_mask, struct ib_udata *udata);
1007 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1008                      int attr_mask, struct ib_qp_init_attr *init_attr);
1009 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn);
1010 u32 c4iw_rqtpool_alloc(struct c4iw_rdev *rdev, int size);
1011 void c4iw_rqtpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
1012 u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size);
1013 void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
1014 u32 c4iw_ocqp_pool_alloc(struct c4iw_rdev *rdev, int size);
1015 void c4iw_ocqp_pool_free(struct c4iw_rdev *rdev, u32 addr, int size);
1016 int c4iw_ofld_send(struct c4iw_rdev *rdev, struct sk_buff *skb);
1017 void c4iw_flush_hw_cq(struct c4iw_cq *chp);
1018 void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
1019 int c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp);
1020 int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count);
1021 int c4iw_flush_sq(struct c4iw_qp *qhp);
1022 int c4iw_ev_handler(struct c4iw_dev *rnicp, u32 qid);
1023 u16 c4iw_rqes_posted(struct c4iw_qp *qhp);
1024 int c4iw_post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe);
1025 u32 c4iw_get_cqid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
1026 void c4iw_put_cqid(struct c4iw_rdev *rdev, u32 qid,
1027                 struct c4iw_dev_ucontext *uctx);
1028 u32 c4iw_get_qpid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
1029 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qid,
1030                 struct c4iw_dev_ucontext *uctx);
1031 void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe);
1032
1033 extern struct cxgb4_client t4c_client;
1034 extern c4iw_handler_func c4iw_handlers[NUM_CPL_CMDS];
1035 void __iomem *c4iw_bar2_addrs(struct c4iw_rdev *rdev, unsigned int qid,
1036                               enum cxgb4_bar2_qtype qtype,
1037                               unsigned int *pbar2_qid, u64 *pbar2_pa);
1038 extern void c4iw_log_wr_stats(struct t4_wq *wq, struct t4_cqe *cqe);
1039 extern int c4iw_wr_log;
1040 extern int db_fc_threshold;
1041 extern int db_coalescing_threshold;
1042 extern int use_dsgl;
1043
1044
1045 #endif