drivers/infiniband/hw/cxgb4/iw_cxgb4.h

   1 /*
   2  * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *      - Redistributions in binary form must reproduce the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer in the documentation and/or other materials
  20  *        provided with the distribution.
  21  *
  22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  23  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  24  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  25  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  26  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  27  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  28  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  29  * SOFTWARE.
  30  */
  31 #ifndef __IW_CXGB4_H__
  32 #define __IW_CXGB4_H__
  33
  34 #include <linux/mutex.h>
  35 #include <linux/list.h>
  36 #include <linux/spinlock.h>
  37 #include <linux/idr.h>
  38 #include <linux/completion.h>
  39 #include <linux/netdevice.h>
  40 #include <linux/sched.h>
  41 #include <linux/pci.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/inet.h>
  44 #include <linux/wait.h>
  45 #include <linux/kref.h>
  46 #include <linux/timer.h>
  47 #include <linux/io.h>
  48
  49 #include <asm/byteorder.h>
  50
  51 #include <net/net_namespace.h>
  52
  53 #include <rdma/ib_verbs.h>
  54 #include <rdma/iw_cm.h>
  55 #include <rdma/rdma_netlink.h>
  56 #include <rdma/iw_portmap.h>
  57
  58 #include "cxgb4.h"
  59 #include "cxgb4_uld.h"
  60 #include "l2t.h"
  61 #include "user.h"
  62
  63 #define DRV_NAME "iw_cxgb4"
  64 #define MOD DRV_NAME ":"
  65
  66 extern int c4iw_debug;
  67 #define PDBG(fmt, args...) \
  68 do { \
  69         if (c4iw_debug) \
  70                 printk(MOD fmt, ## args); \
  71 } while (0)
  72
  73 #include "t4.h"
  74
  75 #define PBL_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->pbl.start)
  76 #define RQT_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->rq.start)
  77
  78 static inline void *cplhdr(struct sk_buff *skb)
  79 {
  80         return skb->data;
  81 }
  82
  83 #define C4IW_ID_TABLE_F_RANDOM 1       /* Pseudo-randomize the id's returned */
  84 #define C4IW_ID_TABLE_F_EMPTY  2       /* Table is initially empty */
  85
  86 struct c4iw_id_table {
  87         u32 flags;
  88         u32 start;              /* logical minimal id */
  89         u32 last;               /* hint for find */
  90         u32 max;
  91         spinlock_t lock;
  92         unsigned long *table;
  93 };
  94
  95 struct c4iw_resource {
  96         struct c4iw_id_table tpt_table;
  97         struct c4iw_id_table qid_table;
  98         struct c4iw_id_table pdid_table;
  99 };
 100
 101 struct c4iw_qid_list {
 102         struct list_head entry;
 103         u32 qid;
 104 };
 105
 106 struct c4iw_dev_ucontext {
 107         struct list_head qpids;
 108         struct list_head cqids;
 109         struct mutex lock;
 110 };
 111
 112 enum c4iw_rdev_flags {
 113         T4_FATAL_ERROR = (1<<0),
 114         T4_STATUS_PAGE_DISABLED = (1<<1),
 115 };
 116
 117 struct c4iw_stat {
 118         u64 total;
 119         u64 cur;
 120         u64 max;
 121         u64 fail;
 122 };
 123
 124 struct c4iw_stats {
 125         struct mutex lock;
 126         struct c4iw_stat qid;
 127         struct c4iw_stat pd;
 128         struct c4iw_stat stag;
 129         struct c4iw_stat pbl;
 130         struct c4iw_stat rqt;
 131         struct c4iw_stat ocqp;
 132         u64  db_full;
 133         u64  db_empty;
 134         u64  db_drop;
 135         u64  db_state_transitions;
 136         u64  db_fc_interruptions;
 137         u64  tcam_full;
 138         u64  act_ofld_conn_fails;
 139         u64  pas_ofld_conn_fails;
 140 };
 141
 142 struct c4iw_hw_queue {
 143         int t4_eq_status_entries;
 144         int t4_max_eq_size;
 145         int t4_max_iq_size;
 146         int t4_max_rq_size;
 147         int t4_max_sq_size;
 148         int t4_max_qp_depth;
 149         int t4_max_cq_depth;
 150         int t4_stat_len;
 151 };
 152
 153 struct wr_log_entry {
 154         struct timespec post_host_ts;
 155         struct timespec poll_host_ts;
 156         u64 post_sge_ts;
 157         u64 cqe_sge_ts;
 158         u64 poll_sge_ts;
 159         u16 qid;
 160         u16 wr_id;
 161         u8 opcode;
 162         u8 valid;
 163 };
 164
 165 struct c4iw_rdev {
 166         struct c4iw_resource resource;
 167         unsigned long qpshift;
 168         u32 qpmask;
 169         unsigned long cqshift;
 170         u32 cqmask;
 171         struct c4iw_dev_ucontext uctx;
 172         struct gen_pool *pbl_pool;
 173         struct gen_pool *rqt_pool;
 174         struct gen_pool *ocqp_pool;
 175         u32 flags;
 176         struct cxgb4_lld_info lldi;
 177         unsigned long bar2_pa;
 178         void __iomem *bar2_kva;
 179         unsigned long oc_mw_pa;
 180         void __iomem *oc_mw_kva;
 181         struct c4iw_stats stats;
 182         struct c4iw_hw_queue hw_queue;
 183         struct t4_dev_status_page *status_page;
 184         atomic_t wr_log_idx;
 185         struct wr_log_entry *wr_log;
 186         int wr_log_size;
 187 };
 188
 189 static inline int c4iw_fatal_error(struct c4iw_rdev *rdev)
 190 {
 191         return rdev->flags & T4_FATAL_ERROR;
 192 }
 193
 194 static inline int c4iw_num_stags(struct c4iw_rdev *rdev)
 195 {
 196         return min((int)T4_MAX_NUM_STAG, (int)(rdev->lldi.vr->stag.size >> 5));
 197 }
 198
 199 #define C4IW_WR_TO (30*HZ)
 200
 201 struct c4iw_wr_wait {
 202         struct completion completion;
 203         int ret;
 204 };
 205
 206 static inline void c4iw_init_wr_wait(struct c4iw_wr_wait *wr_waitp)
 207 {
 208         wr_waitp->ret = 0;
 209         init_completion(&wr_waitp->completion);
 210 }
 211
 212 static inline void c4iw_wake_up(struct c4iw_wr_wait *wr_waitp, int ret)
 213 {
 214         wr_waitp->ret = ret;
 215         complete(&wr_waitp->completion);
 216 }
 217
 218 static inline int c4iw_wait_for_reply(struct c4iw_rdev *rdev,
 219                                  struct c4iw_wr_wait *wr_waitp,
 220                                  u32 hwtid, u32 qpid,
 221                                  const char *func)
 222 {
 223         unsigned to = C4IW_WR_TO;
 224         int ret;
 225
 226         do {
 227                 ret = wait_for_completion_timeout(&wr_waitp->completion, to);
 228                 if (!ret) {
 229                         printk(KERN_ERR MOD "%s - Device %s not responding - "
 230                                "tid %u qpid %u\n", func,
 231                                pci_name(rdev->lldi.pdev), hwtid, qpid);
 232                         if (c4iw_fatal_error(rdev)) {
 233                                 wr_waitp->ret = -EIO;
 234                                 break;
 235                         }
 236                         to = to << 2;
 237                 }
 238         } while (!ret);
 239         if (wr_waitp->ret)
 240                 PDBG("%s: FW reply %d tid %u qpid %u\n",
 241                      pci_name(rdev->lldi.pdev), wr_waitp->ret, hwtid, qpid);
 242         return wr_waitp->ret;
 243 }
 244
 245 enum db_state {
 246         NORMAL = 0,
 247         FLOW_CONTROL = 1,
 248         RECOVERY = 2,
 249         STOPPED = 3
 250 };
 251
 252 struct c4iw_dev {
 253         struct ib_device ibdev;
 254         struct c4iw_rdev rdev;
 255         u32 device_cap_flags;
 256         struct idr cqidr;
 257         struct idr qpidr;
 258         struct idr mmidr;
 259         spinlock_t lock;
 260         struct mutex db_mutex;
 261         struct dentry *debugfs_root;
 262         enum db_state db_state;
 263         struct idr hwtid_idr;
 264         struct idr atid_idr;
 265         struct idr stid_idr;
 266         struct list_head db_fc_list;
 267         u32 avail_ird;
 268 };
 269
 270 static inline struct c4iw_dev *to_c4iw_dev(struct ib_device *ibdev)
 271 {
 272         return container_of(ibdev, struct c4iw_dev, ibdev);
 273 }
 274
 275 static inline struct c4iw_dev *rdev_to_c4iw_dev(struct c4iw_rdev *rdev)
 276 {
 277         return container_of(rdev, struct c4iw_dev, rdev);
 278 }
 279
 280 static inline struct c4iw_cq *get_chp(struct c4iw_dev *rhp, u32 cqid)
 281 {
 282         return idr_find(&rhp->cqidr, cqid);
 283 }
 284
 285 static inline struct c4iw_qp *get_qhp(struct c4iw_dev *rhp, u32 qpid)
 286 {
 287         return idr_find(&rhp->qpidr, qpid);
 288 }
 289
 290 static inline struct c4iw_mr *get_mhp(struct c4iw_dev *rhp, u32 mmid)
 291 {
 292         return idr_find(&rhp->mmidr, mmid);
 293 }
 294
 295 static inline int _insert_handle(struct c4iw_dev *rhp, struct idr *idr,
 296                                  void *handle, u32 id, int lock)
 297 {
 298         int ret;
 299
 300         if (lock) {
 301                 idr_preload(GFP_KERNEL);
 302                 spin_lock_irq(&rhp->lock);
 303         }
 304
 305         ret = idr_alloc(idr, handle, id, id + 1, GFP_ATOMIC);
 306
 307         if (lock) {
 308                 spin_unlock_irq(&rhp->lock);
 309                 idr_preload_end();
 310         }
 311
 312         BUG_ON(ret == -ENOSPC);
 313         return ret < 0 ? ret : 0;
 314 }
 315
 316 static inline int insert_handle(struct c4iw_dev *rhp, struct idr *idr,
 317                                 void *handle, u32 id)
 318 {
 319         return _insert_handle(rhp, idr, handle, id, 1);
 320 }
 321
 322 static inline int insert_handle_nolock(struct c4iw_dev *rhp, struct idr *idr,
 323                                        void *handle, u32 id)
 324 {
 325         return _insert_handle(rhp, idr, handle, id, 0);
 326 }
 327
 328 static inline void _remove_handle(struct c4iw_dev *rhp, struct idr *idr,
 329                                    u32 id, int lock)
 330 {
 331         if (lock)
 332                 spin_lock_irq(&rhp->lock);
 333         idr_remove(idr, id);
 334         if (lock)
 335                 spin_unlock_irq(&rhp->lock);
 336 }
 337
 338 static inline void remove_handle(struct c4iw_dev *rhp, struct idr *idr, u32 id)
 339 {
 340         _remove_handle(rhp, idr, id, 1);
 341 }
 342
 343 static inline void remove_handle_nolock(struct c4iw_dev *rhp,
 344                                          struct idr *idr, u32 id)
 345 {
 346         _remove_handle(rhp, idr, id, 0);
 347 }
 348
 349 extern uint c4iw_max_read_depth;
 350
 351 static inline int cur_max_read_depth(struct c4iw_dev *dev)
 352 {
 353         return min(dev->rdev.lldi.max_ordird_qp, c4iw_max_read_depth);
 354 }
 355
 356 struct c4iw_pd {
 357         struct ib_pd ibpd;
 358         u32 pdid;
 359         struct c4iw_dev *rhp;
 360 };
 361
 362 static inline struct c4iw_pd *to_c4iw_pd(struct ib_pd *ibpd)
 363 {
 364         return container_of(ibpd, struct c4iw_pd, ibpd);
 365 }
 366
 367 struct tpt_attributes {
 368         u64 len;
 369         u64 va_fbo;
 370         enum fw_ri_mem_perms perms;
 371         u32 stag;
 372         u32 pdid;
 373         u32 qpid;
 374         u32 pbl_addr;
 375         u32 pbl_size;
 376         u32 state:1;
 377         u32 type:2;
 378         u32 rsvd:1;
 379         u32 remote_invaliate_disable:1;
 380         u32 zbva:1;
 381         u32 mw_bind_enable:1;
 382         u32 page_size:5;
 383 };
 384
 385 struct c4iw_mr {
 386         struct ib_mr ibmr;
 387         struct ib_umem *umem;
 388         struct c4iw_dev *rhp;
 389         u64 kva;
 390         struct tpt_attributes attr;
 391 };
 392
 393 static inline struct c4iw_mr *to_c4iw_mr(struct ib_mr *ibmr)
 394 {
 395         return container_of(ibmr, struct c4iw_mr, ibmr);
 396 }
 397
 398 struct c4iw_mw {
 399         struct ib_mw ibmw;
 400         struct c4iw_dev *rhp;
 401         u64 kva;
 402         struct tpt_attributes attr;
 403 };
 404
 405 static inline struct c4iw_mw *to_c4iw_mw(struct ib_mw *ibmw)
 406 {
 407         return container_of(ibmw, struct c4iw_mw, ibmw);
 408 }
 409
 410 struct c4iw_fr_page_list {
 411         struct ib_fast_reg_page_list ibpl;
 412         DEFINE_DMA_UNMAP_ADDR(mapping);
 413         dma_addr_t dma_addr;
 414         struct c4iw_dev *dev;
 415         int pll_len;
 416 };
 417
 418 static inline struct c4iw_fr_page_list *to_c4iw_fr_page_list(
 419                                         struct ib_fast_reg_page_list *ibpl)
 420 {
 421         return container_of(ibpl, struct c4iw_fr_page_list, ibpl);
 422 }
 423
 424 struct c4iw_cq {
 425         struct ib_cq ibcq;
 426         struct c4iw_dev *rhp;
 427         struct t4_cq cq;
 428         spinlock_t lock;
 429         spinlock_t comp_handler_lock;
 430         atomic_t refcnt;
 431         wait_queue_head_t wait;
 432 };
 433
 434 static inline struct c4iw_cq *to_c4iw_cq(struct ib_cq *ibcq)
 435 {
 436         return container_of(ibcq, struct c4iw_cq, ibcq);
 437 }
 438
 439 struct c4iw_mpa_attributes {
 440         u8 initiator;
 441         u8 recv_marker_enabled;
 442         u8 xmit_marker_enabled;
 443         u8 crc_enabled;
 444         u8 enhanced_rdma_conn;
 445         u8 version;
 446         u8 p2p_type;
 447 };
 448
 449 struct c4iw_qp_attributes {
 450         u32 scq;
 451         u32 rcq;
 452         u32 sq_num_entries;
 453         u32 rq_num_entries;
 454         u32 sq_max_sges;
 455         u32 sq_max_sges_rdma_write;
 456         u32 rq_max_sges;
 457         u32 state;
 458         u8 enable_rdma_read;
 459         u8 enable_rdma_write;
 460         u8 enable_bind;
 461         u8 enable_mmid0_fastreg;
 462         u32 max_ord;
 463         u32 max_ird;
 464         u32 pd;
 465         u32 next_state;
 466         char terminate_buffer[52];
 467         u32 terminate_msg_len;
 468         u8 is_terminate_local;
 469         struct c4iw_mpa_attributes mpa_attr;
 470         struct c4iw_ep *llp_stream_handle;
 471         u8 layer_etype;
 472         u8 ecode;
 473         u16 sq_db_inc;
 474         u16 rq_db_inc;
 475         u8 send_term;
 476 };
 477
 478 struct c4iw_qp {
 479         struct ib_qp ibqp;
 480         struct list_head db_fc_entry;
 481         struct c4iw_dev *rhp;
 482         struct c4iw_ep *ep;
 483         struct c4iw_qp_attributes attr;
 484         struct t4_wq wq;
 485         spinlock_t lock;
 486         struct mutex mutex;
 487         atomic_t refcnt;
 488         wait_queue_head_t wait;
 489         struct timer_list timer;
 490         int sq_sig_all;
 491 };
 492
 493 static inline struct c4iw_qp *to_c4iw_qp(struct ib_qp *ibqp)
 494 {
 495         return container_of(ibqp, struct c4iw_qp, ibqp);
 496 }
 497
 498 struct c4iw_ucontext {
 499         struct ib_ucontext ibucontext;
 500         struct c4iw_dev_ucontext uctx;
 501         u32 key;
 502         spinlock_t mmap_lock;
 503         struct list_head mmaps;
 504 };
 505
 506 static inline struct c4iw_ucontext *to_c4iw_ucontext(struct ib_ucontext *c)
 507 {
 508         return container_of(c, struct c4iw_ucontext, ibucontext);
 509 }
 510
 511 struct c4iw_mm_entry {
 512         struct list_head entry;
 513         u64 addr;
 514         u32 key;
 515         unsigned len;
 516 };
 517
 518 static inline struct c4iw_mm_entry *remove_mmap(struct c4iw_ucontext *ucontext,
 519                                                 u32 key, unsigned len)
 520 {
 521         struct list_head *pos, *nxt;
 522         struct c4iw_mm_entry *mm;
 523
 524         spin_lock(&ucontext->mmap_lock);
 525         list_for_each_safe(pos, nxt, &ucontext->mmaps) {
 526
 527                 mm = list_entry(pos, struct c4iw_mm_entry, entry);
 528                 if (mm->key == key && mm->len == len) {
 529                         list_del_init(&mm->entry);
 530                         spin_unlock(&ucontext->mmap_lock);
 531                         PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__,
 532                              key, (unsigned long long) mm->addr, mm->len);
 533                         return mm;
 534                 }
 535         }
 536         spin_unlock(&ucontext->mmap_lock);
 537         return NULL;
 538 }
 539
 540 static inline void insert_mmap(struct c4iw_ucontext *ucontext,
 541                                struct c4iw_mm_entry *mm)
 542 {
 543         spin_lock(&ucontext->mmap_lock);
 544         PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__,
 545              mm->key, (unsigned long long) mm->addr, mm->len);
 546         list_add_tail(&mm->entry, &ucontext->mmaps);
 547         spin_unlock(&ucontext->mmap_lock);
 548 }
 549
 550 enum c4iw_qp_attr_mask {
 551         C4IW_QP_ATTR_NEXT_STATE = 1 << 0,
 552         C4IW_QP_ATTR_SQ_DB = 1<<1,
 553         C4IW_QP_ATTR_RQ_DB = 1<<2,
 554         C4IW_QP_ATTR_ENABLE_RDMA_READ = 1 << 7,
 555         C4IW_QP_ATTR_ENABLE_RDMA_WRITE = 1 << 8,
 556         C4IW_QP_ATTR_ENABLE_RDMA_BIND = 1 << 9,
 557         C4IW_QP_ATTR_MAX_ORD = 1 << 11,
 558         C4IW_QP_ATTR_MAX_IRD = 1 << 12,
 559         C4IW_QP_ATTR_LLP_STREAM_HANDLE = 1 << 22,
 560         C4IW_QP_ATTR_STREAM_MSG_BUFFER = 1 << 23,
 561         C4IW_QP_ATTR_MPA_ATTR = 1 << 24,
 562         C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE = 1 << 25,
 563         C4IW_QP_ATTR_VALID_MODIFY = (C4IW_QP_ATTR_ENABLE_RDMA_READ |
 564                                      C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
 565                                      C4IW_QP_ATTR_MAX_ORD |
 566                                      C4IW_QP_ATTR_MAX_IRD |
 567                                      C4IW_QP_ATTR_LLP_STREAM_HANDLE |
 568                                      C4IW_QP_ATTR_STREAM_MSG_BUFFER |
 569                                      C4IW_QP_ATTR_MPA_ATTR |
 570                                      C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE)
 571 };
 572
 573 int c4iw_modify_qp(struct c4iw_dev *rhp,
 574                                 struct c4iw_qp *qhp,
 575                                 enum c4iw_qp_attr_mask mask,
 576                                 struct c4iw_qp_attributes *attrs,
 577                                 int internal);
 578
 579 enum c4iw_qp_state {
 580         C4IW_QP_STATE_IDLE,
 581         C4IW_QP_STATE_RTS,
 582         C4IW_QP_STATE_ERROR,
 583         C4IW_QP_STATE_TERMINATE,
 584         C4IW_QP_STATE_CLOSING,
 585         C4IW_QP_STATE_TOT
 586 };
 587
 588 static inline int c4iw_convert_state(enum ib_qp_state ib_state)
 589 {
 590         switch (ib_state) {
 591         case IB_QPS_RESET:
 592         case IB_QPS_INIT:
 593                 return C4IW_QP_STATE_IDLE;
 594         case IB_QPS_RTS:
 595                 return C4IW_QP_STATE_RTS;
 596         case IB_QPS_SQD:
 597                 return C4IW_QP_STATE_CLOSING;
 598         case IB_QPS_SQE:
 599                 return C4IW_QP_STATE_TERMINATE;
 600         case IB_QPS_ERR:
 601                 return C4IW_QP_STATE_ERROR;
 602         default:
 603                 return -1;
 604         }
 605 }
 606
 607 static inline int to_ib_qp_state(int c4iw_qp_state)
 608 {
 609         switch (c4iw_qp_state) {
 610         case C4IW_QP_STATE_IDLE:
 611                 return IB_QPS_INIT;
 612         case C4IW_QP_STATE_RTS:
 613                 return IB_QPS_RTS;
 614         case C4IW_QP_STATE_CLOSING:
 615                 return IB_QPS_SQD;
 616         case C4IW_QP_STATE_TERMINATE:
 617                 return IB_QPS_SQE;
 618         case C4IW_QP_STATE_ERROR:
 619                 return IB_QPS_ERR;
 620         }
 621         return IB_QPS_ERR;
 622 }
 623
 624 static inline u32 c4iw_ib_to_tpt_access(int a)
 625 {
 626         return (a & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
 627                (a & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0) |
 628                (a & IB_ACCESS_LOCAL_WRITE ? FW_RI_MEM_ACCESS_LOCAL_WRITE : 0) |
 629                FW_RI_MEM_ACCESS_LOCAL_READ;
 630 }
 631
 632 static inline u32 c4iw_ib_to_tpt_bind_access(int acc)
 633 {
 634         return (acc & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
 635                (acc & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0);
 636 }
 637
 638 enum c4iw_mmid_state {
 639         C4IW_STAG_STATE_VALID,
 640         C4IW_STAG_STATE_INVALID
 641 };
 642
 643 #define C4IW_NODE_DESC "cxgb4 Chelsio Communications"
 644
 645 #define MPA_KEY_REQ "MPA ID Req Frame"
 646 #define MPA_KEY_REP "MPA ID Rep Frame"
 647
 648 #define MPA_MAX_PRIVATE_DATA    256
 649 #define MPA_ENHANCED_RDMA_CONN  0x10
 650 #define MPA_REJECT              0x20
 651 #define MPA_CRC                 0x40
 652 #define MPA_MARKERS             0x80
 653 #define MPA_FLAGS_MASK          0xE0
 654
 655 #define MPA_V2_PEER2PEER_MODEL          0x8000
 656 #define MPA_V2_ZERO_LEN_FPDU_RTR        0x4000
 657 #define MPA_V2_RDMA_WRITE_RTR           0x8000
 658 #define MPA_V2_RDMA_READ_RTR            0x4000
 659 #define MPA_V2_IRD_ORD_MASK             0x3FFF
 660
 661 #define c4iw_put_ep(ep) { \
 662         PDBG("put_ep (via %s:%u) ep %p refcnt %d\n", __func__, __LINE__,  \
 663              ep, atomic_read(&((ep)->kref.refcount))); \
 664         WARN_ON(atomic_read(&((ep)->kref.refcount)) < 1); \
 665         kref_put(&((ep)->kref), _c4iw_free_ep); \
 666 }
 667
 668 #define c4iw_get_ep(ep) { \
 669         PDBG("get_ep (via %s:%u) ep %p, refcnt %d\n", __func__, __LINE__, \
 670              ep, atomic_read(&((ep)->kref.refcount))); \
 671         kref_get(&((ep)->kref));  \
 672 }
 673 void _c4iw_free_ep(struct kref *kref);
 674
 675 struct mpa_message {
 676         u8 key[16];
 677         u8 flags;
 678         u8 revision;
 679         __be16 private_data_size;
 680         u8 private_data[0];
 681 };
 682
 683 struct mpa_v2_conn_params {
 684         __be16 ird;
 685         __be16 ord;
 686 };
 687
 688 struct terminate_message {
 689         u8 layer_etype;
 690         u8 ecode;
 691         __be16 hdrct_rsvd;
 692         u8 len_hdrs[0];
 693 };
 694
 695 #define TERM_MAX_LENGTH (sizeof(struct terminate_message) + 2 + 18 + 28)
 696
 697 enum c4iw_layers_types {
 698         LAYER_RDMAP             = 0x00,
 699         LAYER_DDP               = 0x10,
 700         LAYER_MPA               = 0x20,
 701         RDMAP_LOCAL_CATA        = 0x00,
 702         RDMAP_REMOTE_PROT       = 0x01,
 703         RDMAP_REMOTE_OP         = 0x02,
 704         DDP_LOCAL_CATA          = 0x00,
 705         DDP_TAGGED_ERR          = 0x01,
 706         DDP_UNTAGGED_ERR        = 0x02,
 707         DDP_LLP                 = 0x03
 708 };
 709
 710 enum c4iw_rdma_ecodes {
 711         RDMAP_INV_STAG          = 0x00,
 712         RDMAP_BASE_BOUNDS       = 0x01,
 713         RDMAP_ACC_VIOL          = 0x02,
 714         RDMAP_STAG_NOT_ASSOC    = 0x03,
 715         RDMAP_TO_WRAP           = 0x04,
 716         RDMAP_INV_VERS          = 0x05,
 717         RDMAP_INV_OPCODE        = 0x06,
 718         RDMAP_STREAM_CATA       = 0x07,
 719         RDMAP_GLOBAL_CATA       = 0x08,
 720         RDMAP_CANT_INV_STAG     = 0x09,
 721         RDMAP_UNSPECIFIED       = 0xff
 722 };
 723
 724 enum c4iw_ddp_ecodes {
 725         DDPT_INV_STAG           = 0x00,
 726         DDPT_BASE_BOUNDS        = 0x01,
 727         DDPT_STAG_NOT_ASSOC     = 0x02,
 728         DDPT_TO_WRAP            = 0x03,
 729         DDPT_INV_VERS           = 0x04,
 730         DDPU_INV_QN             = 0x01,
 731         DDPU_INV_MSN_NOBUF      = 0x02,
 732         DDPU_INV_MSN_RANGE      = 0x03,
 733         DDPU_INV_MO             = 0x04,
 734         DDPU_MSG_TOOBIG         = 0x05,
 735         DDPU_INV_VERS           = 0x06
 736 };
 737
 738 enum c4iw_mpa_ecodes {
 739         MPA_CRC_ERR             = 0x02,
 740         MPA_MARKER_ERR          = 0x03,
 741         MPA_LOCAL_CATA          = 0x05,
 742         MPA_INSUFF_IRD          = 0x06,
 743         MPA_NOMATCH_RTR         = 0x07,
 744 };
 745
 746 enum c4iw_ep_state {
 747         IDLE = 0,
 748         LISTEN,
 749         CONNECTING,
 750         MPA_REQ_WAIT,
 751         MPA_REQ_SENT,
 752         MPA_REQ_RCVD,
 753         MPA_REP_SENT,
 754         FPDU_MODE,
 755         ABORTING,
 756         CLOSING,
 757         MORIBUND,
 758         DEAD,
 759 };
 760
 761 enum c4iw_ep_flags {
 762         PEER_ABORT_IN_PROGRESS  = 0,
 763         ABORT_REQ_IN_PROGRESS   = 1,
 764         RELEASE_RESOURCES       = 2,
 765         CLOSE_SENT              = 3,
 766         TIMEOUT                 = 4,
 767         QP_REFERENCED           = 5,
 768         RELEASE_MAPINFO         = 6,
 769 };
 770
 771 enum c4iw_ep_history {
 772         ACT_OPEN_REQ            = 0,
 773         ACT_OFLD_CONN           = 1,
 774         ACT_OPEN_RPL            = 2,
 775         ACT_ESTAB               = 3,
 776         PASS_ACCEPT_REQ         = 4,
 777         PASS_ESTAB              = 5,
 778         ABORT_UPCALL            = 6,
 779         ESTAB_UPCALL            = 7,
 780         CLOSE_UPCALL            = 8,
 781         ULP_ACCEPT              = 9,
 782         ULP_REJECT              = 10,
 783         TIMEDOUT                = 11,
 784         PEER_ABORT              = 12,
 785         PEER_CLOSE              = 13,
 786         CONNREQ_UPCALL          = 14,
 787         ABORT_CONN              = 15,
 788         DISCONN_UPCALL          = 16,
 789         EP_DISC_CLOSE           = 17,
 790         EP_DISC_ABORT           = 18,
 791         CONN_RPL_UPCALL         = 19,
 792         ACT_RETRY_NOMEM         = 20,
 793         ACT_RETRY_INUSE         = 21
 794 };
 795
 796 struct c4iw_ep_common {
 797         struct iw_cm_id *cm_id;
 798         struct c4iw_qp *qp;
 799         struct c4iw_dev *dev;
 800         enum c4iw_ep_state state;
 801         struct kref kref;
 802         struct mutex mutex;
 803         struct sockaddr_storage local_addr;
 804         struct sockaddr_storage remote_addr;
 805         struct sockaddr_storage mapped_local_addr;
 806         struct sockaddr_storage mapped_remote_addr;
 807         struct c4iw_wr_wait wr_wait;
 808         unsigned long flags;
 809         unsigned long history;
 810 };
 811
 812 struct c4iw_listen_ep {
 813         struct c4iw_ep_common com;
 814         unsigned int stid;
 815         int backlog;
 816 };
 817
 818 struct c4iw_ep {
 819         struct c4iw_ep_common com;
 820         struct c4iw_ep *parent_ep;
 821         struct timer_list timer;
 822         struct list_head entry;
 823         unsigned int atid;
 824         u32 hwtid;
 825         u32 snd_seq;
 826         u32 rcv_seq;
 827         struct l2t_entry *l2t;
 828         struct dst_entry *dst;
 829         struct sk_buff *mpa_skb;
 830         struct c4iw_mpa_attributes mpa_attr;
 831         u8 mpa_pkt[sizeof(struct mpa_message) + MPA_MAX_PRIVATE_DATA];
 832         unsigned int mpa_pkt_len;
 833         u32 ird;
 834         u32 ord;
 835         u32 smac_idx;
 836         u32 tx_chan;
 837         u32 mtu;
 838         u16 mss;
 839         u16 emss;
 840         u16 plen;
 841         u16 rss_qid;
 842         u16 txq_idx;
 843         u16 ctrlq_idx;
 844         u8 tos;
 845         u8 retry_with_mpa_v1;
 846         u8 tried_with_mpa_v1;
 847         unsigned int retry_count;
 848         int snd_win;
 849         int rcv_win;
 850 };
 851
 852 static inline void print_addr(struct c4iw_ep_common *epc, const char *func,
 853                               const char *msg)
 854 {
 855
 856 #define SINA(a) (&(((struct sockaddr_in *)(a))->sin_addr.s_addr))
 857 #define SINP(a) ntohs(((struct sockaddr_in *)(a))->sin_port)
 858 #define SIN6A(a) (&(((struct sockaddr_in6 *)(a))->sin6_addr))
 859 #define SIN6P(a) ntohs(((struct sockaddr_in6 *)(a))->sin6_port)
 860
 861         if (c4iw_debug) {
 862                 switch (epc->local_addr.ss_family) {
 863                 case AF_INET:
 864                         PDBG("%s %s %pI4:%u/%u <-> %pI4:%u/%u\n",
 865                              func, msg, SINA(&epc->local_addr),
 866                              SINP(&epc->local_addr),
 867                              SINP(&epc->mapped_local_addr),
 868                              SINA(&epc->remote_addr),
 869                              SINP(&epc->remote_addr),
 870                              SINP(&epc->mapped_remote_addr));
 871                         break;
 872                 case AF_INET6:
 873                         PDBG("%s %s %pI6:%u/%u <-> %pI6:%u/%u\n",
 874                              func, msg, SIN6A(&epc->local_addr),
 875                              SIN6P(&epc->local_addr),
 876                              SIN6P(&epc->mapped_local_addr),
 877                              SIN6A(&epc->remote_addr),
 878                              SIN6P(&epc->remote_addr),
 879                              SIN6P(&epc->mapped_remote_addr));
 880                         break;
 881                 default:
 882                         break;
 883                 }
 884         }
 885 #undef SINA
 886 #undef SINP
 887 #undef SIN6A
 888 #undef SIN6P
 889 }
 890
 891 static inline struct c4iw_ep *to_ep(struct iw_cm_id *cm_id)
 892 {
 893         return cm_id->provider_data;
 894 }
 895
 896 static inline struct c4iw_listen_ep *to_listen_ep(struct iw_cm_id *cm_id)
 897 {
 898         return cm_id->provider_data;
 899 }
 900
 901 static inline int compute_wscale(int win)
 902 {
 903         int wscale = 0;
 904
 905         while (wscale < 14 && (65535<<wscale) < win)
 906                 wscale++;
 907         return wscale;
 908 }
 909
 910 static inline int ocqp_supported(const struct cxgb4_lld_info *infop)
 911 {
 912 #if defined(__i386__) || defined(__x86_64__) || defined(CONFIG_PPC64)
 913         return infop->vr->ocq.size > 0;
 914 #else
 915         return 0;
 916 #endif
 917 }
 918
 919 u32 c4iw_id_alloc(struct c4iw_id_table *alloc);
 920 void c4iw_id_free(struct c4iw_id_table *alloc, u32 obj);
 921 int c4iw_id_table_alloc(struct c4iw_id_table *alloc, u32 start, u32 num,
 922                         u32 reserved, u32 flags);
 923 void c4iw_id_table_free(struct c4iw_id_table *alloc);
 924
 925 typedef int (*c4iw_handler_func)(struct c4iw_dev *dev, struct sk_buff *skb);
 926
 927 int c4iw_ep_redirect(void *ctx, struct dst_entry *old, struct dst_entry *new,
 928                      struct l2t_entry *l2t);
 929 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qpid,
 930                    struct c4iw_dev_ucontext *uctx);
 931 u32 c4iw_get_resource(struct c4iw_id_table *id_table);
 932 void c4iw_put_resource(struct c4iw_id_table *id_table, u32 entry);
 933 int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_tpt, u32 nr_pdid);
 934 int c4iw_init_ctrl_qp(struct c4iw_rdev *rdev);
 935 int c4iw_pblpool_create(struct c4iw_rdev *rdev);
 936 int c4iw_rqtpool_create(struct c4iw_rdev *rdev);
 937 int c4iw_ocqp_pool_create(struct c4iw_rdev *rdev);
 938 void c4iw_pblpool_destroy(struct c4iw_rdev *rdev);
 939 void c4iw_rqtpool_destroy(struct c4iw_rdev *rdev);
 940 void c4iw_ocqp_pool_destroy(struct c4iw_rdev *rdev);
 941 void c4iw_destroy_resource(struct c4iw_resource *rscp);
 942 int c4iw_destroy_ctrl_qp(struct c4iw_rdev *rdev);
 943 int c4iw_register_device(struct c4iw_dev *dev);
 944 void c4iw_unregister_device(struct c4iw_dev *dev);
 945 int __init c4iw_cm_init(void);
 946 void __exit c4iw_cm_term(void);
 947 void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
 948                                struct c4iw_dev_ucontext *uctx);
 949 void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
 950                             struct c4iw_dev_ucontext *uctx);
 951 int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
 952 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
 953                       struct ib_send_wr **bad_wr);
 954 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
 955                       struct ib_recv_wr **bad_wr);
 956 int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw,
 957                  struct ib_mw_bind *mw_bind);
 958 int c4iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
 959 int c4iw_create_listen(struct iw_cm_id *cm_id, int backlog);
 960 int c4iw_destroy_listen(struct iw_cm_id *cm_id);
 961 int c4iw_accept_cr(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
 962 int c4iw_reject_cr(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len);
 963 void c4iw_qp_add_ref(struct ib_qp *qp);
 964 void c4iw_qp_rem_ref(struct ib_qp *qp);
 965 void c4iw_free_fastreg_pbl(struct ib_fast_reg_page_list *page_list);
 966 struct ib_fast_reg_page_list *c4iw_alloc_fastreg_pbl(
 967                                         struct ib_device *device,
 968                                         int page_list_len);
 969 struct ib_mr *c4iw_alloc_fast_reg_mr(struct ib_pd *pd, int pbl_depth);
 970 int c4iw_dealloc_mw(struct ib_mw *mw);
 971 struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd, enum ib_mw_type type);
 972 struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start,
 973                                            u64 length, u64 virt, int acc,
 974                                            struct ib_udata *udata);
 975 struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc);
 976 struct ib_mr *c4iw_register_phys_mem(struct ib_pd *pd,
 977                                         struct ib_phys_buf *buffer_list,
 978                                         int num_phys_buf,
 979                                         int acc,
 980                                         u64 *iova_start);
 981 int c4iw_reregister_phys_mem(struct ib_mr *mr,
 982                                      int mr_rereg_mask,
 983                                      struct ib_pd *pd,
 984                                      struct ib_phys_buf *buffer_list,
 985                                      int num_phys_buf,
 986                                      int acc, u64 *iova_start);
 987 int c4iw_dereg_mr(struct ib_mr *ib_mr);
 988 int c4iw_destroy_cq(struct ib_cq *ib_cq);
 989 struct ib_cq *c4iw_create_cq(struct ib_device *ibdev, int entries,
 990                                         int vector,
 991                                         struct ib_ucontext *ib_context,
 992                                         struct ib_udata *udata);
 993 int c4iw_resize_cq(struct ib_cq *cq, int cqe, struct ib_udata *udata);
 994 int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
 995 int c4iw_destroy_qp(struct ib_qp *ib_qp);
 996 struct ib_qp *c4iw_create_qp(struct ib_pd *pd,
 997                              struct ib_qp_init_attr *attrs,
 998                              struct ib_udata *udata);
 999 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1000                                  int attr_mask, struct ib_udata *udata);
1001 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1002                      int attr_mask, struct ib_qp_init_attr *init_attr);
1003 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn);
1004 u32 c4iw_rqtpool_alloc(struct c4iw_rdev *rdev, int size);
1005 void c4iw_rqtpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
1006 u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size);
1007 void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
1008 u32 c4iw_ocqp_pool_alloc(struct c4iw_rdev *rdev, int size);
1009 void c4iw_ocqp_pool_free(struct c4iw_rdev *rdev, u32 addr, int size);
1010 int c4iw_ofld_send(struct c4iw_rdev *rdev, struct sk_buff *skb);
1011 void c4iw_flush_hw_cq(struct c4iw_cq *chp);
1012 void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
1013 int c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp);
1014 int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count);
1015 int c4iw_flush_sq(struct c4iw_qp *qhp);
1016 int c4iw_ev_handler(struct c4iw_dev *rnicp, u32 qid);
1017 u16 c4iw_rqes_posted(struct c4iw_qp *qhp);
1018 int c4iw_post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe);
1019 u32 c4iw_get_cqid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
1020 void c4iw_put_cqid(struct c4iw_rdev *rdev, u32 qid,
1021                 struct c4iw_dev_ucontext *uctx);
1022 u32 c4iw_get_qpid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
1023 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qid,
1024                 struct c4iw_dev_ucontext *uctx);
1025 void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe);
1026
1027 extern struct cxgb4_client t4c_client;
1028 extern c4iw_handler_func c4iw_handlers[NUM_CPL_CMDS];
1029 extern void c4iw_log_wr_stats(struct t4_wq *wq, struct t4_cqe *cqe);
1030 extern int c4iw_wr_log;
1031 extern int db_fc_threshold;
1032 extern int db_coalescing_threshold;
1033 extern int use_dsgl;
1034
1035
1036 #endif