2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 static int ocqp_support
;
35 module_param(ocqp_support
, int, 0644);
36 MODULE_PARM_DESC(ocqp_support
, "Support on-chip SQs (default=0)");
38 static void set_state(struct c4iw_qp
*qhp
, enum c4iw_qp_state state
)
41 spin_lock_irqsave(&qhp
->lock
, flag
);
42 qhp
->attr
.state
= state
;
43 spin_unlock_irqrestore(&qhp
->lock
, flag
);
46 static void dealloc_oc_sq(struct c4iw_rdev
*rdev
, struct t4_sq
*sq
)
48 c4iw_ocqp_pool_free(rdev
, sq
->dma_addr
, sq
->memsize
);
51 static void dealloc_host_sq(struct c4iw_rdev
*rdev
, struct t4_sq
*sq
)
53 dma_free_coherent(&(rdev
->lldi
.pdev
->dev
), sq
->memsize
, sq
->queue
,
54 pci_unmap_addr(sq
, mapping
));
57 static void dealloc_sq(struct c4iw_rdev
*rdev
, struct t4_sq
*sq
)
60 dealloc_oc_sq(rdev
, sq
);
62 dealloc_host_sq(rdev
, sq
);
65 static int alloc_oc_sq(struct c4iw_rdev
*rdev
, struct t4_sq
*sq
)
67 if (!ocqp_support
|| !t4_ocqp_supported())
69 sq
->dma_addr
= c4iw_ocqp_pool_alloc(rdev
, sq
->memsize
);
72 sq
->phys_addr
= rdev
->oc_mw_pa
+ sq
->dma_addr
-
73 rdev
->lldi
.vr
->ocq
.start
;
74 sq
->queue
= (__force
union t4_wr
*)(rdev
->oc_mw_kva
+ sq
->dma_addr
-
75 rdev
->lldi
.vr
->ocq
.start
);
76 sq
->flags
|= T4_SQ_ONCHIP
;
80 static int alloc_host_sq(struct c4iw_rdev
*rdev
, struct t4_sq
*sq
)
82 sq
->queue
= dma_alloc_coherent(&(rdev
->lldi
.pdev
->dev
), sq
->memsize
,
83 &(sq
->dma_addr
), GFP_KERNEL
);
86 sq
->phys_addr
= virt_to_phys(sq
->queue
);
87 pci_unmap_addr_set(sq
, mapping
, sq
->dma_addr
);
91 static int destroy_qp(struct c4iw_rdev
*rdev
, struct t4_wq
*wq
,
92 struct c4iw_dev_ucontext
*uctx
)
95 * uP clears EQ contexts when the connection exits rdma mode,
96 * so no need to post a RESET WR for these EQs.
98 dma_free_coherent(&(rdev
->lldi
.pdev
->dev
),
99 wq
->rq
.memsize
, wq
->rq
.queue
,
100 dma_unmap_addr(&wq
->rq
, mapping
));
101 dealloc_sq(rdev
, &wq
->sq
);
102 c4iw_rqtpool_free(rdev
, wq
->rq
.rqt_hwaddr
, wq
->rq
.rqt_size
);
105 c4iw_put_qpid(rdev
, wq
->rq
.qid
, uctx
);
106 c4iw_put_qpid(rdev
, wq
->sq
.qid
, uctx
);
110 static int create_qp(struct c4iw_rdev
*rdev
, struct t4_wq
*wq
,
111 struct t4_cq
*rcq
, struct t4_cq
*scq
,
112 struct c4iw_dev_ucontext
*uctx
)
114 int user
= (uctx
!= &rdev
->uctx
);
115 struct fw_ri_res_wr
*res_wr
;
116 struct fw_ri_res
*res
;
118 struct c4iw_wr_wait wr_wait
;
123 wq
->sq
.qid
= c4iw_get_qpid(rdev
, uctx
);
127 wq
->rq
.qid
= c4iw_get_qpid(rdev
, uctx
);
132 wq
->sq
.sw_sq
= kzalloc(wq
->sq
.size
* sizeof *wq
->sq
.sw_sq
,
137 wq
->rq
.sw_rq
= kzalloc(wq
->rq
.size
* sizeof *wq
->rq
.sw_rq
,
144 * RQT must be a power of 2.
146 wq
->rq
.rqt_size
= roundup_pow_of_two(wq
->rq
.size
);
147 wq
->rq
.rqt_hwaddr
= c4iw_rqtpool_alloc(rdev
, wq
->rq
.rqt_size
);
148 if (!wq
->rq
.rqt_hwaddr
)
152 if (alloc_oc_sq(rdev
, &wq
->sq
) && alloc_host_sq(rdev
, &wq
->sq
))
155 if (alloc_host_sq(rdev
, &wq
->sq
))
157 memset(wq
->sq
.queue
, 0, wq
->sq
.memsize
);
158 dma_unmap_addr_set(&wq
->sq
, mapping
, wq
->sq
.dma_addr
);
160 wq
->rq
.queue
= dma_alloc_coherent(&(rdev
->lldi
.pdev
->dev
),
161 wq
->rq
.memsize
, &(wq
->rq
.dma_addr
),
165 PDBG("%s sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx\n",
166 __func__
, wq
->sq
.queue
,
167 (unsigned long long)virt_to_phys(wq
->sq
.queue
),
169 (unsigned long long)virt_to_phys(wq
->rq
.queue
));
170 memset(wq
->rq
.queue
, 0, wq
->rq
.memsize
);
171 dma_unmap_addr_set(&wq
->rq
, mapping
, wq
->rq
.dma_addr
);
173 wq
->db
= rdev
->lldi
.db_reg
;
174 wq
->gts
= rdev
->lldi
.gts_reg
;
176 wq
->sq
.udb
= (u64
)pci_resource_start(rdev
->lldi
.pdev
, 2) +
177 (wq
->sq
.qid
<< rdev
->qpshift
);
178 wq
->sq
.udb
&= PAGE_MASK
;
179 wq
->rq
.udb
= (u64
)pci_resource_start(rdev
->lldi
.pdev
, 2) +
180 (wq
->rq
.qid
<< rdev
->qpshift
);
181 wq
->rq
.udb
&= PAGE_MASK
;
186 /* build fw_ri_res_wr */
187 wr_len
= sizeof *res_wr
+ 2 * sizeof *res
;
189 skb
= alloc_skb(wr_len
, GFP_KERNEL
);
194 set_wr_txq(skb
, CPL_PRIORITY_CONTROL
, 0);
196 res_wr
= (struct fw_ri_res_wr
*)__skb_put(skb
, wr_len
);
197 memset(res_wr
, 0, wr_len
);
198 res_wr
->op_nres
= cpu_to_be32(
199 FW_WR_OP(FW_RI_RES_WR
) |
200 V_FW_RI_RES_WR_NRES(2) |
202 res_wr
->len16_pkd
= cpu_to_be32(DIV_ROUND_UP(wr_len
, 16));
203 res_wr
->cookie
= (unsigned long) &wr_wait
;
205 res
->u
.sqrq
.restype
= FW_RI_RES_TYPE_SQ
;
206 res
->u
.sqrq
.op
= FW_RI_RES_OP_WRITE
;
209 * eqsize is the number of 64B entries plus the status page size.
211 eqsize
= wq
->sq
.size
* T4_SQ_NUM_SLOTS
+ T4_EQ_STATUS_ENTRIES
;
213 res
->u
.sqrq
.fetchszm_to_iqid
= cpu_to_be32(
214 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */
215 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */
216 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */
217 t4_sq_onchip(&wq
->sq
) ? F_FW_RI_RES_WR_ONCHIP
: 0 |
218 V_FW_RI_RES_WR_IQID(scq
->cqid
));
219 res
->u
.sqrq
.dcaen_to_eqsize
= cpu_to_be32(
220 V_FW_RI_RES_WR_DCAEN(0) |
221 V_FW_RI_RES_WR_DCACPU(0) |
222 V_FW_RI_RES_WR_FBMIN(2) |
223 V_FW_RI_RES_WR_FBMAX(3) |
224 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
225 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
226 V_FW_RI_RES_WR_EQSIZE(eqsize
));
227 res
->u
.sqrq
.eqid
= cpu_to_be32(wq
->sq
.qid
);
228 res
->u
.sqrq
.eqaddr
= cpu_to_be64(wq
->sq
.dma_addr
);
230 res
->u
.sqrq
.restype
= FW_RI_RES_TYPE_RQ
;
231 res
->u
.sqrq
.op
= FW_RI_RES_OP_WRITE
;
234 * eqsize is the number of 64B entries plus the status page size.
236 eqsize
= wq
->rq
.size
* T4_RQ_NUM_SLOTS
+ T4_EQ_STATUS_ENTRIES
;
237 res
->u
.sqrq
.fetchszm_to_iqid
= cpu_to_be32(
238 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */
239 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */
240 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */
241 V_FW_RI_RES_WR_IQID(rcq
->cqid
));
242 res
->u
.sqrq
.dcaen_to_eqsize
= cpu_to_be32(
243 V_FW_RI_RES_WR_DCAEN(0) |
244 V_FW_RI_RES_WR_DCACPU(0) |
245 V_FW_RI_RES_WR_FBMIN(2) |
246 V_FW_RI_RES_WR_FBMAX(3) |
247 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
248 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
249 V_FW_RI_RES_WR_EQSIZE(eqsize
));
250 res
->u
.sqrq
.eqid
= cpu_to_be32(wq
->rq
.qid
);
251 res
->u
.sqrq
.eqaddr
= cpu_to_be64(wq
->rq
.dma_addr
);
253 c4iw_init_wr_wait(&wr_wait
);
255 ret
= c4iw_ofld_send(rdev
, skb
);
258 ret
= c4iw_wait_for_reply(rdev
, &wr_wait
, 0, wq
->sq
.qid
, __func__
);
262 PDBG("%s sqid 0x%x rqid 0x%x kdb 0x%p squdb 0x%llx rqudb 0x%llx\n",
263 __func__
, wq
->sq
.qid
, wq
->rq
.qid
, wq
->db
,
264 (unsigned long long)wq
->sq
.udb
, (unsigned long long)wq
->rq
.udb
);
268 dma_free_coherent(&(rdev
->lldi
.pdev
->dev
),
269 wq
->rq
.memsize
, wq
->rq
.queue
,
270 dma_unmap_addr(&wq
->rq
, mapping
));
272 dealloc_sq(rdev
, &wq
->sq
);
274 c4iw_rqtpool_free(rdev
, wq
->rq
.rqt_hwaddr
, wq
->rq
.rqt_size
);
280 c4iw_put_qpid(rdev
, wq
->rq
.qid
, uctx
);
282 c4iw_put_qpid(rdev
, wq
->sq
.qid
, uctx
);
286 static int build_immd(struct t4_sq
*sq
, struct fw_ri_immd
*immdp
,
287 struct ib_send_wr
*wr
, int max
, u32
*plenp
)
294 dstp
= (u8
*)immdp
->data
;
295 for (i
= 0; i
< wr
->num_sge
; i
++) {
296 if ((plen
+ wr
->sg_list
[i
].length
) > max
)
298 srcp
= (u8
*)(unsigned long)wr
->sg_list
[i
].addr
;
299 plen
+= wr
->sg_list
[i
].length
;
300 rem
= wr
->sg_list
[i
].length
;
302 if (dstp
== (u8
*)&sq
->queue
[sq
->size
])
303 dstp
= (u8
*)sq
->queue
;
304 if (rem
<= (u8
*)&sq
->queue
[sq
->size
] - dstp
)
307 len
= (u8
*)&sq
->queue
[sq
->size
] - dstp
;
308 memcpy(dstp
, srcp
, len
);
314 len
= roundup(plen
+ sizeof *immdp
, 16) - (plen
+ sizeof *immdp
);
316 memset(dstp
, 0, len
);
317 immdp
->op
= FW_RI_DATA_IMMD
;
320 immdp
->immdlen
= cpu_to_be32(plen
);
325 static int build_isgl(__be64
*queue_start
, __be64
*queue_end
,
326 struct fw_ri_isgl
*isglp
, struct ib_sge
*sg_list
,
327 int num_sge
, u32
*plenp
)
332 __be64
*flitp
= (__be64
*)isglp
->sge
;
334 for (i
= 0; i
< num_sge
; i
++) {
335 if ((plen
+ sg_list
[i
].length
) < plen
)
337 plen
+= sg_list
[i
].length
;
338 *flitp
= cpu_to_be64(((u64
)sg_list
[i
].lkey
<< 32) |
340 if (++flitp
== queue_end
)
342 *flitp
= cpu_to_be64(sg_list
[i
].addr
);
343 if (++flitp
== queue_end
)
346 *flitp
= (__force __be64
)0;
347 isglp
->op
= FW_RI_DATA_ISGL
;
349 isglp
->nsge
= cpu_to_be16(num_sge
);
356 static int build_rdma_send(struct t4_sq
*sq
, union t4_wr
*wqe
,
357 struct ib_send_wr
*wr
, u8
*len16
)
363 if (wr
->num_sge
> T4_MAX_SEND_SGE
)
365 switch (wr
->opcode
) {
367 if (wr
->send_flags
& IB_SEND_SOLICITED
)
368 wqe
->send
.sendop_pkd
= cpu_to_be32(
369 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE
));
371 wqe
->send
.sendop_pkd
= cpu_to_be32(
372 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND
));
373 wqe
->send
.stag_inv
= 0;
375 case IB_WR_SEND_WITH_INV
:
376 if (wr
->send_flags
& IB_SEND_SOLICITED
)
377 wqe
->send
.sendop_pkd
= cpu_to_be32(
378 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE_INV
));
380 wqe
->send
.sendop_pkd
= cpu_to_be32(
381 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_INV
));
382 wqe
->send
.stag_inv
= cpu_to_be32(wr
->ex
.invalidate_rkey
);
391 if (wr
->send_flags
& IB_SEND_INLINE
) {
392 ret
= build_immd(sq
, wqe
->send
.u
.immd_src
, wr
,
393 T4_MAX_SEND_INLINE
, &plen
);
396 size
= sizeof wqe
->send
+ sizeof(struct fw_ri_immd
) +
399 ret
= build_isgl((__be64
*)sq
->queue
,
400 (__be64
*)&sq
->queue
[sq
->size
],
401 wqe
->send
.u
.isgl_src
,
402 wr
->sg_list
, wr
->num_sge
, &plen
);
405 size
= sizeof wqe
->send
+ sizeof(struct fw_ri_isgl
) +
406 wr
->num_sge
* sizeof(struct fw_ri_sge
);
409 wqe
->send
.u
.immd_src
[0].op
= FW_RI_DATA_IMMD
;
410 wqe
->send
.u
.immd_src
[0].r1
= 0;
411 wqe
->send
.u
.immd_src
[0].r2
= 0;
412 wqe
->send
.u
.immd_src
[0].immdlen
= 0;
413 size
= sizeof wqe
->send
+ sizeof(struct fw_ri_immd
);
416 *len16
= DIV_ROUND_UP(size
, 16);
417 wqe
->send
.plen
= cpu_to_be32(plen
);
421 static int build_rdma_write(struct t4_sq
*sq
, union t4_wr
*wqe
,
422 struct ib_send_wr
*wr
, u8
*len16
)
428 if (wr
->num_sge
> T4_MAX_SEND_SGE
)
431 wqe
->write
.stag_sink
= cpu_to_be32(wr
->wr
.rdma
.rkey
);
432 wqe
->write
.to_sink
= cpu_to_be64(wr
->wr
.rdma
.remote_addr
);
434 if (wr
->send_flags
& IB_SEND_INLINE
) {
435 ret
= build_immd(sq
, wqe
->write
.u
.immd_src
, wr
,
436 T4_MAX_WRITE_INLINE
, &plen
);
439 size
= sizeof wqe
->write
+ sizeof(struct fw_ri_immd
) +
442 ret
= build_isgl((__be64
*)sq
->queue
,
443 (__be64
*)&sq
->queue
[sq
->size
],
444 wqe
->write
.u
.isgl_src
,
445 wr
->sg_list
, wr
->num_sge
, &plen
);
448 size
= sizeof wqe
->write
+ sizeof(struct fw_ri_isgl
) +
449 wr
->num_sge
* sizeof(struct fw_ri_sge
);
452 wqe
->write
.u
.immd_src
[0].op
= FW_RI_DATA_IMMD
;
453 wqe
->write
.u
.immd_src
[0].r1
= 0;
454 wqe
->write
.u
.immd_src
[0].r2
= 0;
455 wqe
->write
.u
.immd_src
[0].immdlen
= 0;
456 size
= sizeof wqe
->write
+ sizeof(struct fw_ri_immd
);
459 *len16
= DIV_ROUND_UP(size
, 16);
460 wqe
->write
.plen
= cpu_to_be32(plen
);
464 static int build_rdma_read(union t4_wr
*wqe
, struct ib_send_wr
*wr
, u8
*len16
)
469 wqe
->read
.stag_src
= cpu_to_be32(wr
->wr
.rdma
.rkey
);
470 wqe
->read
.to_src_hi
= cpu_to_be32((u32
)(wr
->wr
.rdma
.remote_addr
472 wqe
->read
.to_src_lo
= cpu_to_be32((u32
)wr
->wr
.rdma
.remote_addr
);
473 wqe
->read
.stag_sink
= cpu_to_be32(wr
->sg_list
[0].lkey
);
474 wqe
->read
.plen
= cpu_to_be32(wr
->sg_list
[0].length
);
475 wqe
->read
.to_sink_hi
= cpu_to_be32((u32
)(wr
->sg_list
[0].addr
477 wqe
->read
.to_sink_lo
= cpu_to_be32((u32
)(wr
->sg_list
[0].addr
));
479 wqe
->read
.stag_src
= cpu_to_be32(2);
480 wqe
->read
.to_src_hi
= 0;
481 wqe
->read
.to_src_lo
= 0;
482 wqe
->read
.stag_sink
= cpu_to_be32(2);
484 wqe
->read
.to_sink_hi
= 0;
485 wqe
->read
.to_sink_lo
= 0;
489 *len16
= DIV_ROUND_UP(sizeof wqe
->read
, 16);
493 static int build_rdma_recv(struct c4iw_qp
*qhp
, union t4_recv_wr
*wqe
,
494 struct ib_recv_wr
*wr
, u8
*len16
)
498 ret
= build_isgl((__be64
*)qhp
->wq
.rq
.queue
,
499 (__be64
*)&qhp
->wq
.rq
.queue
[qhp
->wq
.rq
.size
],
500 &wqe
->recv
.isgl
, wr
->sg_list
, wr
->num_sge
, NULL
);
503 *len16
= DIV_ROUND_UP(sizeof wqe
->recv
+
504 wr
->num_sge
* sizeof(struct fw_ri_sge
), 16);
508 static int build_fastreg(struct t4_sq
*sq
, union t4_wr
*wqe
,
509 struct ib_send_wr
*wr
, u8
*len16
)
512 struct fw_ri_immd
*imdp
;
515 int pbllen
= roundup(wr
->wr
.fast_reg
.page_list_len
* sizeof(u64
), 32);
518 if (wr
->wr
.fast_reg
.page_list_len
> T4_MAX_FR_DEPTH
)
521 wqe
->fr
.qpbinde_to_dcacpu
= 0;
522 wqe
->fr
.pgsz_shift
= wr
->wr
.fast_reg
.page_shift
- 12;
523 wqe
->fr
.addr_type
= FW_RI_VA_BASED_TO
;
524 wqe
->fr
.mem_perms
= c4iw_ib_to_tpt_access(wr
->wr
.fast_reg
.access_flags
);
526 wqe
->fr
.len_lo
= cpu_to_be32(wr
->wr
.fast_reg
.length
);
527 wqe
->fr
.stag
= cpu_to_be32(wr
->wr
.fast_reg
.rkey
);
528 wqe
->fr
.va_hi
= cpu_to_be32(wr
->wr
.fast_reg
.iova_start
>> 32);
529 wqe
->fr
.va_lo_fbo
= cpu_to_be32(wr
->wr
.fast_reg
.iova_start
&
531 WARN_ON(pbllen
> T4_MAX_FR_IMMD
);
532 imdp
= (struct fw_ri_immd
*)(&wqe
->fr
+ 1);
533 imdp
->op
= FW_RI_DATA_IMMD
;
536 imdp
->immdlen
= cpu_to_be32(pbllen
);
537 p
= (__be64
*)(imdp
+ 1);
539 for (i
= 0; i
< wr
->wr
.fast_reg
.page_list_len
; i
++) {
540 *p
= cpu_to_be64((u64
)wr
->wr
.fast_reg
.page_list
->page_list
[i
]);
542 if (++p
== (__be64
*)&sq
->queue
[sq
->size
])
543 p
= (__be64
*)sq
->queue
;
549 if (++p
== (__be64
*)&sq
->queue
[sq
->size
])
550 p
= (__be64
*)sq
->queue
;
552 *len16
= DIV_ROUND_UP(sizeof wqe
->fr
+ sizeof *imdp
+ pbllen
, 16);
556 static int build_inv_stag(union t4_wr
*wqe
, struct ib_send_wr
*wr
,
559 wqe
->inv
.stag_inv
= cpu_to_be32(wr
->ex
.invalidate_rkey
);
561 *len16
= DIV_ROUND_UP(sizeof wqe
->inv
, 16);
565 void c4iw_qp_add_ref(struct ib_qp
*qp
)
567 PDBG("%s ib_qp %p\n", __func__
, qp
);
568 atomic_inc(&(to_c4iw_qp(qp
)->refcnt
));
571 void c4iw_qp_rem_ref(struct ib_qp
*qp
)
573 PDBG("%s ib_qp %p\n", __func__
, qp
);
574 if (atomic_dec_and_test(&(to_c4iw_qp(qp
)->refcnt
)))
575 wake_up(&(to_c4iw_qp(qp
)->wait
));
578 int c4iw_post_send(struct ib_qp
*ibqp
, struct ib_send_wr
*wr
,
579 struct ib_send_wr
**bad_wr
)
583 enum fw_wr_opcodes fw_opcode
= 0;
584 enum fw_ri_wr_flags fw_flags
;
588 struct t4_swsqe
*swsqe
;
592 qhp
= to_c4iw_qp(ibqp
);
593 spin_lock_irqsave(&qhp
->lock
, flag
);
594 if (t4_wq_in_error(&qhp
->wq
)) {
595 spin_unlock_irqrestore(&qhp
->lock
, flag
);
598 num_wrs
= t4_sq_avail(&qhp
->wq
);
600 spin_unlock_irqrestore(&qhp
->lock
, flag
);
609 wqe
= (union t4_wr
*)((u8
*)qhp
->wq
.sq
.queue
+
610 qhp
->wq
.sq
.wq_pidx
* T4_EQ_ENTRY_SIZE
);
613 if (wr
->send_flags
& IB_SEND_SOLICITED
)
614 fw_flags
|= FW_RI_SOLICITED_EVENT_FLAG
;
615 if (wr
->send_flags
& IB_SEND_SIGNALED
)
616 fw_flags
|= FW_RI_COMPLETION_FLAG
;
617 swsqe
= &qhp
->wq
.sq
.sw_sq
[qhp
->wq
.sq
.pidx
];
618 switch (wr
->opcode
) {
619 case IB_WR_SEND_WITH_INV
:
621 if (wr
->send_flags
& IB_SEND_FENCE
)
622 fw_flags
|= FW_RI_READ_FENCE_FLAG
;
623 fw_opcode
= FW_RI_SEND_WR
;
624 if (wr
->opcode
== IB_WR_SEND
)
625 swsqe
->opcode
= FW_RI_SEND
;
627 swsqe
->opcode
= FW_RI_SEND_WITH_INV
;
628 err
= build_rdma_send(&qhp
->wq
.sq
, wqe
, wr
, &len16
);
630 case IB_WR_RDMA_WRITE
:
631 fw_opcode
= FW_RI_RDMA_WRITE_WR
;
632 swsqe
->opcode
= FW_RI_RDMA_WRITE
;
633 err
= build_rdma_write(&qhp
->wq
.sq
, wqe
, wr
, &len16
);
635 case IB_WR_RDMA_READ
:
636 case IB_WR_RDMA_READ_WITH_INV
:
637 fw_opcode
= FW_RI_RDMA_READ_WR
;
638 swsqe
->opcode
= FW_RI_READ_REQ
;
639 if (wr
->opcode
== IB_WR_RDMA_READ_WITH_INV
)
640 fw_flags
= FW_RI_RDMA_READ_INVALIDATE
;
643 err
= build_rdma_read(wqe
, wr
, &len16
);
646 swsqe
->read_len
= wr
->sg_list
[0].length
;
647 if (!qhp
->wq
.sq
.oldest_read
)
648 qhp
->wq
.sq
.oldest_read
= swsqe
;
650 case IB_WR_FAST_REG_MR
:
651 fw_opcode
= FW_RI_FR_NSMR_WR
;
652 swsqe
->opcode
= FW_RI_FAST_REGISTER
;
653 err
= build_fastreg(&qhp
->wq
.sq
, wqe
, wr
, &len16
);
655 case IB_WR_LOCAL_INV
:
656 if (wr
->send_flags
& IB_SEND_FENCE
)
657 fw_flags
|= FW_RI_LOCAL_FENCE_FLAG
;
658 fw_opcode
= FW_RI_INV_LSTAG_WR
;
659 swsqe
->opcode
= FW_RI_LOCAL_INV
;
660 err
= build_inv_stag(wqe
, wr
, &len16
);
663 PDBG("%s post of type=%d TBD!\n", __func__
,
671 swsqe
->idx
= qhp
->wq
.sq
.pidx
;
673 swsqe
->signaled
= (wr
->send_flags
& IB_SEND_SIGNALED
);
674 swsqe
->wr_id
= wr
->wr_id
;
676 init_wr_hdr(wqe
, qhp
->wq
.sq
.pidx
, fw_opcode
, fw_flags
, len16
);
678 PDBG("%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u\n",
679 __func__
, (unsigned long long)wr
->wr_id
, qhp
->wq
.sq
.pidx
,
680 swsqe
->opcode
, swsqe
->read_len
);
683 t4_sq_produce(&qhp
->wq
, len16
);
684 idx
+= DIV_ROUND_UP(len16
*16, T4_EQ_ENTRY_SIZE
);
686 if (t4_wq_db_enabled(&qhp
->wq
))
687 t4_ring_sq_db(&qhp
->wq
, idx
);
688 spin_unlock_irqrestore(&qhp
->lock
, flag
);
692 int c4iw_post_receive(struct ib_qp
*ibqp
, struct ib_recv_wr
*wr
,
693 struct ib_recv_wr
**bad_wr
)
697 union t4_recv_wr
*wqe
;
703 qhp
= to_c4iw_qp(ibqp
);
704 spin_lock_irqsave(&qhp
->lock
, flag
);
705 if (t4_wq_in_error(&qhp
->wq
)) {
706 spin_unlock_irqrestore(&qhp
->lock
, flag
);
709 num_wrs
= t4_rq_avail(&qhp
->wq
);
711 spin_unlock_irqrestore(&qhp
->lock
, flag
);
715 if (wr
->num_sge
> T4_MAX_RECV_SGE
) {
720 wqe
= (union t4_recv_wr
*)((u8
*)qhp
->wq
.rq
.queue
+
724 err
= build_rdma_recv(qhp
, wqe
, wr
, &len16
);
732 qhp
->wq
.rq
.sw_rq
[qhp
->wq
.rq
.pidx
].wr_id
= wr
->wr_id
;
734 wqe
->recv
.opcode
= FW_RI_RECV_WR
;
736 wqe
->recv
.wrid
= qhp
->wq
.rq
.pidx
;
740 wqe
->recv
.len16
= len16
;
741 PDBG("%s cookie 0x%llx pidx %u\n", __func__
,
742 (unsigned long long) wr
->wr_id
, qhp
->wq
.rq
.pidx
);
743 t4_rq_produce(&qhp
->wq
, len16
);
744 idx
+= DIV_ROUND_UP(len16
*16, T4_EQ_ENTRY_SIZE
);
748 if (t4_wq_db_enabled(&qhp
->wq
))
749 t4_ring_rq_db(&qhp
->wq
, idx
);
750 spin_unlock_irqrestore(&qhp
->lock
, flag
);
754 int c4iw_bind_mw(struct ib_qp
*qp
, struct ib_mw
*mw
, struct ib_mw_bind
*mw_bind
)
759 static inline void build_term_codes(struct t4_cqe
*err_cqe
, u8
*layer_type
,
769 *layer_type
= LAYER_RDMAP
|DDP_LOCAL_CATA
;
774 status
= CQE_STATUS(err_cqe
);
775 opcode
= CQE_OPCODE(err_cqe
);
776 rqtype
= RQ_TYPE(err_cqe
);
777 send_inv
= (opcode
== FW_RI_SEND_WITH_INV
) ||
778 (opcode
== FW_RI_SEND_WITH_SE_INV
);
779 tagged
= (opcode
== FW_RI_RDMA_WRITE
) ||
780 (rqtype
&& (opcode
== FW_RI_READ_RESP
));
785 *layer_type
= LAYER_RDMAP
|RDMAP_REMOTE_OP
;
786 *ecode
= RDMAP_CANT_INV_STAG
;
788 *layer_type
= LAYER_RDMAP
|RDMAP_REMOTE_PROT
;
789 *ecode
= RDMAP_INV_STAG
;
793 *layer_type
= LAYER_RDMAP
|RDMAP_REMOTE_PROT
;
794 if ((opcode
== FW_RI_SEND_WITH_INV
) ||
795 (opcode
== FW_RI_SEND_WITH_SE_INV
))
796 *ecode
= RDMAP_CANT_INV_STAG
;
798 *ecode
= RDMAP_STAG_NOT_ASSOC
;
801 *layer_type
= LAYER_RDMAP
|RDMAP_REMOTE_PROT
;
802 *ecode
= RDMAP_STAG_NOT_ASSOC
;
805 *layer_type
= LAYER_RDMAP
|RDMAP_REMOTE_PROT
;
806 *ecode
= RDMAP_ACC_VIOL
;
809 *layer_type
= LAYER_RDMAP
|RDMAP_REMOTE_PROT
;
810 *ecode
= RDMAP_TO_WRAP
;
814 *layer_type
= LAYER_DDP
|DDP_TAGGED_ERR
;
815 *ecode
= DDPT_BASE_BOUNDS
;
817 *layer_type
= LAYER_RDMAP
|RDMAP_REMOTE_PROT
;
818 *ecode
= RDMAP_BASE_BOUNDS
;
821 case T4_ERR_INVALIDATE_SHARED_MR
:
822 case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND
:
823 *layer_type
= LAYER_RDMAP
|RDMAP_REMOTE_OP
;
824 *ecode
= RDMAP_CANT_INV_STAG
;
827 case T4_ERR_ECC_PSTAG
:
828 case T4_ERR_INTERNAL_ERR
:
829 *layer_type
= LAYER_RDMAP
|RDMAP_LOCAL_CATA
;
832 case T4_ERR_OUT_OF_RQE
:
833 *layer_type
= LAYER_DDP
|DDP_UNTAGGED_ERR
;
834 *ecode
= DDPU_INV_MSN_NOBUF
;
836 case T4_ERR_PBL_ADDR_BOUND
:
837 *layer_type
= LAYER_DDP
|DDP_TAGGED_ERR
;
838 *ecode
= DDPT_BASE_BOUNDS
;
841 *layer_type
= LAYER_MPA
|DDP_LLP
;
842 *ecode
= MPA_CRC_ERR
;
845 *layer_type
= LAYER_MPA
|DDP_LLP
;
846 *ecode
= MPA_MARKER_ERR
;
848 case T4_ERR_PDU_LEN_ERR
:
849 *layer_type
= LAYER_DDP
|DDP_UNTAGGED_ERR
;
850 *ecode
= DDPU_MSG_TOOBIG
;
852 case T4_ERR_DDP_VERSION
:
854 *layer_type
= LAYER_DDP
|DDP_TAGGED_ERR
;
855 *ecode
= DDPT_INV_VERS
;
857 *layer_type
= LAYER_DDP
|DDP_UNTAGGED_ERR
;
858 *ecode
= DDPU_INV_VERS
;
861 case T4_ERR_RDMA_VERSION
:
862 *layer_type
= LAYER_RDMAP
|RDMAP_REMOTE_OP
;
863 *ecode
= RDMAP_INV_VERS
;
866 *layer_type
= LAYER_RDMAP
|RDMAP_REMOTE_OP
;
867 *ecode
= RDMAP_INV_OPCODE
;
869 case T4_ERR_DDP_QUEUE_NUM
:
870 *layer_type
= LAYER_DDP
|DDP_UNTAGGED_ERR
;
871 *ecode
= DDPU_INV_QN
;
875 case T4_ERR_MSN_RANGE
:
876 case T4_ERR_IRD_OVERFLOW
:
877 *layer_type
= LAYER_DDP
|DDP_UNTAGGED_ERR
;
878 *ecode
= DDPU_INV_MSN_RANGE
;
881 *layer_type
= LAYER_DDP
|DDP_LOCAL_CATA
;
885 *layer_type
= LAYER_DDP
|DDP_UNTAGGED_ERR
;
886 *ecode
= DDPU_INV_MO
;
889 *layer_type
= LAYER_RDMAP
|DDP_LOCAL_CATA
;
895 int c4iw_post_zb_read(struct c4iw_qp
*qhp
)
901 PDBG("%s enter\n", __func__
);
902 skb
= alloc_skb(40, GFP_KERNEL
);
904 printk(KERN_ERR
"%s cannot send zb_read!!\n", __func__
);
907 set_wr_txq(skb
, CPL_PRIORITY_DATA
, qhp
->ep
->txq_idx
);
909 wqe
= (union t4_wr
*)skb_put(skb
, sizeof wqe
->read
);
910 memset(wqe
, 0, sizeof wqe
->read
);
911 wqe
->read
.r2
= cpu_to_be64(0);
912 wqe
->read
.stag_sink
= cpu_to_be32(1);
913 wqe
->read
.to_sink_hi
= cpu_to_be32(0);
914 wqe
->read
.to_sink_lo
= cpu_to_be32(1);
915 wqe
->read
.stag_src
= cpu_to_be32(1);
916 wqe
->read
.plen
= cpu_to_be32(0);
917 wqe
->read
.to_src_hi
= cpu_to_be32(0);
918 wqe
->read
.to_src_lo
= cpu_to_be32(1);
919 len16
= DIV_ROUND_UP(sizeof wqe
->read
, 16);
920 init_wr_hdr(wqe
, 0, FW_RI_RDMA_READ_WR
, FW_RI_COMPLETION_FLAG
, len16
);
922 return c4iw_ofld_send(&qhp
->rhp
->rdev
, skb
);
925 static void post_terminate(struct c4iw_qp
*qhp
, struct t4_cqe
*err_cqe
,
928 struct fw_ri_wr
*wqe
;
930 struct terminate_message
*term
;
932 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__
, qhp
, qhp
->wq
.sq
.qid
,
935 skb
= alloc_skb(sizeof *wqe
, gfp
);
938 set_wr_txq(skb
, CPL_PRIORITY_DATA
, qhp
->ep
->txq_idx
);
940 wqe
= (struct fw_ri_wr
*)__skb_put(skb
, sizeof(*wqe
));
941 memset(wqe
, 0, sizeof *wqe
);
942 wqe
->op_compl
= cpu_to_be32(FW_WR_OP(FW_RI_INIT_WR
));
943 wqe
->flowid_len16
= cpu_to_be32(
944 FW_WR_FLOWID(qhp
->ep
->hwtid
) |
945 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe
, 16)));
947 wqe
->u
.terminate
.type
= FW_RI_TYPE_TERMINATE
;
948 wqe
->u
.terminate
.immdlen
= cpu_to_be32(sizeof *term
);
949 term
= (struct terminate_message
*)wqe
->u
.terminate
.termmsg
;
950 build_term_codes(err_cqe
, &term
->layer_etype
, &term
->ecode
);
951 c4iw_ofld_send(&qhp
->rhp
->rdev
, skb
);
955 * Assumes qhp lock is held.
957 static void __flush_qp(struct c4iw_qp
*qhp
, struct c4iw_cq
*rchp
,
958 struct c4iw_cq
*schp
)
964 PDBG("%s qhp %p rchp %p schp %p\n", __func__
, qhp
, rchp
, schp
);
966 /* locking hierarchy: cq lock first, then qp lock. */
967 spin_lock_irqsave(&rchp
->lock
, flag
);
968 spin_lock(&qhp
->lock
);
969 c4iw_flush_hw_cq(&rchp
->cq
);
970 c4iw_count_rcqes(&rchp
->cq
, &qhp
->wq
, &count
);
971 flushed
= c4iw_flush_rq(&qhp
->wq
, &rchp
->cq
, count
);
972 spin_unlock(&qhp
->lock
);
973 spin_unlock_irqrestore(&rchp
->lock
, flag
);
975 (*rchp
->ibcq
.comp_handler
)(&rchp
->ibcq
, rchp
->ibcq
.cq_context
);
977 /* locking hierarchy: cq lock first, then qp lock. */
978 spin_lock_irqsave(&schp
->lock
, flag
);
979 spin_lock(&qhp
->lock
);
980 c4iw_flush_hw_cq(&schp
->cq
);
981 c4iw_count_scqes(&schp
->cq
, &qhp
->wq
, &count
);
982 flushed
= c4iw_flush_sq(&qhp
->wq
, &schp
->cq
, count
);
983 spin_unlock(&qhp
->lock
);
984 spin_unlock_irqrestore(&schp
->lock
, flag
);
986 (*schp
->ibcq
.comp_handler
)(&schp
->ibcq
, schp
->ibcq
.cq_context
);
989 static void flush_qp(struct c4iw_qp
*qhp
)
991 struct c4iw_cq
*rchp
, *schp
;
993 rchp
= get_chp(qhp
->rhp
, qhp
->attr
.rcq
);
994 schp
= get_chp(qhp
->rhp
, qhp
->attr
.scq
);
996 if (qhp
->ibqp
.uobject
) {
997 t4_set_wq_in_error(&qhp
->wq
);
998 t4_set_cq_in_error(&rchp
->cq
);
1000 t4_set_cq_in_error(&schp
->cq
);
1003 __flush_qp(qhp
, rchp
, schp
);
1006 static int rdma_fini(struct c4iw_dev
*rhp
, struct c4iw_qp
*qhp
,
1009 struct fw_ri_wr
*wqe
;
1011 struct sk_buff
*skb
;
1013 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__
, qhp
, qhp
->wq
.sq
.qid
,
1016 skb
= alloc_skb(sizeof *wqe
, GFP_KERNEL
);
1019 set_wr_txq(skb
, CPL_PRIORITY_DATA
, ep
->txq_idx
);
1021 wqe
= (struct fw_ri_wr
*)__skb_put(skb
, sizeof(*wqe
));
1022 memset(wqe
, 0, sizeof *wqe
);
1023 wqe
->op_compl
= cpu_to_be32(
1024 FW_WR_OP(FW_RI_INIT_WR
) |
1026 wqe
->flowid_len16
= cpu_to_be32(
1027 FW_WR_FLOWID(ep
->hwtid
) |
1028 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe
, 16)));
1029 wqe
->cookie
= (unsigned long) &ep
->com
.wr_wait
;
1031 wqe
->u
.fini
.type
= FW_RI_TYPE_FINI
;
1032 c4iw_init_wr_wait(&ep
->com
.wr_wait
);
1033 ret
= c4iw_ofld_send(&rhp
->rdev
, skb
);
1037 ret
= c4iw_wait_for_reply(&rhp
->rdev
, &ep
->com
.wr_wait
, qhp
->ep
->hwtid
,
1038 qhp
->wq
.sq
.qid
, __func__
);
1040 PDBG("%s ret %d\n", __func__
, ret
);
1044 static void build_rtr_msg(u8 p2p_type
, struct fw_ri_init
*init
)
1046 memset(&init
->u
, 0, sizeof init
->u
);
1048 case FW_RI_INIT_P2PTYPE_RDMA_WRITE
:
1049 init
->u
.write
.opcode
= FW_RI_RDMA_WRITE_WR
;
1050 init
->u
.write
.stag_sink
= cpu_to_be32(1);
1051 init
->u
.write
.to_sink
= cpu_to_be64(1);
1052 init
->u
.write
.u
.immd_src
[0].op
= FW_RI_DATA_IMMD
;
1053 init
->u
.write
.len16
= DIV_ROUND_UP(sizeof init
->u
.write
+
1054 sizeof(struct fw_ri_immd
),
1057 case FW_RI_INIT_P2PTYPE_READ_REQ
:
1058 init
->u
.write
.opcode
= FW_RI_RDMA_READ_WR
;
1059 init
->u
.read
.stag_src
= cpu_to_be32(1);
1060 init
->u
.read
.to_src_lo
= cpu_to_be32(1);
1061 init
->u
.read
.stag_sink
= cpu_to_be32(1);
1062 init
->u
.read
.to_sink_lo
= cpu_to_be32(1);
1063 init
->u
.read
.len16
= DIV_ROUND_UP(sizeof init
->u
.read
, 16);
1068 static int rdma_init(struct c4iw_dev
*rhp
, struct c4iw_qp
*qhp
)
1070 struct fw_ri_wr
*wqe
;
1072 struct sk_buff
*skb
;
1074 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__
, qhp
, qhp
->wq
.sq
.qid
,
1077 skb
= alloc_skb(sizeof *wqe
, GFP_KERNEL
);
1080 set_wr_txq(skb
, CPL_PRIORITY_DATA
, qhp
->ep
->txq_idx
);
1082 wqe
= (struct fw_ri_wr
*)__skb_put(skb
, sizeof(*wqe
));
1083 memset(wqe
, 0, sizeof *wqe
);
1084 wqe
->op_compl
= cpu_to_be32(
1085 FW_WR_OP(FW_RI_INIT_WR
) |
1087 wqe
->flowid_len16
= cpu_to_be32(
1088 FW_WR_FLOWID(qhp
->ep
->hwtid
) |
1089 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe
, 16)));
1091 wqe
->cookie
= (unsigned long) &qhp
->ep
->com
.wr_wait
;
1093 wqe
->u
.init
.type
= FW_RI_TYPE_INIT
;
1094 wqe
->u
.init
.mpareqbit_p2ptype
=
1095 V_FW_RI_WR_MPAREQBIT(qhp
->attr
.mpa_attr
.initiator
) |
1096 V_FW_RI_WR_P2PTYPE(qhp
->attr
.mpa_attr
.p2p_type
);
1097 wqe
->u
.init
.mpa_attrs
= FW_RI_MPA_IETF_ENABLE
;
1098 if (qhp
->attr
.mpa_attr
.recv_marker_enabled
)
1099 wqe
->u
.init
.mpa_attrs
|= FW_RI_MPA_RX_MARKER_ENABLE
;
1100 if (qhp
->attr
.mpa_attr
.xmit_marker_enabled
)
1101 wqe
->u
.init
.mpa_attrs
|= FW_RI_MPA_TX_MARKER_ENABLE
;
1102 if (qhp
->attr
.mpa_attr
.crc_enabled
)
1103 wqe
->u
.init
.mpa_attrs
|= FW_RI_MPA_CRC_ENABLE
;
1105 wqe
->u
.init
.qp_caps
= FW_RI_QP_RDMA_READ_ENABLE
|
1106 FW_RI_QP_RDMA_WRITE_ENABLE
|
1107 FW_RI_QP_BIND_ENABLE
;
1108 if (!qhp
->ibqp
.uobject
)
1109 wqe
->u
.init
.qp_caps
|= FW_RI_QP_FAST_REGISTER_ENABLE
|
1110 FW_RI_QP_STAG0_ENABLE
;
1111 wqe
->u
.init
.nrqe
= cpu_to_be16(t4_rqes_posted(&qhp
->wq
));
1112 wqe
->u
.init
.pdid
= cpu_to_be32(qhp
->attr
.pd
);
1113 wqe
->u
.init
.qpid
= cpu_to_be32(qhp
->wq
.sq
.qid
);
1114 wqe
->u
.init
.sq_eqid
= cpu_to_be32(qhp
->wq
.sq
.qid
);
1115 wqe
->u
.init
.rq_eqid
= cpu_to_be32(qhp
->wq
.rq
.qid
);
1116 wqe
->u
.init
.scqid
= cpu_to_be32(qhp
->attr
.scq
);
1117 wqe
->u
.init
.rcqid
= cpu_to_be32(qhp
->attr
.rcq
);
1118 wqe
->u
.init
.ord_max
= cpu_to_be32(qhp
->attr
.max_ord
);
1119 wqe
->u
.init
.ird_max
= cpu_to_be32(qhp
->attr
.max_ird
);
1120 wqe
->u
.init
.iss
= cpu_to_be32(qhp
->ep
->snd_seq
);
1121 wqe
->u
.init
.irs
= cpu_to_be32(qhp
->ep
->rcv_seq
);
1122 wqe
->u
.init
.hwrqsize
= cpu_to_be32(qhp
->wq
.rq
.rqt_size
);
1123 wqe
->u
.init
.hwrqaddr
= cpu_to_be32(qhp
->wq
.rq
.rqt_hwaddr
-
1124 rhp
->rdev
.lldi
.vr
->rq
.start
);
1125 if (qhp
->attr
.mpa_attr
.initiator
)
1126 build_rtr_msg(qhp
->attr
.mpa_attr
.p2p_type
, &wqe
->u
.init
);
1128 c4iw_init_wr_wait(&qhp
->ep
->com
.wr_wait
);
1129 ret
= c4iw_ofld_send(&rhp
->rdev
, skb
);
1133 ret
= c4iw_wait_for_reply(&rhp
->rdev
, &qhp
->ep
->com
.wr_wait
,
1134 qhp
->ep
->hwtid
, qhp
->wq
.sq
.qid
, __func__
);
1136 PDBG("%s ret %d\n", __func__
, ret
);
1140 int c4iw_modify_qp(struct c4iw_dev
*rhp
, struct c4iw_qp
*qhp
,
1141 enum c4iw_qp_attr_mask mask
,
1142 struct c4iw_qp_attributes
*attrs
,
1146 struct c4iw_qp_attributes newattr
= qhp
->attr
;
1151 struct c4iw_ep
*ep
= NULL
;
1153 PDBG("%s qhp %p sqid 0x%x rqid 0x%x ep %p state %d -> %d\n", __func__
,
1154 qhp
, qhp
->wq
.sq
.qid
, qhp
->wq
.rq
.qid
, qhp
->ep
, qhp
->attr
.state
,
1155 (mask
& C4IW_QP_ATTR_NEXT_STATE
) ? attrs
->next_state
: -1);
1157 mutex_lock(&qhp
->mutex
);
1159 /* Process attr changes if in IDLE */
1160 if (mask
& C4IW_QP_ATTR_VALID_MODIFY
) {
1161 if (qhp
->attr
.state
!= C4IW_QP_STATE_IDLE
) {
1165 if (mask
& C4IW_QP_ATTR_ENABLE_RDMA_READ
)
1166 newattr
.enable_rdma_read
= attrs
->enable_rdma_read
;
1167 if (mask
& C4IW_QP_ATTR_ENABLE_RDMA_WRITE
)
1168 newattr
.enable_rdma_write
= attrs
->enable_rdma_write
;
1169 if (mask
& C4IW_QP_ATTR_ENABLE_RDMA_BIND
)
1170 newattr
.enable_bind
= attrs
->enable_bind
;
1171 if (mask
& C4IW_QP_ATTR_MAX_ORD
) {
1172 if (attrs
->max_ord
> c4iw_max_read_depth
) {
1176 newattr
.max_ord
= attrs
->max_ord
;
1178 if (mask
& C4IW_QP_ATTR_MAX_IRD
) {
1179 if (attrs
->max_ird
> c4iw_max_read_depth
) {
1183 newattr
.max_ird
= attrs
->max_ird
;
1185 qhp
->attr
= newattr
;
1188 if (!(mask
& C4IW_QP_ATTR_NEXT_STATE
))
1190 if (qhp
->attr
.state
== attrs
->next_state
)
1193 switch (qhp
->attr
.state
) {
1194 case C4IW_QP_STATE_IDLE
:
1195 switch (attrs
->next_state
) {
1196 case C4IW_QP_STATE_RTS
:
1197 if (!(mask
& C4IW_QP_ATTR_LLP_STREAM_HANDLE
)) {
1201 if (!(mask
& C4IW_QP_ATTR_MPA_ATTR
)) {
1205 qhp
->attr
.mpa_attr
= attrs
->mpa_attr
;
1206 qhp
->attr
.llp_stream_handle
= attrs
->llp_stream_handle
;
1207 qhp
->ep
= qhp
->attr
.llp_stream_handle
;
1208 set_state(qhp
, C4IW_QP_STATE_RTS
);
1211 * Ref the endpoint here and deref when we
1212 * disassociate the endpoint from the QP. This
1213 * happens in CLOSING->IDLE transition or *->ERROR
1216 c4iw_get_ep(&qhp
->ep
->com
);
1217 ret
= rdma_init(rhp
, qhp
);
1221 case C4IW_QP_STATE_ERROR
:
1222 set_state(qhp
, C4IW_QP_STATE_ERROR
);
1230 case C4IW_QP_STATE_RTS
:
1231 switch (attrs
->next_state
) {
1232 case C4IW_QP_STATE_CLOSING
:
1233 BUG_ON(atomic_read(&qhp
->ep
->com
.kref
.refcount
) < 2);
1234 set_state(qhp
, C4IW_QP_STATE_CLOSING
);
1239 c4iw_get_ep(&qhp
->ep
->com
);
1241 ret
= rdma_fini(rhp
, qhp
, ep
);
1244 c4iw_get_ep(&qhp
->ep
->com
);
1245 disconnect
= abort
= 1;
1249 case C4IW_QP_STATE_TERMINATE
:
1250 set_state(qhp
, C4IW_QP_STATE_TERMINATE
);
1251 if (qhp
->ibqp
.uobject
)
1252 t4_set_wq_in_error(&qhp
->wq
);
1257 c4iw_get_ep(&qhp
->ep
->com
);
1259 case C4IW_QP_STATE_ERROR
:
1260 set_state(qhp
, C4IW_QP_STATE_ERROR
);
1265 c4iw_get_ep(&qhp
->ep
->com
);
1274 case C4IW_QP_STATE_CLOSING
:
1279 switch (attrs
->next_state
) {
1280 case C4IW_QP_STATE_IDLE
:
1282 set_state(qhp
, C4IW_QP_STATE_IDLE
);
1283 qhp
->attr
.llp_stream_handle
= NULL
;
1284 c4iw_put_ep(&qhp
->ep
->com
);
1286 wake_up(&qhp
->wait
);
1288 case C4IW_QP_STATE_ERROR
:
1295 case C4IW_QP_STATE_ERROR
:
1296 if (attrs
->next_state
!= C4IW_QP_STATE_IDLE
) {
1300 if (!t4_sq_empty(&qhp
->wq
) || !t4_rq_empty(&qhp
->wq
)) {
1304 set_state(qhp
, C4IW_QP_STATE_IDLE
);
1306 case C4IW_QP_STATE_TERMINATE
:
1314 printk(KERN_ERR
"%s in a bad state %d\n",
1315 __func__
, qhp
->attr
.state
);
1322 PDBG("%s disassociating ep %p qpid 0x%x\n", __func__
, qhp
->ep
,
1325 /* disassociate the LLP connection */
1326 qhp
->attr
.llp_stream_handle
= NULL
;
1330 set_state(qhp
, C4IW_QP_STATE_ERROR
);
1332 wake_up(&qhp
->wait
);
1336 mutex_unlock(&qhp
->mutex
);
1339 post_terminate(qhp
, NULL
, internal
? GFP_ATOMIC
: GFP_KERNEL
);
1342 * If disconnect is 1, then we need to initiate a disconnect
1343 * on the EP. This can be a normal close (RTS->CLOSING) or
1344 * an abnormal close (RTS/CLOSING->ERROR).
1347 c4iw_ep_disconnect(ep
, abort
, internal
? GFP_ATOMIC
:
1349 c4iw_put_ep(&ep
->com
);
1353 * If free is 1, then we've disassociated the EP from the QP
1354 * and we need to dereference the EP.
1357 c4iw_put_ep(&ep
->com
);
1358 PDBG("%s exit state %d\n", __func__
, qhp
->attr
.state
);
1362 int c4iw_destroy_qp(struct ib_qp
*ib_qp
)
1364 struct c4iw_dev
*rhp
;
1365 struct c4iw_qp
*qhp
;
1366 struct c4iw_qp_attributes attrs
;
1367 struct c4iw_ucontext
*ucontext
;
1369 qhp
= to_c4iw_qp(ib_qp
);
1372 attrs
.next_state
= C4IW_QP_STATE_ERROR
;
1373 c4iw_modify_qp(rhp
, qhp
, C4IW_QP_ATTR_NEXT_STATE
, &attrs
, 0);
1374 wait_event(qhp
->wait
, !qhp
->ep
);
1376 remove_handle(rhp
, &rhp
->qpidr
, qhp
->wq
.sq
.qid
);
1377 atomic_dec(&qhp
->refcnt
);
1378 wait_event(qhp
->wait
, !atomic_read(&qhp
->refcnt
));
1380 ucontext
= ib_qp
->uobject
?
1381 to_c4iw_ucontext(ib_qp
->uobject
->context
) : NULL
;
1382 destroy_qp(&rhp
->rdev
, &qhp
->wq
,
1383 ucontext
? &ucontext
->uctx
: &rhp
->rdev
.uctx
);
1385 PDBG("%s ib_qp %p qpid 0x%0x\n", __func__
, ib_qp
, qhp
->wq
.sq
.qid
);
1390 struct ib_qp
*c4iw_create_qp(struct ib_pd
*pd
, struct ib_qp_init_attr
*attrs
,
1391 struct ib_udata
*udata
)
1393 struct c4iw_dev
*rhp
;
1394 struct c4iw_qp
*qhp
;
1395 struct c4iw_pd
*php
;
1396 struct c4iw_cq
*schp
;
1397 struct c4iw_cq
*rchp
;
1398 struct c4iw_create_qp_resp uresp
;
1400 struct c4iw_ucontext
*ucontext
;
1402 struct c4iw_mm_entry
*mm1
, *mm2
, *mm3
, *mm4
, *mm5
= NULL
;
1404 PDBG("%s ib_pd %p\n", __func__
, pd
);
1406 if (attrs
->qp_type
!= IB_QPT_RC
)
1407 return ERR_PTR(-EINVAL
);
1409 php
= to_c4iw_pd(pd
);
1411 schp
= get_chp(rhp
, ((struct c4iw_cq
*)attrs
->send_cq
)->cq
.cqid
);
1412 rchp
= get_chp(rhp
, ((struct c4iw_cq
*)attrs
->recv_cq
)->cq
.cqid
);
1414 return ERR_PTR(-EINVAL
);
1416 if (attrs
->cap
.max_inline_data
> T4_MAX_SEND_INLINE
)
1417 return ERR_PTR(-EINVAL
);
1419 rqsize
= roundup(attrs
->cap
.max_recv_wr
+ 1, 16);
1420 if (rqsize
> T4_MAX_RQ_SIZE
)
1421 return ERR_PTR(-E2BIG
);
1423 sqsize
= roundup(attrs
->cap
.max_send_wr
+ 1, 16);
1424 if (sqsize
> T4_MAX_SQ_SIZE
)
1425 return ERR_PTR(-E2BIG
);
1427 ucontext
= pd
->uobject
? to_c4iw_ucontext(pd
->uobject
->context
) : NULL
;
1430 qhp
= kzalloc(sizeof(*qhp
), GFP_KERNEL
);
1432 return ERR_PTR(-ENOMEM
);
1433 qhp
->wq
.sq
.size
= sqsize
;
1434 qhp
->wq
.sq
.memsize
= (sqsize
+ 1) * sizeof *qhp
->wq
.sq
.queue
;
1435 qhp
->wq
.rq
.size
= rqsize
;
1436 qhp
->wq
.rq
.memsize
= (rqsize
+ 1) * sizeof *qhp
->wq
.rq
.queue
;
1439 qhp
->wq
.sq
.memsize
= roundup(qhp
->wq
.sq
.memsize
, PAGE_SIZE
);
1440 qhp
->wq
.rq
.memsize
= roundup(qhp
->wq
.rq
.memsize
, PAGE_SIZE
);
1443 PDBG("%s sqsize %u sqmemsize %zu rqsize %u rqmemsize %zu\n",
1444 __func__
, sqsize
, qhp
->wq
.sq
.memsize
, rqsize
, qhp
->wq
.rq
.memsize
);
1446 ret
= create_qp(&rhp
->rdev
, &qhp
->wq
, &schp
->cq
, &rchp
->cq
,
1447 ucontext
? &ucontext
->uctx
: &rhp
->rdev
.uctx
);
1451 attrs
->cap
.max_recv_wr
= rqsize
- 1;
1452 attrs
->cap
.max_send_wr
= sqsize
- 1;
1453 attrs
->cap
.max_inline_data
= T4_MAX_SEND_INLINE
;
1456 qhp
->attr
.pd
= php
->pdid
;
1457 qhp
->attr
.scq
= ((struct c4iw_cq
*) attrs
->send_cq
)->cq
.cqid
;
1458 qhp
->attr
.rcq
= ((struct c4iw_cq
*) attrs
->recv_cq
)->cq
.cqid
;
1459 qhp
->attr
.sq_num_entries
= attrs
->cap
.max_send_wr
;
1460 qhp
->attr
.rq_num_entries
= attrs
->cap
.max_recv_wr
;
1461 qhp
->attr
.sq_max_sges
= attrs
->cap
.max_send_sge
;
1462 qhp
->attr
.sq_max_sges_rdma_write
= attrs
->cap
.max_send_sge
;
1463 qhp
->attr
.rq_max_sges
= attrs
->cap
.max_recv_sge
;
1464 qhp
->attr
.state
= C4IW_QP_STATE_IDLE
;
1465 qhp
->attr
.next_state
= C4IW_QP_STATE_IDLE
;
1466 qhp
->attr
.enable_rdma_read
= 1;
1467 qhp
->attr
.enable_rdma_write
= 1;
1468 qhp
->attr
.enable_bind
= 1;
1469 qhp
->attr
.max_ord
= 1;
1470 qhp
->attr
.max_ird
= 1;
1471 spin_lock_init(&qhp
->lock
);
1472 mutex_init(&qhp
->mutex
);
1473 init_waitqueue_head(&qhp
->wait
);
1474 atomic_set(&qhp
->refcnt
, 1);
1476 ret
= insert_handle(rhp
, &rhp
->qpidr
, qhp
, qhp
->wq
.sq
.qid
);
1481 mm1
= kmalloc(sizeof *mm1
, GFP_KERNEL
);
1486 mm2
= kmalloc(sizeof *mm2
, GFP_KERNEL
);
1491 mm3
= kmalloc(sizeof *mm3
, GFP_KERNEL
);
1496 mm4
= kmalloc(sizeof *mm4
, GFP_KERNEL
);
1501 if (t4_sq_onchip(&qhp
->wq
.sq
)) {
1502 mm5
= kmalloc(sizeof *mm5
, GFP_KERNEL
);
1507 uresp
.flags
= C4IW_QPF_ONCHIP
;
1510 uresp
.qid_mask
= rhp
->rdev
.qpmask
;
1511 uresp
.sqid
= qhp
->wq
.sq
.qid
;
1512 uresp
.sq_size
= qhp
->wq
.sq
.size
;
1513 uresp
.sq_memsize
= qhp
->wq
.sq
.memsize
;
1514 uresp
.rqid
= qhp
->wq
.rq
.qid
;
1515 uresp
.rq_size
= qhp
->wq
.rq
.size
;
1516 uresp
.rq_memsize
= qhp
->wq
.rq
.memsize
;
1517 spin_lock(&ucontext
->mmap_lock
);
1519 uresp
.ma_sync_key
= ucontext
->key
;
1520 ucontext
->key
+= PAGE_SIZE
;
1522 uresp
.sq_key
= ucontext
->key
;
1523 ucontext
->key
+= PAGE_SIZE
;
1524 uresp
.rq_key
= ucontext
->key
;
1525 ucontext
->key
+= PAGE_SIZE
;
1526 uresp
.sq_db_gts_key
= ucontext
->key
;
1527 ucontext
->key
+= PAGE_SIZE
;
1528 uresp
.rq_db_gts_key
= ucontext
->key
;
1529 ucontext
->key
+= PAGE_SIZE
;
1530 spin_unlock(&ucontext
->mmap_lock
);
1531 ret
= ib_copy_to_udata(udata
, &uresp
, sizeof uresp
);
1534 mm1
->key
= uresp
.sq_key
;
1535 mm1
->addr
= qhp
->wq
.sq
.phys_addr
;
1536 mm1
->len
= PAGE_ALIGN(qhp
->wq
.sq
.memsize
);
1537 insert_mmap(ucontext
, mm1
);
1538 mm2
->key
= uresp
.rq_key
;
1539 mm2
->addr
= virt_to_phys(qhp
->wq
.rq
.queue
);
1540 mm2
->len
= PAGE_ALIGN(qhp
->wq
.rq
.memsize
);
1541 insert_mmap(ucontext
, mm2
);
1542 mm3
->key
= uresp
.sq_db_gts_key
;
1543 mm3
->addr
= qhp
->wq
.sq
.udb
;
1544 mm3
->len
= PAGE_SIZE
;
1545 insert_mmap(ucontext
, mm3
);
1546 mm4
->key
= uresp
.rq_db_gts_key
;
1547 mm4
->addr
= qhp
->wq
.rq
.udb
;
1548 mm4
->len
= PAGE_SIZE
;
1549 insert_mmap(ucontext
, mm4
);
1551 mm5
->key
= uresp
.ma_sync_key
;
1552 mm5
->addr
= (pci_resource_start(rhp
->rdev
.lldi
.pdev
, 0)
1553 + A_PCIE_MA_SYNC
) & PAGE_MASK
;
1554 mm5
->len
= PAGE_SIZE
;
1555 insert_mmap(ucontext
, mm5
);
1558 qhp
->ibqp
.qp_num
= qhp
->wq
.sq
.qid
;
1559 init_timer(&(qhp
->timer
));
1560 PDBG("%s qhp %p sq_num_entries %d, rq_num_entries %d qpid 0x%0x\n",
1561 __func__
, qhp
, qhp
->attr
.sq_num_entries
, qhp
->attr
.rq_num_entries
,
1575 remove_handle(rhp
, &rhp
->qpidr
, qhp
->wq
.sq
.qid
);
1577 destroy_qp(&rhp
->rdev
, &qhp
->wq
,
1578 ucontext
? &ucontext
->uctx
: &rhp
->rdev
.uctx
);
1581 return ERR_PTR(ret
);
1584 int c4iw_ib_modify_qp(struct ib_qp
*ibqp
, struct ib_qp_attr
*attr
,
1585 int attr_mask
, struct ib_udata
*udata
)
1587 struct c4iw_dev
*rhp
;
1588 struct c4iw_qp
*qhp
;
1589 enum c4iw_qp_attr_mask mask
= 0;
1590 struct c4iw_qp_attributes attrs
;
1592 PDBG("%s ib_qp %p\n", __func__
, ibqp
);
1594 /* iwarp does not support the RTR state */
1595 if ((attr_mask
& IB_QP_STATE
) && (attr
->qp_state
== IB_QPS_RTR
))
1596 attr_mask
&= ~IB_QP_STATE
;
1598 /* Make sure we still have something left to do */
1602 memset(&attrs
, 0, sizeof attrs
);
1603 qhp
= to_c4iw_qp(ibqp
);
1606 attrs
.next_state
= c4iw_convert_state(attr
->qp_state
);
1607 attrs
.enable_rdma_read
= (attr
->qp_access_flags
&
1608 IB_ACCESS_REMOTE_READ
) ? 1 : 0;
1609 attrs
.enable_rdma_write
= (attr
->qp_access_flags
&
1610 IB_ACCESS_REMOTE_WRITE
) ? 1 : 0;
1611 attrs
.enable_bind
= (attr
->qp_access_flags
& IB_ACCESS_MW_BIND
) ? 1 : 0;
1614 mask
|= (attr_mask
& IB_QP_STATE
) ? C4IW_QP_ATTR_NEXT_STATE
: 0;
1615 mask
|= (attr_mask
& IB_QP_ACCESS_FLAGS
) ?
1616 (C4IW_QP_ATTR_ENABLE_RDMA_READ
|
1617 C4IW_QP_ATTR_ENABLE_RDMA_WRITE
|
1618 C4IW_QP_ATTR_ENABLE_RDMA_BIND
) : 0;
1620 return c4iw_modify_qp(rhp
, qhp
, mask
, &attrs
, 0);
1623 struct ib_qp
*c4iw_get_qp(struct ib_device
*dev
, int qpn
)
1625 PDBG("%s ib_dev %p qpn 0x%x\n", __func__
, dev
, qpn
);
1626 return (struct ib_qp
*)get_qhp(to_c4iw_dev(dev
), qpn
);