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[mirror_ubuntu-artful-kernel.git] / drivers / infiniband / hw / cxgb4 / qp.c
1 /*
2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/module.h>
34
35 #include "iw_cxgb4.h"
36
37 static int db_delay_usecs = 1;
38 module_param(db_delay_usecs, int, 0644);
39 MODULE_PARM_DESC(db_delay_usecs, "Usecs to delay awaiting db fifo to drain");
40
41 static int ocqp_support = 1;
42 module_param(ocqp_support, int, 0644);
43 MODULE_PARM_DESC(ocqp_support, "Support on-chip SQs (default=1)");
44
45 int db_fc_threshold = 1000;
46 module_param(db_fc_threshold, int, 0644);
47 MODULE_PARM_DESC(db_fc_threshold,
48 "QP count/threshold that triggers"
49 " automatic db flow control mode (default = 1000)");
50
51 int db_coalescing_threshold;
52 module_param(db_coalescing_threshold, int, 0644);
53 MODULE_PARM_DESC(db_coalescing_threshold,
54 "QP count/threshold that triggers"
55 " disabling db coalescing (default = 0)");
56
57 static int max_fr_immd = T4_MAX_FR_IMMD;
58 module_param(max_fr_immd, int, 0644);
59 MODULE_PARM_DESC(max_fr_immd, "fastreg threshold for using DSGL instead of immedate");
60
61 static int alloc_ird(struct c4iw_dev *dev, u32 ird)
62 {
63 int ret = 0;
64
65 spin_lock_irq(&dev->lock);
66 if (ird <= dev->avail_ird)
67 dev->avail_ird -= ird;
68 else
69 ret = -ENOMEM;
70 spin_unlock_irq(&dev->lock);
71
72 if (ret)
73 dev_warn(&dev->rdev.lldi.pdev->dev,
74 "device IRD resources exhausted\n");
75
76 return ret;
77 }
78
79 static void free_ird(struct c4iw_dev *dev, int ird)
80 {
81 spin_lock_irq(&dev->lock);
82 dev->avail_ird += ird;
83 spin_unlock_irq(&dev->lock);
84 }
85
86 static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state)
87 {
88 unsigned long flag;
89 spin_lock_irqsave(&qhp->lock, flag);
90 qhp->attr.state = state;
91 spin_unlock_irqrestore(&qhp->lock, flag);
92 }
93
94 static void dealloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
95 {
96 c4iw_ocqp_pool_free(rdev, sq->dma_addr, sq->memsize);
97 }
98
99 static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
100 {
101 dma_free_coherent(&(rdev->lldi.pdev->dev), sq->memsize, sq->queue,
102 pci_unmap_addr(sq, mapping));
103 }
104
105 static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
106 {
107 if (t4_sq_onchip(sq))
108 dealloc_oc_sq(rdev, sq);
109 else
110 dealloc_host_sq(rdev, sq);
111 }
112
113 static int alloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
114 {
115 if (!ocqp_support || !ocqp_supported(&rdev->lldi))
116 return -ENOSYS;
117 sq->dma_addr = c4iw_ocqp_pool_alloc(rdev, sq->memsize);
118 if (!sq->dma_addr)
119 return -ENOMEM;
120 sq->phys_addr = rdev->oc_mw_pa + sq->dma_addr -
121 rdev->lldi.vr->ocq.start;
122 sq->queue = (__force union t4_wr *)(rdev->oc_mw_kva + sq->dma_addr -
123 rdev->lldi.vr->ocq.start);
124 sq->flags |= T4_SQ_ONCHIP;
125 return 0;
126 }
127
128 static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
129 {
130 sq->queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), sq->memsize,
131 &(sq->dma_addr), GFP_KERNEL);
132 if (!sq->queue)
133 return -ENOMEM;
134 sq->phys_addr = virt_to_phys(sq->queue);
135 pci_unmap_addr_set(sq, mapping, sq->dma_addr);
136 return 0;
137 }
138
139 static int alloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq, int user)
140 {
141 int ret = -ENOSYS;
142 if (user)
143 ret = alloc_oc_sq(rdev, sq);
144 if (ret)
145 ret = alloc_host_sq(rdev, sq);
146 return ret;
147 }
148
149 static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
150 struct c4iw_dev_ucontext *uctx)
151 {
152 /*
153 * uP clears EQ contexts when the connection exits rdma mode,
154 * so no need to post a RESET WR for these EQs.
155 */
156 dma_free_coherent(&(rdev->lldi.pdev->dev),
157 wq->rq.memsize, wq->rq.queue,
158 dma_unmap_addr(&wq->rq, mapping));
159 dealloc_sq(rdev, &wq->sq);
160 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
161 kfree(wq->rq.sw_rq);
162 kfree(wq->sq.sw_sq);
163 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
164 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
165 return 0;
166 }
167
168 /*
169 * Determine the BAR2 virtual address and qid. If pbar2_pa is not NULL,
170 * then this is a user mapping so compute the page-aligned physical address
171 * for mapping.
172 */
173 void __iomem *c4iw_bar2_addrs(struct c4iw_rdev *rdev, unsigned int qid,
174 enum cxgb4_bar2_qtype qtype,
175 unsigned int *pbar2_qid, u64 *pbar2_pa)
176 {
177 u64 bar2_qoffset;
178 int ret;
179
180 ret = cxgb4_bar2_sge_qregs(rdev->lldi.ports[0], qid, qtype,
181 pbar2_pa ? 1 : 0,
182 &bar2_qoffset, pbar2_qid);
183 if (ret)
184 return NULL;
185
186 if (pbar2_pa)
187 *pbar2_pa = (rdev->bar2_pa + bar2_qoffset) & PAGE_MASK;
188
189 if (is_t4(rdev->lldi.adapter_type))
190 return NULL;
191
192 return rdev->bar2_kva + bar2_qoffset;
193 }
194
195 static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
196 struct t4_cq *rcq, struct t4_cq *scq,
197 struct c4iw_dev_ucontext *uctx)
198 {
199 int user = (uctx != &rdev->uctx);
200 struct fw_ri_res_wr *res_wr;
201 struct fw_ri_res *res;
202 int wr_len;
203 struct c4iw_wr_wait wr_wait;
204 struct sk_buff *skb;
205 int ret = 0;
206 int eqsize;
207
208 wq->sq.qid = c4iw_get_qpid(rdev, uctx);
209 if (!wq->sq.qid)
210 return -ENOMEM;
211
212 wq->rq.qid = c4iw_get_qpid(rdev, uctx);
213 if (!wq->rq.qid) {
214 ret = -ENOMEM;
215 goto free_sq_qid;
216 }
217
218 if (!user) {
219 wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq,
220 GFP_KERNEL);
221 if (!wq->sq.sw_sq) {
222 ret = -ENOMEM;
223 goto free_rq_qid;
224 }
225
226 wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq,
227 GFP_KERNEL);
228 if (!wq->rq.sw_rq) {
229 ret = -ENOMEM;
230 goto free_sw_sq;
231 }
232 }
233
234 /*
235 * RQT must be a power of 2 and at least 16 deep.
236 */
237 wq->rq.rqt_size = roundup_pow_of_two(max_t(u16, wq->rq.size, 16));
238 wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size);
239 if (!wq->rq.rqt_hwaddr) {
240 ret = -ENOMEM;
241 goto free_sw_rq;
242 }
243
244 ret = alloc_sq(rdev, &wq->sq, user);
245 if (ret)
246 goto free_hwaddr;
247 memset(wq->sq.queue, 0, wq->sq.memsize);
248 dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr);
249
250 wq->rq.queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev),
251 wq->rq.memsize, &(wq->rq.dma_addr),
252 GFP_KERNEL);
253 if (!wq->rq.queue) {
254 ret = -ENOMEM;
255 goto free_sq;
256 }
257 pr_debug("%s sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx\n",
258 __func__, wq->sq.queue,
259 (unsigned long long)virt_to_phys(wq->sq.queue),
260 wq->rq.queue,
261 (unsigned long long)virt_to_phys(wq->rq.queue));
262 memset(wq->rq.queue, 0, wq->rq.memsize);
263 dma_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr);
264
265 wq->db = rdev->lldi.db_reg;
266
267 wq->sq.bar2_va = c4iw_bar2_addrs(rdev, wq->sq.qid, T4_BAR2_QTYPE_EGRESS,
268 &wq->sq.bar2_qid,
269 user ? &wq->sq.bar2_pa : NULL);
270 wq->rq.bar2_va = c4iw_bar2_addrs(rdev, wq->rq.qid, T4_BAR2_QTYPE_EGRESS,
271 &wq->rq.bar2_qid,
272 user ? &wq->rq.bar2_pa : NULL);
273
274 /*
275 * User mode must have bar2 access.
276 */
277 if (user && (!wq->sq.bar2_pa || !wq->rq.bar2_pa)) {
278 pr_warn("%s: sqid %u or rqid %u not in BAR2 range\n",
279 pci_name(rdev->lldi.pdev), wq->sq.qid, wq->rq.qid);
280 goto free_dma;
281 }
282
283 wq->rdev = rdev;
284 wq->rq.msn = 1;
285
286 /* build fw_ri_res_wr */
287 wr_len = sizeof *res_wr + 2 * sizeof *res;
288
289 skb = alloc_skb(wr_len, GFP_KERNEL);
290 if (!skb) {
291 ret = -ENOMEM;
292 goto free_dma;
293 }
294 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
295
296 res_wr = __skb_put(skb, wr_len);
297 memset(res_wr, 0, wr_len);
298 res_wr->op_nres = cpu_to_be32(
299 FW_WR_OP_V(FW_RI_RES_WR) |
300 FW_RI_RES_WR_NRES_V(2) |
301 FW_WR_COMPL_F);
302 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
303 res_wr->cookie = (uintptr_t)&wr_wait;
304 res = res_wr->res;
305 res->u.sqrq.restype = FW_RI_RES_TYPE_SQ;
306 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
307
308 /*
309 * eqsize is the number of 64B entries plus the status page size.
310 */
311 eqsize = wq->sq.size * T4_SQ_NUM_SLOTS +
312 rdev->hw_queue.t4_eq_status_entries;
313
314 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
315 FW_RI_RES_WR_HOSTFCMODE_V(0) | /* no host cidx updates */
316 FW_RI_RES_WR_CPRIO_V(0) | /* don't keep in chip cache */
317 FW_RI_RES_WR_PCIECHN_V(0) | /* set by uP at ri_init time */
318 (t4_sq_onchip(&wq->sq) ? FW_RI_RES_WR_ONCHIP_F : 0) |
319 FW_RI_RES_WR_IQID_V(scq->cqid));
320 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
321 FW_RI_RES_WR_DCAEN_V(0) |
322 FW_RI_RES_WR_DCACPU_V(0) |
323 FW_RI_RES_WR_FBMIN_V(2) |
324 (t4_sq_onchip(&wq->sq) ? FW_RI_RES_WR_FBMAX_V(2) :
325 FW_RI_RES_WR_FBMAX_V(3)) |
326 FW_RI_RES_WR_CIDXFTHRESHO_V(0) |
327 FW_RI_RES_WR_CIDXFTHRESH_V(0) |
328 FW_RI_RES_WR_EQSIZE_V(eqsize));
329 res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid);
330 res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr);
331 res++;
332 res->u.sqrq.restype = FW_RI_RES_TYPE_RQ;
333 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
334
335 /*
336 * eqsize is the number of 64B entries plus the status page size.
337 */
338 eqsize = wq->rq.size * T4_RQ_NUM_SLOTS +
339 rdev->hw_queue.t4_eq_status_entries;
340 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
341 FW_RI_RES_WR_HOSTFCMODE_V(0) | /* no host cidx updates */
342 FW_RI_RES_WR_CPRIO_V(0) | /* don't keep in chip cache */
343 FW_RI_RES_WR_PCIECHN_V(0) | /* set by uP at ri_init time */
344 FW_RI_RES_WR_IQID_V(rcq->cqid));
345 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
346 FW_RI_RES_WR_DCAEN_V(0) |
347 FW_RI_RES_WR_DCACPU_V(0) |
348 FW_RI_RES_WR_FBMIN_V(2) |
349 FW_RI_RES_WR_FBMAX_V(3) |
350 FW_RI_RES_WR_CIDXFTHRESHO_V(0) |
351 FW_RI_RES_WR_CIDXFTHRESH_V(0) |
352 FW_RI_RES_WR_EQSIZE_V(eqsize));
353 res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid);
354 res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr);
355
356 c4iw_init_wr_wait(&wr_wait);
357
358 ret = c4iw_ofld_send(rdev, skb);
359 if (ret)
360 goto free_dma;
361 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, wq->sq.qid, __func__);
362 if (ret)
363 goto free_dma;
364
365 pr_debug("%s sqid 0x%x rqid 0x%x kdb 0x%p sq_bar2_addr %p rq_bar2_addr %p\n",
366 __func__, wq->sq.qid, wq->rq.qid, wq->db,
367 wq->sq.bar2_va, wq->rq.bar2_va);
368
369 return 0;
370 free_dma:
371 dma_free_coherent(&(rdev->lldi.pdev->dev),
372 wq->rq.memsize, wq->rq.queue,
373 dma_unmap_addr(&wq->rq, mapping));
374 free_sq:
375 dealloc_sq(rdev, &wq->sq);
376 free_hwaddr:
377 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
378 free_sw_rq:
379 kfree(wq->rq.sw_rq);
380 free_sw_sq:
381 kfree(wq->sq.sw_sq);
382 free_rq_qid:
383 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
384 free_sq_qid:
385 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
386 return ret;
387 }
388
389 static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp,
390 struct ib_send_wr *wr, int max, u32 *plenp)
391 {
392 u8 *dstp, *srcp;
393 u32 plen = 0;
394 int i;
395 int rem, len;
396
397 dstp = (u8 *)immdp->data;
398 for (i = 0; i < wr->num_sge; i++) {
399 if ((plen + wr->sg_list[i].length) > max)
400 return -EMSGSIZE;
401 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr;
402 plen += wr->sg_list[i].length;
403 rem = wr->sg_list[i].length;
404 while (rem) {
405 if (dstp == (u8 *)&sq->queue[sq->size])
406 dstp = (u8 *)sq->queue;
407 if (rem <= (u8 *)&sq->queue[sq->size] - dstp)
408 len = rem;
409 else
410 len = (u8 *)&sq->queue[sq->size] - dstp;
411 memcpy(dstp, srcp, len);
412 dstp += len;
413 srcp += len;
414 rem -= len;
415 }
416 }
417 len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp);
418 if (len)
419 memset(dstp, 0, len);
420 immdp->op = FW_RI_DATA_IMMD;
421 immdp->r1 = 0;
422 immdp->r2 = 0;
423 immdp->immdlen = cpu_to_be32(plen);
424 *plenp = plen;
425 return 0;
426 }
427
428 static int build_isgl(__be64 *queue_start, __be64 *queue_end,
429 struct fw_ri_isgl *isglp, struct ib_sge *sg_list,
430 int num_sge, u32 *plenp)
431
432 {
433 int i;
434 u32 plen = 0;
435 __be64 *flitp = (__be64 *)isglp->sge;
436
437 for (i = 0; i < num_sge; i++) {
438 if ((plen + sg_list[i].length) < plen)
439 return -EMSGSIZE;
440 plen += sg_list[i].length;
441 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) |
442 sg_list[i].length);
443 if (++flitp == queue_end)
444 flitp = queue_start;
445 *flitp = cpu_to_be64(sg_list[i].addr);
446 if (++flitp == queue_end)
447 flitp = queue_start;
448 }
449 *flitp = (__force __be64)0;
450 isglp->op = FW_RI_DATA_ISGL;
451 isglp->r1 = 0;
452 isglp->nsge = cpu_to_be16(num_sge);
453 isglp->r2 = 0;
454 if (plenp)
455 *plenp = plen;
456 return 0;
457 }
458
459 static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe,
460 struct ib_send_wr *wr, u8 *len16)
461 {
462 u32 plen;
463 int size;
464 int ret;
465
466 if (wr->num_sge > T4_MAX_SEND_SGE)
467 return -EINVAL;
468 switch (wr->opcode) {
469 case IB_WR_SEND:
470 if (wr->send_flags & IB_SEND_SOLICITED)
471 wqe->send.sendop_pkd = cpu_to_be32(
472 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_SE));
473 else
474 wqe->send.sendop_pkd = cpu_to_be32(
475 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND));
476 wqe->send.stag_inv = 0;
477 break;
478 case IB_WR_SEND_WITH_INV:
479 if (wr->send_flags & IB_SEND_SOLICITED)
480 wqe->send.sendop_pkd = cpu_to_be32(
481 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_SE_INV));
482 else
483 wqe->send.sendop_pkd = cpu_to_be32(
484 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_INV));
485 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
486 break;
487
488 default:
489 return -EINVAL;
490 }
491 wqe->send.r3 = 0;
492 wqe->send.r4 = 0;
493
494 plen = 0;
495 if (wr->num_sge) {
496 if (wr->send_flags & IB_SEND_INLINE) {
497 ret = build_immd(sq, wqe->send.u.immd_src, wr,
498 T4_MAX_SEND_INLINE, &plen);
499 if (ret)
500 return ret;
501 size = sizeof wqe->send + sizeof(struct fw_ri_immd) +
502 plen;
503 } else {
504 ret = build_isgl((__be64 *)sq->queue,
505 (__be64 *)&sq->queue[sq->size],
506 wqe->send.u.isgl_src,
507 wr->sg_list, wr->num_sge, &plen);
508 if (ret)
509 return ret;
510 size = sizeof wqe->send + sizeof(struct fw_ri_isgl) +
511 wr->num_sge * sizeof(struct fw_ri_sge);
512 }
513 } else {
514 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD;
515 wqe->send.u.immd_src[0].r1 = 0;
516 wqe->send.u.immd_src[0].r2 = 0;
517 wqe->send.u.immd_src[0].immdlen = 0;
518 size = sizeof wqe->send + sizeof(struct fw_ri_immd);
519 plen = 0;
520 }
521 *len16 = DIV_ROUND_UP(size, 16);
522 wqe->send.plen = cpu_to_be32(plen);
523 return 0;
524 }
525
526 static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe,
527 struct ib_send_wr *wr, u8 *len16)
528 {
529 u32 plen;
530 int size;
531 int ret;
532
533 if (wr->num_sge > T4_MAX_SEND_SGE)
534 return -EINVAL;
535 wqe->write.r2 = 0;
536 wqe->write.stag_sink = cpu_to_be32(rdma_wr(wr)->rkey);
537 wqe->write.to_sink = cpu_to_be64(rdma_wr(wr)->remote_addr);
538 if (wr->num_sge) {
539 if (wr->send_flags & IB_SEND_INLINE) {
540 ret = build_immd(sq, wqe->write.u.immd_src, wr,
541 T4_MAX_WRITE_INLINE, &plen);
542 if (ret)
543 return ret;
544 size = sizeof wqe->write + sizeof(struct fw_ri_immd) +
545 plen;
546 } else {
547 ret = build_isgl((__be64 *)sq->queue,
548 (__be64 *)&sq->queue[sq->size],
549 wqe->write.u.isgl_src,
550 wr->sg_list, wr->num_sge, &plen);
551 if (ret)
552 return ret;
553 size = sizeof wqe->write + sizeof(struct fw_ri_isgl) +
554 wr->num_sge * sizeof(struct fw_ri_sge);
555 }
556 } else {
557 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD;
558 wqe->write.u.immd_src[0].r1 = 0;
559 wqe->write.u.immd_src[0].r2 = 0;
560 wqe->write.u.immd_src[0].immdlen = 0;
561 size = sizeof wqe->write + sizeof(struct fw_ri_immd);
562 plen = 0;
563 }
564 *len16 = DIV_ROUND_UP(size, 16);
565 wqe->write.plen = cpu_to_be32(plen);
566 return 0;
567 }
568
569 static int build_rdma_read(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16)
570 {
571 if (wr->num_sge > 1)
572 return -EINVAL;
573 if (wr->num_sge) {
574 wqe->read.stag_src = cpu_to_be32(rdma_wr(wr)->rkey);
575 wqe->read.to_src_hi = cpu_to_be32((u32)(rdma_wr(wr)->remote_addr
576 >> 32));
577 wqe->read.to_src_lo = cpu_to_be32((u32)rdma_wr(wr)->remote_addr);
578 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey);
579 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length);
580 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr
581 >> 32));
582 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr));
583 } else {
584 wqe->read.stag_src = cpu_to_be32(2);
585 wqe->read.to_src_hi = 0;
586 wqe->read.to_src_lo = 0;
587 wqe->read.stag_sink = cpu_to_be32(2);
588 wqe->read.plen = 0;
589 wqe->read.to_sink_hi = 0;
590 wqe->read.to_sink_lo = 0;
591 }
592 wqe->read.r2 = 0;
593 wqe->read.r5 = 0;
594 *len16 = DIV_ROUND_UP(sizeof wqe->read, 16);
595 return 0;
596 }
597
598 static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe,
599 struct ib_recv_wr *wr, u8 *len16)
600 {
601 int ret;
602
603 ret = build_isgl((__be64 *)qhp->wq.rq.queue,
604 (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size],
605 &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL);
606 if (ret)
607 return ret;
608 *len16 = DIV_ROUND_UP(sizeof wqe->recv +
609 wr->num_sge * sizeof(struct fw_ri_sge), 16);
610 return 0;
611 }
612
613 static void build_tpte_memreg(struct fw_ri_fr_nsmr_tpte_wr *fr,
614 struct ib_reg_wr *wr, struct c4iw_mr *mhp,
615 u8 *len16)
616 {
617 __be64 *p = (__be64 *)fr->pbl;
618
619 fr->r2 = cpu_to_be32(0);
620 fr->stag = cpu_to_be32(mhp->ibmr.rkey);
621
622 fr->tpte.valid_to_pdid = cpu_to_be32(FW_RI_TPTE_VALID_F |
623 FW_RI_TPTE_STAGKEY_V((mhp->ibmr.rkey & FW_RI_TPTE_STAGKEY_M)) |
624 FW_RI_TPTE_STAGSTATE_V(1) |
625 FW_RI_TPTE_STAGTYPE_V(FW_RI_STAG_NSMR) |
626 FW_RI_TPTE_PDID_V(mhp->attr.pdid));
627 fr->tpte.locread_to_qpid = cpu_to_be32(
628 FW_RI_TPTE_PERM_V(c4iw_ib_to_tpt_access(wr->access)) |
629 FW_RI_TPTE_ADDRTYPE_V(FW_RI_VA_BASED_TO) |
630 FW_RI_TPTE_PS_V(ilog2(wr->mr->page_size) - 12));
631 fr->tpte.nosnoop_pbladdr = cpu_to_be32(FW_RI_TPTE_PBLADDR_V(
632 PBL_OFF(&mhp->rhp->rdev, mhp->attr.pbl_addr)>>3));
633 fr->tpte.dca_mwbcnt_pstag = cpu_to_be32(0);
634 fr->tpte.len_hi = cpu_to_be32(0);
635 fr->tpte.len_lo = cpu_to_be32(mhp->ibmr.length);
636 fr->tpte.va_hi = cpu_to_be32(mhp->ibmr.iova >> 32);
637 fr->tpte.va_lo_fbo = cpu_to_be32(mhp->ibmr.iova & 0xffffffff);
638
639 p[0] = cpu_to_be64((u64)mhp->mpl[0]);
640 p[1] = cpu_to_be64((u64)mhp->mpl[1]);
641
642 *len16 = DIV_ROUND_UP(sizeof(*fr), 16);
643 }
644
645 static int build_memreg(struct t4_sq *sq, union t4_wr *wqe,
646 struct ib_reg_wr *wr, struct c4iw_mr *mhp, u8 *len16,
647 bool dsgl_supported)
648 {
649 struct fw_ri_immd *imdp;
650 __be64 *p;
651 int i;
652 int pbllen = roundup(mhp->mpl_len * sizeof(u64), 32);
653 int rem;
654
655 if (mhp->mpl_len > t4_max_fr_depth(dsgl_supported && use_dsgl))
656 return -EINVAL;
657
658 wqe->fr.qpbinde_to_dcacpu = 0;
659 wqe->fr.pgsz_shift = ilog2(wr->mr->page_size) - 12;
660 wqe->fr.addr_type = FW_RI_VA_BASED_TO;
661 wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->access);
662 wqe->fr.len_hi = 0;
663 wqe->fr.len_lo = cpu_to_be32(mhp->ibmr.length);
664 wqe->fr.stag = cpu_to_be32(wr->key);
665 wqe->fr.va_hi = cpu_to_be32(mhp->ibmr.iova >> 32);
666 wqe->fr.va_lo_fbo = cpu_to_be32(mhp->ibmr.iova &
667 0xffffffff);
668
669 if (dsgl_supported && use_dsgl && (pbllen > max_fr_immd)) {
670 struct fw_ri_dsgl *sglp;
671
672 for (i = 0; i < mhp->mpl_len; i++)
673 mhp->mpl[i] = (__force u64)cpu_to_be64((u64)mhp->mpl[i]);
674
675 sglp = (struct fw_ri_dsgl *)(&wqe->fr + 1);
676 sglp->op = FW_RI_DATA_DSGL;
677 sglp->r1 = 0;
678 sglp->nsge = cpu_to_be16(1);
679 sglp->addr0 = cpu_to_be64(mhp->mpl_addr);
680 sglp->len0 = cpu_to_be32(pbllen);
681
682 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*sglp), 16);
683 } else {
684 imdp = (struct fw_ri_immd *)(&wqe->fr + 1);
685 imdp->op = FW_RI_DATA_IMMD;
686 imdp->r1 = 0;
687 imdp->r2 = 0;
688 imdp->immdlen = cpu_to_be32(pbllen);
689 p = (__be64 *)(imdp + 1);
690 rem = pbllen;
691 for (i = 0; i < mhp->mpl_len; i++) {
692 *p = cpu_to_be64((u64)mhp->mpl[i]);
693 rem -= sizeof(*p);
694 if (++p == (__be64 *)&sq->queue[sq->size])
695 p = (__be64 *)sq->queue;
696 }
697 BUG_ON(rem < 0);
698 while (rem) {
699 *p = 0;
700 rem -= sizeof(*p);
701 if (++p == (__be64 *)&sq->queue[sq->size])
702 p = (__be64 *)sq->queue;
703 }
704 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*imdp)
705 + pbllen, 16);
706 }
707 return 0;
708 }
709
710 static int build_inv_stag(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16)
711 {
712 wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
713 wqe->inv.r2 = 0;
714 *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16);
715 return 0;
716 }
717
718 static void free_qp_work(struct work_struct *work)
719 {
720 struct c4iw_ucontext *ucontext;
721 struct c4iw_qp *qhp;
722 struct c4iw_dev *rhp;
723
724 qhp = container_of(work, struct c4iw_qp, free_work);
725 ucontext = qhp->ucontext;
726 rhp = qhp->rhp;
727
728 pr_debug("%s qhp %p ucontext %p\n", __func__, qhp, ucontext);
729 destroy_qp(&rhp->rdev, &qhp->wq,
730 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
731
732 if (ucontext)
733 c4iw_put_ucontext(ucontext);
734 kfree(qhp);
735 }
736
737 static void queue_qp_free(struct kref *kref)
738 {
739 struct c4iw_qp *qhp;
740
741 qhp = container_of(kref, struct c4iw_qp, kref);
742 pr_debug("%s qhp %p\n", __func__, qhp);
743 queue_work(qhp->rhp->rdev.free_workq, &qhp->free_work);
744 }
745
746 void c4iw_qp_add_ref(struct ib_qp *qp)
747 {
748 pr_debug("%s ib_qp %p\n", __func__, qp);
749 kref_get(&to_c4iw_qp(qp)->kref);
750 }
751
752 void c4iw_qp_rem_ref(struct ib_qp *qp)
753 {
754 pr_debug("%s ib_qp %p\n", __func__, qp);
755 kref_put(&to_c4iw_qp(qp)->kref, queue_qp_free);
756 }
757
758 static void add_to_fc_list(struct list_head *head, struct list_head *entry)
759 {
760 if (list_empty(entry))
761 list_add_tail(entry, head);
762 }
763
764 static int ring_kernel_sq_db(struct c4iw_qp *qhp, u16 inc)
765 {
766 unsigned long flags;
767
768 spin_lock_irqsave(&qhp->rhp->lock, flags);
769 spin_lock(&qhp->lock);
770 if (qhp->rhp->db_state == NORMAL)
771 t4_ring_sq_db(&qhp->wq, inc, NULL);
772 else {
773 add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry);
774 qhp->wq.sq.wq_pidx_inc += inc;
775 }
776 spin_unlock(&qhp->lock);
777 spin_unlock_irqrestore(&qhp->rhp->lock, flags);
778 return 0;
779 }
780
781 static int ring_kernel_rq_db(struct c4iw_qp *qhp, u16 inc)
782 {
783 unsigned long flags;
784
785 spin_lock_irqsave(&qhp->rhp->lock, flags);
786 spin_lock(&qhp->lock);
787 if (qhp->rhp->db_state == NORMAL)
788 t4_ring_rq_db(&qhp->wq, inc, NULL);
789 else {
790 add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry);
791 qhp->wq.rq.wq_pidx_inc += inc;
792 }
793 spin_unlock(&qhp->lock);
794 spin_unlock_irqrestore(&qhp->rhp->lock, flags);
795 return 0;
796 }
797
798 static void complete_sq_drain_wr(struct c4iw_qp *qhp, struct ib_send_wr *wr)
799 {
800 struct t4_cqe cqe = {};
801 struct c4iw_cq *schp;
802 unsigned long flag;
803 struct t4_cq *cq;
804
805 schp = to_c4iw_cq(qhp->ibqp.send_cq);
806 cq = &schp->cq;
807
808 cqe.u.drain_cookie = wr->wr_id;
809 cqe.header = cpu_to_be32(CQE_STATUS_V(T4_ERR_SWFLUSH) |
810 CQE_OPCODE_V(C4IW_DRAIN_OPCODE) |
811 CQE_TYPE_V(1) |
812 CQE_SWCQE_V(1) |
813 CQE_QPID_V(qhp->wq.sq.qid));
814
815 spin_lock_irqsave(&schp->lock, flag);
816 cqe.bits_type_ts = cpu_to_be64(CQE_GENBIT_V((u64)cq->gen));
817 cq->sw_queue[cq->sw_pidx] = cqe;
818 t4_swcq_produce(cq);
819 spin_unlock_irqrestore(&schp->lock, flag);
820
821 spin_lock_irqsave(&schp->comp_handler_lock, flag);
822 (*schp->ibcq.comp_handler)(&schp->ibcq,
823 schp->ibcq.cq_context);
824 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
825 }
826
827 static void complete_rq_drain_wr(struct c4iw_qp *qhp, struct ib_recv_wr *wr)
828 {
829 struct t4_cqe cqe = {};
830 struct c4iw_cq *rchp;
831 unsigned long flag;
832 struct t4_cq *cq;
833
834 rchp = to_c4iw_cq(qhp->ibqp.recv_cq);
835 cq = &rchp->cq;
836
837 cqe.u.drain_cookie = wr->wr_id;
838 cqe.header = cpu_to_be32(CQE_STATUS_V(T4_ERR_SWFLUSH) |
839 CQE_OPCODE_V(C4IW_DRAIN_OPCODE) |
840 CQE_TYPE_V(0) |
841 CQE_SWCQE_V(1) |
842 CQE_QPID_V(qhp->wq.sq.qid));
843
844 spin_lock_irqsave(&rchp->lock, flag);
845 cqe.bits_type_ts = cpu_to_be64(CQE_GENBIT_V((u64)cq->gen));
846 cq->sw_queue[cq->sw_pidx] = cqe;
847 t4_swcq_produce(cq);
848 spin_unlock_irqrestore(&rchp->lock, flag);
849
850 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
851 (*rchp->ibcq.comp_handler)(&rchp->ibcq,
852 rchp->ibcq.cq_context);
853 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
854 }
855
856 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
857 struct ib_send_wr **bad_wr)
858 {
859 int err = 0;
860 u8 len16 = 0;
861 enum fw_wr_opcodes fw_opcode = 0;
862 enum fw_ri_wr_flags fw_flags;
863 struct c4iw_qp *qhp;
864 union t4_wr *wqe = NULL;
865 u32 num_wrs;
866 struct t4_swsqe *swsqe;
867 unsigned long flag;
868 u16 idx = 0;
869
870 qhp = to_c4iw_qp(ibqp);
871 spin_lock_irqsave(&qhp->lock, flag);
872 if (t4_wq_in_error(&qhp->wq)) {
873 spin_unlock_irqrestore(&qhp->lock, flag);
874 complete_sq_drain_wr(qhp, wr);
875 return err;
876 }
877 num_wrs = t4_sq_avail(&qhp->wq);
878 if (num_wrs == 0) {
879 spin_unlock_irqrestore(&qhp->lock, flag);
880 *bad_wr = wr;
881 return -ENOMEM;
882 }
883 while (wr) {
884 if (num_wrs == 0) {
885 err = -ENOMEM;
886 *bad_wr = wr;
887 break;
888 }
889 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue +
890 qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE);
891
892 fw_flags = 0;
893 if (wr->send_flags & IB_SEND_SOLICITED)
894 fw_flags |= FW_RI_SOLICITED_EVENT_FLAG;
895 if (wr->send_flags & IB_SEND_SIGNALED || qhp->sq_sig_all)
896 fw_flags |= FW_RI_COMPLETION_FLAG;
897 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx];
898 switch (wr->opcode) {
899 case IB_WR_SEND_WITH_INV:
900 case IB_WR_SEND:
901 if (wr->send_flags & IB_SEND_FENCE)
902 fw_flags |= FW_RI_READ_FENCE_FLAG;
903 fw_opcode = FW_RI_SEND_WR;
904 if (wr->opcode == IB_WR_SEND)
905 swsqe->opcode = FW_RI_SEND;
906 else
907 swsqe->opcode = FW_RI_SEND_WITH_INV;
908 err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16);
909 break;
910 case IB_WR_RDMA_WRITE:
911 fw_opcode = FW_RI_RDMA_WRITE_WR;
912 swsqe->opcode = FW_RI_RDMA_WRITE;
913 err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16);
914 break;
915 case IB_WR_RDMA_READ:
916 case IB_WR_RDMA_READ_WITH_INV:
917 fw_opcode = FW_RI_RDMA_READ_WR;
918 swsqe->opcode = FW_RI_READ_REQ;
919 if (wr->opcode == IB_WR_RDMA_READ_WITH_INV) {
920 c4iw_invalidate_mr(qhp->rhp,
921 wr->sg_list[0].lkey);
922 fw_flags = FW_RI_RDMA_READ_INVALIDATE;
923 } else {
924 fw_flags = 0;
925 }
926 err = build_rdma_read(wqe, wr, &len16);
927 if (err)
928 break;
929 swsqe->read_len = wr->sg_list[0].length;
930 if (!qhp->wq.sq.oldest_read)
931 qhp->wq.sq.oldest_read = swsqe;
932 break;
933 case IB_WR_REG_MR: {
934 struct c4iw_mr *mhp = to_c4iw_mr(reg_wr(wr)->mr);
935
936 swsqe->opcode = FW_RI_FAST_REGISTER;
937 if (qhp->rhp->rdev.lldi.fr_nsmr_tpte_wr_support &&
938 !mhp->attr.state && mhp->mpl_len <= 2) {
939 fw_opcode = FW_RI_FR_NSMR_TPTE_WR;
940 build_tpte_memreg(&wqe->fr_tpte, reg_wr(wr),
941 mhp, &len16);
942 } else {
943 fw_opcode = FW_RI_FR_NSMR_WR;
944 err = build_memreg(&qhp->wq.sq, wqe, reg_wr(wr),
945 mhp, &len16,
946 qhp->rhp->rdev.lldi.ulptx_memwrite_dsgl);
947 if (err)
948 break;
949 }
950 mhp->attr.state = 1;
951 break;
952 }
953 case IB_WR_LOCAL_INV:
954 if (wr->send_flags & IB_SEND_FENCE)
955 fw_flags |= FW_RI_LOCAL_FENCE_FLAG;
956 fw_opcode = FW_RI_INV_LSTAG_WR;
957 swsqe->opcode = FW_RI_LOCAL_INV;
958 err = build_inv_stag(wqe, wr, &len16);
959 c4iw_invalidate_mr(qhp->rhp, wr->ex.invalidate_rkey);
960 break;
961 default:
962 pr_debug("%s post of type=%d TBD!\n", __func__,
963 wr->opcode);
964 err = -EINVAL;
965 }
966 if (err) {
967 *bad_wr = wr;
968 break;
969 }
970 swsqe->idx = qhp->wq.sq.pidx;
971 swsqe->complete = 0;
972 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED) ||
973 qhp->sq_sig_all;
974 swsqe->flushed = 0;
975 swsqe->wr_id = wr->wr_id;
976 if (c4iw_wr_log) {
977 swsqe->sge_ts = cxgb4_read_sge_timestamp(
978 qhp->rhp->rdev.lldi.ports[0]);
979 getnstimeofday(&swsqe->host_ts);
980 }
981
982 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16);
983
984 pr_debug("%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u\n",
985 __func__,
986 (unsigned long long)wr->wr_id, qhp->wq.sq.pidx,
987 swsqe->opcode, swsqe->read_len);
988 wr = wr->next;
989 num_wrs--;
990 t4_sq_produce(&qhp->wq, len16);
991 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
992 }
993 if (!qhp->rhp->rdev.status_page->db_off) {
994 t4_ring_sq_db(&qhp->wq, idx, wqe);
995 spin_unlock_irqrestore(&qhp->lock, flag);
996 } else {
997 spin_unlock_irqrestore(&qhp->lock, flag);
998 ring_kernel_sq_db(qhp, idx);
999 }
1000 return err;
1001 }
1002
1003 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1004 struct ib_recv_wr **bad_wr)
1005 {
1006 int err = 0;
1007 struct c4iw_qp *qhp;
1008 union t4_recv_wr *wqe = NULL;
1009 u32 num_wrs;
1010 u8 len16 = 0;
1011 unsigned long flag;
1012 u16 idx = 0;
1013
1014 qhp = to_c4iw_qp(ibqp);
1015 spin_lock_irqsave(&qhp->lock, flag);
1016 if (t4_wq_in_error(&qhp->wq)) {
1017 spin_unlock_irqrestore(&qhp->lock, flag);
1018 complete_rq_drain_wr(qhp, wr);
1019 return err;
1020 }
1021 num_wrs = t4_rq_avail(&qhp->wq);
1022 if (num_wrs == 0) {
1023 spin_unlock_irqrestore(&qhp->lock, flag);
1024 *bad_wr = wr;
1025 return -ENOMEM;
1026 }
1027 while (wr) {
1028 if (wr->num_sge > T4_MAX_RECV_SGE) {
1029 err = -EINVAL;
1030 *bad_wr = wr;
1031 break;
1032 }
1033 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue +
1034 qhp->wq.rq.wq_pidx *
1035 T4_EQ_ENTRY_SIZE);
1036 if (num_wrs)
1037 err = build_rdma_recv(qhp, wqe, wr, &len16);
1038 else
1039 err = -ENOMEM;
1040 if (err) {
1041 *bad_wr = wr;
1042 break;
1043 }
1044
1045 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id;
1046 if (c4iw_wr_log) {
1047 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].sge_ts =
1048 cxgb4_read_sge_timestamp(
1049 qhp->rhp->rdev.lldi.ports[0]);
1050 getnstimeofday(
1051 &qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].host_ts);
1052 }
1053
1054 wqe->recv.opcode = FW_RI_RECV_WR;
1055 wqe->recv.r1 = 0;
1056 wqe->recv.wrid = qhp->wq.rq.pidx;
1057 wqe->recv.r2[0] = 0;
1058 wqe->recv.r2[1] = 0;
1059 wqe->recv.r2[2] = 0;
1060 wqe->recv.len16 = len16;
1061 pr_debug("%s cookie 0x%llx pidx %u\n",
1062 __func__,
1063 (unsigned long long)wr->wr_id, qhp->wq.rq.pidx);
1064 t4_rq_produce(&qhp->wq, len16);
1065 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
1066 wr = wr->next;
1067 num_wrs--;
1068 }
1069 if (!qhp->rhp->rdev.status_page->db_off) {
1070 t4_ring_rq_db(&qhp->wq, idx, wqe);
1071 spin_unlock_irqrestore(&qhp->lock, flag);
1072 } else {
1073 spin_unlock_irqrestore(&qhp->lock, flag);
1074 ring_kernel_rq_db(qhp, idx);
1075 }
1076 return err;
1077 }
1078
1079 static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type,
1080 u8 *ecode)
1081 {
1082 int status;
1083 int tagged;
1084 int opcode;
1085 int rqtype;
1086 int send_inv;
1087
1088 if (!err_cqe) {
1089 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
1090 *ecode = 0;
1091 return;
1092 }
1093
1094 status = CQE_STATUS(err_cqe);
1095 opcode = CQE_OPCODE(err_cqe);
1096 rqtype = RQ_TYPE(err_cqe);
1097 send_inv = (opcode == FW_RI_SEND_WITH_INV) ||
1098 (opcode == FW_RI_SEND_WITH_SE_INV);
1099 tagged = (opcode == FW_RI_RDMA_WRITE) ||
1100 (rqtype && (opcode == FW_RI_READ_RESP));
1101
1102 switch (status) {
1103 case T4_ERR_STAG:
1104 if (send_inv) {
1105 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1106 *ecode = RDMAP_CANT_INV_STAG;
1107 } else {
1108 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1109 *ecode = RDMAP_INV_STAG;
1110 }
1111 break;
1112 case T4_ERR_PDID:
1113 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1114 if ((opcode == FW_RI_SEND_WITH_INV) ||
1115 (opcode == FW_RI_SEND_WITH_SE_INV))
1116 *ecode = RDMAP_CANT_INV_STAG;
1117 else
1118 *ecode = RDMAP_STAG_NOT_ASSOC;
1119 break;
1120 case T4_ERR_QPID:
1121 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1122 *ecode = RDMAP_STAG_NOT_ASSOC;
1123 break;
1124 case T4_ERR_ACCESS:
1125 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1126 *ecode = RDMAP_ACC_VIOL;
1127 break;
1128 case T4_ERR_WRAP:
1129 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1130 *ecode = RDMAP_TO_WRAP;
1131 break;
1132 case T4_ERR_BOUND:
1133 if (tagged) {
1134 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
1135 *ecode = DDPT_BASE_BOUNDS;
1136 } else {
1137 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
1138 *ecode = RDMAP_BASE_BOUNDS;
1139 }
1140 break;
1141 case T4_ERR_INVALIDATE_SHARED_MR:
1142 case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:
1143 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1144 *ecode = RDMAP_CANT_INV_STAG;
1145 break;
1146 case T4_ERR_ECC:
1147 case T4_ERR_ECC_PSTAG:
1148 case T4_ERR_INTERNAL_ERR:
1149 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA;
1150 *ecode = 0;
1151 break;
1152 case T4_ERR_OUT_OF_RQE:
1153 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1154 *ecode = DDPU_INV_MSN_NOBUF;
1155 break;
1156 case T4_ERR_PBL_ADDR_BOUND:
1157 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
1158 *ecode = DDPT_BASE_BOUNDS;
1159 break;
1160 case T4_ERR_CRC:
1161 *layer_type = LAYER_MPA|DDP_LLP;
1162 *ecode = MPA_CRC_ERR;
1163 break;
1164 case T4_ERR_MARKER:
1165 *layer_type = LAYER_MPA|DDP_LLP;
1166 *ecode = MPA_MARKER_ERR;
1167 break;
1168 case T4_ERR_PDU_LEN_ERR:
1169 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1170 *ecode = DDPU_MSG_TOOBIG;
1171 break;
1172 case T4_ERR_DDP_VERSION:
1173 if (tagged) {
1174 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
1175 *ecode = DDPT_INV_VERS;
1176 } else {
1177 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1178 *ecode = DDPU_INV_VERS;
1179 }
1180 break;
1181 case T4_ERR_RDMA_VERSION:
1182 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1183 *ecode = RDMAP_INV_VERS;
1184 break;
1185 case T4_ERR_OPCODE:
1186 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1187 *ecode = RDMAP_INV_OPCODE;
1188 break;
1189 case T4_ERR_DDP_QUEUE_NUM:
1190 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1191 *ecode = DDPU_INV_QN;
1192 break;
1193 case T4_ERR_MSN:
1194 case T4_ERR_MSN_GAP:
1195 case T4_ERR_MSN_RANGE:
1196 case T4_ERR_IRD_OVERFLOW:
1197 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1198 *ecode = DDPU_INV_MSN_RANGE;
1199 break;
1200 case T4_ERR_TBIT:
1201 *layer_type = LAYER_DDP|DDP_LOCAL_CATA;
1202 *ecode = 0;
1203 break;
1204 case T4_ERR_MO:
1205 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1206 *ecode = DDPU_INV_MO;
1207 break;
1208 default:
1209 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
1210 *ecode = 0;
1211 break;
1212 }
1213 }
1214
1215 static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe,
1216 gfp_t gfp)
1217 {
1218 struct fw_ri_wr *wqe;
1219 struct sk_buff *skb;
1220 struct terminate_message *term;
1221
1222 pr_debug("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1223 qhp->ep->hwtid);
1224
1225 skb = skb_dequeue(&qhp->ep->com.ep_skb_list);
1226 if (WARN_ON(!skb))
1227 return;
1228
1229 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1230
1231 wqe = __skb_put(skb, sizeof(*wqe));
1232 memset(wqe, 0, sizeof *wqe);
1233 wqe->op_compl = cpu_to_be32(FW_WR_OP_V(FW_RI_INIT_WR));
1234 wqe->flowid_len16 = cpu_to_be32(
1235 FW_WR_FLOWID_V(qhp->ep->hwtid) |
1236 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16)));
1237
1238 wqe->u.terminate.type = FW_RI_TYPE_TERMINATE;
1239 wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term);
1240 term = (struct terminate_message *)wqe->u.terminate.termmsg;
1241 if (qhp->attr.layer_etype == (LAYER_MPA|DDP_LLP)) {
1242 term->layer_etype = qhp->attr.layer_etype;
1243 term->ecode = qhp->attr.ecode;
1244 } else
1245 build_term_codes(err_cqe, &term->layer_etype, &term->ecode);
1246 c4iw_ofld_send(&qhp->rhp->rdev, skb);
1247 }
1248
1249 /*
1250 * Assumes qhp lock is held.
1251 */
1252 static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp,
1253 struct c4iw_cq *schp)
1254 {
1255 int count;
1256 int rq_flushed, sq_flushed;
1257 unsigned long flag;
1258
1259 pr_debug("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp);
1260
1261 /* locking hierarchy: cq lock first, then qp lock. */
1262 spin_lock_irqsave(&rchp->lock, flag);
1263 spin_lock(&qhp->lock);
1264
1265 if (qhp->wq.flushed) {
1266 spin_unlock(&qhp->lock);
1267 spin_unlock_irqrestore(&rchp->lock, flag);
1268 return;
1269 }
1270 qhp->wq.flushed = 1;
1271
1272 c4iw_flush_hw_cq(rchp);
1273 c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count);
1274 rq_flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count);
1275 spin_unlock(&qhp->lock);
1276 spin_unlock_irqrestore(&rchp->lock, flag);
1277
1278 /* locking hierarchy: cq lock first, then qp lock. */
1279 spin_lock_irqsave(&schp->lock, flag);
1280 spin_lock(&qhp->lock);
1281 if (schp != rchp)
1282 c4iw_flush_hw_cq(schp);
1283 sq_flushed = c4iw_flush_sq(qhp);
1284 spin_unlock(&qhp->lock);
1285 spin_unlock_irqrestore(&schp->lock, flag);
1286
1287 if (schp == rchp) {
1288 if (t4_clear_cq_armed(&rchp->cq) &&
1289 (rq_flushed || sq_flushed)) {
1290 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1291 (*rchp->ibcq.comp_handler)(&rchp->ibcq,
1292 rchp->ibcq.cq_context);
1293 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1294 }
1295 } else {
1296 if (t4_clear_cq_armed(&rchp->cq) && rq_flushed) {
1297 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1298 (*rchp->ibcq.comp_handler)(&rchp->ibcq,
1299 rchp->ibcq.cq_context);
1300 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1301 }
1302 if (t4_clear_cq_armed(&schp->cq) && sq_flushed) {
1303 spin_lock_irqsave(&schp->comp_handler_lock, flag);
1304 (*schp->ibcq.comp_handler)(&schp->ibcq,
1305 schp->ibcq.cq_context);
1306 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1307 }
1308 }
1309 }
1310
1311 static void flush_qp(struct c4iw_qp *qhp)
1312 {
1313 struct c4iw_cq *rchp, *schp;
1314 unsigned long flag;
1315
1316 rchp = to_c4iw_cq(qhp->ibqp.recv_cq);
1317 schp = to_c4iw_cq(qhp->ibqp.send_cq);
1318
1319 t4_set_wq_in_error(&qhp->wq);
1320 if (qhp->ibqp.uobject) {
1321 t4_set_cq_in_error(&rchp->cq);
1322 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1323 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
1324 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1325 if (schp != rchp) {
1326 t4_set_cq_in_error(&schp->cq);
1327 spin_lock_irqsave(&schp->comp_handler_lock, flag);
1328 (*schp->ibcq.comp_handler)(&schp->ibcq,
1329 schp->ibcq.cq_context);
1330 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1331 }
1332 return;
1333 }
1334 __flush_qp(qhp, rchp, schp);
1335 }
1336
1337 static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1338 struct c4iw_ep *ep)
1339 {
1340 struct fw_ri_wr *wqe;
1341 int ret;
1342 struct sk_buff *skb;
1343
1344 pr_debug("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1345 ep->hwtid);
1346
1347 skb = skb_dequeue(&ep->com.ep_skb_list);
1348 if (WARN_ON(!skb))
1349 return -ENOMEM;
1350
1351 set_wr_txq(skb, CPL_PRIORITY_DATA, ep->txq_idx);
1352
1353 wqe = __skb_put(skb, sizeof(*wqe));
1354 memset(wqe, 0, sizeof *wqe);
1355 wqe->op_compl = cpu_to_be32(
1356 FW_WR_OP_V(FW_RI_INIT_WR) |
1357 FW_WR_COMPL_F);
1358 wqe->flowid_len16 = cpu_to_be32(
1359 FW_WR_FLOWID_V(ep->hwtid) |
1360 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16)));
1361 wqe->cookie = (uintptr_t)&ep->com.wr_wait;
1362
1363 wqe->u.fini.type = FW_RI_TYPE_FINI;
1364 ret = c4iw_ofld_send(&rhp->rdev, skb);
1365 if (ret)
1366 goto out;
1367
1368 ret = c4iw_wait_for_reply(&rhp->rdev, &ep->com.wr_wait, qhp->ep->hwtid,
1369 qhp->wq.sq.qid, __func__);
1370 out:
1371 pr_debug("%s ret %d\n", __func__, ret);
1372 return ret;
1373 }
1374
1375 static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init)
1376 {
1377 pr_debug("%s p2p_type = %d\n", __func__, p2p_type);
1378 memset(&init->u, 0, sizeof init->u);
1379 switch (p2p_type) {
1380 case FW_RI_INIT_P2PTYPE_RDMA_WRITE:
1381 init->u.write.opcode = FW_RI_RDMA_WRITE_WR;
1382 init->u.write.stag_sink = cpu_to_be32(1);
1383 init->u.write.to_sink = cpu_to_be64(1);
1384 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD;
1385 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write +
1386 sizeof(struct fw_ri_immd),
1387 16);
1388 break;
1389 case FW_RI_INIT_P2PTYPE_READ_REQ:
1390 init->u.write.opcode = FW_RI_RDMA_READ_WR;
1391 init->u.read.stag_src = cpu_to_be32(1);
1392 init->u.read.to_src_lo = cpu_to_be32(1);
1393 init->u.read.stag_sink = cpu_to_be32(1);
1394 init->u.read.to_sink_lo = cpu_to_be32(1);
1395 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16);
1396 break;
1397 }
1398 }
1399
1400 static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp)
1401 {
1402 struct fw_ri_wr *wqe;
1403 int ret;
1404 struct sk_buff *skb;
1405
1406 pr_debug("%s qhp %p qid 0x%x tid %u ird %u ord %u\n", __func__, qhp,
1407 qhp->wq.sq.qid, qhp->ep->hwtid, qhp->ep->ird, qhp->ep->ord);
1408
1409 skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
1410 if (!skb) {
1411 ret = -ENOMEM;
1412 goto out;
1413 }
1414 ret = alloc_ird(rhp, qhp->attr.max_ird);
1415 if (ret) {
1416 qhp->attr.max_ird = 0;
1417 kfree_skb(skb);
1418 goto out;
1419 }
1420 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1421
1422 wqe = __skb_put(skb, sizeof(*wqe));
1423 memset(wqe, 0, sizeof *wqe);
1424 wqe->op_compl = cpu_to_be32(
1425 FW_WR_OP_V(FW_RI_INIT_WR) |
1426 FW_WR_COMPL_F);
1427 wqe->flowid_len16 = cpu_to_be32(
1428 FW_WR_FLOWID_V(qhp->ep->hwtid) |
1429 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16)));
1430
1431 wqe->cookie = (uintptr_t)&qhp->ep->com.wr_wait;
1432
1433 wqe->u.init.type = FW_RI_TYPE_INIT;
1434 wqe->u.init.mpareqbit_p2ptype =
1435 FW_RI_WR_MPAREQBIT_V(qhp->attr.mpa_attr.initiator) |
1436 FW_RI_WR_P2PTYPE_V(qhp->attr.mpa_attr.p2p_type);
1437 wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE;
1438 if (qhp->attr.mpa_attr.recv_marker_enabled)
1439 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE;
1440 if (qhp->attr.mpa_attr.xmit_marker_enabled)
1441 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE;
1442 if (qhp->attr.mpa_attr.crc_enabled)
1443 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE;
1444
1445 wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE |
1446 FW_RI_QP_RDMA_WRITE_ENABLE |
1447 FW_RI_QP_BIND_ENABLE;
1448 if (!qhp->ibqp.uobject)
1449 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE |
1450 FW_RI_QP_STAG0_ENABLE;
1451 wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq));
1452 wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd);
1453 wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid);
1454 wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid);
1455 wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid);
1456 wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq);
1457 wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq);
1458 wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord);
1459 wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird);
1460 wqe->u.init.iss = cpu_to_be32(qhp->ep->snd_seq);
1461 wqe->u.init.irs = cpu_to_be32(qhp->ep->rcv_seq);
1462 wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size);
1463 wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr -
1464 rhp->rdev.lldi.vr->rq.start);
1465 if (qhp->attr.mpa_attr.initiator)
1466 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init);
1467
1468 ret = c4iw_ofld_send(&rhp->rdev, skb);
1469 if (ret)
1470 goto err1;
1471
1472 ret = c4iw_wait_for_reply(&rhp->rdev, &qhp->ep->com.wr_wait,
1473 qhp->ep->hwtid, qhp->wq.sq.qid, __func__);
1474 if (!ret)
1475 goto out;
1476 err1:
1477 free_ird(rhp, qhp->attr.max_ird);
1478 out:
1479 pr_debug("%s ret %d\n", __func__, ret);
1480 return ret;
1481 }
1482
1483 int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1484 enum c4iw_qp_attr_mask mask,
1485 struct c4iw_qp_attributes *attrs,
1486 int internal)
1487 {
1488 int ret = 0;
1489 struct c4iw_qp_attributes newattr = qhp->attr;
1490 int disconnect = 0;
1491 int terminate = 0;
1492 int abort = 0;
1493 int free = 0;
1494 struct c4iw_ep *ep = NULL;
1495
1496 pr_debug("%s qhp %p sqid 0x%x rqid 0x%x ep %p state %d -> %d\n",
1497 __func__,
1498 qhp, qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep, qhp->attr.state,
1499 (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1);
1500
1501 mutex_lock(&qhp->mutex);
1502
1503 /* Process attr changes if in IDLE */
1504 if (mask & C4IW_QP_ATTR_VALID_MODIFY) {
1505 if (qhp->attr.state != C4IW_QP_STATE_IDLE) {
1506 ret = -EIO;
1507 goto out;
1508 }
1509 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ)
1510 newattr.enable_rdma_read = attrs->enable_rdma_read;
1511 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE)
1512 newattr.enable_rdma_write = attrs->enable_rdma_write;
1513 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND)
1514 newattr.enable_bind = attrs->enable_bind;
1515 if (mask & C4IW_QP_ATTR_MAX_ORD) {
1516 if (attrs->max_ord > c4iw_max_read_depth) {
1517 ret = -EINVAL;
1518 goto out;
1519 }
1520 newattr.max_ord = attrs->max_ord;
1521 }
1522 if (mask & C4IW_QP_ATTR_MAX_IRD) {
1523 if (attrs->max_ird > cur_max_read_depth(rhp)) {
1524 ret = -EINVAL;
1525 goto out;
1526 }
1527 newattr.max_ird = attrs->max_ird;
1528 }
1529 qhp->attr = newattr;
1530 }
1531
1532 if (mask & C4IW_QP_ATTR_SQ_DB) {
1533 ret = ring_kernel_sq_db(qhp, attrs->sq_db_inc);
1534 goto out;
1535 }
1536 if (mask & C4IW_QP_ATTR_RQ_DB) {
1537 ret = ring_kernel_rq_db(qhp, attrs->rq_db_inc);
1538 goto out;
1539 }
1540
1541 if (!(mask & C4IW_QP_ATTR_NEXT_STATE))
1542 goto out;
1543 if (qhp->attr.state == attrs->next_state)
1544 goto out;
1545
1546 switch (qhp->attr.state) {
1547 case C4IW_QP_STATE_IDLE:
1548 switch (attrs->next_state) {
1549 case C4IW_QP_STATE_RTS:
1550 if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) {
1551 ret = -EINVAL;
1552 goto out;
1553 }
1554 if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) {
1555 ret = -EINVAL;
1556 goto out;
1557 }
1558 qhp->attr.mpa_attr = attrs->mpa_attr;
1559 qhp->attr.llp_stream_handle = attrs->llp_stream_handle;
1560 qhp->ep = qhp->attr.llp_stream_handle;
1561 set_state(qhp, C4IW_QP_STATE_RTS);
1562
1563 /*
1564 * Ref the endpoint here and deref when we
1565 * disassociate the endpoint from the QP. This
1566 * happens in CLOSING->IDLE transition or *->ERROR
1567 * transition.
1568 */
1569 c4iw_get_ep(&qhp->ep->com);
1570 ret = rdma_init(rhp, qhp);
1571 if (ret)
1572 goto err;
1573 break;
1574 case C4IW_QP_STATE_ERROR:
1575 set_state(qhp, C4IW_QP_STATE_ERROR);
1576 flush_qp(qhp);
1577 break;
1578 default:
1579 ret = -EINVAL;
1580 goto out;
1581 }
1582 break;
1583 case C4IW_QP_STATE_RTS:
1584 switch (attrs->next_state) {
1585 case C4IW_QP_STATE_CLOSING:
1586 BUG_ON(kref_read(&qhp->ep->com.kref) < 2);
1587 t4_set_wq_in_error(&qhp->wq);
1588 set_state(qhp, C4IW_QP_STATE_CLOSING);
1589 ep = qhp->ep;
1590 if (!internal) {
1591 abort = 0;
1592 disconnect = 1;
1593 c4iw_get_ep(&qhp->ep->com);
1594 }
1595 ret = rdma_fini(rhp, qhp, ep);
1596 if (ret)
1597 goto err;
1598 break;
1599 case C4IW_QP_STATE_TERMINATE:
1600 t4_set_wq_in_error(&qhp->wq);
1601 set_state(qhp, C4IW_QP_STATE_TERMINATE);
1602 qhp->attr.layer_etype = attrs->layer_etype;
1603 qhp->attr.ecode = attrs->ecode;
1604 ep = qhp->ep;
1605 if (!internal) {
1606 c4iw_get_ep(&qhp->ep->com);
1607 terminate = 1;
1608 disconnect = 1;
1609 } else {
1610 terminate = qhp->attr.send_term;
1611 ret = rdma_fini(rhp, qhp, ep);
1612 if (ret)
1613 goto err;
1614 }
1615 break;
1616 case C4IW_QP_STATE_ERROR:
1617 t4_set_wq_in_error(&qhp->wq);
1618 set_state(qhp, C4IW_QP_STATE_ERROR);
1619 if (!internal) {
1620 abort = 1;
1621 disconnect = 1;
1622 ep = qhp->ep;
1623 c4iw_get_ep(&qhp->ep->com);
1624 }
1625 goto err;
1626 break;
1627 default:
1628 ret = -EINVAL;
1629 goto out;
1630 }
1631 break;
1632 case C4IW_QP_STATE_CLOSING:
1633
1634 /*
1635 * Allow kernel users to move to ERROR for qp draining.
1636 */
1637 if (!internal && (qhp->ibqp.uobject || attrs->next_state !=
1638 C4IW_QP_STATE_ERROR)) {
1639 ret = -EINVAL;
1640 goto out;
1641 }
1642 switch (attrs->next_state) {
1643 case C4IW_QP_STATE_IDLE:
1644 flush_qp(qhp);
1645 set_state(qhp, C4IW_QP_STATE_IDLE);
1646 qhp->attr.llp_stream_handle = NULL;
1647 c4iw_put_ep(&qhp->ep->com);
1648 qhp->ep = NULL;
1649 wake_up(&qhp->wait);
1650 break;
1651 case C4IW_QP_STATE_ERROR:
1652 goto err;
1653 default:
1654 ret = -EINVAL;
1655 goto err;
1656 }
1657 break;
1658 case C4IW_QP_STATE_ERROR:
1659 if (attrs->next_state != C4IW_QP_STATE_IDLE) {
1660 ret = -EINVAL;
1661 goto out;
1662 }
1663 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) {
1664 ret = -EINVAL;
1665 goto out;
1666 }
1667 set_state(qhp, C4IW_QP_STATE_IDLE);
1668 break;
1669 case C4IW_QP_STATE_TERMINATE:
1670 if (!internal) {
1671 ret = -EINVAL;
1672 goto out;
1673 }
1674 goto err;
1675 break;
1676 default:
1677 pr_err("%s in a bad state %d\n", __func__, qhp->attr.state);
1678 ret = -EINVAL;
1679 goto err;
1680 break;
1681 }
1682 goto out;
1683 err:
1684 pr_debug("%s disassociating ep %p qpid 0x%x\n", __func__, qhp->ep,
1685 qhp->wq.sq.qid);
1686
1687 /* disassociate the LLP connection */
1688 qhp->attr.llp_stream_handle = NULL;
1689 if (!ep)
1690 ep = qhp->ep;
1691 qhp->ep = NULL;
1692 set_state(qhp, C4IW_QP_STATE_ERROR);
1693 free = 1;
1694 abort = 1;
1695 BUG_ON(!ep);
1696 flush_qp(qhp);
1697 wake_up(&qhp->wait);
1698 out:
1699 mutex_unlock(&qhp->mutex);
1700
1701 if (terminate)
1702 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL);
1703
1704 /*
1705 * If disconnect is 1, then we need to initiate a disconnect
1706 * on the EP. This can be a normal close (RTS->CLOSING) or
1707 * an abnormal close (RTS/CLOSING->ERROR).
1708 */
1709 if (disconnect) {
1710 c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC :
1711 GFP_KERNEL);
1712 c4iw_put_ep(&ep->com);
1713 }
1714
1715 /*
1716 * If free is 1, then we've disassociated the EP from the QP
1717 * and we need to dereference the EP.
1718 */
1719 if (free)
1720 c4iw_put_ep(&ep->com);
1721 pr_debug("%s exit state %d\n", __func__, qhp->attr.state);
1722 return ret;
1723 }
1724
1725 int c4iw_destroy_qp(struct ib_qp *ib_qp)
1726 {
1727 struct c4iw_dev *rhp;
1728 struct c4iw_qp *qhp;
1729 struct c4iw_qp_attributes attrs;
1730
1731 qhp = to_c4iw_qp(ib_qp);
1732 rhp = qhp->rhp;
1733
1734 attrs.next_state = C4IW_QP_STATE_ERROR;
1735 if (qhp->attr.state == C4IW_QP_STATE_TERMINATE)
1736 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1);
1737 else
1738 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0);
1739 wait_event(qhp->wait, !qhp->ep);
1740
1741 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1742
1743 spin_lock_irq(&rhp->lock);
1744 if (!list_empty(&qhp->db_fc_entry))
1745 list_del_init(&qhp->db_fc_entry);
1746 spin_unlock_irq(&rhp->lock);
1747 free_ird(rhp, qhp->attr.max_ird);
1748
1749 c4iw_qp_rem_ref(ib_qp);
1750
1751 pr_debug("%s ib_qp %p qpid 0x%0x\n", __func__, ib_qp, qhp->wq.sq.qid);
1752 return 0;
1753 }
1754
1755 struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1756 struct ib_udata *udata)
1757 {
1758 struct c4iw_dev *rhp;
1759 struct c4iw_qp *qhp;
1760 struct c4iw_pd *php;
1761 struct c4iw_cq *schp;
1762 struct c4iw_cq *rchp;
1763 struct c4iw_create_qp_resp uresp;
1764 unsigned int sqsize, rqsize;
1765 struct c4iw_ucontext *ucontext;
1766 int ret;
1767 struct c4iw_mm_entry *sq_key_mm, *rq_key_mm = NULL, *sq_db_key_mm;
1768 struct c4iw_mm_entry *rq_db_key_mm = NULL, *ma_sync_key_mm = NULL;
1769
1770 pr_debug("%s ib_pd %p\n", __func__, pd);
1771
1772 if (attrs->qp_type != IB_QPT_RC)
1773 return ERR_PTR(-EINVAL);
1774
1775 php = to_c4iw_pd(pd);
1776 rhp = php->rhp;
1777 schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid);
1778 rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid);
1779 if (!schp || !rchp)
1780 return ERR_PTR(-EINVAL);
1781
1782 if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE)
1783 return ERR_PTR(-EINVAL);
1784
1785 if (attrs->cap.max_recv_wr > rhp->rdev.hw_queue.t4_max_rq_size)
1786 return ERR_PTR(-E2BIG);
1787 rqsize = attrs->cap.max_recv_wr + 1;
1788 if (rqsize < 8)
1789 rqsize = 8;
1790
1791 if (attrs->cap.max_send_wr > rhp->rdev.hw_queue.t4_max_sq_size)
1792 return ERR_PTR(-E2BIG);
1793 sqsize = attrs->cap.max_send_wr + 1;
1794 if (sqsize < 8)
1795 sqsize = 8;
1796
1797 ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL;
1798
1799 qhp = kzalloc(sizeof(*qhp), GFP_KERNEL);
1800 if (!qhp)
1801 return ERR_PTR(-ENOMEM);
1802 qhp->wq.sq.size = sqsize;
1803 qhp->wq.sq.memsize =
1804 (sqsize + rhp->rdev.hw_queue.t4_eq_status_entries) *
1805 sizeof(*qhp->wq.sq.queue) + 16 * sizeof(__be64);
1806 qhp->wq.sq.flush_cidx = -1;
1807 qhp->wq.rq.size = rqsize;
1808 qhp->wq.rq.memsize =
1809 (rqsize + rhp->rdev.hw_queue.t4_eq_status_entries) *
1810 sizeof(*qhp->wq.rq.queue);
1811
1812 if (ucontext) {
1813 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE);
1814 qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE);
1815 }
1816
1817 ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq,
1818 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1819 if (ret)
1820 goto err1;
1821
1822 attrs->cap.max_recv_wr = rqsize - 1;
1823 attrs->cap.max_send_wr = sqsize - 1;
1824 attrs->cap.max_inline_data = T4_MAX_SEND_INLINE;
1825
1826 qhp->rhp = rhp;
1827 qhp->attr.pd = php->pdid;
1828 qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid;
1829 qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid;
1830 qhp->attr.sq_num_entries = attrs->cap.max_send_wr;
1831 qhp->attr.rq_num_entries = attrs->cap.max_recv_wr;
1832 qhp->attr.sq_max_sges = attrs->cap.max_send_sge;
1833 qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge;
1834 qhp->attr.rq_max_sges = attrs->cap.max_recv_sge;
1835 qhp->attr.state = C4IW_QP_STATE_IDLE;
1836 qhp->attr.next_state = C4IW_QP_STATE_IDLE;
1837 qhp->attr.enable_rdma_read = 1;
1838 qhp->attr.enable_rdma_write = 1;
1839 qhp->attr.enable_bind = 1;
1840 qhp->attr.max_ord = 0;
1841 qhp->attr.max_ird = 0;
1842 qhp->sq_sig_all = attrs->sq_sig_type == IB_SIGNAL_ALL_WR;
1843 spin_lock_init(&qhp->lock);
1844 mutex_init(&qhp->mutex);
1845 init_waitqueue_head(&qhp->wait);
1846 kref_init(&qhp->kref);
1847 INIT_WORK(&qhp->free_work, free_qp_work);
1848
1849 ret = insert_handle(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid);
1850 if (ret)
1851 goto err2;
1852
1853 if (udata) {
1854 sq_key_mm = kmalloc(sizeof(*sq_key_mm), GFP_KERNEL);
1855 if (!sq_key_mm) {
1856 ret = -ENOMEM;
1857 goto err3;
1858 }
1859 rq_key_mm = kmalloc(sizeof(*rq_key_mm), GFP_KERNEL);
1860 if (!rq_key_mm) {
1861 ret = -ENOMEM;
1862 goto err4;
1863 }
1864 sq_db_key_mm = kmalloc(sizeof(*sq_db_key_mm), GFP_KERNEL);
1865 if (!sq_db_key_mm) {
1866 ret = -ENOMEM;
1867 goto err5;
1868 }
1869 rq_db_key_mm = kmalloc(sizeof(*rq_db_key_mm), GFP_KERNEL);
1870 if (!rq_db_key_mm) {
1871 ret = -ENOMEM;
1872 goto err6;
1873 }
1874 if (t4_sq_onchip(&qhp->wq.sq)) {
1875 ma_sync_key_mm = kmalloc(sizeof(*ma_sync_key_mm),
1876 GFP_KERNEL);
1877 if (!ma_sync_key_mm) {
1878 ret = -ENOMEM;
1879 goto err7;
1880 }
1881 uresp.flags = C4IW_QPF_ONCHIP;
1882 } else
1883 uresp.flags = 0;
1884 uresp.qid_mask = rhp->rdev.qpmask;
1885 uresp.sqid = qhp->wq.sq.qid;
1886 uresp.sq_size = qhp->wq.sq.size;
1887 uresp.sq_memsize = qhp->wq.sq.memsize;
1888 uresp.rqid = qhp->wq.rq.qid;
1889 uresp.rq_size = qhp->wq.rq.size;
1890 uresp.rq_memsize = qhp->wq.rq.memsize;
1891 spin_lock(&ucontext->mmap_lock);
1892 if (ma_sync_key_mm) {
1893 uresp.ma_sync_key = ucontext->key;
1894 ucontext->key += PAGE_SIZE;
1895 } else {
1896 uresp.ma_sync_key = 0;
1897 }
1898 uresp.sq_key = ucontext->key;
1899 ucontext->key += PAGE_SIZE;
1900 uresp.rq_key = ucontext->key;
1901 ucontext->key += PAGE_SIZE;
1902 uresp.sq_db_gts_key = ucontext->key;
1903 ucontext->key += PAGE_SIZE;
1904 uresp.rq_db_gts_key = ucontext->key;
1905 ucontext->key += PAGE_SIZE;
1906 spin_unlock(&ucontext->mmap_lock);
1907 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp);
1908 if (ret)
1909 goto err8;
1910 sq_key_mm->key = uresp.sq_key;
1911 sq_key_mm->addr = qhp->wq.sq.phys_addr;
1912 sq_key_mm->len = PAGE_ALIGN(qhp->wq.sq.memsize);
1913 insert_mmap(ucontext, sq_key_mm);
1914 rq_key_mm->key = uresp.rq_key;
1915 rq_key_mm->addr = virt_to_phys(qhp->wq.rq.queue);
1916 rq_key_mm->len = PAGE_ALIGN(qhp->wq.rq.memsize);
1917 insert_mmap(ucontext, rq_key_mm);
1918 sq_db_key_mm->key = uresp.sq_db_gts_key;
1919 sq_db_key_mm->addr = (u64)(unsigned long)qhp->wq.sq.bar2_pa;
1920 sq_db_key_mm->len = PAGE_SIZE;
1921 insert_mmap(ucontext, sq_db_key_mm);
1922 rq_db_key_mm->key = uresp.rq_db_gts_key;
1923 rq_db_key_mm->addr = (u64)(unsigned long)qhp->wq.rq.bar2_pa;
1924 rq_db_key_mm->len = PAGE_SIZE;
1925 insert_mmap(ucontext, rq_db_key_mm);
1926 if (ma_sync_key_mm) {
1927 ma_sync_key_mm->key = uresp.ma_sync_key;
1928 ma_sync_key_mm->addr =
1929 (pci_resource_start(rhp->rdev.lldi.pdev, 0) +
1930 PCIE_MA_SYNC_A) & PAGE_MASK;
1931 ma_sync_key_mm->len = PAGE_SIZE;
1932 insert_mmap(ucontext, ma_sync_key_mm);
1933 }
1934
1935 c4iw_get_ucontext(ucontext);
1936 qhp->ucontext = ucontext;
1937 }
1938 qhp->ibqp.qp_num = qhp->wq.sq.qid;
1939 init_timer(&(qhp->timer));
1940 INIT_LIST_HEAD(&qhp->db_fc_entry);
1941 pr_debug("%s sq id %u size %u memsize %zu num_entries %u rq id %u size %u memsize %zu num_entries %u\n",
1942 __func__,
1943 qhp->wq.sq.qid, qhp->wq.sq.size, qhp->wq.sq.memsize,
1944 attrs->cap.max_send_wr, qhp->wq.rq.qid, qhp->wq.rq.size,
1945 qhp->wq.rq.memsize, attrs->cap.max_recv_wr);
1946 return &qhp->ibqp;
1947 err8:
1948 kfree(ma_sync_key_mm);
1949 err7:
1950 kfree(rq_db_key_mm);
1951 err6:
1952 kfree(sq_db_key_mm);
1953 err5:
1954 kfree(rq_key_mm);
1955 err4:
1956 kfree(sq_key_mm);
1957 err3:
1958 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1959 err2:
1960 destroy_qp(&rhp->rdev, &qhp->wq,
1961 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1962 err1:
1963 kfree(qhp);
1964 return ERR_PTR(ret);
1965 }
1966
1967 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1968 int attr_mask, struct ib_udata *udata)
1969 {
1970 struct c4iw_dev *rhp;
1971 struct c4iw_qp *qhp;
1972 enum c4iw_qp_attr_mask mask = 0;
1973 struct c4iw_qp_attributes attrs;
1974
1975 pr_debug("%s ib_qp %p\n", __func__, ibqp);
1976
1977 /* iwarp does not support the RTR state */
1978 if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR))
1979 attr_mask &= ~IB_QP_STATE;
1980
1981 /* Make sure we still have something left to do */
1982 if (!attr_mask)
1983 return 0;
1984
1985 memset(&attrs, 0, sizeof attrs);
1986 qhp = to_c4iw_qp(ibqp);
1987 rhp = qhp->rhp;
1988
1989 attrs.next_state = c4iw_convert_state(attr->qp_state);
1990 attrs.enable_rdma_read = (attr->qp_access_flags &
1991 IB_ACCESS_REMOTE_READ) ? 1 : 0;
1992 attrs.enable_rdma_write = (attr->qp_access_flags &
1993 IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
1994 attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0;
1995
1996
1997 mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0;
1998 mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ?
1999 (C4IW_QP_ATTR_ENABLE_RDMA_READ |
2000 C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
2001 C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0;
2002
2003 /*
2004 * Use SQ_PSN and RQ_PSN to pass in IDX_INC values for
2005 * ringing the queue db when we're in DB_FULL mode.
2006 * Only allow this on T4 devices.
2007 */
2008 attrs.sq_db_inc = attr->sq_psn;
2009 attrs.rq_db_inc = attr->rq_psn;
2010 mask |= (attr_mask & IB_QP_SQ_PSN) ? C4IW_QP_ATTR_SQ_DB : 0;
2011 mask |= (attr_mask & IB_QP_RQ_PSN) ? C4IW_QP_ATTR_RQ_DB : 0;
2012 if (!is_t4(to_c4iw_qp(ibqp)->rhp->rdev.lldi.adapter_type) &&
2013 (mask & (C4IW_QP_ATTR_SQ_DB|C4IW_QP_ATTR_RQ_DB)))
2014 return -EINVAL;
2015
2016 return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0);
2017 }
2018
2019 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn)
2020 {
2021 pr_debug("%s ib_dev %p qpn 0x%x\n", __func__, dev, qpn);
2022 return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn);
2023 }
2024
2025 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2026 int attr_mask, struct ib_qp_init_attr *init_attr)
2027 {
2028 struct c4iw_qp *qhp = to_c4iw_qp(ibqp);
2029
2030 memset(attr, 0, sizeof *attr);
2031 memset(init_attr, 0, sizeof *init_attr);
2032 attr->qp_state = to_ib_qp_state(qhp->attr.state);
2033 init_attr->cap.max_send_wr = qhp->attr.sq_num_entries;
2034 init_attr->cap.max_recv_wr = qhp->attr.rq_num_entries;
2035 init_attr->cap.max_send_sge = qhp->attr.sq_max_sges;
2036 init_attr->cap.max_recv_sge = qhp->attr.sq_max_sges;
2037 init_attr->cap.max_inline_data = T4_MAX_SEND_INLINE;
2038 init_attr->sq_sig_type = qhp->sq_sig_all ? IB_SIGNAL_ALL_WR : 0;
2039 return 0;
2040 }
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