2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/module.h>
37 static int db_delay_usecs
= 1;
38 module_param(db_delay_usecs
, int, 0644);
39 MODULE_PARM_DESC(db_delay_usecs
, "Usecs to delay awaiting db fifo to drain");
41 static int ocqp_support
= 1;
42 module_param(ocqp_support
, int, 0644);
43 MODULE_PARM_DESC(ocqp_support
, "Support on-chip SQs (default=1)");
45 int db_fc_threshold
= 1000;
46 module_param(db_fc_threshold
, int, 0644);
47 MODULE_PARM_DESC(db_fc_threshold
,
48 "QP count/threshold that triggers"
49 " automatic db flow control mode (default = 1000)");
51 int db_coalescing_threshold
;
52 module_param(db_coalescing_threshold
, int, 0644);
53 MODULE_PARM_DESC(db_coalescing_threshold
,
54 "QP count/threshold that triggers"
55 " disabling db coalescing (default = 0)");
57 static int max_fr_immd
= T4_MAX_FR_IMMD
;
58 module_param(max_fr_immd
, int, 0644);
59 MODULE_PARM_DESC(max_fr_immd
, "fastreg threshold for using DSGL instead of immedate");
61 static int alloc_ird(struct c4iw_dev
*dev
, u32 ird
)
65 spin_lock_irq(&dev
->lock
);
66 if (ird
<= dev
->avail_ird
)
67 dev
->avail_ird
-= ird
;
70 spin_unlock_irq(&dev
->lock
);
73 dev_warn(&dev
->rdev
.lldi
.pdev
->dev
,
74 "device IRD resources exhausted\n");
79 static void free_ird(struct c4iw_dev
*dev
, int ird
)
81 spin_lock_irq(&dev
->lock
);
82 dev
->avail_ird
+= ird
;
83 spin_unlock_irq(&dev
->lock
);
86 static void set_state(struct c4iw_qp
*qhp
, enum c4iw_qp_state state
)
89 spin_lock_irqsave(&qhp
->lock
, flag
);
90 qhp
->attr
.state
= state
;
91 spin_unlock_irqrestore(&qhp
->lock
, flag
);
94 static void dealloc_oc_sq(struct c4iw_rdev
*rdev
, struct t4_sq
*sq
)
96 c4iw_ocqp_pool_free(rdev
, sq
->dma_addr
, sq
->memsize
);
99 static void dealloc_host_sq(struct c4iw_rdev
*rdev
, struct t4_sq
*sq
)
101 dma_free_coherent(&(rdev
->lldi
.pdev
->dev
), sq
->memsize
, sq
->queue
,
102 pci_unmap_addr(sq
, mapping
));
105 static void dealloc_sq(struct c4iw_rdev
*rdev
, struct t4_sq
*sq
)
107 if (t4_sq_onchip(sq
))
108 dealloc_oc_sq(rdev
, sq
);
110 dealloc_host_sq(rdev
, sq
);
113 static int alloc_oc_sq(struct c4iw_rdev
*rdev
, struct t4_sq
*sq
)
115 if (!ocqp_support
|| !ocqp_supported(&rdev
->lldi
))
117 sq
->dma_addr
= c4iw_ocqp_pool_alloc(rdev
, sq
->memsize
);
120 sq
->phys_addr
= rdev
->oc_mw_pa
+ sq
->dma_addr
-
121 rdev
->lldi
.vr
->ocq
.start
;
122 sq
->queue
= (__force
union t4_wr
*)(rdev
->oc_mw_kva
+ sq
->dma_addr
-
123 rdev
->lldi
.vr
->ocq
.start
);
124 sq
->flags
|= T4_SQ_ONCHIP
;
128 static int alloc_host_sq(struct c4iw_rdev
*rdev
, struct t4_sq
*sq
)
130 sq
->queue
= dma_alloc_coherent(&(rdev
->lldi
.pdev
->dev
), sq
->memsize
,
131 &(sq
->dma_addr
), GFP_KERNEL
);
134 sq
->phys_addr
= virt_to_phys(sq
->queue
);
135 pci_unmap_addr_set(sq
, mapping
, sq
->dma_addr
);
139 static int alloc_sq(struct c4iw_rdev
*rdev
, struct t4_sq
*sq
, int user
)
143 ret
= alloc_oc_sq(rdev
, sq
);
145 ret
= alloc_host_sq(rdev
, sq
);
149 static int destroy_qp(struct c4iw_rdev
*rdev
, struct t4_wq
*wq
,
150 struct c4iw_dev_ucontext
*uctx
)
153 * uP clears EQ contexts when the connection exits rdma mode,
154 * so no need to post a RESET WR for these EQs.
156 dma_free_coherent(&(rdev
->lldi
.pdev
->dev
),
157 wq
->rq
.memsize
, wq
->rq
.queue
,
158 dma_unmap_addr(&wq
->rq
, mapping
));
159 dealloc_sq(rdev
, &wq
->sq
);
160 c4iw_rqtpool_free(rdev
, wq
->rq
.rqt_hwaddr
, wq
->rq
.rqt_size
);
163 c4iw_put_qpid(rdev
, wq
->rq
.qid
, uctx
);
164 c4iw_put_qpid(rdev
, wq
->sq
.qid
, uctx
);
169 * Determine the BAR2 virtual address and qid. If pbar2_pa is not NULL,
170 * then this is a user mapping so compute the page-aligned physical address
173 void __iomem
*c4iw_bar2_addrs(struct c4iw_rdev
*rdev
, unsigned int qid
,
174 enum cxgb4_bar2_qtype qtype
,
175 unsigned int *pbar2_qid
, u64
*pbar2_pa
)
180 ret
= cxgb4_bar2_sge_qregs(rdev
->lldi
.ports
[0], qid
, qtype
,
182 &bar2_qoffset
, pbar2_qid
);
187 *pbar2_pa
= (rdev
->bar2_pa
+ bar2_qoffset
) & PAGE_MASK
;
189 if (is_t4(rdev
->lldi
.adapter_type
))
192 return rdev
->bar2_kva
+ bar2_qoffset
;
195 static int create_qp(struct c4iw_rdev
*rdev
, struct t4_wq
*wq
,
196 struct t4_cq
*rcq
, struct t4_cq
*scq
,
197 struct c4iw_dev_ucontext
*uctx
)
199 int user
= (uctx
!= &rdev
->uctx
);
200 struct fw_ri_res_wr
*res_wr
;
201 struct fw_ri_res
*res
;
203 struct c4iw_wr_wait wr_wait
;
208 wq
->sq
.qid
= c4iw_get_qpid(rdev
, uctx
);
212 wq
->rq
.qid
= c4iw_get_qpid(rdev
, uctx
);
219 wq
->sq
.sw_sq
= kzalloc(wq
->sq
.size
* sizeof *wq
->sq
.sw_sq
,
226 wq
->rq
.sw_rq
= kzalloc(wq
->rq
.size
* sizeof *wq
->rq
.sw_rq
,
235 * RQT must be a power of 2 and at least 16 deep.
237 wq
->rq
.rqt_size
= roundup_pow_of_two(max_t(u16
, wq
->rq
.size
, 16));
238 wq
->rq
.rqt_hwaddr
= c4iw_rqtpool_alloc(rdev
, wq
->rq
.rqt_size
);
239 if (!wq
->rq
.rqt_hwaddr
) {
244 ret
= alloc_sq(rdev
, &wq
->sq
, user
);
247 memset(wq
->sq
.queue
, 0, wq
->sq
.memsize
);
248 dma_unmap_addr_set(&wq
->sq
, mapping
, wq
->sq
.dma_addr
);
250 wq
->rq
.queue
= dma_alloc_coherent(&(rdev
->lldi
.pdev
->dev
),
251 wq
->rq
.memsize
, &(wq
->rq
.dma_addr
),
257 PDBG("%s sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx\n",
258 __func__
, wq
->sq
.queue
,
259 (unsigned long long)virt_to_phys(wq
->sq
.queue
),
261 (unsigned long long)virt_to_phys(wq
->rq
.queue
));
262 memset(wq
->rq
.queue
, 0, wq
->rq
.memsize
);
263 dma_unmap_addr_set(&wq
->rq
, mapping
, wq
->rq
.dma_addr
);
265 wq
->db
= rdev
->lldi
.db_reg
;
267 wq
->sq
.bar2_va
= c4iw_bar2_addrs(rdev
, wq
->sq
.qid
, T4_BAR2_QTYPE_EGRESS
,
269 user
? &wq
->sq
.bar2_pa
: NULL
);
270 wq
->rq
.bar2_va
= c4iw_bar2_addrs(rdev
, wq
->rq
.qid
, T4_BAR2_QTYPE_EGRESS
,
272 user
? &wq
->rq
.bar2_pa
: NULL
);
275 * User mode must have bar2 access.
277 if (user
&& (!wq
->sq
.bar2_pa
|| !wq
->rq
.bar2_pa
)) {
278 pr_warn(MOD
"%s: sqid %u or rqid %u not in BAR2 range.\n",
279 pci_name(rdev
->lldi
.pdev
), wq
->sq
.qid
, wq
->rq
.qid
);
286 /* build fw_ri_res_wr */
287 wr_len
= sizeof *res_wr
+ 2 * sizeof *res
;
289 skb
= alloc_skb(wr_len
, GFP_KERNEL
);
294 set_wr_txq(skb
, CPL_PRIORITY_CONTROL
, 0);
296 res_wr
= (struct fw_ri_res_wr
*)__skb_put(skb
, wr_len
);
297 memset(res_wr
, 0, wr_len
);
298 res_wr
->op_nres
= cpu_to_be32(
299 FW_WR_OP_V(FW_RI_RES_WR
) |
300 FW_RI_RES_WR_NRES_V(2) |
302 res_wr
->len16_pkd
= cpu_to_be32(DIV_ROUND_UP(wr_len
, 16));
303 res_wr
->cookie
= (uintptr_t)&wr_wait
;
305 res
->u
.sqrq
.restype
= FW_RI_RES_TYPE_SQ
;
306 res
->u
.sqrq
.op
= FW_RI_RES_OP_WRITE
;
309 * eqsize is the number of 64B entries plus the status page size.
311 eqsize
= wq
->sq
.size
* T4_SQ_NUM_SLOTS
+
312 rdev
->hw_queue
.t4_eq_status_entries
;
314 res
->u
.sqrq
.fetchszm_to_iqid
= cpu_to_be32(
315 FW_RI_RES_WR_HOSTFCMODE_V(0) | /* no host cidx updates */
316 FW_RI_RES_WR_CPRIO_V(0) | /* don't keep in chip cache */
317 FW_RI_RES_WR_PCIECHN_V(0) | /* set by uP at ri_init time */
318 (t4_sq_onchip(&wq
->sq
) ? FW_RI_RES_WR_ONCHIP_F
: 0) |
319 FW_RI_RES_WR_IQID_V(scq
->cqid
));
320 res
->u
.sqrq
.dcaen_to_eqsize
= cpu_to_be32(
321 FW_RI_RES_WR_DCAEN_V(0) |
322 FW_RI_RES_WR_DCACPU_V(0) |
323 FW_RI_RES_WR_FBMIN_V(2) |
324 (t4_sq_onchip(&wq
->sq
) ? FW_RI_RES_WR_FBMAX_V(2) :
325 FW_RI_RES_WR_FBMAX_V(3)) |
326 FW_RI_RES_WR_CIDXFTHRESHO_V(0) |
327 FW_RI_RES_WR_CIDXFTHRESH_V(0) |
328 FW_RI_RES_WR_EQSIZE_V(eqsize
));
329 res
->u
.sqrq
.eqid
= cpu_to_be32(wq
->sq
.qid
);
330 res
->u
.sqrq
.eqaddr
= cpu_to_be64(wq
->sq
.dma_addr
);
332 res
->u
.sqrq
.restype
= FW_RI_RES_TYPE_RQ
;
333 res
->u
.sqrq
.op
= FW_RI_RES_OP_WRITE
;
336 * eqsize is the number of 64B entries plus the status page size.
338 eqsize
= wq
->rq
.size
* T4_RQ_NUM_SLOTS
+
339 rdev
->hw_queue
.t4_eq_status_entries
;
340 res
->u
.sqrq
.fetchszm_to_iqid
= cpu_to_be32(
341 FW_RI_RES_WR_HOSTFCMODE_V(0) | /* no host cidx updates */
342 FW_RI_RES_WR_CPRIO_V(0) | /* don't keep in chip cache */
343 FW_RI_RES_WR_PCIECHN_V(0) | /* set by uP at ri_init time */
344 FW_RI_RES_WR_IQID_V(rcq
->cqid
));
345 res
->u
.sqrq
.dcaen_to_eqsize
= cpu_to_be32(
346 FW_RI_RES_WR_DCAEN_V(0) |
347 FW_RI_RES_WR_DCACPU_V(0) |
348 FW_RI_RES_WR_FBMIN_V(2) |
349 FW_RI_RES_WR_FBMAX_V(3) |
350 FW_RI_RES_WR_CIDXFTHRESHO_V(0) |
351 FW_RI_RES_WR_CIDXFTHRESH_V(0) |
352 FW_RI_RES_WR_EQSIZE_V(eqsize
));
353 res
->u
.sqrq
.eqid
= cpu_to_be32(wq
->rq
.qid
);
354 res
->u
.sqrq
.eqaddr
= cpu_to_be64(wq
->rq
.dma_addr
);
356 c4iw_init_wr_wait(&wr_wait
);
358 ret
= c4iw_ofld_send(rdev
, skb
);
361 ret
= c4iw_wait_for_reply(rdev
, &wr_wait
, 0, wq
->sq
.qid
, __func__
);
365 PDBG("%s sqid 0x%x rqid 0x%x kdb 0x%p sq_bar2_addr %p rq_bar2_addr %p\n",
366 __func__
, wq
->sq
.qid
, wq
->rq
.qid
, wq
->db
,
367 wq
->sq
.bar2_va
, wq
->rq
.bar2_va
);
371 dma_free_coherent(&(rdev
->lldi
.pdev
->dev
),
372 wq
->rq
.memsize
, wq
->rq
.queue
,
373 dma_unmap_addr(&wq
->rq
, mapping
));
375 dealloc_sq(rdev
, &wq
->sq
);
377 c4iw_rqtpool_free(rdev
, wq
->rq
.rqt_hwaddr
, wq
->rq
.rqt_size
);
383 c4iw_put_qpid(rdev
, wq
->rq
.qid
, uctx
);
385 c4iw_put_qpid(rdev
, wq
->sq
.qid
, uctx
);
389 static int build_immd(struct t4_sq
*sq
, struct fw_ri_immd
*immdp
,
390 struct ib_send_wr
*wr
, int max
, u32
*plenp
)
397 dstp
= (u8
*)immdp
->data
;
398 for (i
= 0; i
< wr
->num_sge
; i
++) {
399 if ((plen
+ wr
->sg_list
[i
].length
) > max
)
401 srcp
= (u8
*)(unsigned long)wr
->sg_list
[i
].addr
;
402 plen
+= wr
->sg_list
[i
].length
;
403 rem
= wr
->sg_list
[i
].length
;
405 if (dstp
== (u8
*)&sq
->queue
[sq
->size
])
406 dstp
= (u8
*)sq
->queue
;
407 if (rem
<= (u8
*)&sq
->queue
[sq
->size
] - dstp
)
410 len
= (u8
*)&sq
->queue
[sq
->size
] - dstp
;
411 memcpy(dstp
, srcp
, len
);
417 len
= roundup(plen
+ sizeof *immdp
, 16) - (plen
+ sizeof *immdp
);
419 memset(dstp
, 0, len
);
420 immdp
->op
= FW_RI_DATA_IMMD
;
423 immdp
->immdlen
= cpu_to_be32(plen
);
428 static int build_isgl(__be64
*queue_start
, __be64
*queue_end
,
429 struct fw_ri_isgl
*isglp
, struct ib_sge
*sg_list
,
430 int num_sge
, u32
*plenp
)
435 __be64
*flitp
= (__be64
*)isglp
->sge
;
437 for (i
= 0; i
< num_sge
; i
++) {
438 if ((plen
+ sg_list
[i
].length
) < plen
)
440 plen
+= sg_list
[i
].length
;
441 *flitp
= cpu_to_be64(((u64
)sg_list
[i
].lkey
<< 32) |
443 if (++flitp
== queue_end
)
445 *flitp
= cpu_to_be64(sg_list
[i
].addr
);
446 if (++flitp
== queue_end
)
449 *flitp
= (__force __be64
)0;
450 isglp
->op
= FW_RI_DATA_ISGL
;
452 isglp
->nsge
= cpu_to_be16(num_sge
);
459 static int build_rdma_send(struct t4_sq
*sq
, union t4_wr
*wqe
,
460 struct ib_send_wr
*wr
, u8
*len16
)
466 if (wr
->num_sge
> T4_MAX_SEND_SGE
)
468 switch (wr
->opcode
) {
470 if (wr
->send_flags
& IB_SEND_SOLICITED
)
471 wqe
->send
.sendop_pkd
= cpu_to_be32(
472 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_SE
));
474 wqe
->send
.sendop_pkd
= cpu_to_be32(
475 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND
));
476 wqe
->send
.stag_inv
= 0;
478 case IB_WR_SEND_WITH_INV
:
479 if (wr
->send_flags
& IB_SEND_SOLICITED
)
480 wqe
->send
.sendop_pkd
= cpu_to_be32(
481 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_SE_INV
));
483 wqe
->send
.sendop_pkd
= cpu_to_be32(
484 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_INV
));
485 wqe
->send
.stag_inv
= cpu_to_be32(wr
->ex
.invalidate_rkey
);
496 if (wr
->send_flags
& IB_SEND_INLINE
) {
497 ret
= build_immd(sq
, wqe
->send
.u
.immd_src
, wr
,
498 T4_MAX_SEND_INLINE
, &plen
);
501 size
= sizeof wqe
->send
+ sizeof(struct fw_ri_immd
) +
504 ret
= build_isgl((__be64
*)sq
->queue
,
505 (__be64
*)&sq
->queue
[sq
->size
],
506 wqe
->send
.u
.isgl_src
,
507 wr
->sg_list
, wr
->num_sge
, &plen
);
510 size
= sizeof wqe
->send
+ sizeof(struct fw_ri_isgl
) +
511 wr
->num_sge
* sizeof(struct fw_ri_sge
);
514 wqe
->send
.u
.immd_src
[0].op
= FW_RI_DATA_IMMD
;
515 wqe
->send
.u
.immd_src
[0].r1
= 0;
516 wqe
->send
.u
.immd_src
[0].r2
= 0;
517 wqe
->send
.u
.immd_src
[0].immdlen
= 0;
518 size
= sizeof wqe
->send
+ sizeof(struct fw_ri_immd
);
521 *len16
= DIV_ROUND_UP(size
, 16);
522 wqe
->send
.plen
= cpu_to_be32(plen
);
526 static int build_rdma_write(struct t4_sq
*sq
, union t4_wr
*wqe
,
527 struct ib_send_wr
*wr
, u8
*len16
)
533 if (wr
->num_sge
> T4_MAX_SEND_SGE
)
536 wqe
->write
.stag_sink
= cpu_to_be32(rdma_wr(wr
)->rkey
);
537 wqe
->write
.to_sink
= cpu_to_be64(rdma_wr(wr
)->remote_addr
);
539 if (wr
->send_flags
& IB_SEND_INLINE
) {
540 ret
= build_immd(sq
, wqe
->write
.u
.immd_src
, wr
,
541 T4_MAX_WRITE_INLINE
, &plen
);
544 size
= sizeof wqe
->write
+ sizeof(struct fw_ri_immd
) +
547 ret
= build_isgl((__be64
*)sq
->queue
,
548 (__be64
*)&sq
->queue
[sq
->size
],
549 wqe
->write
.u
.isgl_src
,
550 wr
->sg_list
, wr
->num_sge
, &plen
);
553 size
= sizeof wqe
->write
+ sizeof(struct fw_ri_isgl
) +
554 wr
->num_sge
* sizeof(struct fw_ri_sge
);
557 wqe
->write
.u
.immd_src
[0].op
= FW_RI_DATA_IMMD
;
558 wqe
->write
.u
.immd_src
[0].r1
= 0;
559 wqe
->write
.u
.immd_src
[0].r2
= 0;
560 wqe
->write
.u
.immd_src
[0].immdlen
= 0;
561 size
= sizeof wqe
->write
+ sizeof(struct fw_ri_immd
);
564 *len16
= DIV_ROUND_UP(size
, 16);
565 wqe
->write
.plen
= cpu_to_be32(plen
);
569 static int build_rdma_read(union t4_wr
*wqe
, struct ib_send_wr
*wr
, u8
*len16
)
574 wqe
->read
.stag_src
= cpu_to_be32(rdma_wr(wr
)->rkey
);
575 wqe
->read
.to_src_hi
= cpu_to_be32((u32
)(rdma_wr(wr
)->remote_addr
577 wqe
->read
.to_src_lo
= cpu_to_be32((u32
)rdma_wr(wr
)->remote_addr
);
578 wqe
->read
.stag_sink
= cpu_to_be32(wr
->sg_list
[0].lkey
);
579 wqe
->read
.plen
= cpu_to_be32(wr
->sg_list
[0].length
);
580 wqe
->read
.to_sink_hi
= cpu_to_be32((u32
)(wr
->sg_list
[0].addr
582 wqe
->read
.to_sink_lo
= cpu_to_be32((u32
)(wr
->sg_list
[0].addr
));
584 wqe
->read
.stag_src
= cpu_to_be32(2);
585 wqe
->read
.to_src_hi
= 0;
586 wqe
->read
.to_src_lo
= 0;
587 wqe
->read
.stag_sink
= cpu_to_be32(2);
589 wqe
->read
.to_sink_hi
= 0;
590 wqe
->read
.to_sink_lo
= 0;
594 *len16
= DIV_ROUND_UP(sizeof wqe
->read
, 16);
598 static int build_rdma_recv(struct c4iw_qp
*qhp
, union t4_recv_wr
*wqe
,
599 struct ib_recv_wr
*wr
, u8
*len16
)
603 ret
= build_isgl((__be64
*)qhp
->wq
.rq
.queue
,
604 (__be64
*)&qhp
->wq
.rq
.queue
[qhp
->wq
.rq
.size
],
605 &wqe
->recv
.isgl
, wr
->sg_list
, wr
->num_sge
, NULL
);
608 *len16
= DIV_ROUND_UP(sizeof wqe
->recv
+
609 wr
->num_sge
* sizeof(struct fw_ri_sge
), 16);
613 static void build_tpte_memreg(struct fw_ri_fr_nsmr_tpte_wr
*fr
,
614 struct ib_reg_wr
*wr
, struct c4iw_mr
*mhp
,
617 __be64
*p
= (__be64
*)fr
->pbl
;
619 fr
->r2
= cpu_to_be32(0);
620 fr
->stag
= cpu_to_be32(mhp
->ibmr
.rkey
);
622 fr
->tpte
.valid_to_pdid
= cpu_to_be32(FW_RI_TPTE_VALID_F
|
623 FW_RI_TPTE_STAGKEY_V((mhp
->ibmr
.rkey
& FW_RI_TPTE_STAGKEY_M
)) |
624 FW_RI_TPTE_STAGSTATE_V(1) |
625 FW_RI_TPTE_STAGTYPE_V(FW_RI_STAG_NSMR
) |
626 FW_RI_TPTE_PDID_V(mhp
->attr
.pdid
));
627 fr
->tpte
.locread_to_qpid
= cpu_to_be32(
628 FW_RI_TPTE_PERM_V(c4iw_ib_to_tpt_access(wr
->access
)) |
629 FW_RI_TPTE_ADDRTYPE_V(FW_RI_VA_BASED_TO
) |
630 FW_RI_TPTE_PS_V(ilog2(wr
->mr
->page_size
) - 12));
631 fr
->tpte
.nosnoop_pbladdr
= cpu_to_be32(FW_RI_TPTE_PBLADDR_V(
632 PBL_OFF(&mhp
->rhp
->rdev
, mhp
->attr
.pbl_addr
)>>3));
633 fr
->tpte
.dca_mwbcnt_pstag
= cpu_to_be32(0);
634 fr
->tpte
.len_hi
= cpu_to_be32(0);
635 fr
->tpte
.len_lo
= cpu_to_be32(mhp
->ibmr
.length
);
636 fr
->tpte
.va_hi
= cpu_to_be32(mhp
->ibmr
.iova
>> 32);
637 fr
->tpte
.va_lo_fbo
= cpu_to_be32(mhp
->ibmr
.iova
& 0xffffffff);
639 p
[0] = cpu_to_be64((u64
)mhp
->mpl
[0]);
640 p
[1] = cpu_to_be64((u64
)mhp
->mpl
[1]);
642 *len16
= DIV_ROUND_UP(sizeof(*fr
), 16);
645 static int build_memreg(struct t4_sq
*sq
, union t4_wr
*wqe
,
646 struct ib_reg_wr
*wr
, struct c4iw_mr
*mhp
, u8
*len16
,
649 struct fw_ri_immd
*imdp
;
652 int pbllen
= roundup(mhp
->mpl_len
* sizeof(u64
), 32);
655 if (mhp
->mpl_len
> t4_max_fr_depth(dsgl_supported
&& use_dsgl
))
658 wqe
->fr
.qpbinde_to_dcacpu
= 0;
659 wqe
->fr
.pgsz_shift
= ilog2(wr
->mr
->page_size
) - 12;
660 wqe
->fr
.addr_type
= FW_RI_VA_BASED_TO
;
661 wqe
->fr
.mem_perms
= c4iw_ib_to_tpt_access(wr
->access
);
663 wqe
->fr
.len_lo
= cpu_to_be32(mhp
->ibmr
.length
);
664 wqe
->fr
.stag
= cpu_to_be32(wr
->key
);
665 wqe
->fr
.va_hi
= cpu_to_be32(mhp
->ibmr
.iova
>> 32);
666 wqe
->fr
.va_lo_fbo
= cpu_to_be32(mhp
->ibmr
.iova
&
669 if (dsgl_supported
&& use_dsgl
&& (pbllen
> max_fr_immd
)) {
670 struct fw_ri_dsgl
*sglp
;
672 for (i
= 0; i
< mhp
->mpl_len
; i
++)
673 mhp
->mpl
[i
] = (__force u64
)cpu_to_be64((u64
)mhp
->mpl
[i
]);
675 sglp
= (struct fw_ri_dsgl
*)(&wqe
->fr
+ 1);
676 sglp
->op
= FW_RI_DATA_DSGL
;
678 sglp
->nsge
= cpu_to_be16(1);
679 sglp
->addr0
= cpu_to_be64(mhp
->mpl_addr
);
680 sglp
->len0
= cpu_to_be32(pbllen
);
682 *len16
= DIV_ROUND_UP(sizeof(wqe
->fr
) + sizeof(*sglp
), 16);
684 imdp
= (struct fw_ri_immd
*)(&wqe
->fr
+ 1);
685 imdp
->op
= FW_RI_DATA_IMMD
;
688 imdp
->immdlen
= cpu_to_be32(pbllen
);
689 p
= (__be64
*)(imdp
+ 1);
691 for (i
= 0; i
< mhp
->mpl_len
; i
++) {
692 *p
= cpu_to_be64((u64
)mhp
->mpl
[i
]);
694 if (++p
== (__be64
*)&sq
->queue
[sq
->size
])
695 p
= (__be64
*)sq
->queue
;
701 if (++p
== (__be64
*)&sq
->queue
[sq
->size
])
702 p
= (__be64
*)sq
->queue
;
704 *len16
= DIV_ROUND_UP(sizeof(wqe
->fr
) + sizeof(*imdp
)
710 static int build_inv_stag(union t4_wr
*wqe
, struct ib_send_wr
*wr
, u8
*len16
)
712 wqe
->inv
.stag_inv
= cpu_to_be32(wr
->ex
.invalidate_rkey
);
714 *len16
= DIV_ROUND_UP(sizeof wqe
->inv
, 16);
718 static void free_qp_work(struct work_struct
*work
)
720 struct c4iw_ucontext
*ucontext
;
722 struct c4iw_dev
*rhp
;
724 qhp
= container_of(work
, struct c4iw_qp
, free_work
);
725 ucontext
= qhp
->ucontext
;
728 PDBG("%s qhp %p ucontext %p\n", __func__
, qhp
, ucontext
);
729 destroy_qp(&rhp
->rdev
, &qhp
->wq
,
730 ucontext
? &ucontext
->uctx
: &rhp
->rdev
.uctx
);
733 c4iw_put_ucontext(ucontext
);
737 static void queue_qp_free(struct kref
*kref
)
741 qhp
= container_of(kref
, struct c4iw_qp
, kref
);
742 PDBG("%s qhp %p\n", __func__
, qhp
);
743 queue_work(qhp
->rhp
->rdev
.free_workq
, &qhp
->free_work
);
746 void c4iw_qp_add_ref(struct ib_qp
*qp
)
748 PDBG("%s ib_qp %p\n", __func__
, qp
);
749 kref_get(&to_c4iw_qp(qp
)->kref
);
752 void c4iw_qp_rem_ref(struct ib_qp
*qp
)
754 PDBG("%s ib_qp %p\n", __func__
, qp
);
755 kref_put(&to_c4iw_qp(qp
)->kref
, queue_qp_free
);
758 static void add_to_fc_list(struct list_head
*head
, struct list_head
*entry
)
760 if (list_empty(entry
))
761 list_add_tail(entry
, head
);
764 static int ring_kernel_sq_db(struct c4iw_qp
*qhp
, u16 inc
)
768 spin_lock_irqsave(&qhp
->rhp
->lock
, flags
);
769 spin_lock(&qhp
->lock
);
770 if (qhp
->rhp
->db_state
== NORMAL
)
771 t4_ring_sq_db(&qhp
->wq
, inc
, NULL
);
773 add_to_fc_list(&qhp
->rhp
->db_fc_list
, &qhp
->db_fc_entry
);
774 qhp
->wq
.sq
.wq_pidx_inc
+= inc
;
776 spin_unlock(&qhp
->lock
);
777 spin_unlock_irqrestore(&qhp
->rhp
->lock
, flags
);
781 static int ring_kernel_rq_db(struct c4iw_qp
*qhp
, u16 inc
)
785 spin_lock_irqsave(&qhp
->rhp
->lock
, flags
);
786 spin_lock(&qhp
->lock
);
787 if (qhp
->rhp
->db_state
== NORMAL
)
788 t4_ring_rq_db(&qhp
->wq
, inc
, NULL
);
790 add_to_fc_list(&qhp
->rhp
->db_fc_list
, &qhp
->db_fc_entry
);
791 qhp
->wq
.rq
.wq_pidx_inc
+= inc
;
793 spin_unlock(&qhp
->lock
);
794 spin_unlock_irqrestore(&qhp
->rhp
->lock
, flags
);
798 static void complete_sq_drain_wr(struct c4iw_qp
*qhp
, struct ib_send_wr
*wr
)
800 struct t4_cqe cqe
= {};
801 struct c4iw_cq
*schp
;
805 schp
= to_c4iw_cq(qhp
->ibqp
.send_cq
);
808 cqe
.u
.drain_cookie
= wr
->wr_id
;
809 cqe
.header
= cpu_to_be32(CQE_STATUS_V(T4_ERR_SWFLUSH
) |
810 CQE_OPCODE_V(C4IW_DRAIN_OPCODE
) |
813 CQE_QPID_V(qhp
->wq
.sq
.qid
));
815 spin_lock_irqsave(&schp
->lock
, flag
);
816 cqe
.bits_type_ts
= cpu_to_be64(CQE_GENBIT_V((u64
)cq
->gen
));
817 cq
->sw_queue
[cq
->sw_pidx
] = cqe
;
819 spin_unlock_irqrestore(&schp
->lock
, flag
);
821 spin_lock_irqsave(&schp
->comp_handler_lock
, flag
);
822 (*schp
->ibcq
.comp_handler
)(&schp
->ibcq
,
823 schp
->ibcq
.cq_context
);
824 spin_unlock_irqrestore(&schp
->comp_handler_lock
, flag
);
827 static void complete_rq_drain_wr(struct c4iw_qp
*qhp
, struct ib_recv_wr
*wr
)
829 struct t4_cqe cqe
= {};
830 struct c4iw_cq
*rchp
;
834 rchp
= to_c4iw_cq(qhp
->ibqp
.recv_cq
);
837 cqe
.u
.drain_cookie
= wr
->wr_id
;
838 cqe
.header
= cpu_to_be32(CQE_STATUS_V(T4_ERR_SWFLUSH
) |
839 CQE_OPCODE_V(C4IW_DRAIN_OPCODE
) |
842 CQE_QPID_V(qhp
->wq
.sq
.qid
));
844 spin_lock_irqsave(&rchp
->lock
, flag
);
845 cqe
.bits_type_ts
= cpu_to_be64(CQE_GENBIT_V((u64
)cq
->gen
));
846 cq
->sw_queue
[cq
->sw_pidx
] = cqe
;
848 spin_unlock_irqrestore(&rchp
->lock
, flag
);
850 spin_lock_irqsave(&rchp
->comp_handler_lock
, flag
);
851 (*rchp
->ibcq
.comp_handler
)(&rchp
->ibcq
,
852 rchp
->ibcq
.cq_context
);
853 spin_unlock_irqrestore(&rchp
->comp_handler_lock
, flag
);
856 int c4iw_post_send(struct ib_qp
*ibqp
, struct ib_send_wr
*wr
,
857 struct ib_send_wr
**bad_wr
)
861 enum fw_wr_opcodes fw_opcode
= 0;
862 enum fw_ri_wr_flags fw_flags
;
864 union t4_wr
*wqe
= NULL
;
866 struct t4_swsqe
*swsqe
;
870 qhp
= to_c4iw_qp(ibqp
);
871 spin_lock_irqsave(&qhp
->lock
, flag
);
872 if (t4_wq_in_error(&qhp
->wq
)) {
873 spin_unlock_irqrestore(&qhp
->lock
, flag
);
874 complete_sq_drain_wr(qhp
, wr
);
877 num_wrs
= t4_sq_avail(&qhp
->wq
);
879 spin_unlock_irqrestore(&qhp
->lock
, flag
);
889 wqe
= (union t4_wr
*)((u8
*)qhp
->wq
.sq
.queue
+
890 qhp
->wq
.sq
.wq_pidx
* T4_EQ_ENTRY_SIZE
);
893 if (wr
->send_flags
& IB_SEND_SOLICITED
)
894 fw_flags
|= FW_RI_SOLICITED_EVENT_FLAG
;
895 if (wr
->send_flags
& IB_SEND_SIGNALED
|| qhp
->sq_sig_all
)
896 fw_flags
|= FW_RI_COMPLETION_FLAG
;
897 swsqe
= &qhp
->wq
.sq
.sw_sq
[qhp
->wq
.sq
.pidx
];
898 switch (wr
->opcode
) {
899 case IB_WR_SEND_WITH_INV
:
901 if (wr
->send_flags
& IB_SEND_FENCE
)
902 fw_flags
|= FW_RI_READ_FENCE_FLAG
;
903 fw_opcode
= FW_RI_SEND_WR
;
904 if (wr
->opcode
== IB_WR_SEND
)
905 swsqe
->opcode
= FW_RI_SEND
;
907 swsqe
->opcode
= FW_RI_SEND_WITH_INV
;
908 err
= build_rdma_send(&qhp
->wq
.sq
, wqe
, wr
, &len16
);
910 case IB_WR_RDMA_WRITE
:
911 fw_opcode
= FW_RI_RDMA_WRITE_WR
;
912 swsqe
->opcode
= FW_RI_RDMA_WRITE
;
913 err
= build_rdma_write(&qhp
->wq
.sq
, wqe
, wr
, &len16
);
915 case IB_WR_RDMA_READ
:
916 case IB_WR_RDMA_READ_WITH_INV
:
917 fw_opcode
= FW_RI_RDMA_READ_WR
;
918 swsqe
->opcode
= FW_RI_READ_REQ
;
919 if (wr
->opcode
== IB_WR_RDMA_READ_WITH_INV
) {
920 c4iw_invalidate_mr(qhp
->rhp
,
921 wr
->sg_list
[0].lkey
);
922 fw_flags
= FW_RI_RDMA_READ_INVALIDATE
;
926 err
= build_rdma_read(wqe
, wr
, &len16
);
929 swsqe
->read_len
= wr
->sg_list
[0].length
;
930 if (!qhp
->wq
.sq
.oldest_read
)
931 qhp
->wq
.sq
.oldest_read
= swsqe
;
934 struct c4iw_mr
*mhp
= to_c4iw_mr(reg_wr(wr
)->mr
);
936 swsqe
->opcode
= FW_RI_FAST_REGISTER
;
937 if (qhp
->rhp
->rdev
.lldi
.fr_nsmr_tpte_wr_support
&&
938 !mhp
->attr
.state
&& mhp
->mpl_len
<= 2) {
939 fw_opcode
= FW_RI_FR_NSMR_TPTE_WR
;
940 build_tpte_memreg(&wqe
->fr_tpte
, reg_wr(wr
),
943 fw_opcode
= FW_RI_FR_NSMR_WR
;
944 err
= build_memreg(&qhp
->wq
.sq
, wqe
, reg_wr(wr
),
946 qhp
->rhp
->rdev
.lldi
.ulptx_memwrite_dsgl
);
953 case IB_WR_LOCAL_INV
:
954 if (wr
->send_flags
& IB_SEND_FENCE
)
955 fw_flags
|= FW_RI_LOCAL_FENCE_FLAG
;
956 fw_opcode
= FW_RI_INV_LSTAG_WR
;
957 swsqe
->opcode
= FW_RI_LOCAL_INV
;
958 err
= build_inv_stag(wqe
, wr
, &len16
);
959 c4iw_invalidate_mr(qhp
->rhp
, wr
->ex
.invalidate_rkey
);
962 PDBG("%s post of type=%d TBD!\n", __func__
,
970 swsqe
->idx
= qhp
->wq
.sq
.pidx
;
972 swsqe
->signaled
= (wr
->send_flags
& IB_SEND_SIGNALED
) ||
975 swsqe
->wr_id
= wr
->wr_id
;
977 swsqe
->sge_ts
= cxgb4_read_sge_timestamp(
978 qhp
->rhp
->rdev
.lldi
.ports
[0]);
979 getnstimeofday(&swsqe
->host_ts
);
982 init_wr_hdr(wqe
, qhp
->wq
.sq
.pidx
, fw_opcode
, fw_flags
, len16
);
984 PDBG("%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u\n",
985 __func__
, (unsigned long long)wr
->wr_id
, qhp
->wq
.sq
.pidx
,
986 swsqe
->opcode
, swsqe
->read_len
);
989 t4_sq_produce(&qhp
->wq
, len16
);
990 idx
+= DIV_ROUND_UP(len16
*16, T4_EQ_ENTRY_SIZE
);
992 if (!qhp
->rhp
->rdev
.status_page
->db_off
) {
993 t4_ring_sq_db(&qhp
->wq
, idx
, wqe
);
994 spin_unlock_irqrestore(&qhp
->lock
, flag
);
996 spin_unlock_irqrestore(&qhp
->lock
, flag
);
997 ring_kernel_sq_db(qhp
, idx
);
1002 int c4iw_post_receive(struct ib_qp
*ibqp
, struct ib_recv_wr
*wr
,
1003 struct ib_recv_wr
**bad_wr
)
1006 struct c4iw_qp
*qhp
;
1007 union t4_recv_wr
*wqe
= NULL
;
1013 qhp
= to_c4iw_qp(ibqp
);
1014 spin_lock_irqsave(&qhp
->lock
, flag
);
1015 if (t4_wq_in_error(&qhp
->wq
)) {
1016 spin_unlock_irqrestore(&qhp
->lock
, flag
);
1017 complete_rq_drain_wr(qhp
, wr
);
1020 num_wrs
= t4_rq_avail(&qhp
->wq
);
1022 spin_unlock_irqrestore(&qhp
->lock
, flag
);
1027 if (wr
->num_sge
> T4_MAX_RECV_SGE
) {
1032 wqe
= (union t4_recv_wr
*)((u8
*)qhp
->wq
.rq
.queue
+
1033 qhp
->wq
.rq
.wq_pidx
*
1036 err
= build_rdma_recv(qhp
, wqe
, wr
, &len16
);
1044 qhp
->wq
.rq
.sw_rq
[qhp
->wq
.rq
.pidx
].wr_id
= wr
->wr_id
;
1046 qhp
->wq
.rq
.sw_rq
[qhp
->wq
.rq
.pidx
].sge_ts
=
1047 cxgb4_read_sge_timestamp(
1048 qhp
->rhp
->rdev
.lldi
.ports
[0]);
1050 &qhp
->wq
.rq
.sw_rq
[qhp
->wq
.rq
.pidx
].host_ts
);
1053 wqe
->recv
.opcode
= FW_RI_RECV_WR
;
1055 wqe
->recv
.wrid
= qhp
->wq
.rq
.pidx
;
1056 wqe
->recv
.r2
[0] = 0;
1057 wqe
->recv
.r2
[1] = 0;
1058 wqe
->recv
.r2
[2] = 0;
1059 wqe
->recv
.len16
= len16
;
1060 PDBG("%s cookie 0x%llx pidx %u\n", __func__
,
1061 (unsigned long long) wr
->wr_id
, qhp
->wq
.rq
.pidx
);
1062 t4_rq_produce(&qhp
->wq
, len16
);
1063 idx
+= DIV_ROUND_UP(len16
*16, T4_EQ_ENTRY_SIZE
);
1067 if (!qhp
->rhp
->rdev
.status_page
->db_off
) {
1068 t4_ring_rq_db(&qhp
->wq
, idx
, wqe
);
1069 spin_unlock_irqrestore(&qhp
->lock
, flag
);
1071 spin_unlock_irqrestore(&qhp
->lock
, flag
);
1072 ring_kernel_rq_db(qhp
, idx
);
1077 static inline void build_term_codes(struct t4_cqe
*err_cqe
, u8
*layer_type
,
1087 *layer_type
= LAYER_RDMAP
|DDP_LOCAL_CATA
;
1092 status
= CQE_STATUS(err_cqe
);
1093 opcode
= CQE_OPCODE(err_cqe
);
1094 rqtype
= RQ_TYPE(err_cqe
);
1095 send_inv
= (opcode
== FW_RI_SEND_WITH_INV
) ||
1096 (opcode
== FW_RI_SEND_WITH_SE_INV
);
1097 tagged
= (opcode
== FW_RI_RDMA_WRITE
) ||
1098 (rqtype
&& (opcode
== FW_RI_READ_RESP
));
1103 *layer_type
= LAYER_RDMAP
|RDMAP_REMOTE_OP
;
1104 *ecode
= RDMAP_CANT_INV_STAG
;
1106 *layer_type
= LAYER_RDMAP
|RDMAP_REMOTE_PROT
;
1107 *ecode
= RDMAP_INV_STAG
;
1111 *layer_type
= LAYER_RDMAP
|RDMAP_REMOTE_PROT
;
1112 if ((opcode
== FW_RI_SEND_WITH_INV
) ||
1113 (opcode
== FW_RI_SEND_WITH_SE_INV
))
1114 *ecode
= RDMAP_CANT_INV_STAG
;
1116 *ecode
= RDMAP_STAG_NOT_ASSOC
;
1119 *layer_type
= LAYER_RDMAP
|RDMAP_REMOTE_PROT
;
1120 *ecode
= RDMAP_STAG_NOT_ASSOC
;
1123 *layer_type
= LAYER_RDMAP
|RDMAP_REMOTE_PROT
;
1124 *ecode
= RDMAP_ACC_VIOL
;
1127 *layer_type
= LAYER_RDMAP
|RDMAP_REMOTE_PROT
;
1128 *ecode
= RDMAP_TO_WRAP
;
1132 *layer_type
= LAYER_DDP
|DDP_TAGGED_ERR
;
1133 *ecode
= DDPT_BASE_BOUNDS
;
1135 *layer_type
= LAYER_RDMAP
|RDMAP_REMOTE_PROT
;
1136 *ecode
= RDMAP_BASE_BOUNDS
;
1139 case T4_ERR_INVALIDATE_SHARED_MR
:
1140 case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND
:
1141 *layer_type
= LAYER_RDMAP
|RDMAP_REMOTE_OP
;
1142 *ecode
= RDMAP_CANT_INV_STAG
;
1145 case T4_ERR_ECC_PSTAG
:
1146 case T4_ERR_INTERNAL_ERR
:
1147 *layer_type
= LAYER_RDMAP
|RDMAP_LOCAL_CATA
;
1150 case T4_ERR_OUT_OF_RQE
:
1151 *layer_type
= LAYER_DDP
|DDP_UNTAGGED_ERR
;
1152 *ecode
= DDPU_INV_MSN_NOBUF
;
1154 case T4_ERR_PBL_ADDR_BOUND
:
1155 *layer_type
= LAYER_DDP
|DDP_TAGGED_ERR
;
1156 *ecode
= DDPT_BASE_BOUNDS
;
1159 *layer_type
= LAYER_MPA
|DDP_LLP
;
1160 *ecode
= MPA_CRC_ERR
;
1163 *layer_type
= LAYER_MPA
|DDP_LLP
;
1164 *ecode
= MPA_MARKER_ERR
;
1166 case T4_ERR_PDU_LEN_ERR
:
1167 *layer_type
= LAYER_DDP
|DDP_UNTAGGED_ERR
;
1168 *ecode
= DDPU_MSG_TOOBIG
;
1170 case T4_ERR_DDP_VERSION
:
1172 *layer_type
= LAYER_DDP
|DDP_TAGGED_ERR
;
1173 *ecode
= DDPT_INV_VERS
;
1175 *layer_type
= LAYER_DDP
|DDP_UNTAGGED_ERR
;
1176 *ecode
= DDPU_INV_VERS
;
1179 case T4_ERR_RDMA_VERSION
:
1180 *layer_type
= LAYER_RDMAP
|RDMAP_REMOTE_OP
;
1181 *ecode
= RDMAP_INV_VERS
;
1184 *layer_type
= LAYER_RDMAP
|RDMAP_REMOTE_OP
;
1185 *ecode
= RDMAP_INV_OPCODE
;
1187 case T4_ERR_DDP_QUEUE_NUM
:
1188 *layer_type
= LAYER_DDP
|DDP_UNTAGGED_ERR
;
1189 *ecode
= DDPU_INV_QN
;
1192 case T4_ERR_MSN_GAP
:
1193 case T4_ERR_MSN_RANGE
:
1194 case T4_ERR_IRD_OVERFLOW
:
1195 *layer_type
= LAYER_DDP
|DDP_UNTAGGED_ERR
;
1196 *ecode
= DDPU_INV_MSN_RANGE
;
1199 *layer_type
= LAYER_DDP
|DDP_LOCAL_CATA
;
1203 *layer_type
= LAYER_DDP
|DDP_UNTAGGED_ERR
;
1204 *ecode
= DDPU_INV_MO
;
1207 *layer_type
= LAYER_RDMAP
|DDP_LOCAL_CATA
;
1213 static void post_terminate(struct c4iw_qp
*qhp
, struct t4_cqe
*err_cqe
,
1216 struct fw_ri_wr
*wqe
;
1217 struct sk_buff
*skb
;
1218 struct terminate_message
*term
;
1220 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__
, qhp
, qhp
->wq
.sq
.qid
,
1223 skb
= skb_dequeue(&qhp
->ep
->com
.ep_skb_list
);
1227 set_wr_txq(skb
, CPL_PRIORITY_DATA
, qhp
->ep
->txq_idx
);
1229 wqe
= (struct fw_ri_wr
*)__skb_put(skb
, sizeof(*wqe
));
1230 memset(wqe
, 0, sizeof *wqe
);
1231 wqe
->op_compl
= cpu_to_be32(FW_WR_OP_V(FW_RI_INIT_WR
));
1232 wqe
->flowid_len16
= cpu_to_be32(
1233 FW_WR_FLOWID_V(qhp
->ep
->hwtid
) |
1234 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe
), 16)));
1236 wqe
->u
.terminate
.type
= FW_RI_TYPE_TERMINATE
;
1237 wqe
->u
.terminate
.immdlen
= cpu_to_be32(sizeof *term
);
1238 term
= (struct terminate_message
*)wqe
->u
.terminate
.termmsg
;
1239 if (qhp
->attr
.layer_etype
== (LAYER_MPA
|DDP_LLP
)) {
1240 term
->layer_etype
= qhp
->attr
.layer_etype
;
1241 term
->ecode
= qhp
->attr
.ecode
;
1243 build_term_codes(err_cqe
, &term
->layer_etype
, &term
->ecode
);
1244 c4iw_ofld_send(&qhp
->rhp
->rdev
, skb
);
1248 * Assumes qhp lock is held.
1250 static void __flush_qp(struct c4iw_qp
*qhp
, struct c4iw_cq
*rchp
,
1251 struct c4iw_cq
*schp
)
1254 int rq_flushed
, sq_flushed
;
1257 PDBG("%s qhp %p rchp %p schp %p\n", __func__
, qhp
, rchp
, schp
);
1259 /* locking hierarchy: cq lock first, then qp lock. */
1260 spin_lock_irqsave(&rchp
->lock
, flag
);
1261 spin_lock(&qhp
->lock
);
1263 if (qhp
->wq
.flushed
) {
1264 spin_unlock(&qhp
->lock
);
1265 spin_unlock_irqrestore(&rchp
->lock
, flag
);
1268 qhp
->wq
.flushed
= 1;
1270 c4iw_flush_hw_cq(rchp
);
1271 c4iw_count_rcqes(&rchp
->cq
, &qhp
->wq
, &count
);
1272 rq_flushed
= c4iw_flush_rq(&qhp
->wq
, &rchp
->cq
, count
);
1273 spin_unlock(&qhp
->lock
);
1274 spin_unlock_irqrestore(&rchp
->lock
, flag
);
1276 /* locking hierarchy: cq lock first, then qp lock. */
1277 spin_lock_irqsave(&schp
->lock
, flag
);
1278 spin_lock(&qhp
->lock
);
1280 c4iw_flush_hw_cq(schp
);
1281 sq_flushed
= c4iw_flush_sq(qhp
);
1282 spin_unlock(&qhp
->lock
);
1283 spin_unlock_irqrestore(&schp
->lock
, flag
);
1286 if (t4_clear_cq_armed(&rchp
->cq
) &&
1287 (rq_flushed
|| sq_flushed
)) {
1288 spin_lock_irqsave(&rchp
->comp_handler_lock
, flag
);
1289 (*rchp
->ibcq
.comp_handler
)(&rchp
->ibcq
,
1290 rchp
->ibcq
.cq_context
);
1291 spin_unlock_irqrestore(&rchp
->comp_handler_lock
, flag
);
1294 if (t4_clear_cq_armed(&rchp
->cq
) && rq_flushed
) {
1295 spin_lock_irqsave(&rchp
->comp_handler_lock
, flag
);
1296 (*rchp
->ibcq
.comp_handler
)(&rchp
->ibcq
,
1297 rchp
->ibcq
.cq_context
);
1298 spin_unlock_irqrestore(&rchp
->comp_handler_lock
, flag
);
1300 if (t4_clear_cq_armed(&schp
->cq
) && sq_flushed
) {
1301 spin_lock_irqsave(&schp
->comp_handler_lock
, flag
);
1302 (*schp
->ibcq
.comp_handler
)(&schp
->ibcq
,
1303 schp
->ibcq
.cq_context
);
1304 spin_unlock_irqrestore(&schp
->comp_handler_lock
, flag
);
1309 static void flush_qp(struct c4iw_qp
*qhp
)
1311 struct c4iw_cq
*rchp
, *schp
;
1314 rchp
= to_c4iw_cq(qhp
->ibqp
.recv_cq
);
1315 schp
= to_c4iw_cq(qhp
->ibqp
.send_cq
);
1317 t4_set_wq_in_error(&qhp
->wq
);
1318 if (qhp
->ibqp
.uobject
) {
1319 t4_set_cq_in_error(&rchp
->cq
);
1320 spin_lock_irqsave(&rchp
->comp_handler_lock
, flag
);
1321 (*rchp
->ibcq
.comp_handler
)(&rchp
->ibcq
, rchp
->ibcq
.cq_context
);
1322 spin_unlock_irqrestore(&rchp
->comp_handler_lock
, flag
);
1324 t4_set_cq_in_error(&schp
->cq
);
1325 spin_lock_irqsave(&schp
->comp_handler_lock
, flag
);
1326 (*schp
->ibcq
.comp_handler
)(&schp
->ibcq
,
1327 schp
->ibcq
.cq_context
);
1328 spin_unlock_irqrestore(&schp
->comp_handler_lock
, flag
);
1332 __flush_qp(qhp
, rchp
, schp
);
1335 static int rdma_fini(struct c4iw_dev
*rhp
, struct c4iw_qp
*qhp
,
1338 struct fw_ri_wr
*wqe
;
1340 struct sk_buff
*skb
;
1342 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__
, qhp
, qhp
->wq
.sq
.qid
,
1345 skb
= skb_dequeue(&ep
->com
.ep_skb_list
);
1349 set_wr_txq(skb
, CPL_PRIORITY_DATA
, ep
->txq_idx
);
1351 wqe
= (struct fw_ri_wr
*)__skb_put(skb
, sizeof(*wqe
));
1352 memset(wqe
, 0, sizeof *wqe
);
1353 wqe
->op_compl
= cpu_to_be32(
1354 FW_WR_OP_V(FW_RI_INIT_WR
) |
1356 wqe
->flowid_len16
= cpu_to_be32(
1357 FW_WR_FLOWID_V(ep
->hwtid
) |
1358 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe
), 16)));
1359 wqe
->cookie
= (uintptr_t)&ep
->com
.wr_wait
;
1361 wqe
->u
.fini
.type
= FW_RI_TYPE_FINI
;
1362 ret
= c4iw_ofld_send(&rhp
->rdev
, skb
);
1366 ret
= c4iw_wait_for_reply(&rhp
->rdev
, &ep
->com
.wr_wait
, qhp
->ep
->hwtid
,
1367 qhp
->wq
.sq
.qid
, __func__
);
1369 PDBG("%s ret %d\n", __func__
, ret
);
1373 static void build_rtr_msg(u8 p2p_type
, struct fw_ri_init
*init
)
1375 PDBG("%s p2p_type = %d\n", __func__
, p2p_type
);
1376 memset(&init
->u
, 0, sizeof init
->u
);
1378 case FW_RI_INIT_P2PTYPE_RDMA_WRITE
:
1379 init
->u
.write
.opcode
= FW_RI_RDMA_WRITE_WR
;
1380 init
->u
.write
.stag_sink
= cpu_to_be32(1);
1381 init
->u
.write
.to_sink
= cpu_to_be64(1);
1382 init
->u
.write
.u
.immd_src
[0].op
= FW_RI_DATA_IMMD
;
1383 init
->u
.write
.len16
= DIV_ROUND_UP(sizeof init
->u
.write
+
1384 sizeof(struct fw_ri_immd
),
1387 case FW_RI_INIT_P2PTYPE_READ_REQ
:
1388 init
->u
.write
.opcode
= FW_RI_RDMA_READ_WR
;
1389 init
->u
.read
.stag_src
= cpu_to_be32(1);
1390 init
->u
.read
.to_src_lo
= cpu_to_be32(1);
1391 init
->u
.read
.stag_sink
= cpu_to_be32(1);
1392 init
->u
.read
.to_sink_lo
= cpu_to_be32(1);
1393 init
->u
.read
.len16
= DIV_ROUND_UP(sizeof init
->u
.read
, 16);
1398 static int rdma_init(struct c4iw_dev
*rhp
, struct c4iw_qp
*qhp
)
1400 struct fw_ri_wr
*wqe
;
1402 struct sk_buff
*skb
;
1404 PDBG("%s qhp %p qid 0x%x tid %u ird %u ord %u\n", __func__
, qhp
,
1405 qhp
->wq
.sq
.qid
, qhp
->ep
->hwtid
, qhp
->ep
->ird
, qhp
->ep
->ord
);
1407 skb
= alloc_skb(sizeof *wqe
, GFP_KERNEL
);
1412 ret
= alloc_ird(rhp
, qhp
->attr
.max_ird
);
1414 qhp
->attr
.max_ird
= 0;
1418 set_wr_txq(skb
, CPL_PRIORITY_DATA
, qhp
->ep
->txq_idx
);
1420 wqe
= (struct fw_ri_wr
*)__skb_put(skb
, sizeof(*wqe
));
1421 memset(wqe
, 0, sizeof *wqe
);
1422 wqe
->op_compl
= cpu_to_be32(
1423 FW_WR_OP_V(FW_RI_INIT_WR
) |
1425 wqe
->flowid_len16
= cpu_to_be32(
1426 FW_WR_FLOWID_V(qhp
->ep
->hwtid
) |
1427 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe
), 16)));
1429 wqe
->cookie
= (uintptr_t)&qhp
->ep
->com
.wr_wait
;
1431 wqe
->u
.init
.type
= FW_RI_TYPE_INIT
;
1432 wqe
->u
.init
.mpareqbit_p2ptype
=
1433 FW_RI_WR_MPAREQBIT_V(qhp
->attr
.mpa_attr
.initiator
) |
1434 FW_RI_WR_P2PTYPE_V(qhp
->attr
.mpa_attr
.p2p_type
);
1435 wqe
->u
.init
.mpa_attrs
= FW_RI_MPA_IETF_ENABLE
;
1436 if (qhp
->attr
.mpa_attr
.recv_marker_enabled
)
1437 wqe
->u
.init
.mpa_attrs
|= FW_RI_MPA_RX_MARKER_ENABLE
;
1438 if (qhp
->attr
.mpa_attr
.xmit_marker_enabled
)
1439 wqe
->u
.init
.mpa_attrs
|= FW_RI_MPA_TX_MARKER_ENABLE
;
1440 if (qhp
->attr
.mpa_attr
.crc_enabled
)
1441 wqe
->u
.init
.mpa_attrs
|= FW_RI_MPA_CRC_ENABLE
;
1443 wqe
->u
.init
.qp_caps
= FW_RI_QP_RDMA_READ_ENABLE
|
1444 FW_RI_QP_RDMA_WRITE_ENABLE
|
1445 FW_RI_QP_BIND_ENABLE
;
1446 if (!qhp
->ibqp
.uobject
)
1447 wqe
->u
.init
.qp_caps
|= FW_RI_QP_FAST_REGISTER_ENABLE
|
1448 FW_RI_QP_STAG0_ENABLE
;
1449 wqe
->u
.init
.nrqe
= cpu_to_be16(t4_rqes_posted(&qhp
->wq
));
1450 wqe
->u
.init
.pdid
= cpu_to_be32(qhp
->attr
.pd
);
1451 wqe
->u
.init
.qpid
= cpu_to_be32(qhp
->wq
.sq
.qid
);
1452 wqe
->u
.init
.sq_eqid
= cpu_to_be32(qhp
->wq
.sq
.qid
);
1453 wqe
->u
.init
.rq_eqid
= cpu_to_be32(qhp
->wq
.rq
.qid
);
1454 wqe
->u
.init
.scqid
= cpu_to_be32(qhp
->attr
.scq
);
1455 wqe
->u
.init
.rcqid
= cpu_to_be32(qhp
->attr
.rcq
);
1456 wqe
->u
.init
.ord_max
= cpu_to_be32(qhp
->attr
.max_ord
);
1457 wqe
->u
.init
.ird_max
= cpu_to_be32(qhp
->attr
.max_ird
);
1458 wqe
->u
.init
.iss
= cpu_to_be32(qhp
->ep
->snd_seq
);
1459 wqe
->u
.init
.irs
= cpu_to_be32(qhp
->ep
->rcv_seq
);
1460 wqe
->u
.init
.hwrqsize
= cpu_to_be32(qhp
->wq
.rq
.rqt_size
);
1461 wqe
->u
.init
.hwrqaddr
= cpu_to_be32(qhp
->wq
.rq
.rqt_hwaddr
-
1462 rhp
->rdev
.lldi
.vr
->rq
.start
);
1463 if (qhp
->attr
.mpa_attr
.initiator
)
1464 build_rtr_msg(qhp
->attr
.mpa_attr
.p2p_type
, &wqe
->u
.init
);
1466 ret
= c4iw_ofld_send(&rhp
->rdev
, skb
);
1470 ret
= c4iw_wait_for_reply(&rhp
->rdev
, &qhp
->ep
->com
.wr_wait
,
1471 qhp
->ep
->hwtid
, qhp
->wq
.sq
.qid
, __func__
);
1475 free_ird(rhp
, qhp
->attr
.max_ird
);
1477 PDBG("%s ret %d\n", __func__
, ret
);
1481 int c4iw_modify_qp(struct c4iw_dev
*rhp
, struct c4iw_qp
*qhp
,
1482 enum c4iw_qp_attr_mask mask
,
1483 struct c4iw_qp_attributes
*attrs
,
1487 struct c4iw_qp_attributes newattr
= qhp
->attr
;
1492 struct c4iw_ep
*ep
= NULL
;
1494 PDBG("%s qhp %p sqid 0x%x rqid 0x%x ep %p state %d -> %d\n", __func__
,
1495 qhp
, qhp
->wq
.sq
.qid
, qhp
->wq
.rq
.qid
, qhp
->ep
, qhp
->attr
.state
,
1496 (mask
& C4IW_QP_ATTR_NEXT_STATE
) ? attrs
->next_state
: -1);
1498 mutex_lock(&qhp
->mutex
);
1500 /* Process attr changes if in IDLE */
1501 if (mask
& C4IW_QP_ATTR_VALID_MODIFY
) {
1502 if (qhp
->attr
.state
!= C4IW_QP_STATE_IDLE
) {
1506 if (mask
& C4IW_QP_ATTR_ENABLE_RDMA_READ
)
1507 newattr
.enable_rdma_read
= attrs
->enable_rdma_read
;
1508 if (mask
& C4IW_QP_ATTR_ENABLE_RDMA_WRITE
)
1509 newattr
.enable_rdma_write
= attrs
->enable_rdma_write
;
1510 if (mask
& C4IW_QP_ATTR_ENABLE_RDMA_BIND
)
1511 newattr
.enable_bind
= attrs
->enable_bind
;
1512 if (mask
& C4IW_QP_ATTR_MAX_ORD
) {
1513 if (attrs
->max_ord
> c4iw_max_read_depth
) {
1517 newattr
.max_ord
= attrs
->max_ord
;
1519 if (mask
& C4IW_QP_ATTR_MAX_IRD
) {
1520 if (attrs
->max_ird
> cur_max_read_depth(rhp
)) {
1524 newattr
.max_ird
= attrs
->max_ird
;
1526 qhp
->attr
= newattr
;
1529 if (mask
& C4IW_QP_ATTR_SQ_DB
) {
1530 ret
= ring_kernel_sq_db(qhp
, attrs
->sq_db_inc
);
1533 if (mask
& C4IW_QP_ATTR_RQ_DB
) {
1534 ret
= ring_kernel_rq_db(qhp
, attrs
->rq_db_inc
);
1538 if (!(mask
& C4IW_QP_ATTR_NEXT_STATE
))
1540 if (qhp
->attr
.state
== attrs
->next_state
)
1543 switch (qhp
->attr
.state
) {
1544 case C4IW_QP_STATE_IDLE
:
1545 switch (attrs
->next_state
) {
1546 case C4IW_QP_STATE_RTS
:
1547 if (!(mask
& C4IW_QP_ATTR_LLP_STREAM_HANDLE
)) {
1551 if (!(mask
& C4IW_QP_ATTR_MPA_ATTR
)) {
1555 qhp
->attr
.mpa_attr
= attrs
->mpa_attr
;
1556 qhp
->attr
.llp_stream_handle
= attrs
->llp_stream_handle
;
1557 qhp
->ep
= qhp
->attr
.llp_stream_handle
;
1558 set_state(qhp
, C4IW_QP_STATE_RTS
);
1561 * Ref the endpoint here and deref when we
1562 * disassociate the endpoint from the QP. This
1563 * happens in CLOSING->IDLE transition or *->ERROR
1566 c4iw_get_ep(&qhp
->ep
->com
);
1567 ret
= rdma_init(rhp
, qhp
);
1571 case C4IW_QP_STATE_ERROR
:
1572 set_state(qhp
, C4IW_QP_STATE_ERROR
);
1580 case C4IW_QP_STATE_RTS
:
1581 switch (attrs
->next_state
) {
1582 case C4IW_QP_STATE_CLOSING
:
1583 BUG_ON(kref_read(&qhp
->ep
->com
.kref
) < 2);
1584 t4_set_wq_in_error(&qhp
->wq
);
1585 set_state(qhp
, C4IW_QP_STATE_CLOSING
);
1590 c4iw_get_ep(&qhp
->ep
->com
);
1592 ret
= rdma_fini(rhp
, qhp
, ep
);
1596 case C4IW_QP_STATE_TERMINATE
:
1597 t4_set_wq_in_error(&qhp
->wq
);
1598 set_state(qhp
, C4IW_QP_STATE_TERMINATE
);
1599 qhp
->attr
.layer_etype
= attrs
->layer_etype
;
1600 qhp
->attr
.ecode
= attrs
->ecode
;
1603 c4iw_get_ep(&qhp
->ep
->com
);
1607 terminate
= qhp
->attr
.send_term
;
1608 ret
= rdma_fini(rhp
, qhp
, ep
);
1613 case C4IW_QP_STATE_ERROR
:
1614 t4_set_wq_in_error(&qhp
->wq
);
1615 set_state(qhp
, C4IW_QP_STATE_ERROR
);
1620 c4iw_get_ep(&qhp
->ep
->com
);
1629 case C4IW_QP_STATE_CLOSING
:
1632 * Allow kernel users to move to ERROR for qp draining.
1634 if (!internal
&& (qhp
->ibqp
.uobject
|| attrs
->next_state
!=
1635 C4IW_QP_STATE_ERROR
)) {
1639 switch (attrs
->next_state
) {
1640 case C4IW_QP_STATE_IDLE
:
1642 set_state(qhp
, C4IW_QP_STATE_IDLE
);
1643 qhp
->attr
.llp_stream_handle
= NULL
;
1644 c4iw_put_ep(&qhp
->ep
->com
);
1646 wake_up(&qhp
->wait
);
1648 case C4IW_QP_STATE_ERROR
:
1655 case C4IW_QP_STATE_ERROR
:
1656 if (attrs
->next_state
!= C4IW_QP_STATE_IDLE
) {
1660 if (!t4_sq_empty(&qhp
->wq
) || !t4_rq_empty(&qhp
->wq
)) {
1664 set_state(qhp
, C4IW_QP_STATE_IDLE
);
1666 case C4IW_QP_STATE_TERMINATE
:
1674 printk(KERN_ERR
"%s in a bad state %d\n",
1675 __func__
, qhp
->attr
.state
);
1682 PDBG("%s disassociating ep %p qpid 0x%x\n", __func__
, qhp
->ep
,
1685 /* disassociate the LLP connection */
1686 qhp
->attr
.llp_stream_handle
= NULL
;
1690 set_state(qhp
, C4IW_QP_STATE_ERROR
);
1695 wake_up(&qhp
->wait
);
1697 mutex_unlock(&qhp
->mutex
);
1700 post_terminate(qhp
, NULL
, internal
? GFP_ATOMIC
: GFP_KERNEL
);
1703 * If disconnect is 1, then we need to initiate a disconnect
1704 * on the EP. This can be a normal close (RTS->CLOSING) or
1705 * an abnormal close (RTS/CLOSING->ERROR).
1708 c4iw_ep_disconnect(ep
, abort
, internal
? GFP_ATOMIC
:
1710 c4iw_put_ep(&ep
->com
);
1714 * If free is 1, then we've disassociated the EP from the QP
1715 * and we need to dereference the EP.
1718 c4iw_put_ep(&ep
->com
);
1719 PDBG("%s exit state %d\n", __func__
, qhp
->attr
.state
);
1723 int c4iw_destroy_qp(struct ib_qp
*ib_qp
)
1725 struct c4iw_dev
*rhp
;
1726 struct c4iw_qp
*qhp
;
1727 struct c4iw_qp_attributes attrs
;
1729 qhp
= to_c4iw_qp(ib_qp
);
1732 attrs
.next_state
= C4IW_QP_STATE_ERROR
;
1733 if (qhp
->attr
.state
== C4IW_QP_STATE_TERMINATE
)
1734 c4iw_modify_qp(rhp
, qhp
, C4IW_QP_ATTR_NEXT_STATE
, &attrs
, 1);
1736 c4iw_modify_qp(rhp
, qhp
, C4IW_QP_ATTR_NEXT_STATE
, &attrs
, 0);
1737 wait_event(qhp
->wait
, !qhp
->ep
);
1739 remove_handle(rhp
, &rhp
->qpidr
, qhp
->wq
.sq
.qid
);
1741 spin_lock_irq(&rhp
->lock
);
1742 if (!list_empty(&qhp
->db_fc_entry
))
1743 list_del_init(&qhp
->db_fc_entry
);
1744 spin_unlock_irq(&rhp
->lock
);
1745 free_ird(rhp
, qhp
->attr
.max_ird
);
1747 c4iw_qp_rem_ref(ib_qp
);
1749 PDBG("%s ib_qp %p qpid 0x%0x\n", __func__
, ib_qp
, qhp
->wq
.sq
.qid
);
1753 struct ib_qp
*c4iw_create_qp(struct ib_pd
*pd
, struct ib_qp_init_attr
*attrs
,
1754 struct ib_udata
*udata
)
1756 struct c4iw_dev
*rhp
;
1757 struct c4iw_qp
*qhp
;
1758 struct c4iw_pd
*php
;
1759 struct c4iw_cq
*schp
;
1760 struct c4iw_cq
*rchp
;
1761 struct c4iw_create_qp_resp uresp
;
1762 unsigned int sqsize
, rqsize
;
1763 struct c4iw_ucontext
*ucontext
;
1765 struct c4iw_mm_entry
*sq_key_mm
, *rq_key_mm
= NULL
, *sq_db_key_mm
;
1766 struct c4iw_mm_entry
*rq_db_key_mm
= NULL
, *ma_sync_key_mm
= NULL
;
1768 PDBG("%s ib_pd %p\n", __func__
, pd
);
1770 if (attrs
->qp_type
!= IB_QPT_RC
)
1771 return ERR_PTR(-EINVAL
);
1773 php
= to_c4iw_pd(pd
);
1775 schp
= get_chp(rhp
, ((struct c4iw_cq
*)attrs
->send_cq
)->cq
.cqid
);
1776 rchp
= get_chp(rhp
, ((struct c4iw_cq
*)attrs
->recv_cq
)->cq
.cqid
);
1778 return ERR_PTR(-EINVAL
);
1780 if (attrs
->cap
.max_inline_data
> T4_MAX_SEND_INLINE
)
1781 return ERR_PTR(-EINVAL
);
1783 if (attrs
->cap
.max_recv_wr
> rhp
->rdev
.hw_queue
.t4_max_rq_size
)
1784 return ERR_PTR(-E2BIG
);
1785 rqsize
= attrs
->cap
.max_recv_wr
+ 1;
1789 if (attrs
->cap
.max_send_wr
> rhp
->rdev
.hw_queue
.t4_max_sq_size
)
1790 return ERR_PTR(-E2BIG
);
1791 sqsize
= attrs
->cap
.max_send_wr
+ 1;
1795 ucontext
= pd
->uobject
? to_c4iw_ucontext(pd
->uobject
->context
) : NULL
;
1797 qhp
= kzalloc(sizeof(*qhp
), GFP_KERNEL
);
1799 return ERR_PTR(-ENOMEM
);
1800 qhp
->wq
.sq
.size
= sqsize
;
1801 qhp
->wq
.sq
.memsize
=
1802 (sqsize
+ rhp
->rdev
.hw_queue
.t4_eq_status_entries
) *
1803 sizeof(*qhp
->wq
.sq
.queue
) + 16 * sizeof(__be64
);
1804 qhp
->wq
.sq
.flush_cidx
= -1;
1805 qhp
->wq
.rq
.size
= rqsize
;
1806 qhp
->wq
.rq
.memsize
=
1807 (rqsize
+ rhp
->rdev
.hw_queue
.t4_eq_status_entries
) *
1808 sizeof(*qhp
->wq
.rq
.queue
);
1811 qhp
->wq
.sq
.memsize
= roundup(qhp
->wq
.sq
.memsize
, PAGE_SIZE
);
1812 qhp
->wq
.rq
.memsize
= roundup(qhp
->wq
.rq
.memsize
, PAGE_SIZE
);
1815 ret
= create_qp(&rhp
->rdev
, &qhp
->wq
, &schp
->cq
, &rchp
->cq
,
1816 ucontext
? &ucontext
->uctx
: &rhp
->rdev
.uctx
);
1820 attrs
->cap
.max_recv_wr
= rqsize
- 1;
1821 attrs
->cap
.max_send_wr
= sqsize
- 1;
1822 attrs
->cap
.max_inline_data
= T4_MAX_SEND_INLINE
;
1825 qhp
->attr
.pd
= php
->pdid
;
1826 qhp
->attr
.scq
= ((struct c4iw_cq
*) attrs
->send_cq
)->cq
.cqid
;
1827 qhp
->attr
.rcq
= ((struct c4iw_cq
*) attrs
->recv_cq
)->cq
.cqid
;
1828 qhp
->attr
.sq_num_entries
= attrs
->cap
.max_send_wr
;
1829 qhp
->attr
.rq_num_entries
= attrs
->cap
.max_recv_wr
;
1830 qhp
->attr
.sq_max_sges
= attrs
->cap
.max_send_sge
;
1831 qhp
->attr
.sq_max_sges_rdma_write
= attrs
->cap
.max_send_sge
;
1832 qhp
->attr
.rq_max_sges
= attrs
->cap
.max_recv_sge
;
1833 qhp
->attr
.state
= C4IW_QP_STATE_IDLE
;
1834 qhp
->attr
.next_state
= C4IW_QP_STATE_IDLE
;
1835 qhp
->attr
.enable_rdma_read
= 1;
1836 qhp
->attr
.enable_rdma_write
= 1;
1837 qhp
->attr
.enable_bind
= 1;
1838 qhp
->attr
.max_ord
= 0;
1839 qhp
->attr
.max_ird
= 0;
1840 qhp
->sq_sig_all
= attrs
->sq_sig_type
== IB_SIGNAL_ALL_WR
;
1841 spin_lock_init(&qhp
->lock
);
1842 mutex_init(&qhp
->mutex
);
1843 init_waitqueue_head(&qhp
->wait
);
1844 kref_init(&qhp
->kref
);
1845 INIT_WORK(&qhp
->free_work
, free_qp_work
);
1847 ret
= insert_handle(rhp
, &rhp
->qpidr
, qhp
, qhp
->wq
.sq
.qid
);
1852 sq_key_mm
= kmalloc(sizeof(*sq_key_mm
), GFP_KERNEL
);
1857 rq_key_mm
= kmalloc(sizeof(*rq_key_mm
), GFP_KERNEL
);
1862 sq_db_key_mm
= kmalloc(sizeof(*sq_db_key_mm
), GFP_KERNEL
);
1863 if (!sq_db_key_mm
) {
1867 rq_db_key_mm
= kmalloc(sizeof(*rq_db_key_mm
), GFP_KERNEL
);
1868 if (!rq_db_key_mm
) {
1872 if (t4_sq_onchip(&qhp
->wq
.sq
)) {
1873 ma_sync_key_mm
= kmalloc(sizeof(*ma_sync_key_mm
),
1875 if (!ma_sync_key_mm
) {
1879 uresp
.flags
= C4IW_QPF_ONCHIP
;
1882 uresp
.qid_mask
= rhp
->rdev
.qpmask
;
1883 uresp
.sqid
= qhp
->wq
.sq
.qid
;
1884 uresp
.sq_size
= qhp
->wq
.sq
.size
;
1885 uresp
.sq_memsize
= qhp
->wq
.sq
.memsize
;
1886 uresp
.rqid
= qhp
->wq
.rq
.qid
;
1887 uresp
.rq_size
= qhp
->wq
.rq
.size
;
1888 uresp
.rq_memsize
= qhp
->wq
.rq
.memsize
;
1889 spin_lock(&ucontext
->mmap_lock
);
1890 if (ma_sync_key_mm
) {
1891 uresp
.ma_sync_key
= ucontext
->key
;
1892 ucontext
->key
+= PAGE_SIZE
;
1894 uresp
.ma_sync_key
= 0;
1896 uresp
.sq_key
= ucontext
->key
;
1897 ucontext
->key
+= PAGE_SIZE
;
1898 uresp
.rq_key
= ucontext
->key
;
1899 ucontext
->key
+= PAGE_SIZE
;
1900 uresp
.sq_db_gts_key
= ucontext
->key
;
1901 ucontext
->key
+= PAGE_SIZE
;
1902 uresp
.rq_db_gts_key
= ucontext
->key
;
1903 ucontext
->key
+= PAGE_SIZE
;
1904 spin_unlock(&ucontext
->mmap_lock
);
1905 ret
= ib_copy_to_udata(udata
, &uresp
, sizeof uresp
);
1908 sq_key_mm
->key
= uresp
.sq_key
;
1909 sq_key_mm
->addr
= qhp
->wq
.sq
.phys_addr
;
1910 sq_key_mm
->len
= PAGE_ALIGN(qhp
->wq
.sq
.memsize
);
1911 insert_mmap(ucontext
, sq_key_mm
);
1912 rq_key_mm
->key
= uresp
.rq_key
;
1913 rq_key_mm
->addr
= virt_to_phys(qhp
->wq
.rq
.queue
);
1914 rq_key_mm
->len
= PAGE_ALIGN(qhp
->wq
.rq
.memsize
);
1915 insert_mmap(ucontext
, rq_key_mm
);
1916 sq_db_key_mm
->key
= uresp
.sq_db_gts_key
;
1917 sq_db_key_mm
->addr
= (u64
)(unsigned long)qhp
->wq
.sq
.bar2_pa
;
1918 sq_db_key_mm
->len
= PAGE_SIZE
;
1919 insert_mmap(ucontext
, sq_db_key_mm
);
1920 rq_db_key_mm
->key
= uresp
.rq_db_gts_key
;
1921 rq_db_key_mm
->addr
= (u64
)(unsigned long)qhp
->wq
.rq
.bar2_pa
;
1922 rq_db_key_mm
->len
= PAGE_SIZE
;
1923 insert_mmap(ucontext
, rq_db_key_mm
);
1924 if (ma_sync_key_mm
) {
1925 ma_sync_key_mm
->key
= uresp
.ma_sync_key
;
1926 ma_sync_key_mm
->addr
=
1927 (pci_resource_start(rhp
->rdev
.lldi
.pdev
, 0) +
1928 PCIE_MA_SYNC_A
) & PAGE_MASK
;
1929 ma_sync_key_mm
->len
= PAGE_SIZE
;
1930 insert_mmap(ucontext
, ma_sync_key_mm
);
1933 c4iw_get_ucontext(ucontext
);
1934 qhp
->ucontext
= ucontext
;
1936 qhp
->ibqp
.qp_num
= qhp
->wq
.sq
.qid
;
1937 init_timer(&(qhp
->timer
));
1938 INIT_LIST_HEAD(&qhp
->db_fc_entry
);
1939 PDBG("%s sq id %u size %u memsize %zu num_entries %u "
1940 "rq id %u size %u memsize %zu num_entries %u\n", __func__
,
1941 qhp
->wq
.sq
.qid
, qhp
->wq
.sq
.size
, qhp
->wq
.sq
.memsize
,
1942 attrs
->cap
.max_send_wr
, qhp
->wq
.rq
.qid
, qhp
->wq
.rq
.size
,
1943 qhp
->wq
.rq
.memsize
, attrs
->cap
.max_recv_wr
);
1946 kfree(ma_sync_key_mm
);
1948 kfree(rq_db_key_mm
);
1950 kfree(sq_db_key_mm
);
1956 remove_handle(rhp
, &rhp
->qpidr
, qhp
->wq
.sq
.qid
);
1958 destroy_qp(&rhp
->rdev
, &qhp
->wq
,
1959 ucontext
? &ucontext
->uctx
: &rhp
->rdev
.uctx
);
1962 return ERR_PTR(ret
);
1965 int c4iw_ib_modify_qp(struct ib_qp
*ibqp
, struct ib_qp_attr
*attr
,
1966 int attr_mask
, struct ib_udata
*udata
)
1968 struct c4iw_dev
*rhp
;
1969 struct c4iw_qp
*qhp
;
1970 enum c4iw_qp_attr_mask mask
= 0;
1971 struct c4iw_qp_attributes attrs
;
1973 PDBG("%s ib_qp %p\n", __func__
, ibqp
);
1975 /* iwarp does not support the RTR state */
1976 if ((attr_mask
& IB_QP_STATE
) && (attr
->qp_state
== IB_QPS_RTR
))
1977 attr_mask
&= ~IB_QP_STATE
;
1979 /* Make sure we still have something left to do */
1983 memset(&attrs
, 0, sizeof attrs
);
1984 qhp
= to_c4iw_qp(ibqp
);
1987 attrs
.next_state
= c4iw_convert_state(attr
->qp_state
);
1988 attrs
.enable_rdma_read
= (attr
->qp_access_flags
&
1989 IB_ACCESS_REMOTE_READ
) ? 1 : 0;
1990 attrs
.enable_rdma_write
= (attr
->qp_access_flags
&
1991 IB_ACCESS_REMOTE_WRITE
) ? 1 : 0;
1992 attrs
.enable_bind
= (attr
->qp_access_flags
& IB_ACCESS_MW_BIND
) ? 1 : 0;
1995 mask
|= (attr_mask
& IB_QP_STATE
) ? C4IW_QP_ATTR_NEXT_STATE
: 0;
1996 mask
|= (attr_mask
& IB_QP_ACCESS_FLAGS
) ?
1997 (C4IW_QP_ATTR_ENABLE_RDMA_READ
|
1998 C4IW_QP_ATTR_ENABLE_RDMA_WRITE
|
1999 C4IW_QP_ATTR_ENABLE_RDMA_BIND
) : 0;
2002 * Use SQ_PSN and RQ_PSN to pass in IDX_INC values for
2003 * ringing the queue db when we're in DB_FULL mode.
2004 * Only allow this on T4 devices.
2006 attrs
.sq_db_inc
= attr
->sq_psn
;
2007 attrs
.rq_db_inc
= attr
->rq_psn
;
2008 mask
|= (attr_mask
& IB_QP_SQ_PSN
) ? C4IW_QP_ATTR_SQ_DB
: 0;
2009 mask
|= (attr_mask
& IB_QP_RQ_PSN
) ? C4IW_QP_ATTR_RQ_DB
: 0;
2010 if (!is_t4(to_c4iw_qp(ibqp
)->rhp
->rdev
.lldi
.adapter_type
) &&
2011 (mask
& (C4IW_QP_ATTR_SQ_DB
|C4IW_QP_ATTR_RQ_DB
)))
2014 return c4iw_modify_qp(rhp
, qhp
, mask
, &attrs
, 0);
2017 struct ib_qp
*c4iw_get_qp(struct ib_device
*dev
, int qpn
)
2019 PDBG("%s ib_dev %p qpn 0x%x\n", __func__
, dev
, qpn
);
2020 return (struct ib_qp
*)get_qhp(to_c4iw_dev(dev
), qpn
);
2023 int c4iw_ib_query_qp(struct ib_qp
*ibqp
, struct ib_qp_attr
*attr
,
2024 int attr_mask
, struct ib_qp_init_attr
*init_attr
)
2026 struct c4iw_qp
*qhp
= to_c4iw_qp(ibqp
);
2028 memset(attr
, 0, sizeof *attr
);
2029 memset(init_attr
, 0, sizeof *init_attr
);
2030 attr
->qp_state
= to_ib_qp_state(qhp
->attr
.state
);
2031 init_attr
->cap
.max_send_wr
= qhp
->attr
.sq_num_entries
;
2032 init_attr
->cap
.max_recv_wr
= qhp
->attr
.rq_num_entries
;
2033 init_attr
->cap
.max_send_sge
= qhp
->attr
.sq_max_sges
;
2034 init_attr
->cap
.max_recv_sge
= qhp
->attr
.sq_max_sges
;
2035 init_attr
->cap
.max_inline_data
= T4_MAX_SEND_INLINE
;
2036 init_attr
->sq_sig_type
= qhp
->sq_sig_all
? IB_SIGNAL_ALL_WR
: 0;