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Merge branch 'for-4.7/pwm-regulator' of git://git.kernel.org/pub/scm/linux/kernel...
[mirror_ubuntu-hirsute-kernel.git] / drivers / infiniband / hw / cxgb4 / qp.c
1 /*
2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/module.h>
34
35 #include "iw_cxgb4.h"
36
37 static int db_delay_usecs = 1;
38 module_param(db_delay_usecs, int, 0644);
39 MODULE_PARM_DESC(db_delay_usecs, "Usecs to delay awaiting db fifo to drain");
40
41 static int ocqp_support = 1;
42 module_param(ocqp_support, int, 0644);
43 MODULE_PARM_DESC(ocqp_support, "Support on-chip SQs (default=1)");
44
45 int db_fc_threshold = 1000;
46 module_param(db_fc_threshold, int, 0644);
47 MODULE_PARM_DESC(db_fc_threshold,
48 "QP count/threshold that triggers"
49 " automatic db flow control mode (default = 1000)");
50
51 int db_coalescing_threshold;
52 module_param(db_coalescing_threshold, int, 0644);
53 MODULE_PARM_DESC(db_coalescing_threshold,
54 "QP count/threshold that triggers"
55 " disabling db coalescing (default = 0)");
56
57 static int max_fr_immd = T4_MAX_FR_IMMD;
58 module_param(max_fr_immd, int, 0644);
59 MODULE_PARM_DESC(max_fr_immd, "fastreg threshold for using DSGL instead of immedate");
60
61 static int alloc_ird(struct c4iw_dev *dev, u32 ird)
62 {
63 int ret = 0;
64
65 spin_lock_irq(&dev->lock);
66 if (ird <= dev->avail_ird)
67 dev->avail_ird -= ird;
68 else
69 ret = -ENOMEM;
70 spin_unlock_irq(&dev->lock);
71
72 if (ret)
73 dev_warn(&dev->rdev.lldi.pdev->dev,
74 "device IRD resources exhausted\n");
75
76 return ret;
77 }
78
79 static void free_ird(struct c4iw_dev *dev, int ird)
80 {
81 spin_lock_irq(&dev->lock);
82 dev->avail_ird += ird;
83 spin_unlock_irq(&dev->lock);
84 }
85
86 static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state)
87 {
88 unsigned long flag;
89 spin_lock_irqsave(&qhp->lock, flag);
90 qhp->attr.state = state;
91 spin_unlock_irqrestore(&qhp->lock, flag);
92 }
93
94 static void dealloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
95 {
96 c4iw_ocqp_pool_free(rdev, sq->dma_addr, sq->memsize);
97 }
98
99 static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
100 {
101 dma_free_coherent(&(rdev->lldi.pdev->dev), sq->memsize, sq->queue,
102 pci_unmap_addr(sq, mapping));
103 }
104
105 static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
106 {
107 if (t4_sq_onchip(sq))
108 dealloc_oc_sq(rdev, sq);
109 else
110 dealloc_host_sq(rdev, sq);
111 }
112
113 static int alloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
114 {
115 if (!ocqp_support || !ocqp_supported(&rdev->lldi))
116 return -ENOSYS;
117 sq->dma_addr = c4iw_ocqp_pool_alloc(rdev, sq->memsize);
118 if (!sq->dma_addr)
119 return -ENOMEM;
120 sq->phys_addr = rdev->oc_mw_pa + sq->dma_addr -
121 rdev->lldi.vr->ocq.start;
122 sq->queue = (__force union t4_wr *)(rdev->oc_mw_kva + sq->dma_addr -
123 rdev->lldi.vr->ocq.start);
124 sq->flags |= T4_SQ_ONCHIP;
125 return 0;
126 }
127
128 static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
129 {
130 sq->queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), sq->memsize,
131 &(sq->dma_addr), GFP_KERNEL);
132 if (!sq->queue)
133 return -ENOMEM;
134 sq->phys_addr = virt_to_phys(sq->queue);
135 pci_unmap_addr_set(sq, mapping, sq->dma_addr);
136 return 0;
137 }
138
139 static int alloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq, int user)
140 {
141 int ret = -ENOSYS;
142 if (user)
143 ret = alloc_oc_sq(rdev, sq);
144 if (ret)
145 ret = alloc_host_sq(rdev, sq);
146 return ret;
147 }
148
149 static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
150 struct c4iw_dev_ucontext *uctx)
151 {
152 /*
153 * uP clears EQ contexts when the connection exits rdma mode,
154 * so no need to post a RESET WR for these EQs.
155 */
156 dma_free_coherent(&(rdev->lldi.pdev->dev),
157 wq->rq.memsize, wq->rq.queue,
158 dma_unmap_addr(&wq->rq, mapping));
159 dealloc_sq(rdev, &wq->sq);
160 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
161 kfree(wq->rq.sw_rq);
162 kfree(wq->sq.sw_sq);
163 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
164 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
165 return 0;
166 }
167
168 /*
169 * Determine the BAR2 virtual address and qid. If pbar2_pa is not NULL,
170 * then this is a user mapping so compute the page-aligned physical address
171 * for mapping.
172 */
173 void __iomem *c4iw_bar2_addrs(struct c4iw_rdev *rdev, unsigned int qid,
174 enum cxgb4_bar2_qtype qtype,
175 unsigned int *pbar2_qid, u64 *pbar2_pa)
176 {
177 u64 bar2_qoffset;
178 int ret;
179
180 ret = cxgb4_bar2_sge_qregs(rdev->lldi.ports[0], qid, qtype,
181 pbar2_pa ? 1 : 0,
182 &bar2_qoffset, pbar2_qid);
183 if (ret)
184 return NULL;
185
186 if (pbar2_pa)
187 *pbar2_pa = (rdev->bar2_pa + bar2_qoffset) & PAGE_MASK;
188 return rdev->bar2_kva + bar2_qoffset;
189 }
190
191 static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
192 struct t4_cq *rcq, struct t4_cq *scq,
193 struct c4iw_dev_ucontext *uctx)
194 {
195 int user = (uctx != &rdev->uctx);
196 struct fw_ri_res_wr *res_wr;
197 struct fw_ri_res *res;
198 int wr_len;
199 struct c4iw_wr_wait wr_wait;
200 struct sk_buff *skb;
201 int ret = 0;
202 int eqsize;
203
204 wq->sq.qid = c4iw_get_qpid(rdev, uctx);
205 if (!wq->sq.qid)
206 return -ENOMEM;
207
208 wq->rq.qid = c4iw_get_qpid(rdev, uctx);
209 if (!wq->rq.qid) {
210 ret = -ENOMEM;
211 goto free_sq_qid;
212 }
213
214 if (!user) {
215 wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq,
216 GFP_KERNEL);
217 if (!wq->sq.sw_sq) {
218 ret = -ENOMEM;
219 goto free_rq_qid;
220 }
221
222 wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq,
223 GFP_KERNEL);
224 if (!wq->rq.sw_rq) {
225 ret = -ENOMEM;
226 goto free_sw_sq;
227 }
228 }
229
230 /*
231 * RQT must be a power of 2 and at least 16 deep.
232 */
233 wq->rq.rqt_size = roundup_pow_of_two(max_t(u16, wq->rq.size, 16));
234 wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size);
235 if (!wq->rq.rqt_hwaddr) {
236 ret = -ENOMEM;
237 goto free_sw_rq;
238 }
239
240 ret = alloc_sq(rdev, &wq->sq, user);
241 if (ret)
242 goto free_hwaddr;
243 memset(wq->sq.queue, 0, wq->sq.memsize);
244 dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr);
245
246 wq->rq.queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev),
247 wq->rq.memsize, &(wq->rq.dma_addr),
248 GFP_KERNEL);
249 if (!wq->rq.queue) {
250 ret = -ENOMEM;
251 goto free_sq;
252 }
253 PDBG("%s sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx\n",
254 __func__, wq->sq.queue,
255 (unsigned long long)virt_to_phys(wq->sq.queue),
256 wq->rq.queue,
257 (unsigned long long)virt_to_phys(wq->rq.queue));
258 memset(wq->rq.queue, 0, wq->rq.memsize);
259 dma_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr);
260
261 wq->db = rdev->lldi.db_reg;
262
263 wq->sq.bar2_va = c4iw_bar2_addrs(rdev, wq->sq.qid, T4_BAR2_QTYPE_EGRESS,
264 &wq->sq.bar2_qid,
265 user ? &wq->sq.bar2_pa : NULL);
266 wq->rq.bar2_va = c4iw_bar2_addrs(rdev, wq->rq.qid, T4_BAR2_QTYPE_EGRESS,
267 &wq->rq.bar2_qid,
268 user ? &wq->rq.bar2_pa : NULL);
269
270 /*
271 * User mode must have bar2 access.
272 */
273 if (user && (!wq->sq.bar2_va || !wq->rq.bar2_va)) {
274 pr_warn(MOD "%s: sqid %u or rqid %u not in BAR2 range.\n",
275 pci_name(rdev->lldi.pdev), wq->sq.qid, wq->rq.qid);
276 goto free_dma;
277 }
278
279 wq->rdev = rdev;
280 wq->rq.msn = 1;
281
282 /* build fw_ri_res_wr */
283 wr_len = sizeof *res_wr + 2 * sizeof *res;
284
285 skb = alloc_skb(wr_len, GFP_KERNEL);
286 if (!skb) {
287 ret = -ENOMEM;
288 goto free_dma;
289 }
290 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
291
292 res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len);
293 memset(res_wr, 0, wr_len);
294 res_wr->op_nres = cpu_to_be32(
295 FW_WR_OP_V(FW_RI_RES_WR) |
296 FW_RI_RES_WR_NRES_V(2) |
297 FW_WR_COMPL_F);
298 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
299 res_wr->cookie = (uintptr_t)&wr_wait;
300 res = res_wr->res;
301 res->u.sqrq.restype = FW_RI_RES_TYPE_SQ;
302 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
303
304 /*
305 * eqsize is the number of 64B entries plus the status page size.
306 */
307 eqsize = wq->sq.size * T4_SQ_NUM_SLOTS +
308 rdev->hw_queue.t4_eq_status_entries;
309
310 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
311 FW_RI_RES_WR_HOSTFCMODE_V(0) | /* no host cidx updates */
312 FW_RI_RES_WR_CPRIO_V(0) | /* don't keep in chip cache */
313 FW_RI_RES_WR_PCIECHN_V(0) | /* set by uP at ri_init time */
314 (t4_sq_onchip(&wq->sq) ? FW_RI_RES_WR_ONCHIP_F : 0) |
315 FW_RI_RES_WR_IQID_V(scq->cqid));
316 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
317 FW_RI_RES_WR_DCAEN_V(0) |
318 FW_RI_RES_WR_DCACPU_V(0) |
319 FW_RI_RES_WR_FBMIN_V(2) |
320 FW_RI_RES_WR_FBMAX_V(2) |
321 FW_RI_RES_WR_CIDXFTHRESHO_V(0) |
322 FW_RI_RES_WR_CIDXFTHRESH_V(0) |
323 FW_RI_RES_WR_EQSIZE_V(eqsize));
324 res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid);
325 res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr);
326 res++;
327 res->u.sqrq.restype = FW_RI_RES_TYPE_RQ;
328 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
329
330 /*
331 * eqsize is the number of 64B entries plus the status page size.
332 */
333 eqsize = wq->rq.size * T4_RQ_NUM_SLOTS +
334 rdev->hw_queue.t4_eq_status_entries;
335 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
336 FW_RI_RES_WR_HOSTFCMODE_V(0) | /* no host cidx updates */
337 FW_RI_RES_WR_CPRIO_V(0) | /* don't keep in chip cache */
338 FW_RI_RES_WR_PCIECHN_V(0) | /* set by uP at ri_init time */
339 FW_RI_RES_WR_IQID_V(rcq->cqid));
340 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
341 FW_RI_RES_WR_DCAEN_V(0) |
342 FW_RI_RES_WR_DCACPU_V(0) |
343 FW_RI_RES_WR_FBMIN_V(2) |
344 FW_RI_RES_WR_FBMAX_V(2) |
345 FW_RI_RES_WR_CIDXFTHRESHO_V(0) |
346 FW_RI_RES_WR_CIDXFTHRESH_V(0) |
347 FW_RI_RES_WR_EQSIZE_V(eqsize));
348 res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid);
349 res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr);
350
351 c4iw_init_wr_wait(&wr_wait);
352
353 ret = c4iw_ofld_send(rdev, skb);
354 if (ret)
355 goto free_dma;
356 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, wq->sq.qid, __func__);
357 if (ret)
358 goto free_dma;
359
360 PDBG("%s sqid 0x%x rqid 0x%x kdb 0x%p sq_bar2_addr %p rq_bar2_addr %p\n",
361 __func__, wq->sq.qid, wq->rq.qid, wq->db,
362 wq->sq.bar2_va, wq->rq.bar2_va);
363
364 return 0;
365 free_dma:
366 dma_free_coherent(&(rdev->lldi.pdev->dev),
367 wq->rq.memsize, wq->rq.queue,
368 dma_unmap_addr(&wq->rq, mapping));
369 free_sq:
370 dealloc_sq(rdev, &wq->sq);
371 free_hwaddr:
372 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
373 free_sw_rq:
374 kfree(wq->rq.sw_rq);
375 free_sw_sq:
376 kfree(wq->sq.sw_sq);
377 free_rq_qid:
378 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
379 free_sq_qid:
380 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
381 return ret;
382 }
383
384 static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp,
385 struct ib_send_wr *wr, int max, u32 *plenp)
386 {
387 u8 *dstp, *srcp;
388 u32 plen = 0;
389 int i;
390 int rem, len;
391
392 dstp = (u8 *)immdp->data;
393 for (i = 0; i < wr->num_sge; i++) {
394 if ((plen + wr->sg_list[i].length) > max)
395 return -EMSGSIZE;
396 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr;
397 plen += wr->sg_list[i].length;
398 rem = wr->sg_list[i].length;
399 while (rem) {
400 if (dstp == (u8 *)&sq->queue[sq->size])
401 dstp = (u8 *)sq->queue;
402 if (rem <= (u8 *)&sq->queue[sq->size] - dstp)
403 len = rem;
404 else
405 len = (u8 *)&sq->queue[sq->size] - dstp;
406 memcpy(dstp, srcp, len);
407 dstp += len;
408 srcp += len;
409 rem -= len;
410 }
411 }
412 len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp);
413 if (len)
414 memset(dstp, 0, len);
415 immdp->op = FW_RI_DATA_IMMD;
416 immdp->r1 = 0;
417 immdp->r2 = 0;
418 immdp->immdlen = cpu_to_be32(plen);
419 *plenp = plen;
420 return 0;
421 }
422
423 static int build_isgl(__be64 *queue_start, __be64 *queue_end,
424 struct fw_ri_isgl *isglp, struct ib_sge *sg_list,
425 int num_sge, u32 *plenp)
426
427 {
428 int i;
429 u32 plen = 0;
430 __be64 *flitp = (__be64 *)isglp->sge;
431
432 for (i = 0; i < num_sge; i++) {
433 if ((plen + sg_list[i].length) < plen)
434 return -EMSGSIZE;
435 plen += sg_list[i].length;
436 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) |
437 sg_list[i].length);
438 if (++flitp == queue_end)
439 flitp = queue_start;
440 *flitp = cpu_to_be64(sg_list[i].addr);
441 if (++flitp == queue_end)
442 flitp = queue_start;
443 }
444 *flitp = (__force __be64)0;
445 isglp->op = FW_RI_DATA_ISGL;
446 isglp->r1 = 0;
447 isglp->nsge = cpu_to_be16(num_sge);
448 isglp->r2 = 0;
449 if (plenp)
450 *plenp = plen;
451 return 0;
452 }
453
454 static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe,
455 struct ib_send_wr *wr, u8 *len16)
456 {
457 u32 plen;
458 int size;
459 int ret;
460
461 if (wr->num_sge > T4_MAX_SEND_SGE)
462 return -EINVAL;
463 switch (wr->opcode) {
464 case IB_WR_SEND:
465 if (wr->send_flags & IB_SEND_SOLICITED)
466 wqe->send.sendop_pkd = cpu_to_be32(
467 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_SE));
468 else
469 wqe->send.sendop_pkd = cpu_to_be32(
470 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND));
471 wqe->send.stag_inv = 0;
472 break;
473 case IB_WR_SEND_WITH_INV:
474 if (wr->send_flags & IB_SEND_SOLICITED)
475 wqe->send.sendop_pkd = cpu_to_be32(
476 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_SE_INV));
477 else
478 wqe->send.sendop_pkd = cpu_to_be32(
479 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_INV));
480 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
481 break;
482
483 default:
484 return -EINVAL;
485 }
486 wqe->send.r3 = 0;
487 wqe->send.r4 = 0;
488
489 plen = 0;
490 if (wr->num_sge) {
491 if (wr->send_flags & IB_SEND_INLINE) {
492 ret = build_immd(sq, wqe->send.u.immd_src, wr,
493 T4_MAX_SEND_INLINE, &plen);
494 if (ret)
495 return ret;
496 size = sizeof wqe->send + sizeof(struct fw_ri_immd) +
497 plen;
498 } else {
499 ret = build_isgl((__be64 *)sq->queue,
500 (__be64 *)&sq->queue[sq->size],
501 wqe->send.u.isgl_src,
502 wr->sg_list, wr->num_sge, &plen);
503 if (ret)
504 return ret;
505 size = sizeof wqe->send + sizeof(struct fw_ri_isgl) +
506 wr->num_sge * sizeof(struct fw_ri_sge);
507 }
508 } else {
509 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD;
510 wqe->send.u.immd_src[0].r1 = 0;
511 wqe->send.u.immd_src[0].r2 = 0;
512 wqe->send.u.immd_src[0].immdlen = 0;
513 size = sizeof wqe->send + sizeof(struct fw_ri_immd);
514 plen = 0;
515 }
516 *len16 = DIV_ROUND_UP(size, 16);
517 wqe->send.plen = cpu_to_be32(plen);
518 return 0;
519 }
520
521 static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe,
522 struct ib_send_wr *wr, u8 *len16)
523 {
524 u32 plen;
525 int size;
526 int ret;
527
528 if (wr->num_sge > T4_MAX_SEND_SGE)
529 return -EINVAL;
530 wqe->write.r2 = 0;
531 wqe->write.stag_sink = cpu_to_be32(rdma_wr(wr)->rkey);
532 wqe->write.to_sink = cpu_to_be64(rdma_wr(wr)->remote_addr);
533 if (wr->num_sge) {
534 if (wr->send_flags & IB_SEND_INLINE) {
535 ret = build_immd(sq, wqe->write.u.immd_src, wr,
536 T4_MAX_WRITE_INLINE, &plen);
537 if (ret)
538 return ret;
539 size = sizeof wqe->write + sizeof(struct fw_ri_immd) +
540 plen;
541 } else {
542 ret = build_isgl((__be64 *)sq->queue,
543 (__be64 *)&sq->queue[sq->size],
544 wqe->write.u.isgl_src,
545 wr->sg_list, wr->num_sge, &plen);
546 if (ret)
547 return ret;
548 size = sizeof wqe->write + sizeof(struct fw_ri_isgl) +
549 wr->num_sge * sizeof(struct fw_ri_sge);
550 }
551 } else {
552 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD;
553 wqe->write.u.immd_src[0].r1 = 0;
554 wqe->write.u.immd_src[0].r2 = 0;
555 wqe->write.u.immd_src[0].immdlen = 0;
556 size = sizeof wqe->write + sizeof(struct fw_ri_immd);
557 plen = 0;
558 }
559 *len16 = DIV_ROUND_UP(size, 16);
560 wqe->write.plen = cpu_to_be32(plen);
561 return 0;
562 }
563
564 static int build_rdma_read(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16)
565 {
566 if (wr->num_sge > 1)
567 return -EINVAL;
568 if (wr->num_sge) {
569 wqe->read.stag_src = cpu_to_be32(rdma_wr(wr)->rkey);
570 wqe->read.to_src_hi = cpu_to_be32((u32)(rdma_wr(wr)->remote_addr
571 >> 32));
572 wqe->read.to_src_lo = cpu_to_be32((u32)rdma_wr(wr)->remote_addr);
573 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey);
574 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length);
575 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr
576 >> 32));
577 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr));
578 } else {
579 wqe->read.stag_src = cpu_to_be32(2);
580 wqe->read.to_src_hi = 0;
581 wqe->read.to_src_lo = 0;
582 wqe->read.stag_sink = cpu_to_be32(2);
583 wqe->read.plen = 0;
584 wqe->read.to_sink_hi = 0;
585 wqe->read.to_sink_lo = 0;
586 }
587 wqe->read.r2 = 0;
588 wqe->read.r5 = 0;
589 *len16 = DIV_ROUND_UP(sizeof wqe->read, 16);
590 return 0;
591 }
592
593 static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe,
594 struct ib_recv_wr *wr, u8 *len16)
595 {
596 int ret;
597
598 ret = build_isgl((__be64 *)qhp->wq.rq.queue,
599 (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size],
600 &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL);
601 if (ret)
602 return ret;
603 *len16 = DIV_ROUND_UP(sizeof wqe->recv +
604 wr->num_sge * sizeof(struct fw_ri_sge), 16);
605 return 0;
606 }
607
608 static int build_memreg(struct t4_sq *sq, union t4_wr *wqe,
609 struct ib_reg_wr *wr, u8 *len16, bool dsgl_supported)
610 {
611 struct c4iw_mr *mhp = to_c4iw_mr(wr->mr);
612 struct fw_ri_immd *imdp;
613 __be64 *p;
614 int i;
615 int pbllen = roundup(mhp->mpl_len * sizeof(u64), 32);
616 int rem;
617
618 if (mhp->mpl_len > t4_max_fr_depth(dsgl_supported && use_dsgl))
619 return -EINVAL;
620
621 wqe->fr.qpbinde_to_dcacpu = 0;
622 wqe->fr.pgsz_shift = ilog2(wr->mr->page_size) - 12;
623 wqe->fr.addr_type = FW_RI_VA_BASED_TO;
624 wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->access);
625 wqe->fr.len_hi = 0;
626 wqe->fr.len_lo = cpu_to_be32(mhp->ibmr.length);
627 wqe->fr.stag = cpu_to_be32(wr->key);
628 wqe->fr.va_hi = cpu_to_be32(mhp->ibmr.iova >> 32);
629 wqe->fr.va_lo_fbo = cpu_to_be32(mhp->ibmr.iova &
630 0xffffffff);
631
632 if (dsgl_supported && use_dsgl && (pbllen > max_fr_immd)) {
633 struct fw_ri_dsgl *sglp;
634
635 for (i = 0; i < mhp->mpl_len; i++)
636 mhp->mpl[i] = (__force u64)cpu_to_be64((u64)mhp->mpl[i]);
637
638 sglp = (struct fw_ri_dsgl *)(&wqe->fr + 1);
639 sglp->op = FW_RI_DATA_DSGL;
640 sglp->r1 = 0;
641 sglp->nsge = cpu_to_be16(1);
642 sglp->addr0 = cpu_to_be64(mhp->mpl_addr);
643 sglp->len0 = cpu_to_be32(pbllen);
644
645 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*sglp), 16);
646 } else {
647 imdp = (struct fw_ri_immd *)(&wqe->fr + 1);
648 imdp->op = FW_RI_DATA_IMMD;
649 imdp->r1 = 0;
650 imdp->r2 = 0;
651 imdp->immdlen = cpu_to_be32(pbllen);
652 p = (__be64 *)(imdp + 1);
653 rem = pbllen;
654 for (i = 0; i < mhp->mpl_len; i++) {
655 *p = cpu_to_be64((u64)mhp->mpl[i]);
656 rem -= sizeof(*p);
657 if (++p == (__be64 *)&sq->queue[sq->size])
658 p = (__be64 *)sq->queue;
659 }
660 BUG_ON(rem < 0);
661 while (rem) {
662 *p = 0;
663 rem -= sizeof(*p);
664 if (++p == (__be64 *)&sq->queue[sq->size])
665 p = (__be64 *)sq->queue;
666 }
667 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*imdp)
668 + pbllen, 16);
669 }
670 return 0;
671 }
672
673 static int build_inv_stag(union t4_wr *wqe, struct ib_send_wr *wr,
674 u8 *len16)
675 {
676 wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
677 wqe->inv.r2 = 0;
678 *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16);
679 return 0;
680 }
681
682 void c4iw_qp_add_ref(struct ib_qp *qp)
683 {
684 PDBG("%s ib_qp %p\n", __func__, qp);
685 atomic_inc(&(to_c4iw_qp(qp)->refcnt));
686 }
687
688 void c4iw_qp_rem_ref(struct ib_qp *qp)
689 {
690 PDBG("%s ib_qp %p\n", __func__, qp);
691 if (atomic_dec_and_test(&(to_c4iw_qp(qp)->refcnt)))
692 wake_up(&(to_c4iw_qp(qp)->wait));
693 }
694
695 static void add_to_fc_list(struct list_head *head, struct list_head *entry)
696 {
697 if (list_empty(entry))
698 list_add_tail(entry, head);
699 }
700
701 static int ring_kernel_sq_db(struct c4iw_qp *qhp, u16 inc)
702 {
703 unsigned long flags;
704
705 spin_lock_irqsave(&qhp->rhp->lock, flags);
706 spin_lock(&qhp->lock);
707 if (qhp->rhp->db_state == NORMAL)
708 t4_ring_sq_db(&qhp->wq, inc, NULL);
709 else {
710 add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry);
711 qhp->wq.sq.wq_pidx_inc += inc;
712 }
713 spin_unlock(&qhp->lock);
714 spin_unlock_irqrestore(&qhp->rhp->lock, flags);
715 return 0;
716 }
717
718 static int ring_kernel_rq_db(struct c4iw_qp *qhp, u16 inc)
719 {
720 unsigned long flags;
721
722 spin_lock_irqsave(&qhp->rhp->lock, flags);
723 spin_lock(&qhp->lock);
724 if (qhp->rhp->db_state == NORMAL)
725 t4_ring_rq_db(&qhp->wq, inc, NULL);
726 else {
727 add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry);
728 qhp->wq.rq.wq_pidx_inc += inc;
729 }
730 spin_unlock(&qhp->lock);
731 spin_unlock_irqrestore(&qhp->rhp->lock, flags);
732 return 0;
733 }
734
735 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
736 struct ib_send_wr **bad_wr)
737 {
738 int err = 0;
739 u8 len16 = 0;
740 enum fw_wr_opcodes fw_opcode = 0;
741 enum fw_ri_wr_flags fw_flags;
742 struct c4iw_qp *qhp;
743 union t4_wr *wqe = NULL;
744 u32 num_wrs;
745 struct t4_swsqe *swsqe;
746 unsigned long flag;
747 u16 idx = 0;
748
749 qhp = to_c4iw_qp(ibqp);
750 spin_lock_irqsave(&qhp->lock, flag);
751 if (t4_wq_in_error(&qhp->wq)) {
752 spin_unlock_irqrestore(&qhp->lock, flag);
753 return -EINVAL;
754 }
755 num_wrs = t4_sq_avail(&qhp->wq);
756 if (num_wrs == 0) {
757 spin_unlock_irqrestore(&qhp->lock, flag);
758 return -ENOMEM;
759 }
760 while (wr) {
761 if (num_wrs == 0) {
762 err = -ENOMEM;
763 *bad_wr = wr;
764 break;
765 }
766 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue +
767 qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE);
768
769 fw_flags = 0;
770 if (wr->send_flags & IB_SEND_SOLICITED)
771 fw_flags |= FW_RI_SOLICITED_EVENT_FLAG;
772 if (wr->send_flags & IB_SEND_SIGNALED || qhp->sq_sig_all)
773 fw_flags |= FW_RI_COMPLETION_FLAG;
774 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx];
775 switch (wr->opcode) {
776 case IB_WR_SEND_WITH_INV:
777 case IB_WR_SEND:
778 if (wr->send_flags & IB_SEND_FENCE)
779 fw_flags |= FW_RI_READ_FENCE_FLAG;
780 fw_opcode = FW_RI_SEND_WR;
781 if (wr->opcode == IB_WR_SEND)
782 swsqe->opcode = FW_RI_SEND;
783 else
784 swsqe->opcode = FW_RI_SEND_WITH_INV;
785 err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16);
786 break;
787 case IB_WR_RDMA_WRITE:
788 fw_opcode = FW_RI_RDMA_WRITE_WR;
789 swsqe->opcode = FW_RI_RDMA_WRITE;
790 err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16);
791 break;
792 case IB_WR_RDMA_READ:
793 case IB_WR_RDMA_READ_WITH_INV:
794 fw_opcode = FW_RI_RDMA_READ_WR;
795 swsqe->opcode = FW_RI_READ_REQ;
796 if (wr->opcode == IB_WR_RDMA_READ_WITH_INV)
797 fw_flags = FW_RI_RDMA_READ_INVALIDATE;
798 else
799 fw_flags = 0;
800 err = build_rdma_read(wqe, wr, &len16);
801 if (err)
802 break;
803 swsqe->read_len = wr->sg_list[0].length;
804 if (!qhp->wq.sq.oldest_read)
805 qhp->wq.sq.oldest_read = swsqe;
806 break;
807 case IB_WR_REG_MR:
808 fw_opcode = FW_RI_FR_NSMR_WR;
809 swsqe->opcode = FW_RI_FAST_REGISTER;
810 err = build_memreg(&qhp->wq.sq, wqe, reg_wr(wr), &len16,
811 qhp->rhp->rdev.lldi.ulptx_memwrite_dsgl);
812 break;
813 case IB_WR_LOCAL_INV:
814 if (wr->send_flags & IB_SEND_FENCE)
815 fw_flags |= FW_RI_LOCAL_FENCE_FLAG;
816 fw_opcode = FW_RI_INV_LSTAG_WR;
817 swsqe->opcode = FW_RI_LOCAL_INV;
818 err = build_inv_stag(wqe, wr, &len16);
819 break;
820 default:
821 PDBG("%s post of type=%d TBD!\n", __func__,
822 wr->opcode);
823 err = -EINVAL;
824 }
825 if (err) {
826 *bad_wr = wr;
827 break;
828 }
829 swsqe->idx = qhp->wq.sq.pidx;
830 swsqe->complete = 0;
831 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED) ||
832 qhp->sq_sig_all;
833 swsqe->flushed = 0;
834 swsqe->wr_id = wr->wr_id;
835 if (c4iw_wr_log) {
836 swsqe->sge_ts = cxgb4_read_sge_timestamp(
837 qhp->rhp->rdev.lldi.ports[0]);
838 getnstimeofday(&swsqe->host_ts);
839 }
840
841 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16);
842
843 PDBG("%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u\n",
844 __func__, (unsigned long long)wr->wr_id, qhp->wq.sq.pidx,
845 swsqe->opcode, swsqe->read_len);
846 wr = wr->next;
847 num_wrs--;
848 t4_sq_produce(&qhp->wq, len16);
849 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
850 }
851 if (!qhp->rhp->rdev.status_page->db_off) {
852 t4_ring_sq_db(&qhp->wq, idx, wqe);
853 spin_unlock_irqrestore(&qhp->lock, flag);
854 } else {
855 spin_unlock_irqrestore(&qhp->lock, flag);
856 ring_kernel_sq_db(qhp, idx);
857 }
858 return err;
859 }
860
861 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
862 struct ib_recv_wr **bad_wr)
863 {
864 int err = 0;
865 struct c4iw_qp *qhp;
866 union t4_recv_wr *wqe = NULL;
867 u32 num_wrs;
868 u8 len16 = 0;
869 unsigned long flag;
870 u16 idx = 0;
871
872 qhp = to_c4iw_qp(ibqp);
873 spin_lock_irqsave(&qhp->lock, flag);
874 if (t4_wq_in_error(&qhp->wq)) {
875 spin_unlock_irqrestore(&qhp->lock, flag);
876 return -EINVAL;
877 }
878 num_wrs = t4_rq_avail(&qhp->wq);
879 if (num_wrs == 0) {
880 spin_unlock_irqrestore(&qhp->lock, flag);
881 return -ENOMEM;
882 }
883 while (wr) {
884 if (wr->num_sge > T4_MAX_RECV_SGE) {
885 err = -EINVAL;
886 *bad_wr = wr;
887 break;
888 }
889 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue +
890 qhp->wq.rq.wq_pidx *
891 T4_EQ_ENTRY_SIZE);
892 if (num_wrs)
893 err = build_rdma_recv(qhp, wqe, wr, &len16);
894 else
895 err = -ENOMEM;
896 if (err) {
897 *bad_wr = wr;
898 break;
899 }
900
901 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id;
902 if (c4iw_wr_log) {
903 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].sge_ts =
904 cxgb4_read_sge_timestamp(
905 qhp->rhp->rdev.lldi.ports[0]);
906 getnstimeofday(
907 &qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].host_ts);
908 }
909
910 wqe->recv.opcode = FW_RI_RECV_WR;
911 wqe->recv.r1 = 0;
912 wqe->recv.wrid = qhp->wq.rq.pidx;
913 wqe->recv.r2[0] = 0;
914 wqe->recv.r2[1] = 0;
915 wqe->recv.r2[2] = 0;
916 wqe->recv.len16 = len16;
917 PDBG("%s cookie 0x%llx pidx %u\n", __func__,
918 (unsigned long long) wr->wr_id, qhp->wq.rq.pidx);
919 t4_rq_produce(&qhp->wq, len16);
920 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
921 wr = wr->next;
922 num_wrs--;
923 }
924 if (!qhp->rhp->rdev.status_page->db_off) {
925 t4_ring_rq_db(&qhp->wq, idx, wqe);
926 spin_unlock_irqrestore(&qhp->lock, flag);
927 } else {
928 spin_unlock_irqrestore(&qhp->lock, flag);
929 ring_kernel_rq_db(qhp, idx);
930 }
931 return err;
932 }
933
934 static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type,
935 u8 *ecode)
936 {
937 int status;
938 int tagged;
939 int opcode;
940 int rqtype;
941 int send_inv;
942
943 if (!err_cqe) {
944 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
945 *ecode = 0;
946 return;
947 }
948
949 status = CQE_STATUS(err_cqe);
950 opcode = CQE_OPCODE(err_cqe);
951 rqtype = RQ_TYPE(err_cqe);
952 send_inv = (opcode == FW_RI_SEND_WITH_INV) ||
953 (opcode == FW_RI_SEND_WITH_SE_INV);
954 tagged = (opcode == FW_RI_RDMA_WRITE) ||
955 (rqtype && (opcode == FW_RI_READ_RESP));
956
957 switch (status) {
958 case T4_ERR_STAG:
959 if (send_inv) {
960 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
961 *ecode = RDMAP_CANT_INV_STAG;
962 } else {
963 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
964 *ecode = RDMAP_INV_STAG;
965 }
966 break;
967 case T4_ERR_PDID:
968 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
969 if ((opcode == FW_RI_SEND_WITH_INV) ||
970 (opcode == FW_RI_SEND_WITH_SE_INV))
971 *ecode = RDMAP_CANT_INV_STAG;
972 else
973 *ecode = RDMAP_STAG_NOT_ASSOC;
974 break;
975 case T4_ERR_QPID:
976 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
977 *ecode = RDMAP_STAG_NOT_ASSOC;
978 break;
979 case T4_ERR_ACCESS:
980 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
981 *ecode = RDMAP_ACC_VIOL;
982 break;
983 case T4_ERR_WRAP:
984 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
985 *ecode = RDMAP_TO_WRAP;
986 break;
987 case T4_ERR_BOUND:
988 if (tagged) {
989 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
990 *ecode = DDPT_BASE_BOUNDS;
991 } else {
992 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
993 *ecode = RDMAP_BASE_BOUNDS;
994 }
995 break;
996 case T4_ERR_INVALIDATE_SHARED_MR:
997 case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:
998 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
999 *ecode = RDMAP_CANT_INV_STAG;
1000 break;
1001 case T4_ERR_ECC:
1002 case T4_ERR_ECC_PSTAG:
1003 case T4_ERR_INTERNAL_ERR:
1004 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA;
1005 *ecode = 0;
1006 break;
1007 case T4_ERR_OUT_OF_RQE:
1008 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1009 *ecode = DDPU_INV_MSN_NOBUF;
1010 break;
1011 case T4_ERR_PBL_ADDR_BOUND:
1012 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
1013 *ecode = DDPT_BASE_BOUNDS;
1014 break;
1015 case T4_ERR_CRC:
1016 *layer_type = LAYER_MPA|DDP_LLP;
1017 *ecode = MPA_CRC_ERR;
1018 break;
1019 case T4_ERR_MARKER:
1020 *layer_type = LAYER_MPA|DDP_LLP;
1021 *ecode = MPA_MARKER_ERR;
1022 break;
1023 case T4_ERR_PDU_LEN_ERR:
1024 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1025 *ecode = DDPU_MSG_TOOBIG;
1026 break;
1027 case T4_ERR_DDP_VERSION:
1028 if (tagged) {
1029 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
1030 *ecode = DDPT_INV_VERS;
1031 } else {
1032 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1033 *ecode = DDPU_INV_VERS;
1034 }
1035 break;
1036 case T4_ERR_RDMA_VERSION:
1037 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1038 *ecode = RDMAP_INV_VERS;
1039 break;
1040 case T4_ERR_OPCODE:
1041 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1042 *ecode = RDMAP_INV_OPCODE;
1043 break;
1044 case T4_ERR_DDP_QUEUE_NUM:
1045 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1046 *ecode = DDPU_INV_QN;
1047 break;
1048 case T4_ERR_MSN:
1049 case T4_ERR_MSN_GAP:
1050 case T4_ERR_MSN_RANGE:
1051 case T4_ERR_IRD_OVERFLOW:
1052 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1053 *ecode = DDPU_INV_MSN_RANGE;
1054 break;
1055 case T4_ERR_TBIT:
1056 *layer_type = LAYER_DDP|DDP_LOCAL_CATA;
1057 *ecode = 0;
1058 break;
1059 case T4_ERR_MO:
1060 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1061 *ecode = DDPU_INV_MO;
1062 break;
1063 default:
1064 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
1065 *ecode = 0;
1066 break;
1067 }
1068 }
1069
1070 static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe,
1071 gfp_t gfp)
1072 {
1073 struct fw_ri_wr *wqe;
1074 struct sk_buff *skb;
1075 struct terminate_message *term;
1076
1077 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1078 qhp->ep->hwtid);
1079
1080 skb = alloc_skb(sizeof *wqe, gfp);
1081 if (!skb)
1082 return;
1083 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1084
1085 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1086 memset(wqe, 0, sizeof *wqe);
1087 wqe->op_compl = cpu_to_be32(FW_WR_OP_V(FW_RI_INIT_WR));
1088 wqe->flowid_len16 = cpu_to_be32(
1089 FW_WR_FLOWID_V(qhp->ep->hwtid) |
1090 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16)));
1091
1092 wqe->u.terminate.type = FW_RI_TYPE_TERMINATE;
1093 wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term);
1094 term = (struct terminate_message *)wqe->u.terminate.termmsg;
1095 if (qhp->attr.layer_etype == (LAYER_MPA|DDP_LLP)) {
1096 term->layer_etype = qhp->attr.layer_etype;
1097 term->ecode = qhp->attr.ecode;
1098 } else
1099 build_term_codes(err_cqe, &term->layer_etype, &term->ecode);
1100 c4iw_ofld_send(&qhp->rhp->rdev, skb);
1101 }
1102
1103 /*
1104 * Assumes qhp lock is held.
1105 */
1106 static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp,
1107 struct c4iw_cq *schp)
1108 {
1109 int count;
1110 int rq_flushed, sq_flushed;
1111 unsigned long flag;
1112
1113 PDBG("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp);
1114
1115 /* locking hierarchy: cq lock first, then qp lock. */
1116 spin_lock_irqsave(&rchp->lock, flag);
1117 spin_lock(&qhp->lock);
1118
1119 if (qhp->wq.flushed) {
1120 spin_unlock(&qhp->lock);
1121 spin_unlock_irqrestore(&rchp->lock, flag);
1122 return;
1123 }
1124 qhp->wq.flushed = 1;
1125
1126 c4iw_flush_hw_cq(rchp);
1127 c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count);
1128 rq_flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count);
1129 spin_unlock(&qhp->lock);
1130 spin_unlock_irqrestore(&rchp->lock, flag);
1131
1132 /* locking hierarchy: cq lock first, then qp lock. */
1133 spin_lock_irqsave(&schp->lock, flag);
1134 spin_lock(&qhp->lock);
1135 if (schp != rchp)
1136 c4iw_flush_hw_cq(schp);
1137 sq_flushed = c4iw_flush_sq(qhp);
1138 spin_unlock(&qhp->lock);
1139 spin_unlock_irqrestore(&schp->lock, flag);
1140
1141 if (schp == rchp) {
1142 if (t4_clear_cq_armed(&rchp->cq) &&
1143 (rq_flushed || sq_flushed)) {
1144 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1145 (*rchp->ibcq.comp_handler)(&rchp->ibcq,
1146 rchp->ibcq.cq_context);
1147 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1148 }
1149 } else {
1150 if (t4_clear_cq_armed(&rchp->cq) && rq_flushed) {
1151 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1152 (*rchp->ibcq.comp_handler)(&rchp->ibcq,
1153 rchp->ibcq.cq_context);
1154 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1155 }
1156 if (t4_clear_cq_armed(&schp->cq) && sq_flushed) {
1157 spin_lock_irqsave(&schp->comp_handler_lock, flag);
1158 (*schp->ibcq.comp_handler)(&schp->ibcq,
1159 schp->ibcq.cq_context);
1160 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1161 }
1162 }
1163 }
1164
1165 static void flush_qp(struct c4iw_qp *qhp)
1166 {
1167 struct c4iw_cq *rchp, *schp;
1168 unsigned long flag;
1169
1170 rchp = to_c4iw_cq(qhp->ibqp.recv_cq);
1171 schp = to_c4iw_cq(qhp->ibqp.send_cq);
1172
1173 t4_set_wq_in_error(&qhp->wq);
1174 if (qhp->ibqp.uobject) {
1175 t4_set_cq_in_error(&rchp->cq);
1176 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1177 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
1178 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1179 if (schp != rchp) {
1180 t4_set_cq_in_error(&schp->cq);
1181 spin_lock_irqsave(&schp->comp_handler_lock, flag);
1182 (*schp->ibcq.comp_handler)(&schp->ibcq,
1183 schp->ibcq.cq_context);
1184 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1185 }
1186 return;
1187 }
1188 __flush_qp(qhp, rchp, schp);
1189 }
1190
1191 static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1192 struct c4iw_ep *ep)
1193 {
1194 struct fw_ri_wr *wqe;
1195 int ret;
1196 struct sk_buff *skb;
1197
1198 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1199 ep->hwtid);
1200
1201 skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
1202 if (!skb)
1203 return -ENOMEM;
1204 set_wr_txq(skb, CPL_PRIORITY_DATA, ep->txq_idx);
1205
1206 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1207 memset(wqe, 0, sizeof *wqe);
1208 wqe->op_compl = cpu_to_be32(
1209 FW_WR_OP_V(FW_RI_INIT_WR) |
1210 FW_WR_COMPL_F);
1211 wqe->flowid_len16 = cpu_to_be32(
1212 FW_WR_FLOWID_V(ep->hwtid) |
1213 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16)));
1214 wqe->cookie = (uintptr_t)&ep->com.wr_wait;
1215
1216 wqe->u.fini.type = FW_RI_TYPE_FINI;
1217 ret = c4iw_ofld_send(&rhp->rdev, skb);
1218 if (ret)
1219 goto out;
1220
1221 ret = c4iw_wait_for_reply(&rhp->rdev, &ep->com.wr_wait, qhp->ep->hwtid,
1222 qhp->wq.sq.qid, __func__);
1223 out:
1224 PDBG("%s ret %d\n", __func__, ret);
1225 return ret;
1226 }
1227
1228 static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init)
1229 {
1230 PDBG("%s p2p_type = %d\n", __func__, p2p_type);
1231 memset(&init->u, 0, sizeof init->u);
1232 switch (p2p_type) {
1233 case FW_RI_INIT_P2PTYPE_RDMA_WRITE:
1234 init->u.write.opcode = FW_RI_RDMA_WRITE_WR;
1235 init->u.write.stag_sink = cpu_to_be32(1);
1236 init->u.write.to_sink = cpu_to_be64(1);
1237 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD;
1238 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write +
1239 sizeof(struct fw_ri_immd),
1240 16);
1241 break;
1242 case FW_RI_INIT_P2PTYPE_READ_REQ:
1243 init->u.write.opcode = FW_RI_RDMA_READ_WR;
1244 init->u.read.stag_src = cpu_to_be32(1);
1245 init->u.read.to_src_lo = cpu_to_be32(1);
1246 init->u.read.stag_sink = cpu_to_be32(1);
1247 init->u.read.to_sink_lo = cpu_to_be32(1);
1248 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16);
1249 break;
1250 }
1251 }
1252
1253 static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp)
1254 {
1255 struct fw_ri_wr *wqe;
1256 int ret;
1257 struct sk_buff *skb;
1258
1259 PDBG("%s qhp %p qid 0x%x tid %u ird %u ord %u\n", __func__, qhp,
1260 qhp->wq.sq.qid, qhp->ep->hwtid, qhp->ep->ird, qhp->ep->ord);
1261
1262 skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
1263 if (!skb) {
1264 ret = -ENOMEM;
1265 goto out;
1266 }
1267 ret = alloc_ird(rhp, qhp->attr.max_ird);
1268 if (ret) {
1269 qhp->attr.max_ird = 0;
1270 kfree_skb(skb);
1271 goto out;
1272 }
1273 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1274
1275 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1276 memset(wqe, 0, sizeof *wqe);
1277 wqe->op_compl = cpu_to_be32(
1278 FW_WR_OP_V(FW_RI_INIT_WR) |
1279 FW_WR_COMPL_F);
1280 wqe->flowid_len16 = cpu_to_be32(
1281 FW_WR_FLOWID_V(qhp->ep->hwtid) |
1282 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16)));
1283
1284 wqe->cookie = (uintptr_t)&qhp->ep->com.wr_wait;
1285
1286 wqe->u.init.type = FW_RI_TYPE_INIT;
1287 wqe->u.init.mpareqbit_p2ptype =
1288 FW_RI_WR_MPAREQBIT_V(qhp->attr.mpa_attr.initiator) |
1289 FW_RI_WR_P2PTYPE_V(qhp->attr.mpa_attr.p2p_type);
1290 wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE;
1291 if (qhp->attr.mpa_attr.recv_marker_enabled)
1292 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE;
1293 if (qhp->attr.mpa_attr.xmit_marker_enabled)
1294 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE;
1295 if (qhp->attr.mpa_attr.crc_enabled)
1296 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE;
1297
1298 wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE |
1299 FW_RI_QP_RDMA_WRITE_ENABLE |
1300 FW_RI_QP_BIND_ENABLE;
1301 if (!qhp->ibqp.uobject)
1302 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE |
1303 FW_RI_QP_STAG0_ENABLE;
1304 wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq));
1305 wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd);
1306 wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid);
1307 wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid);
1308 wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid);
1309 wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq);
1310 wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq);
1311 wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord);
1312 wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird);
1313 wqe->u.init.iss = cpu_to_be32(qhp->ep->snd_seq);
1314 wqe->u.init.irs = cpu_to_be32(qhp->ep->rcv_seq);
1315 wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size);
1316 wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr -
1317 rhp->rdev.lldi.vr->rq.start);
1318 if (qhp->attr.mpa_attr.initiator)
1319 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init);
1320
1321 ret = c4iw_ofld_send(&rhp->rdev, skb);
1322 if (ret)
1323 goto err1;
1324
1325 ret = c4iw_wait_for_reply(&rhp->rdev, &qhp->ep->com.wr_wait,
1326 qhp->ep->hwtid, qhp->wq.sq.qid, __func__);
1327 if (!ret)
1328 goto out;
1329 err1:
1330 free_ird(rhp, qhp->attr.max_ird);
1331 out:
1332 PDBG("%s ret %d\n", __func__, ret);
1333 return ret;
1334 }
1335
1336 int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1337 enum c4iw_qp_attr_mask mask,
1338 struct c4iw_qp_attributes *attrs,
1339 int internal)
1340 {
1341 int ret = 0;
1342 struct c4iw_qp_attributes newattr = qhp->attr;
1343 int disconnect = 0;
1344 int terminate = 0;
1345 int abort = 0;
1346 int free = 0;
1347 struct c4iw_ep *ep = NULL;
1348
1349 PDBG("%s qhp %p sqid 0x%x rqid 0x%x ep %p state %d -> %d\n", __func__,
1350 qhp, qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep, qhp->attr.state,
1351 (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1);
1352
1353 mutex_lock(&qhp->mutex);
1354
1355 /* Process attr changes if in IDLE */
1356 if (mask & C4IW_QP_ATTR_VALID_MODIFY) {
1357 if (qhp->attr.state != C4IW_QP_STATE_IDLE) {
1358 ret = -EIO;
1359 goto out;
1360 }
1361 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ)
1362 newattr.enable_rdma_read = attrs->enable_rdma_read;
1363 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE)
1364 newattr.enable_rdma_write = attrs->enable_rdma_write;
1365 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND)
1366 newattr.enable_bind = attrs->enable_bind;
1367 if (mask & C4IW_QP_ATTR_MAX_ORD) {
1368 if (attrs->max_ord > c4iw_max_read_depth) {
1369 ret = -EINVAL;
1370 goto out;
1371 }
1372 newattr.max_ord = attrs->max_ord;
1373 }
1374 if (mask & C4IW_QP_ATTR_MAX_IRD) {
1375 if (attrs->max_ird > cur_max_read_depth(rhp)) {
1376 ret = -EINVAL;
1377 goto out;
1378 }
1379 newattr.max_ird = attrs->max_ird;
1380 }
1381 qhp->attr = newattr;
1382 }
1383
1384 if (mask & C4IW_QP_ATTR_SQ_DB) {
1385 ret = ring_kernel_sq_db(qhp, attrs->sq_db_inc);
1386 goto out;
1387 }
1388 if (mask & C4IW_QP_ATTR_RQ_DB) {
1389 ret = ring_kernel_rq_db(qhp, attrs->rq_db_inc);
1390 goto out;
1391 }
1392
1393 if (!(mask & C4IW_QP_ATTR_NEXT_STATE))
1394 goto out;
1395 if (qhp->attr.state == attrs->next_state)
1396 goto out;
1397
1398 switch (qhp->attr.state) {
1399 case C4IW_QP_STATE_IDLE:
1400 switch (attrs->next_state) {
1401 case C4IW_QP_STATE_RTS:
1402 if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) {
1403 ret = -EINVAL;
1404 goto out;
1405 }
1406 if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) {
1407 ret = -EINVAL;
1408 goto out;
1409 }
1410 qhp->attr.mpa_attr = attrs->mpa_attr;
1411 qhp->attr.llp_stream_handle = attrs->llp_stream_handle;
1412 qhp->ep = qhp->attr.llp_stream_handle;
1413 set_state(qhp, C4IW_QP_STATE_RTS);
1414
1415 /*
1416 * Ref the endpoint here and deref when we
1417 * disassociate the endpoint from the QP. This
1418 * happens in CLOSING->IDLE transition or *->ERROR
1419 * transition.
1420 */
1421 c4iw_get_ep(&qhp->ep->com);
1422 ret = rdma_init(rhp, qhp);
1423 if (ret)
1424 goto err;
1425 break;
1426 case C4IW_QP_STATE_ERROR:
1427 set_state(qhp, C4IW_QP_STATE_ERROR);
1428 flush_qp(qhp);
1429 break;
1430 default:
1431 ret = -EINVAL;
1432 goto out;
1433 }
1434 break;
1435 case C4IW_QP_STATE_RTS:
1436 switch (attrs->next_state) {
1437 case C4IW_QP_STATE_CLOSING:
1438 BUG_ON(atomic_read(&qhp->ep->com.kref.refcount) < 2);
1439 t4_set_wq_in_error(&qhp->wq);
1440 set_state(qhp, C4IW_QP_STATE_CLOSING);
1441 ep = qhp->ep;
1442 if (!internal) {
1443 abort = 0;
1444 disconnect = 1;
1445 c4iw_get_ep(&qhp->ep->com);
1446 }
1447 ret = rdma_fini(rhp, qhp, ep);
1448 if (ret)
1449 goto err;
1450 break;
1451 case C4IW_QP_STATE_TERMINATE:
1452 t4_set_wq_in_error(&qhp->wq);
1453 set_state(qhp, C4IW_QP_STATE_TERMINATE);
1454 qhp->attr.layer_etype = attrs->layer_etype;
1455 qhp->attr.ecode = attrs->ecode;
1456 ep = qhp->ep;
1457 if (!internal) {
1458 c4iw_get_ep(&qhp->ep->com);
1459 terminate = 1;
1460 disconnect = 1;
1461 } else {
1462 terminate = qhp->attr.send_term;
1463 ret = rdma_fini(rhp, qhp, ep);
1464 if (ret)
1465 goto err;
1466 }
1467 break;
1468 case C4IW_QP_STATE_ERROR:
1469 t4_set_wq_in_error(&qhp->wq);
1470 set_state(qhp, C4IW_QP_STATE_ERROR);
1471 if (!internal) {
1472 abort = 1;
1473 disconnect = 1;
1474 ep = qhp->ep;
1475 c4iw_get_ep(&qhp->ep->com);
1476 }
1477 goto err;
1478 break;
1479 default:
1480 ret = -EINVAL;
1481 goto out;
1482 }
1483 break;
1484 case C4IW_QP_STATE_CLOSING:
1485 if (!internal) {
1486 ret = -EINVAL;
1487 goto out;
1488 }
1489 switch (attrs->next_state) {
1490 case C4IW_QP_STATE_IDLE:
1491 flush_qp(qhp);
1492 set_state(qhp, C4IW_QP_STATE_IDLE);
1493 qhp->attr.llp_stream_handle = NULL;
1494 c4iw_put_ep(&qhp->ep->com);
1495 qhp->ep = NULL;
1496 wake_up(&qhp->wait);
1497 break;
1498 case C4IW_QP_STATE_ERROR:
1499 goto err;
1500 default:
1501 ret = -EINVAL;
1502 goto err;
1503 }
1504 break;
1505 case C4IW_QP_STATE_ERROR:
1506 if (attrs->next_state != C4IW_QP_STATE_IDLE) {
1507 ret = -EINVAL;
1508 goto out;
1509 }
1510 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) {
1511 ret = -EINVAL;
1512 goto out;
1513 }
1514 set_state(qhp, C4IW_QP_STATE_IDLE);
1515 break;
1516 case C4IW_QP_STATE_TERMINATE:
1517 if (!internal) {
1518 ret = -EINVAL;
1519 goto out;
1520 }
1521 goto err;
1522 break;
1523 default:
1524 printk(KERN_ERR "%s in a bad state %d\n",
1525 __func__, qhp->attr.state);
1526 ret = -EINVAL;
1527 goto err;
1528 break;
1529 }
1530 goto out;
1531 err:
1532 PDBG("%s disassociating ep %p qpid 0x%x\n", __func__, qhp->ep,
1533 qhp->wq.sq.qid);
1534
1535 /* disassociate the LLP connection */
1536 qhp->attr.llp_stream_handle = NULL;
1537 if (!ep)
1538 ep = qhp->ep;
1539 qhp->ep = NULL;
1540 set_state(qhp, C4IW_QP_STATE_ERROR);
1541 free = 1;
1542 abort = 1;
1543 BUG_ON(!ep);
1544 flush_qp(qhp);
1545 wake_up(&qhp->wait);
1546 out:
1547 mutex_unlock(&qhp->mutex);
1548
1549 if (terminate)
1550 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL);
1551
1552 /*
1553 * If disconnect is 1, then we need to initiate a disconnect
1554 * on the EP. This can be a normal close (RTS->CLOSING) or
1555 * an abnormal close (RTS/CLOSING->ERROR).
1556 */
1557 if (disconnect) {
1558 c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC :
1559 GFP_KERNEL);
1560 c4iw_put_ep(&ep->com);
1561 }
1562
1563 /*
1564 * If free is 1, then we've disassociated the EP from the QP
1565 * and we need to dereference the EP.
1566 */
1567 if (free)
1568 c4iw_put_ep(&ep->com);
1569 PDBG("%s exit state %d\n", __func__, qhp->attr.state);
1570 return ret;
1571 }
1572
1573 int c4iw_destroy_qp(struct ib_qp *ib_qp)
1574 {
1575 struct c4iw_dev *rhp;
1576 struct c4iw_qp *qhp;
1577 struct c4iw_qp_attributes attrs;
1578 struct c4iw_ucontext *ucontext;
1579
1580 qhp = to_c4iw_qp(ib_qp);
1581 rhp = qhp->rhp;
1582
1583 attrs.next_state = C4IW_QP_STATE_ERROR;
1584 if (qhp->attr.state == C4IW_QP_STATE_TERMINATE)
1585 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1);
1586 else
1587 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0);
1588 wait_event(qhp->wait, !qhp->ep);
1589
1590 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1591 atomic_dec(&qhp->refcnt);
1592 wait_event(qhp->wait, !atomic_read(&qhp->refcnt));
1593
1594 spin_lock_irq(&rhp->lock);
1595 if (!list_empty(&qhp->db_fc_entry))
1596 list_del_init(&qhp->db_fc_entry);
1597 spin_unlock_irq(&rhp->lock);
1598 free_ird(rhp, qhp->attr.max_ird);
1599
1600 ucontext = ib_qp->uobject ?
1601 to_c4iw_ucontext(ib_qp->uobject->context) : NULL;
1602 destroy_qp(&rhp->rdev, &qhp->wq,
1603 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1604
1605 PDBG("%s ib_qp %p qpid 0x%0x\n", __func__, ib_qp, qhp->wq.sq.qid);
1606 kfree(qhp);
1607 return 0;
1608 }
1609
1610 struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1611 struct ib_udata *udata)
1612 {
1613 struct c4iw_dev *rhp;
1614 struct c4iw_qp *qhp;
1615 struct c4iw_pd *php;
1616 struct c4iw_cq *schp;
1617 struct c4iw_cq *rchp;
1618 struct c4iw_create_qp_resp uresp;
1619 unsigned int sqsize, rqsize;
1620 struct c4iw_ucontext *ucontext;
1621 int ret;
1622 struct c4iw_mm_entry *sq_key_mm, *rq_key_mm = NULL, *sq_db_key_mm;
1623 struct c4iw_mm_entry *rq_db_key_mm = NULL, *ma_sync_key_mm = NULL;
1624
1625 PDBG("%s ib_pd %p\n", __func__, pd);
1626
1627 if (attrs->qp_type != IB_QPT_RC)
1628 return ERR_PTR(-EINVAL);
1629
1630 php = to_c4iw_pd(pd);
1631 rhp = php->rhp;
1632 schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid);
1633 rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid);
1634 if (!schp || !rchp)
1635 return ERR_PTR(-EINVAL);
1636
1637 if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE)
1638 return ERR_PTR(-EINVAL);
1639
1640 if (attrs->cap.max_recv_wr > rhp->rdev.hw_queue.t4_max_rq_size)
1641 return ERR_PTR(-E2BIG);
1642 rqsize = attrs->cap.max_recv_wr + 1;
1643 if (rqsize < 8)
1644 rqsize = 8;
1645
1646 if (attrs->cap.max_send_wr > rhp->rdev.hw_queue.t4_max_sq_size)
1647 return ERR_PTR(-E2BIG);
1648 sqsize = attrs->cap.max_send_wr + 1;
1649 if (sqsize < 8)
1650 sqsize = 8;
1651
1652 ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL;
1653
1654 qhp = kzalloc(sizeof(*qhp), GFP_KERNEL);
1655 if (!qhp)
1656 return ERR_PTR(-ENOMEM);
1657 qhp->wq.sq.size = sqsize;
1658 qhp->wq.sq.memsize =
1659 (sqsize + rhp->rdev.hw_queue.t4_eq_status_entries) *
1660 sizeof(*qhp->wq.sq.queue) + 16 * sizeof(__be64);
1661 qhp->wq.sq.flush_cidx = -1;
1662 qhp->wq.rq.size = rqsize;
1663 qhp->wq.rq.memsize =
1664 (rqsize + rhp->rdev.hw_queue.t4_eq_status_entries) *
1665 sizeof(*qhp->wq.rq.queue);
1666
1667 if (ucontext) {
1668 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE);
1669 qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE);
1670 }
1671
1672 ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq,
1673 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1674 if (ret)
1675 goto err1;
1676
1677 attrs->cap.max_recv_wr = rqsize - 1;
1678 attrs->cap.max_send_wr = sqsize - 1;
1679 attrs->cap.max_inline_data = T4_MAX_SEND_INLINE;
1680
1681 qhp->rhp = rhp;
1682 qhp->attr.pd = php->pdid;
1683 qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid;
1684 qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid;
1685 qhp->attr.sq_num_entries = attrs->cap.max_send_wr;
1686 qhp->attr.rq_num_entries = attrs->cap.max_recv_wr;
1687 qhp->attr.sq_max_sges = attrs->cap.max_send_sge;
1688 qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge;
1689 qhp->attr.rq_max_sges = attrs->cap.max_recv_sge;
1690 qhp->attr.state = C4IW_QP_STATE_IDLE;
1691 qhp->attr.next_state = C4IW_QP_STATE_IDLE;
1692 qhp->attr.enable_rdma_read = 1;
1693 qhp->attr.enable_rdma_write = 1;
1694 qhp->attr.enable_bind = 1;
1695 qhp->attr.max_ord = 0;
1696 qhp->attr.max_ird = 0;
1697 qhp->sq_sig_all = attrs->sq_sig_type == IB_SIGNAL_ALL_WR;
1698 spin_lock_init(&qhp->lock);
1699 init_completion(&qhp->sq_drained);
1700 init_completion(&qhp->rq_drained);
1701 mutex_init(&qhp->mutex);
1702 init_waitqueue_head(&qhp->wait);
1703 atomic_set(&qhp->refcnt, 1);
1704
1705 ret = insert_handle(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid);
1706 if (ret)
1707 goto err2;
1708
1709 if (udata) {
1710 sq_key_mm = kmalloc(sizeof(*sq_key_mm), GFP_KERNEL);
1711 if (!sq_key_mm) {
1712 ret = -ENOMEM;
1713 goto err3;
1714 }
1715 rq_key_mm = kmalloc(sizeof(*rq_key_mm), GFP_KERNEL);
1716 if (!rq_key_mm) {
1717 ret = -ENOMEM;
1718 goto err4;
1719 }
1720 sq_db_key_mm = kmalloc(sizeof(*sq_db_key_mm), GFP_KERNEL);
1721 if (!sq_db_key_mm) {
1722 ret = -ENOMEM;
1723 goto err5;
1724 }
1725 rq_db_key_mm = kmalloc(sizeof(*rq_db_key_mm), GFP_KERNEL);
1726 if (!rq_db_key_mm) {
1727 ret = -ENOMEM;
1728 goto err6;
1729 }
1730 if (t4_sq_onchip(&qhp->wq.sq)) {
1731 ma_sync_key_mm = kmalloc(sizeof(*ma_sync_key_mm),
1732 GFP_KERNEL);
1733 if (!ma_sync_key_mm) {
1734 ret = -ENOMEM;
1735 goto err7;
1736 }
1737 uresp.flags = C4IW_QPF_ONCHIP;
1738 } else
1739 uresp.flags = 0;
1740 uresp.qid_mask = rhp->rdev.qpmask;
1741 uresp.sqid = qhp->wq.sq.qid;
1742 uresp.sq_size = qhp->wq.sq.size;
1743 uresp.sq_memsize = qhp->wq.sq.memsize;
1744 uresp.rqid = qhp->wq.rq.qid;
1745 uresp.rq_size = qhp->wq.rq.size;
1746 uresp.rq_memsize = qhp->wq.rq.memsize;
1747 spin_lock(&ucontext->mmap_lock);
1748 if (ma_sync_key_mm) {
1749 uresp.ma_sync_key = ucontext->key;
1750 ucontext->key += PAGE_SIZE;
1751 } else {
1752 uresp.ma_sync_key = 0;
1753 }
1754 uresp.sq_key = ucontext->key;
1755 ucontext->key += PAGE_SIZE;
1756 uresp.rq_key = ucontext->key;
1757 ucontext->key += PAGE_SIZE;
1758 uresp.sq_db_gts_key = ucontext->key;
1759 ucontext->key += PAGE_SIZE;
1760 uresp.rq_db_gts_key = ucontext->key;
1761 ucontext->key += PAGE_SIZE;
1762 spin_unlock(&ucontext->mmap_lock);
1763 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp);
1764 if (ret)
1765 goto err8;
1766 sq_key_mm->key = uresp.sq_key;
1767 sq_key_mm->addr = qhp->wq.sq.phys_addr;
1768 sq_key_mm->len = PAGE_ALIGN(qhp->wq.sq.memsize);
1769 insert_mmap(ucontext, sq_key_mm);
1770 rq_key_mm->key = uresp.rq_key;
1771 rq_key_mm->addr = virt_to_phys(qhp->wq.rq.queue);
1772 rq_key_mm->len = PAGE_ALIGN(qhp->wq.rq.memsize);
1773 insert_mmap(ucontext, rq_key_mm);
1774 sq_db_key_mm->key = uresp.sq_db_gts_key;
1775 sq_db_key_mm->addr = (u64)(unsigned long)qhp->wq.sq.bar2_pa;
1776 sq_db_key_mm->len = PAGE_SIZE;
1777 insert_mmap(ucontext, sq_db_key_mm);
1778 rq_db_key_mm->key = uresp.rq_db_gts_key;
1779 rq_db_key_mm->addr = (u64)(unsigned long)qhp->wq.rq.bar2_pa;
1780 rq_db_key_mm->len = PAGE_SIZE;
1781 insert_mmap(ucontext, rq_db_key_mm);
1782 if (ma_sync_key_mm) {
1783 ma_sync_key_mm->key = uresp.ma_sync_key;
1784 ma_sync_key_mm->addr =
1785 (pci_resource_start(rhp->rdev.lldi.pdev, 0) +
1786 PCIE_MA_SYNC_A) & PAGE_MASK;
1787 ma_sync_key_mm->len = PAGE_SIZE;
1788 insert_mmap(ucontext, ma_sync_key_mm);
1789 }
1790 }
1791 qhp->ibqp.qp_num = qhp->wq.sq.qid;
1792 init_timer(&(qhp->timer));
1793 INIT_LIST_HEAD(&qhp->db_fc_entry);
1794 PDBG("%s sq id %u size %u memsize %zu num_entries %u "
1795 "rq id %u size %u memsize %zu num_entries %u\n", __func__,
1796 qhp->wq.sq.qid, qhp->wq.sq.size, qhp->wq.sq.memsize,
1797 attrs->cap.max_send_wr, qhp->wq.rq.qid, qhp->wq.rq.size,
1798 qhp->wq.rq.memsize, attrs->cap.max_recv_wr);
1799 return &qhp->ibqp;
1800 err8:
1801 kfree(ma_sync_key_mm);
1802 err7:
1803 kfree(rq_db_key_mm);
1804 err6:
1805 kfree(sq_db_key_mm);
1806 err5:
1807 kfree(rq_key_mm);
1808 err4:
1809 kfree(sq_key_mm);
1810 err3:
1811 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1812 err2:
1813 destroy_qp(&rhp->rdev, &qhp->wq,
1814 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1815 err1:
1816 kfree(qhp);
1817 return ERR_PTR(ret);
1818 }
1819
1820 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1821 int attr_mask, struct ib_udata *udata)
1822 {
1823 struct c4iw_dev *rhp;
1824 struct c4iw_qp *qhp;
1825 enum c4iw_qp_attr_mask mask = 0;
1826 struct c4iw_qp_attributes attrs;
1827
1828 PDBG("%s ib_qp %p\n", __func__, ibqp);
1829
1830 /* iwarp does not support the RTR state */
1831 if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR))
1832 attr_mask &= ~IB_QP_STATE;
1833
1834 /* Make sure we still have something left to do */
1835 if (!attr_mask)
1836 return 0;
1837
1838 memset(&attrs, 0, sizeof attrs);
1839 qhp = to_c4iw_qp(ibqp);
1840 rhp = qhp->rhp;
1841
1842 attrs.next_state = c4iw_convert_state(attr->qp_state);
1843 attrs.enable_rdma_read = (attr->qp_access_flags &
1844 IB_ACCESS_REMOTE_READ) ? 1 : 0;
1845 attrs.enable_rdma_write = (attr->qp_access_flags &
1846 IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
1847 attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0;
1848
1849
1850 mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0;
1851 mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ?
1852 (C4IW_QP_ATTR_ENABLE_RDMA_READ |
1853 C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
1854 C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0;
1855
1856 /*
1857 * Use SQ_PSN and RQ_PSN to pass in IDX_INC values for
1858 * ringing the queue db when we're in DB_FULL mode.
1859 * Only allow this on T4 devices.
1860 */
1861 attrs.sq_db_inc = attr->sq_psn;
1862 attrs.rq_db_inc = attr->rq_psn;
1863 mask |= (attr_mask & IB_QP_SQ_PSN) ? C4IW_QP_ATTR_SQ_DB : 0;
1864 mask |= (attr_mask & IB_QP_RQ_PSN) ? C4IW_QP_ATTR_RQ_DB : 0;
1865 if (!is_t4(to_c4iw_qp(ibqp)->rhp->rdev.lldi.adapter_type) &&
1866 (mask & (C4IW_QP_ATTR_SQ_DB|C4IW_QP_ATTR_RQ_DB)))
1867 return -EINVAL;
1868
1869 return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0);
1870 }
1871
1872 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn)
1873 {
1874 PDBG("%s ib_dev %p qpn 0x%x\n", __func__, dev, qpn);
1875 return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn);
1876 }
1877
1878 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1879 int attr_mask, struct ib_qp_init_attr *init_attr)
1880 {
1881 struct c4iw_qp *qhp = to_c4iw_qp(ibqp);
1882
1883 memset(attr, 0, sizeof *attr);
1884 memset(init_attr, 0, sizeof *init_attr);
1885 attr->qp_state = to_ib_qp_state(qhp->attr.state);
1886 init_attr->cap.max_send_wr = qhp->attr.sq_num_entries;
1887 init_attr->cap.max_recv_wr = qhp->attr.rq_num_entries;
1888 init_attr->cap.max_send_sge = qhp->attr.sq_max_sges;
1889 init_attr->cap.max_recv_sge = qhp->attr.sq_max_sges;
1890 init_attr->cap.max_inline_data = T4_MAX_SEND_INLINE;
1891 init_attr->sq_sig_type = qhp->sq_sig_all ? IB_SIGNAL_ALL_WR : 0;
1892 return 0;
1893 }
1894
1895 void c4iw_drain_sq(struct ib_qp *ibqp)
1896 {
1897 struct c4iw_qp *qp = to_c4iw_qp(ibqp);
1898
1899 wait_for_completion(&qp->sq_drained);
1900 }
1901
1902 void c4iw_drain_rq(struct ib_qp *ibqp)
1903 {
1904 struct c4iw_qp *qp = to_c4iw_qp(ibqp);
1905
1906 wait_for_completion(&qp->rq_drained);
1907 }
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