2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/module.h>
37 static int db_delay_usecs
= 1;
38 module_param(db_delay_usecs
, int, 0644);
39 MODULE_PARM_DESC(db_delay_usecs
, "Usecs to delay awaiting db fifo to drain");
41 static int ocqp_support
= 1;
42 module_param(ocqp_support
, int, 0644);
43 MODULE_PARM_DESC(ocqp_support
, "Support on-chip SQs (default=1)");
45 int db_fc_threshold
= 1000;
46 module_param(db_fc_threshold
, int, 0644);
47 MODULE_PARM_DESC(db_fc_threshold
,
48 "QP count/threshold that triggers"
49 " automatic db flow control mode (default = 1000)");
51 int db_coalescing_threshold
;
52 module_param(db_coalescing_threshold
, int, 0644);
53 MODULE_PARM_DESC(db_coalescing_threshold
,
54 "QP count/threshold that triggers"
55 " disabling db coalescing (default = 0)");
57 static int max_fr_immd
= T4_MAX_FR_IMMD
;
58 module_param(max_fr_immd
, int, 0644);
59 MODULE_PARM_DESC(max_fr_immd
, "fastreg threshold for using DSGL instead of immedate");
61 static int alloc_ird(struct c4iw_dev
*dev
, u32 ird
)
65 spin_lock_irq(&dev
->lock
);
66 if (ird
<= dev
->avail_ird
)
67 dev
->avail_ird
-= ird
;
70 spin_unlock_irq(&dev
->lock
);
73 dev_warn(&dev
->rdev
.lldi
.pdev
->dev
,
74 "device IRD resources exhausted\n");
79 static void free_ird(struct c4iw_dev
*dev
, int ird
)
81 spin_lock_irq(&dev
->lock
);
82 dev
->avail_ird
+= ird
;
83 spin_unlock_irq(&dev
->lock
);
86 static void set_state(struct c4iw_qp
*qhp
, enum c4iw_qp_state state
)
89 spin_lock_irqsave(&qhp
->lock
, flag
);
90 qhp
->attr
.state
= state
;
91 spin_unlock_irqrestore(&qhp
->lock
, flag
);
94 static void dealloc_oc_sq(struct c4iw_rdev
*rdev
, struct t4_sq
*sq
)
96 c4iw_ocqp_pool_free(rdev
, sq
->dma_addr
, sq
->memsize
);
99 static void dealloc_host_sq(struct c4iw_rdev
*rdev
, struct t4_sq
*sq
)
101 dma_free_coherent(&(rdev
->lldi
.pdev
->dev
), sq
->memsize
, sq
->queue
,
102 pci_unmap_addr(sq
, mapping
));
105 static void dealloc_sq(struct c4iw_rdev
*rdev
, struct t4_sq
*sq
)
107 if (t4_sq_onchip(sq
))
108 dealloc_oc_sq(rdev
, sq
);
110 dealloc_host_sq(rdev
, sq
);
113 static int alloc_oc_sq(struct c4iw_rdev
*rdev
, struct t4_sq
*sq
)
115 if (!ocqp_support
|| !ocqp_supported(&rdev
->lldi
))
117 sq
->dma_addr
= c4iw_ocqp_pool_alloc(rdev
, sq
->memsize
);
120 sq
->phys_addr
= rdev
->oc_mw_pa
+ sq
->dma_addr
-
121 rdev
->lldi
.vr
->ocq
.start
;
122 sq
->queue
= (__force
union t4_wr
*)(rdev
->oc_mw_kva
+ sq
->dma_addr
-
123 rdev
->lldi
.vr
->ocq
.start
);
124 sq
->flags
|= T4_SQ_ONCHIP
;
128 static int alloc_host_sq(struct c4iw_rdev
*rdev
, struct t4_sq
*sq
)
130 sq
->queue
= dma_alloc_coherent(&(rdev
->lldi
.pdev
->dev
), sq
->memsize
,
131 &(sq
->dma_addr
), GFP_KERNEL
);
134 sq
->phys_addr
= virt_to_phys(sq
->queue
);
135 pci_unmap_addr_set(sq
, mapping
, sq
->dma_addr
);
139 static int alloc_sq(struct c4iw_rdev
*rdev
, struct t4_sq
*sq
, int user
)
143 ret
= alloc_oc_sq(rdev
, sq
);
145 ret
= alloc_host_sq(rdev
, sq
);
149 static int destroy_qp(struct c4iw_rdev
*rdev
, struct t4_wq
*wq
,
150 struct c4iw_dev_ucontext
*uctx
)
153 * uP clears EQ contexts when the connection exits rdma mode,
154 * so no need to post a RESET WR for these EQs.
156 dma_free_coherent(&(rdev
->lldi
.pdev
->dev
),
157 wq
->rq
.memsize
, wq
->rq
.queue
,
158 dma_unmap_addr(&wq
->rq
, mapping
));
159 dealloc_sq(rdev
, &wq
->sq
);
160 c4iw_rqtpool_free(rdev
, wq
->rq
.rqt_hwaddr
, wq
->rq
.rqt_size
);
163 c4iw_put_qpid(rdev
, wq
->rq
.qid
, uctx
);
164 c4iw_put_qpid(rdev
, wq
->sq
.qid
, uctx
);
169 * Determine the BAR2 virtual address and qid. If pbar2_pa is not NULL,
170 * then this is a user mapping so compute the page-aligned physical address
173 void __iomem
*c4iw_bar2_addrs(struct c4iw_rdev
*rdev
, unsigned int qid
,
174 enum cxgb4_bar2_qtype qtype
,
175 unsigned int *pbar2_qid
, u64
*pbar2_pa
)
180 ret
= cxgb4_bar2_sge_qregs(rdev
->lldi
.ports
[0], qid
, qtype
,
182 &bar2_qoffset
, pbar2_qid
);
187 *pbar2_pa
= (rdev
->bar2_pa
+ bar2_qoffset
) & PAGE_MASK
;
189 if (is_t4(rdev
->lldi
.adapter_type
))
192 return rdev
->bar2_kva
+ bar2_qoffset
;
195 static int create_qp(struct c4iw_rdev
*rdev
, struct t4_wq
*wq
,
196 struct t4_cq
*rcq
, struct t4_cq
*scq
,
197 struct c4iw_dev_ucontext
*uctx
)
199 int user
= (uctx
!= &rdev
->uctx
);
200 struct fw_ri_res_wr
*res_wr
;
201 struct fw_ri_res
*res
;
203 struct c4iw_wr_wait wr_wait
;
208 wq
->sq
.qid
= c4iw_get_qpid(rdev
, uctx
);
212 wq
->rq
.qid
= c4iw_get_qpid(rdev
, uctx
);
219 wq
->sq
.sw_sq
= kzalloc(wq
->sq
.size
* sizeof *wq
->sq
.sw_sq
,
226 wq
->rq
.sw_rq
= kzalloc(wq
->rq
.size
* sizeof *wq
->rq
.sw_rq
,
235 * RQT must be a power of 2 and at least 16 deep.
237 wq
->rq
.rqt_size
= roundup_pow_of_two(max_t(u16
, wq
->rq
.size
, 16));
238 wq
->rq
.rqt_hwaddr
= c4iw_rqtpool_alloc(rdev
, wq
->rq
.rqt_size
);
239 if (!wq
->rq
.rqt_hwaddr
) {
244 ret
= alloc_sq(rdev
, &wq
->sq
, user
);
247 memset(wq
->sq
.queue
, 0, wq
->sq
.memsize
);
248 dma_unmap_addr_set(&wq
->sq
, mapping
, wq
->sq
.dma_addr
);
250 wq
->rq
.queue
= dma_alloc_coherent(&(rdev
->lldi
.pdev
->dev
),
251 wq
->rq
.memsize
, &(wq
->rq
.dma_addr
),
257 PDBG("%s sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx\n",
258 __func__
, wq
->sq
.queue
,
259 (unsigned long long)virt_to_phys(wq
->sq
.queue
),
261 (unsigned long long)virt_to_phys(wq
->rq
.queue
));
262 memset(wq
->rq
.queue
, 0, wq
->rq
.memsize
);
263 dma_unmap_addr_set(&wq
->rq
, mapping
, wq
->rq
.dma_addr
);
265 wq
->db
= rdev
->lldi
.db_reg
;
267 wq
->sq
.bar2_va
= c4iw_bar2_addrs(rdev
, wq
->sq
.qid
, T4_BAR2_QTYPE_EGRESS
,
269 user
? &wq
->sq
.bar2_pa
: NULL
);
270 wq
->rq
.bar2_va
= c4iw_bar2_addrs(rdev
, wq
->rq
.qid
, T4_BAR2_QTYPE_EGRESS
,
272 user
? &wq
->rq
.bar2_pa
: NULL
);
275 * User mode must have bar2 access.
277 if (user
&& (!wq
->sq
.bar2_pa
|| !wq
->rq
.bar2_pa
)) {
278 pr_warn(MOD
"%s: sqid %u or rqid %u not in BAR2 range.\n",
279 pci_name(rdev
->lldi
.pdev
), wq
->sq
.qid
, wq
->rq
.qid
);
286 /* build fw_ri_res_wr */
287 wr_len
= sizeof *res_wr
+ 2 * sizeof *res
;
289 skb
= alloc_skb(wr_len
, GFP_KERNEL
);
294 set_wr_txq(skb
, CPL_PRIORITY_CONTROL
, 0);
296 res_wr
= (struct fw_ri_res_wr
*)__skb_put(skb
, wr_len
);
297 memset(res_wr
, 0, wr_len
);
298 res_wr
->op_nres
= cpu_to_be32(
299 FW_WR_OP_V(FW_RI_RES_WR
) |
300 FW_RI_RES_WR_NRES_V(2) |
302 res_wr
->len16_pkd
= cpu_to_be32(DIV_ROUND_UP(wr_len
, 16));
303 res_wr
->cookie
= (uintptr_t)&wr_wait
;
305 res
->u
.sqrq
.restype
= FW_RI_RES_TYPE_SQ
;
306 res
->u
.sqrq
.op
= FW_RI_RES_OP_WRITE
;
309 * eqsize is the number of 64B entries plus the status page size.
311 eqsize
= wq
->sq
.size
* T4_SQ_NUM_SLOTS
+
312 rdev
->hw_queue
.t4_eq_status_entries
;
314 res
->u
.sqrq
.fetchszm_to_iqid
= cpu_to_be32(
315 FW_RI_RES_WR_HOSTFCMODE_V(0) | /* no host cidx updates */
316 FW_RI_RES_WR_CPRIO_V(0) | /* don't keep in chip cache */
317 FW_RI_RES_WR_PCIECHN_V(0) | /* set by uP at ri_init time */
318 (t4_sq_onchip(&wq
->sq
) ? FW_RI_RES_WR_ONCHIP_F
: 0) |
319 FW_RI_RES_WR_IQID_V(scq
->cqid
));
320 res
->u
.sqrq
.dcaen_to_eqsize
= cpu_to_be32(
321 FW_RI_RES_WR_DCAEN_V(0) |
322 FW_RI_RES_WR_DCACPU_V(0) |
323 FW_RI_RES_WR_FBMIN_V(2) |
324 FW_RI_RES_WR_FBMAX_V(2) |
325 FW_RI_RES_WR_CIDXFTHRESHO_V(0) |
326 FW_RI_RES_WR_CIDXFTHRESH_V(0) |
327 FW_RI_RES_WR_EQSIZE_V(eqsize
));
328 res
->u
.sqrq
.eqid
= cpu_to_be32(wq
->sq
.qid
);
329 res
->u
.sqrq
.eqaddr
= cpu_to_be64(wq
->sq
.dma_addr
);
331 res
->u
.sqrq
.restype
= FW_RI_RES_TYPE_RQ
;
332 res
->u
.sqrq
.op
= FW_RI_RES_OP_WRITE
;
335 * eqsize is the number of 64B entries plus the status page size.
337 eqsize
= wq
->rq
.size
* T4_RQ_NUM_SLOTS
+
338 rdev
->hw_queue
.t4_eq_status_entries
;
339 res
->u
.sqrq
.fetchszm_to_iqid
= cpu_to_be32(
340 FW_RI_RES_WR_HOSTFCMODE_V(0) | /* no host cidx updates */
341 FW_RI_RES_WR_CPRIO_V(0) | /* don't keep in chip cache */
342 FW_RI_RES_WR_PCIECHN_V(0) | /* set by uP at ri_init time */
343 FW_RI_RES_WR_IQID_V(rcq
->cqid
));
344 res
->u
.sqrq
.dcaen_to_eqsize
= cpu_to_be32(
345 FW_RI_RES_WR_DCAEN_V(0) |
346 FW_RI_RES_WR_DCACPU_V(0) |
347 FW_RI_RES_WR_FBMIN_V(2) |
348 FW_RI_RES_WR_FBMAX_V(2) |
349 FW_RI_RES_WR_CIDXFTHRESHO_V(0) |
350 FW_RI_RES_WR_CIDXFTHRESH_V(0) |
351 FW_RI_RES_WR_EQSIZE_V(eqsize
));
352 res
->u
.sqrq
.eqid
= cpu_to_be32(wq
->rq
.qid
);
353 res
->u
.sqrq
.eqaddr
= cpu_to_be64(wq
->rq
.dma_addr
);
355 c4iw_init_wr_wait(&wr_wait
);
357 ret
= c4iw_ofld_send(rdev
, skb
);
360 ret
= c4iw_wait_for_reply(rdev
, &wr_wait
, 0, wq
->sq
.qid
, __func__
);
364 PDBG("%s sqid 0x%x rqid 0x%x kdb 0x%p sq_bar2_addr %p rq_bar2_addr %p\n",
365 __func__
, wq
->sq
.qid
, wq
->rq
.qid
, wq
->db
,
366 wq
->sq
.bar2_va
, wq
->rq
.bar2_va
);
370 dma_free_coherent(&(rdev
->lldi
.pdev
->dev
),
371 wq
->rq
.memsize
, wq
->rq
.queue
,
372 dma_unmap_addr(&wq
->rq
, mapping
));
374 dealloc_sq(rdev
, &wq
->sq
);
376 c4iw_rqtpool_free(rdev
, wq
->rq
.rqt_hwaddr
, wq
->rq
.rqt_size
);
382 c4iw_put_qpid(rdev
, wq
->rq
.qid
, uctx
);
384 c4iw_put_qpid(rdev
, wq
->sq
.qid
, uctx
);
388 static int build_immd(struct t4_sq
*sq
, struct fw_ri_immd
*immdp
,
389 struct ib_send_wr
*wr
, int max
, u32
*plenp
)
396 dstp
= (u8
*)immdp
->data
;
397 for (i
= 0; i
< wr
->num_sge
; i
++) {
398 if ((plen
+ wr
->sg_list
[i
].length
) > max
)
400 srcp
= (u8
*)(unsigned long)wr
->sg_list
[i
].addr
;
401 plen
+= wr
->sg_list
[i
].length
;
402 rem
= wr
->sg_list
[i
].length
;
404 if (dstp
== (u8
*)&sq
->queue
[sq
->size
])
405 dstp
= (u8
*)sq
->queue
;
406 if (rem
<= (u8
*)&sq
->queue
[sq
->size
] - dstp
)
409 len
= (u8
*)&sq
->queue
[sq
->size
] - dstp
;
410 memcpy(dstp
, srcp
, len
);
416 len
= roundup(plen
+ sizeof *immdp
, 16) - (plen
+ sizeof *immdp
);
418 memset(dstp
, 0, len
);
419 immdp
->op
= FW_RI_DATA_IMMD
;
422 immdp
->immdlen
= cpu_to_be32(plen
);
427 static int build_isgl(__be64
*queue_start
, __be64
*queue_end
,
428 struct fw_ri_isgl
*isglp
, struct ib_sge
*sg_list
,
429 int num_sge
, u32
*plenp
)
434 __be64
*flitp
= (__be64
*)isglp
->sge
;
436 for (i
= 0; i
< num_sge
; i
++) {
437 if ((plen
+ sg_list
[i
].length
) < plen
)
439 plen
+= sg_list
[i
].length
;
440 *flitp
= cpu_to_be64(((u64
)sg_list
[i
].lkey
<< 32) |
442 if (++flitp
== queue_end
)
444 *flitp
= cpu_to_be64(sg_list
[i
].addr
);
445 if (++flitp
== queue_end
)
448 *flitp
= (__force __be64
)0;
449 isglp
->op
= FW_RI_DATA_ISGL
;
451 isglp
->nsge
= cpu_to_be16(num_sge
);
458 static int build_rdma_send(struct t4_sq
*sq
, union t4_wr
*wqe
,
459 struct ib_send_wr
*wr
, u8
*len16
)
465 if (wr
->num_sge
> T4_MAX_SEND_SGE
)
467 switch (wr
->opcode
) {
469 if (wr
->send_flags
& IB_SEND_SOLICITED
)
470 wqe
->send
.sendop_pkd
= cpu_to_be32(
471 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_SE
));
473 wqe
->send
.sendop_pkd
= cpu_to_be32(
474 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND
));
475 wqe
->send
.stag_inv
= 0;
477 case IB_WR_SEND_WITH_INV
:
478 if (wr
->send_flags
& IB_SEND_SOLICITED
)
479 wqe
->send
.sendop_pkd
= cpu_to_be32(
480 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_SE_INV
));
482 wqe
->send
.sendop_pkd
= cpu_to_be32(
483 FW_RI_SEND_WR_SENDOP_V(FW_RI_SEND_WITH_INV
));
484 wqe
->send
.stag_inv
= cpu_to_be32(wr
->ex
.invalidate_rkey
);
495 if (wr
->send_flags
& IB_SEND_INLINE
) {
496 ret
= build_immd(sq
, wqe
->send
.u
.immd_src
, wr
,
497 T4_MAX_SEND_INLINE
, &plen
);
500 size
= sizeof wqe
->send
+ sizeof(struct fw_ri_immd
) +
503 ret
= build_isgl((__be64
*)sq
->queue
,
504 (__be64
*)&sq
->queue
[sq
->size
],
505 wqe
->send
.u
.isgl_src
,
506 wr
->sg_list
, wr
->num_sge
, &plen
);
509 size
= sizeof wqe
->send
+ sizeof(struct fw_ri_isgl
) +
510 wr
->num_sge
* sizeof(struct fw_ri_sge
);
513 wqe
->send
.u
.immd_src
[0].op
= FW_RI_DATA_IMMD
;
514 wqe
->send
.u
.immd_src
[0].r1
= 0;
515 wqe
->send
.u
.immd_src
[0].r2
= 0;
516 wqe
->send
.u
.immd_src
[0].immdlen
= 0;
517 size
= sizeof wqe
->send
+ sizeof(struct fw_ri_immd
);
520 *len16
= DIV_ROUND_UP(size
, 16);
521 wqe
->send
.plen
= cpu_to_be32(plen
);
525 static int build_rdma_write(struct t4_sq
*sq
, union t4_wr
*wqe
,
526 struct ib_send_wr
*wr
, u8
*len16
)
532 if (wr
->num_sge
> T4_MAX_SEND_SGE
)
535 wqe
->write
.stag_sink
= cpu_to_be32(rdma_wr(wr
)->rkey
);
536 wqe
->write
.to_sink
= cpu_to_be64(rdma_wr(wr
)->remote_addr
);
538 if (wr
->send_flags
& IB_SEND_INLINE
) {
539 ret
= build_immd(sq
, wqe
->write
.u
.immd_src
, wr
,
540 T4_MAX_WRITE_INLINE
, &plen
);
543 size
= sizeof wqe
->write
+ sizeof(struct fw_ri_immd
) +
546 ret
= build_isgl((__be64
*)sq
->queue
,
547 (__be64
*)&sq
->queue
[sq
->size
],
548 wqe
->write
.u
.isgl_src
,
549 wr
->sg_list
, wr
->num_sge
, &plen
);
552 size
= sizeof wqe
->write
+ sizeof(struct fw_ri_isgl
) +
553 wr
->num_sge
* sizeof(struct fw_ri_sge
);
556 wqe
->write
.u
.immd_src
[0].op
= FW_RI_DATA_IMMD
;
557 wqe
->write
.u
.immd_src
[0].r1
= 0;
558 wqe
->write
.u
.immd_src
[0].r2
= 0;
559 wqe
->write
.u
.immd_src
[0].immdlen
= 0;
560 size
= sizeof wqe
->write
+ sizeof(struct fw_ri_immd
);
563 *len16
= DIV_ROUND_UP(size
, 16);
564 wqe
->write
.plen
= cpu_to_be32(plen
);
568 static int build_rdma_read(union t4_wr
*wqe
, struct ib_send_wr
*wr
, u8
*len16
)
573 wqe
->read
.stag_src
= cpu_to_be32(rdma_wr(wr
)->rkey
);
574 wqe
->read
.to_src_hi
= cpu_to_be32((u32
)(rdma_wr(wr
)->remote_addr
576 wqe
->read
.to_src_lo
= cpu_to_be32((u32
)rdma_wr(wr
)->remote_addr
);
577 wqe
->read
.stag_sink
= cpu_to_be32(wr
->sg_list
[0].lkey
);
578 wqe
->read
.plen
= cpu_to_be32(wr
->sg_list
[0].length
);
579 wqe
->read
.to_sink_hi
= cpu_to_be32((u32
)(wr
->sg_list
[0].addr
581 wqe
->read
.to_sink_lo
= cpu_to_be32((u32
)(wr
->sg_list
[0].addr
));
583 wqe
->read
.stag_src
= cpu_to_be32(2);
584 wqe
->read
.to_src_hi
= 0;
585 wqe
->read
.to_src_lo
= 0;
586 wqe
->read
.stag_sink
= cpu_to_be32(2);
588 wqe
->read
.to_sink_hi
= 0;
589 wqe
->read
.to_sink_lo
= 0;
593 *len16
= DIV_ROUND_UP(sizeof wqe
->read
, 16);
597 static int build_rdma_recv(struct c4iw_qp
*qhp
, union t4_recv_wr
*wqe
,
598 struct ib_recv_wr
*wr
, u8
*len16
)
602 ret
= build_isgl((__be64
*)qhp
->wq
.rq
.queue
,
603 (__be64
*)&qhp
->wq
.rq
.queue
[qhp
->wq
.rq
.size
],
604 &wqe
->recv
.isgl
, wr
->sg_list
, wr
->num_sge
, NULL
);
607 *len16
= DIV_ROUND_UP(sizeof wqe
->recv
+
608 wr
->num_sge
* sizeof(struct fw_ri_sge
), 16);
612 static int build_memreg(struct t4_sq
*sq
, union t4_wr
*wqe
,
613 struct ib_reg_wr
*wr
, u8
*len16
, bool dsgl_supported
)
615 struct c4iw_mr
*mhp
= to_c4iw_mr(wr
->mr
);
616 struct fw_ri_immd
*imdp
;
619 int pbllen
= roundup(mhp
->mpl_len
* sizeof(u64
), 32);
622 if (mhp
->mpl_len
> t4_max_fr_depth(dsgl_supported
&& use_dsgl
))
625 wqe
->fr
.qpbinde_to_dcacpu
= 0;
626 wqe
->fr
.pgsz_shift
= ilog2(wr
->mr
->page_size
) - 12;
627 wqe
->fr
.addr_type
= FW_RI_VA_BASED_TO
;
628 wqe
->fr
.mem_perms
= c4iw_ib_to_tpt_access(wr
->access
);
630 wqe
->fr
.len_lo
= cpu_to_be32(mhp
->ibmr
.length
);
631 wqe
->fr
.stag
= cpu_to_be32(wr
->key
);
632 wqe
->fr
.va_hi
= cpu_to_be32(mhp
->ibmr
.iova
>> 32);
633 wqe
->fr
.va_lo_fbo
= cpu_to_be32(mhp
->ibmr
.iova
&
636 if (dsgl_supported
&& use_dsgl
&& (pbllen
> max_fr_immd
)) {
637 struct fw_ri_dsgl
*sglp
;
639 for (i
= 0; i
< mhp
->mpl_len
; i
++)
640 mhp
->mpl
[i
] = (__force u64
)cpu_to_be64((u64
)mhp
->mpl
[i
]);
642 sglp
= (struct fw_ri_dsgl
*)(&wqe
->fr
+ 1);
643 sglp
->op
= FW_RI_DATA_DSGL
;
645 sglp
->nsge
= cpu_to_be16(1);
646 sglp
->addr0
= cpu_to_be64(mhp
->mpl_addr
);
647 sglp
->len0
= cpu_to_be32(pbllen
);
649 *len16
= DIV_ROUND_UP(sizeof(wqe
->fr
) + sizeof(*sglp
), 16);
651 imdp
= (struct fw_ri_immd
*)(&wqe
->fr
+ 1);
652 imdp
->op
= FW_RI_DATA_IMMD
;
655 imdp
->immdlen
= cpu_to_be32(pbllen
);
656 p
= (__be64
*)(imdp
+ 1);
658 for (i
= 0; i
< mhp
->mpl_len
; i
++) {
659 *p
= cpu_to_be64((u64
)mhp
->mpl
[i
]);
661 if (++p
== (__be64
*)&sq
->queue
[sq
->size
])
662 p
= (__be64
*)sq
->queue
;
668 if (++p
== (__be64
*)&sq
->queue
[sq
->size
])
669 p
= (__be64
*)sq
->queue
;
671 *len16
= DIV_ROUND_UP(sizeof(wqe
->fr
) + sizeof(*imdp
)
677 static int build_inv_stag(union t4_wr
*wqe
, struct ib_send_wr
*wr
,
680 wqe
->inv
.stag_inv
= cpu_to_be32(wr
->ex
.invalidate_rkey
);
682 *len16
= DIV_ROUND_UP(sizeof wqe
->inv
, 16);
686 void c4iw_qp_add_ref(struct ib_qp
*qp
)
688 PDBG("%s ib_qp %p\n", __func__
, qp
);
689 atomic_inc(&(to_c4iw_qp(qp
)->refcnt
));
692 void c4iw_qp_rem_ref(struct ib_qp
*qp
)
694 PDBG("%s ib_qp %p\n", __func__
, qp
);
695 if (atomic_dec_and_test(&(to_c4iw_qp(qp
)->refcnt
)))
696 wake_up(&(to_c4iw_qp(qp
)->wait
));
699 static void add_to_fc_list(struct list_head
*head
, struct list_head
*entry
)
701 if (list_empty(entry
))
702 list_add_tail(entry
, head
);
705 static int ring_kernel_sq_db(struct c4iw_qp
*qhp
, u16 inc
)
709 spin_lock_irqsave(&qhp
->rhp
->lock
, flags
);
710 spin_lock(&qhp
->lock
);
711 if (qhp
->rhp
->db_state
== NORMAL
)
712 t4_ring_sq_db(&qhp
->wq
, inc
, NULL
);
714 add_to_fc_list(&qhp
->rhp
->db_fc_list
, &qhp
->db_fc_entry
);
715 qhp
->wq
.sq
.wq_pidx_inc
+= inc
;
717 spin_unlock(&qhp
->lock
);
718 spin_unlock_irqrestore(&qhp
->rhp
->lock
, flags
);
722 static int ring_kernel_rq_db(struct c4iw_qp
*qhp
, u16 inc
)
726 spin_lock_irqsave(&qhp
->rhp
->lock
, flags
);
727 spin_lock(&qhp
->lock
);
728 if (qhp
->rhp
->db_state
== NORMAL
)
729 t4_ring_rq_db(&qhp
->wq
, inc
, NULL
);
731 add_to_fc_list(&qhp
->rhp
->db_fc_list
, &qhp
->db_fc_entry
);
732 qhp
->wq
.rq
.wq_pidx_inc
+= inc
;
734 spin_unlock(&qhp
->lock
);
735 spin_unlock_irqrestore(&qhp
->rhp
->lock
, flags
);
739 int c4iw_post_send(struct ib_qp
*ibqp
, struct ib_send_wr
*wr
,
740 struct ib_send_wr
**bad_wr
)
744 enum fw_wr_opcodes fw_opcode
= 0;
745 enum fw_ri_wr_flags fw_flags
;
747 union t4_wr
*wqe
= NULL
;
749 struct t4_swsqe
*swsqe
;
753 qhp
= to_c4iw_qp(ibqp
);
754 spin_lock_irqsave(&qhp
->lock
, flag
);
755 if (t4_wq_in_error(&qhp
->wq
)) {
756 spin_unlock_irqrestore(&qhp
->lock
, flag
);
759 num_wrs
= t4_sq_avail(&qhp
->wq
);
761 spin_unlock_irqrestore(&qhp
->lock
, flag
);
770 wqe
= (union t4_wr
*)((u8
*)qhp
->wq
.sq
.queue
+
771 qhp
->wq
.sq
.wq_pidx
* T4_EQ_ENTRY_SIZE
);
774 if (wr
->send_flags
& IB_SEND_SOLICITED
)
775 fw_flags
|= FW_RI_SOLICITED_EVENT_FLAG
;
776 if (wr
->send_flags
& IB_SEND_SIGNALED
|| qhp
->sq_sig_all
)
777 fw_flags
|= FW_RI_COMPLETION_FLAG
;
778 swsqe
= &qhp
->wq
.sq
.sw_sq
[qhp
->wq
.sq
.pidx
];
779 switch (wr
->opcode
) {
780 case IB_WR_SEND_WITH_INV
:
782 if (wr
->send_flags
& IB_SEND_FENCE
)
783 fw_flags
|= FW_RI_READ_FENCE_FLAG
;
784 fw_opcode
= FW_RI_SEND_WR
;
785 if (wr
->opcode
== IB_WR_SEND
)
786 swsqe
->opcode
= FW_RI_SEND
;
788 swsqe
->opcode
= FW_RI_SEND_WITH_INV
;
789 err
= build_rdma_send(&qhp
->wq
.sq
, wqe
, wr
, &len16
);
791 case IB_WR_RDMA_WRITE
:
792 fw_opcode
= FW_RI_RDMA_WRITE_WR
;
793 swsqe
->opcode
= FW_RI_RDMA_WRITE
;
794 err
= build_rdma_write(&qhp
->wq
.sq
, wqe
, wr
, &len16
);
796 case IB_WR_RDMA_READ
:
797 case IB_WR_RDMA_READ_WITH_INV
:
798 fw_opcode
= FW_RI_RDMA_READ_WR
;
799 swsqe
->opcode
= FW_RI_READ_REQ
;
800 if (wr
->opcode
== IB_WR_RDMA_READ_WITH_INV
)
801 fw_flags
= FW_RI_RDMA_READ_INVALIDATE
;
804 err
= build_rdma_read(wqe
, wr
, &len16
);
807 swsqe
->read_len
= wr
->sg_list
[0].length
;
808 if (!qhp
->wq
.sq
.oldest_read
)
809 qhp
->wq
.sq
.oldest_read
= swsqe
;
812 fw_opcode
= FW_RI_FR_NSMR_WR
;
813 swsqe
->opcode
= FW_RI_FAST_REGISTER
;
814 err
= build_memreg(&qhp
->wq
.sq
, wqe
, reg_wr(wr
), &len16
,
815 qhp
->rhp
->rdev
.lldi
.ulptx_memwrite_dsgl
);
817 case IB_WR_LOCAL_INV
:
818 if (wr
->send_flags
& IB_SEND_FENCE
)
819 fw_flags
|= FW_RI_LOCAL_FENCE_FLAG
;
820 fw_opcode
= FW_RI_INV_LSTAG_WR
;
821 swsqe
->opcode
= FW_RI_LOCAL_INV
;
822 err
= build_inv_stag(wqe
, wr
, &len16
);
825 PDBG("%s post of type=%d TBD!\n", __func__
,
833 swsqe
->idx
= qhp
->wq
.sq
.pidx
;
835 swsqe
->signaled
= (wr
->send_flags
& IB_SEND_SIGNALED
) ||
838 swsqe
->wr_id
= wr
->wr_id
;
840 swsqe
->sge_ts
= cxgb4_read_sge_timestamp(
841 qhp
->rhp
->rdev
.lldi
.ports
[0]);
842 getnstimeofday(&swsqe
->host_ts
);
845 init_wr_hdr(wqe
, qhp
->wq
.sq
.pidx
, fw_opcode
, fw_flags
, len16
);
847 PDBG("%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u\n",
848 __func__
, (unsigned long long)wr
->wr_id
, qhp
->wq
.sq
.pidx
,
849 swsqe
->opcode
, swsqe
->read_len
);
852 t4_sq_produce(&qhp
->wq
, len16
);
853 idx
+= DIV_ROUND_UP(len16
*16, T4_EQ_ENTRY_SIZE
);
855 if (!qhp
->rhp
->rdev
.status_page
->db_off
) {
856 t4_ring_sq_db(&qhp
->wq
, idx
, wqe
);
857 spin_unlock_irqrestore(&qhp
->lock
, flag
);
859 spin_unlock_irqrestore(&qhp
->lock
, flag
);
860 ring_kernel_sq_db(qhp
, idx
);
865 int c4iw_post_receive(struct ib_qp
*ibqp
, struct ib_recv_wr
*wr
,
866 struct ib_recv_wr
**bad_wr
)
870 union t4_recv_wr
*wqe
= NULL
;
876 qhp
= to_c4iw_qp(ibqp
);
877 spin_lock_irqsave(&qhp
->lock
, flag
);
878 if (t4_wq_in_error(&qhp
->wq
)) {
879 spin_unlock_irqrestore(&qhp
->lock
, flag
);
882 num_wrs
= t4_rq_avail(&qhp
->wq
);
884 spin_unlock_irqrestore(&qhp
->lock
, flag
);
888 if (wr
->num_sge
> T4_MAX_RECV_SGE
) {
893 wqe
= (union t4_recv_wr
*)((u8
*)qhp
->wq
.rq
.queue
+
897 err
= build_rdma_recv(qhp
, wqe
, wr
, &len16
);
905 qhp
->wq
.rq
.sw_rq
[qhp
->wq
.rq
.pidx
].wr_id
= wr
->wr_id
;
907 qhp
->wq
.rq
.sw_rq
[qhp
->wq
.rq
.pidx
].sge_ts
=
908 cxgb4_read_sge_timestamp(
909 qhp
->rhp
->rdev
.lldi
.ports
[0]);
911 &qhp
->wq
.rq
.sw_rq
[qhp
->wq
.rq
.pidx
].host_ts
);
914 wqe
->recv
.opcode
= FW_RI_RECV_WR
;
916 wqe
->recv
.wrid
= qhp
->wq
.rq
.pidx
;
920 wqe
->recv
.len16
= len16
;
921 PDBG("%s cookie 0x%llx pidx %u\n", __func__
,
922 (unsigned long long) wr
->wr_id
, qhp
->wq
.rq
.pidx
);
923 t4_rq_produce(&qhp
->wq
, len16
);
924 idx
+= DIV_ROUND_UP(len16
*16, T4_EQ_ENTRY_SIZE
);
928 if (!qhp
->rhp
->rdev
.status_page
->db_off
) {
929 t4_ring_rq_db(&qhp
->wq
, idx
, wqe
);
930 spin_unlock_irqrestore(&qhp
->lock
, flag
);
932 spin_unlock_irqrestore(&qhp
->lock
, flag
);
933 ring_kernel_rq_db(qhp
, idx
);
938 static inline void build_term_codes(struct t4_cqe
*err_cqe
, u8
*layer_type
,
948 *layer_type
= LAYER_RDMAP
|DDP_LOCAL_CATA
;
953 status
= CQE_STATUS(err_cqe
);
954 opcode
= CQE_OPCODE(err_cqe
);
955 rqtype
= RQ_TYPE(err_cqe
);
956 send_inv
= (opcode
== FW_RI_SEND_WITH_INV
) ||
957 (opcode
== FW_RI_SEND_WITH_SE_INV
);
958 tagged
= (opcode
== FW_RI_RDMA_WRITE
) ||
959 (rqtype
&& (opcode
== FW_RI_READ_RESP
));
964 *layer_type
= LAYER_RDMAP
|RDMAP_REMOTE_OP
;
965 *ecode
= RDMAP_CANT_INV_STAG
;
967 *layer_type
= LAYER_RDMAP
|RDMAP_REMOTE_PROT
;
968 *ecode
= RDMAP_INV_STAG
;
972 *layer_type
= LAYER_RDMAP
|RDMAP_REMOTE_PROT
;
973 if ((opcode
== FW_RI_SEND_WITH_INV
) ||
974 (opcode
== FW_RI_SEND_WITH_SE_INV
))
975 *ecode
= RDMAP_CANT_INV_STAG
;
977 *ecode
= RDMAP_STAG_NOT_ASSOC
;
980 *layer_type
= LAYER_RDMAP
|RDMAP_REMOTE_PROT
;
981 *ecode
= RDMAP_STAG_NOT_ASSOC
;
984 *layer_type
= LAYER_RDMAP
|RDMAP_REMOTE_PROT
;
985 *ecode
= RDMAP_ACC_VIOL
;
988 *layer_type
= LAYER_RDMAP
|RDMAP_REMOTE_PROT
;
989 *ecode
= RDMAP_TO_WRAP
;
993 *layer_type
= LAYER_DDP
|DDP_TAGGED_ERR
;
994 *ecode
= DDPT_BASE_BOUNDS
;
996 *layer_type
= LAYER_RDMAP
|RDMAP_REMOTE_PROT
;
997 *ecode
= RDMAP_BASE_BOUNDS
;
1000 case T4_ERR_INVALIDATE_SHARED_MR
:
1001 case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND
:
1002 *layer_type
= LAYER_RDMAP
|RDMAP_REMOTE_OP
;
1003 *ecode
= RDMAP_CANT_INV_STAG
;
1006 case T4_ERR_ECC_PSTAG
:
1007 case T4_ERR_INTERNAL_ERR
:
1008 *layer_type
= LAYER_RDMAP
|RDMAP_LOCAL_CATA
;
1011 case T4_ERR_OUT_OF_RQE
:
1012 *layer_type
= LAYER_DDP
|DDP_UNTAGGED_ERR
;
1013 *ecode
= DDPU_INV_MSN_NOBUF
;
1015 case T4_ERR_PBL_ADDR_BOUND
:
1016 *layer_type
= LAYER_DDP
|DDP_TAGGED_ERR
;
1017 *ecode
= DDPT_BASE_BOUNDS
;
1020 *layer_type
= LAYER_MPA
|DDP_LLP
;
1021 *ecode
= MPA_CRC_ERR
;
1024 *layer_type
= LAYER_MPA
|DDP_LLP
;
1025 *ecode
= MPA_MARKER_ERR
;
1027 case T4_ERR_PDU_LEN_ERR
:
1028 *layer_type
= LAYER_DDP
|DDP_UNTAGGED_ERR
;
1029 *ecode
= DDPU_MSG_TOOBIG
;
1031 case T4_ERR_DDP_VERSION
:
1033 *layer_type
= LAYER_DDP
|DDP_TAGGED_ERR
;
1034 *ecode
= DDPT_INV_VERS
;
1036 *layer_type
= LAYER_DDP
|DDP_UNTAGGED_ERR
;
1037 *ecode
= DDPU_INV_VERS
;
1040 case T4_ERR_RDMA_VERSION
:
1041 *layer_type
= LAYER_RDMAP
|RDMAP_REMOTE_OP
;
1042 *ecode
= RDMAP_INV_VERS
;
1045 *layer_type
= LAYER_RDMAP
|RDMAP_REMOTE_OP
;
1046 *ecode
= RDMAP_INV_OPCODE
;
1048 case T4_ERR_DDP_QUEUE_NUM
:
1049 *layer_type
= LAYER_DDP
|DDP_UNTAGGED_ERR
;
1050 *ecode
= DDPU_INV_QN
;
1053 case T4_ERR_MSN_GAP
:
1054 case T4_ERR_MSN_RANGE
:
1055 case T4_ERR_IRD_OVERFLOW
:
1056 *layer_type
= LAYER_DDP
|DDP_UNTAGGED_ERR
;
1057 *ecode
= DDPU_INV_MSN_RANGE
;
1060 *layer_type
= LAYER_DDP
|DDP_LOCAL_CATA
;
1064 *layer_type
= LAYER_DDP
|DDP_UNTAGGED_ERR
;
1065 *ecode
= DDPU_INV_MO
;
1068 *layer_type
= LAYER_RDMAP
|DDP_LOCAL_CATA
;
1074 static void post_terminate(struct c4iw_qp
*qhp
, struct t4_cqe
*err_cqe
,
1077 struct fw_ri_wr
*wqe
;
1078 struct sk_buff
*skb
;
1079 struct terminate_message
*term
;
1081 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__
, qhp
, qhp
->wq
.sq
.qid
,
1084 skb
= alloc_skb(sizeof *wqe
, gfp
);
1087 set_wr_txq(skb
, CPL_PRIORITY_DATA
, qhp
->ep
->txq_idx
);
1089 wqe
= (struct fw_ri_wr
*)__skb_put(skb
, sizeof(*wqe
));
1090 memset(wqe
, 0, sizeof *wqe
);
1091 wqe
->op_compl
= cpu_to_be32(FW_WR_OP_V(FW_RI_INIT_WR
));
1092 wqe
->flowid_len16
= cpu_to_be32(
1093 FW_WR_FLOWID_V(qhp
->ep
->hwtid
) |
1094 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe
), 16)));
1096 wqe
->u
.terminate
.type
= FW_RI_TYPE_TERMINATE
;
1097 wqe
->u
.terminate
.immdlen
= cpu_to_be32(sizeof *term
);
1098 term
= (struct terminate_message
*)wqe
->u
.terminate
.termmsg
;
1099 if (qhp
->attr
.layer_etype
== (LAYER_MPA
|DDP_LLP
)) {
1100 term
->layer_etype
= qhp
->attr
.layer_etype
;
1101 term
->ecode
= qhp
->attr
.ecode
;
1103 build_term_codes(err_cqe
, &term
->layer_etype
, &term
->ecode
);
1104 c4iw_ofld_send(&qhp
->rhp
->rdev
, skb
);
1108 * Assumes qhp lock is held.
1110 static void __flush_qp(struct c4iw_qp
*qhp
, struct c4iw_cq
*rchp
,
1111 struct c4iw_cq
*schp
)
1114 int rq_flushed
, sq_flushed
;
1117 PDBG("%s qhp %p rchp %p schp %p\n", __func__
, qhp
, rchp
, schp
);
1119 /* locking hierarchy: cq lock first, then qp lock. */
1120 spin_lock_irqsave(&rchp
->lock
, flag
);
1121 spin_lock(&qhp
->lock
);
1123 if (qhp
->wq
.flushed
) {
1124 spin_unlock(&qhp
->lock
);
1125 spin_unlock_irqrestore(&rchp
->lock
, flag
);
1128 qhp
->wq
.flushed
= 1;
1130 c4iw_flush_hw_cq(rchp
);
1131 c4iw_count_rcqes(&rchp
->cq
, &qhp
->wq
, &count
);
1132 rq_flushed
= c4iw_flush_rq(&qhp
->wq
, &rchp
->cq
, count
);
1133 spin_unlock(&qhp
->lock
);
1134 spin_unlock_irqrestore(&rchp
->lock
, flag
);
1136 /* locking hierarchy: cq lock first, then qp lock. */
1137 spin_lock_irqsave(&schp
->lock
, flag
);
1138 spin_lock(&qhp
->lock
);
1140 c4iw_flush_hw_cq(schp
);
1141 sq_flushed
= c4iw_flush_sq(qhp
);
1142 spin_unlock(&qhp
->lock
);
1143 spin_unlock_irqrestore(&schp
->lock
, flag
);
1146 if (t4_clear_cq_armed(&rchp
->cq
) &&
1147 (rq_flushed
|| sq_flushed
)) {
1148 spin_lock_irqsave(&rchp
->comp_handler_lock
, flag
);
1149 (*rchp
->ibcq
.comp_handler
)(&rchp
->ibcq
,
1150 rchp
->ibcq
.cq_context
);
1151 spin_unlock_irqrestore(&rchp
->comp_handler_lock
, flag
);
1154 if (t4_clear_cq_armed(&rchp
->cq
) && rq_flushed
) {
1155 spin_lock_irqsave(&rchp
->comp_handler_lock
, flag
);
1156 (*rchp
->ibcq
.comp_handler
)(&rchp
->ibcq
,
1157 rchp
->ibcq
.cq_context
);
1158 spin_unlock_irqrestore(&rchp
->comp_handler_lock
, flag
);
1160 if (t4_clear_cq_armed(&schp
->cq
) && sq_flushed
) {
1161 spin_lock_irqsave(&schp
->comp_handler_lock
, flag
);
1162 (*schp
->ibcq
.comp_handler
)(&schp
->ibcq
,
1163 schp
->ibcq
.cq_context
);
1164 spin_unlock_irqrestore(&schp
->comp_handler_lock
, flag
);
1169 static void flush_qp(struct c4iw_qp
*qhp
)
1171 struct c4iw_cq
*rchp
, *schp
;
1174 rchp
= to_c4iw_cq(qhp
->ibqp
.recv_cq
);
1175 schp
= to_c4iw_cq(qhp
->ibqp
.send_cq
);
1177 t4_set_wq_in_error(&qhp
->wq
);
1178 if (qhp
->ibqp
.uobject
) {
1179 t4_set_cq_in_error(&rchp
->cq
);
1180 spin_lock_irqsave(&rchp
->comp_handler_lock
, flag
);
1181 (*rchp
->ibcq
.comp_handler
)(&rchp
->ibcq
, rchp
->ibcq
.cq_context
);
1182 spin_unlock_irqrestore(&rchp
->comp_handler_lock
, flag
);
1184 t4_set_cq_in_error(&schp
->cq
);
1185 spin_lock_irqsave(&schp
->comp_handler_lock
, flag
);
1186 (*schp
->ibcq
.comp_handler
)(&schp
->ibcq
,
1187 schp
->ibcq
.cq_context
);
1188 spin_unlock_irqrestore(&schp
->comp_handler_lock
, flag
);
1192 __flush_qp(qhp
, rchp
, schp
);
1195 static int rdma_fini(struct c4iw_dev
*rhp
, struct c4iw_qp
*qhp
,
1198 struct fw_ri_wr
*wqe
;
1200 struct sk_buff
*skb
;
1202 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__
, qhp
, qhp
->wq
.sq
.qid
,
1205 skb
= alloc_skb(sizeof *wqe
, GFP_KERNEL
);
1208 set_wr_txq(skb
, CPL_PRIORITY_DATA
, ep
->txq_idx
);
1210 wqe
= (struct fw_ri_wr
*)__skb_put(skb
, sizeof(*wqe
));
1211 memset(wqe
, 0, sizeof *wqe
);
1212 wqe
->op_compl
= cpu_to_be32(
1213 FW_WR_OP_V(FW_RI_INIT_WR
) |
1215 wqe
->flowid_len16
= cpu_to_be32(
1216 FW_WR_FLOWID_V(ep
->hwtid
) |
1217 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe
), 16)));
1218 wqe
->cookie
= (uintptr_t)&ep
->com
.wr_wait
;
1220 wqe
->u
.fini
.type
= FW_RI_TYPE_FINI
;
1221 ret
= c4iw_ofld_send(&rhp
->rdev
, skb
);
1225 ret
= c4iw_wait_for_reply(&rhp
->rdev
, &ep
->com
.wr_wait
, qhp
->ep
->hwtid
,
1226 qhp
->wq
.sq
.qid
, __func__
);
1228 PDBG("%s ret %d\n", __func__
, ret
);
1232 static void build_rtr_msg(u8 p2p_type
, struct fw_ri_init
*init
)
1234 PDBG("%s p2p_type = %d\n", __func__
, p2p_type
);
1235 memset(&init
->u
, 0, sizeof init
->u
);
1237 case FW_RI_INIT_P2PTYPE_RDMA_WRITE
:
1238 init
->u
.write
.opcode
= FW_RI_RDMA_WRITE_WR
;
1239 init
->u
.write
.stag_sink
= cpu_to_be32(1);
1240 init
->u
.write
.to_sink
= cpu_to_be64(1);
1241 init
->u
.write
.u
.immd_src
[0].op
= FW_RI_DATA_IMMD
;
1242 init
->u
.write
.len16
= DIV_ROUND_UP(sizeof init
->u
.write
+
1243 sizeof(struct fw_ri_immd
),
1246 case FW_RI_INIT_P2PTYPE_READ_REQ
:
1247 init
->u
.write
.opcode
= FW_RI_RDMA_READ_WR
;
1248 init
->u
.read
.stag_src
= cpu_to_be32(1);
1249 init
->u
.read
.to_src_lo
= cpu_to_be32(1);
1250 init
->u
.read
.stag_sink
= cpu_to_be32(1);
1251 init
->u
.read
.to_sink_lo
= cpu_to_be32(1);
1252 init
->u
.read
.len16
= DIV_ROUND_UP(sizeof init
->u
.read
, 16);
1257 static int rdma_init(struct c4iw_dev
*rhp
, struct c4iw_qp
*qhp
)
1259 struct fw_ri_wr
*wqe
;
1261 struct sk_buff
*skb
;
1263 PDBG("%s qhp %p qid 0x%x tid %u ird %u ord %u\n", __func__
, qhp
,
1264 qhp
->wq
.sq
.qid
, qhp
->ep
->hwtid
, qhp
->ep
->ird
, qhp
->ep
->ord
);
1266 skb
= alloc_skb(sizeof *wqe
, GFP_KERNEL
);
1271 ret
= alloc_ird(rhp
, qhp
->attr
.max_ird
);
1273 qhp
->attr
.max_ird
= 0;
1277 set_wr_txq(skb
, CPL_PRIORITY_DATA
, qhp
->ep
->txq_idx
);
1279 wqe
= (struct fw_ri_wr
*)__skb_put(skb
, sizeof(*wqe
));
1280 memset(wqe
, 0, sizeof *wqe
);
1281 wqe
->op_compl
= cpu_to_be32(
1282 FW_WR_OP_V(FW_RI_INIT_WR
) |
1284 wqe
->flowid_len16
= cpu_to_be32(
1285 FW_WR_FLOWID_V(qhp
->ep
->hwtid
) |
1286 FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe
), 16)));
1288 wqe
->cookie
= (uintptr_t)&qhp
->ep
->com
.wr_wait
;
1290 wqe
->u
.init
.type
= FW_RI_TYPE_INIT
;
1291 wqe
->u
.init
.mpareqbit_p2ptype
=
1292 FW_RI_WR_MPAREQBIT_V(qhp
->attr
.mpa_attr
.initiator
) |
1293 FW_RI_WR_P2PTYPE_V(qhp
->attr
.mpa_attr
.p2p_type
);
1294 wqe
->u
.init
.mpa_attrs
= FW_RI_MPA_IETF_ENABLE
;
1295 if (qhp
->attr
.mpa_attr
.recv_marker_enabled
)
1296 wqe
->u
.init
.mpa_attrs
|= FW_RI_MPA_RX_MARKER_ENABLE
;
1297 if (qhp
->attr
.mpa_attr
.xmit_marker_enabled
)
1298 wqe
->u
.init
.mpa_attrs
|= FW_RI_MPA_TX_MARKER_ENABLE
;
1299 if (qhp
->attr
.mpa_attr
.crc_enabled
)
1300 wqe
->u
.init
.mpa_attrs
|= FW_RI_MPA_CRC_ENABLE
;
1302 wqe
->u
.init
.qp_caps
= FW_RI_QP_RDMA_READ_ENABLE
|
1303 FW_RI_QP_RDMA_WRITE_ENABLE
|
1304 FW_RI_QP_BIND_ENABLE
;
1305 if (!qhp
->ibqp
.uobject
)
1306 wqe
->u
.init
.qp_caps
|= FW_RI_QP_FAST_REGISTER_ENABLE
|
1307 FW_RI_QP_STAG0_ENABLE
;
1308 wqe
->u
.init
.nrqe
= cpu_to_be16(t4_rqes_posted(&qhp
->wq
));
1309 wqe
->u
.init
.pdid
= cpu_to_be32(qhp
->attr
.pd
);
1310 wqe
->u
.init
.qpid
= cpu_to_be32(qhp
->wq
.sq
.qid
);
1311 wqe
->u
.init
.sq_eqid
= cpu_to_be32(qhp
->wq
.sq
.qid
);
1312 wqe
->u
.init
.rq_eqid
= cpu_to_be32(qhp
->wq
.rq
.qid
);
1313 wqe
->u
.init
.scqid
= cpu_to_be32(qhp
->attr
.scq
);
1314 wqe
->u
.init
.rcqid
= cpu_to_be32(qhp
->attr
.rcq
);
1315 wqe
->u
.init
.ord_max
= cpu_to_be32(qhp
->attr
.max_ord
);
1316 wqe
->u
.init
.ird_max
= cpu_to_be32(qhp
->attr
.max_ird
);
1317 wqe
->u
.init
.iss
= cpu_to_be32(qhp
->ep
->snd_seq
);
1318 wqe
->u
.init
.irs
= cpu_to_be32(qhp
->ep
->rcv_seq
);
1319 wqe
->u
.init
.hwrqsize
= cpu_to_be32(qhp
->wq
.rq
.rqt_size
);
1320 wqe
->u
.init
.hwrqaddr
= cpu_to_be32(qhp
->wq
.rq
.rqt_hwaddr
-
1321 rhp
->rdev
.lldi
.vr
->rq
.start
);
1322 if (qhp
->attr
.mpa_attr
.initiator
)
1323 build_rtr_msg(qhp
->attr
.mpa_attr
.p2p_type
, &wqe
->u
.init
);
1325 ret
= c4iw_ofld_send(&rhp
->rdev
, skb
);
1329 ret
= c4iw_wait_for_reply(&rhp
->rdev
, &qhp
->ep
->com
.wr_wait
,
1330 qhp
->ep
->hwtid
, qhp
->wq
.sq
.qid
, __func__
);
1334 free_ird(rhp
, qhp
->attr
.max_ird
);
1336 PDBG("%s ret %d\n", __func__
, ret
);
1340 int c4iw_modify_qp(struct c4iw_dev
*rhp
, struct c4iw_qp
*qhp
,
1341 enum c4iw_qp_attr_mask mask
,
1342 struct c4iw_qp_attributes
*attrs
,
1346 struct c4iw_qp_attributes newattr
= qhp
->attr
;
1351 struct c4iw_ep
*ep
= NULL
;
1353 PDBG("%s qhp %p sqid 0x%x rqid 0x%x ep %p state %d -> %d\n", __func__
,
1354 qhp
, qhp
->wq
.sq
.qid
, qhp
->wq
.rq
.qid
, qhp
->ep
, qhp
->attr
.state
,
1355 (mask
& C4IW_QP_ATTR_NEXT_STATE
) ? attrs
->next_state
: -1);
1357 mutex_lock(&qhp
->mutex
);
1359 /* Process attr changes if in IDLE */
1360 if (mask
& C4IW_QP_ATTR_VALID_MODIFY
) {
1361 if (qhp
->attr
.state
!= C4IW_QP_STATE_IDLE
) {
1365 if (mask
& C4IW_QP_ATTR_ENABLE_RDMA_READ
)
1366 newattr
.enable_rdma_read
= attrs
->enable_rdma_read
;
1367 if (mask
& C4IW_QP_ATTR_ENABLE_RDMA_WRITE
)
1368 newattr
.enable_rdma_write
= attrs
->enable_rdma_write
;
1369 if (mask
& C4IW_QP_ATTR_ENABLE_RDMA_BIND
)
1370 newattr
.enable_bind
= attrs
->enable_bind
;
1371 if (mask
& C4IW_QP_ATTR_MAX_ORD
) {
1372 if (attrs
->max_ord
> c4iw_max_read_depth
) {
1376 newattr
.max_ord
= attrs
->max_ord
;
1378 if (mask
& C4IW_QP_ATTR_MAX_IRD
) {
1379 if (attrs
->max_ird
> cur_max_read_depth(rhp
)) {
1383 newattr
.max_ird
= attrs
->max_ird
;
1385 qhp
->attr
= newattr
;
1388 if (mask
& C4IW_QP_ATTR_SQ_DB
) {
1389 ret
= ring_kernel_sq_db(qhp
, attrs
->sq_db_inc
);
1392 if (mask
& C4IW_QP_ATTR_RQ_DB
) {
1393 ret
= ring_kernel_rq_db(qhp
, attrs
->rq_db_inc
);
1397 if (!(mask
& C4IW_QP_ATTR_NEXT_STATE
))
1399 if (qhp
->attr
.state
== attrs
->next_state
)
1402 switch (qhp
->attr
.state
) {
1403 case C4IW_QP_STATE_IDLE
:
1404 switch (attrs
->next_state
) {
1405 case C4IW_QP_STATE_RTS
:
1406 if (!(mask
& C4IW_QP_ATTR_LLP_STREAM_HANDLE
)) {
1410 if (!(mask
& C4IW_QP_ATTR_MPA_ATTR
)) {
1414 qhp
->attr
.mpa_attr
= attrs
->mpa_attr
;
1415 qhp
->attr
.llp_stream_handle
= attrs
->llp_stream_handle
;
1416 qhp
->ep
= qhp
->attr
.llp_stream_handle
;
1417 set_state(qhp
, C4IW_QP_STATE_RTS
);
1420 * Ref the endpoint here and deref when we
1421 * disassociate the endpoint from the QP. This
1422 * happens in CLOSING->IDLE transition or *->ERROR
1425 c4iw_get_ep(&qhp
->ep
->com
);
1426 ret
= rdma_init(rhp
, qhp
);
1430 case C4IW_QP_STATE_ERROR
:
1431 set_state(qhp
, C4IW_QP_STATE_ERROR
);
1439 case C4IW_QP_STATE_RTS
:
1440 switch (attrs
->next_state
) {
1441 case C4IW_QP_STATE_CLOSING
:
1442 BUG_ON(atomic_read(&qhp
->ep
->com
.kref
.refcount
) < 2);
1443 t4_set_wq_in_error(&qhp
->wq
);
1444 set_state(qhp
, C4IW_QP_STATE_CLOSING
);
1449 c4iw_get_ep(&qhp
->ep
->com
);
1451 ret
= rdma_fini(rhp
, qhp
, ep
);
1455 case C4IW_QP_STATE_TERMINATE
:
1456 t4_set_wq_in_error(&qhp
->wq
);
1457 set_state(qhp
, C4IW_QP_STATE_TERMINATE
);
1458 qhp
->attr
.layer_etype
= attrs
->layer_etype
;
1459 qhp
->attr
.ecode
= attrs
->ecode
;
1462 c4iw_get_ep(&qhp
->ep
->com
);
1466 terminate
= qhp
->attr
.send_term
;
1467 ret
= rdma_fini(rhp
, qhp
, ep
);
1472 case C4IW_QP_STATE_ERROR
:
1473 t4_set_wq_in_error(&qhp
->wq
);
1474 set_state(qhp
, C4IW_QP_STATE_ERROR
);
1479 c4iw_get_ep(&qhp
->ep
->com
);
1488 case C4IW_QP_STATE_CLOSING
:
1493 switch (attrs
->next_state
) {
1494 case C4IW_QP_STATE_IDLE
:
1496 set_state(qhp
, C4IW_QP_STATE_IDLE
);
1497 qhp
->attr
.llp_stream_handle
= NULL
;
1498 c4iw_put_ep(&qhp
->ep
->com
);
1500 wake_up(&qhp
->wait
);
1502 case C4IW_QP_STATE_ERROR
:
1509 case C4IW_QP_STATE_ERROR
:
1510 if (attrs
->next_state
!= C4IW_QP_STATE_IDLE
) {
1514 if (!t4_sq_empty(&qhp
->wq
) || !t4_rq_empty(&qhp
->wq
)) {
1518 set_state(qhp
, C4IW_QP_STATE_IDLE
);
1520 case C4IW_QP_STATE_TERMINATE
:
1528 printk(KERN_ERR
"%s in a bad state %d\n",
1529 __func__
, qhp
->attr
.state
);
1536 PDBG("%s disassociating ep %p qpid 0x%x\n", __func__
, qhp
->ep
,
1539 /* disassociate the LLP connection */
1540 qhp
->attr
.llp_stream_handle
= NULL
;
1544 set_state(qhp
, C4IW_QP_STATE_ERROR
);
1549 wake_up(&qhp
->wait
);
1551 mutex_unlock(&qhp
->mutex
);
1554 post_terminate(qhp
, NULL
, internal
? GFP_ATOMIC
: GFP_KERNEL
);
1557 * If disconnect is 1, then we need to initiate a disconnect
1558 * on the EP. This can be a normal close (RTS->CLOSING) or
1559 * an abnormal close (RTS/CLOSING->ERROR).
1562 c4iw_ep_disconnect(ep
, abort
, internal
? GFP_ATOMIC
:
1564 c4iw_put_ep(&ep
->com
);
1568 * If free is 1, then we've disassociated the EP from the QP
1569 * and we need to dereference the EP.
1572 c4iw_put_ep(&ep
->com
);
1573 PDBG("%s exit state %d\n", __func__
, qhp
->attr
.state
);
1577 int c4iw_destroy_qp(struct ib_qp
*ib_qp
)
1579 struct c4iw_dev
*rhp
;
1580 struct c4iw_qp
*qhp
;
1581 struct c4iw_qp_attributes attrs
;
1582 struct c4iw_ucontext
*ucontext
;
1584 qhp
= to_c4iw_qp(ib_qp
);
1587 attrs
.next_state
= C4IW_QP_STATE_ERROR
;
1588 if (qhp
->attr
.state
== C4IW_QP_STATE_TERMINATE
)
1589 c4iw_modify_qp(rhp
, qhp
, C4IW_QP_ATTR_NEXT_STATE
, &attrs
, 1);
1591 c4iw_modify_qp(rhp
, qhp
, C4IW_QP_ATTR_NEXT_STATE
, &attrs
, 0);
1592 wait_event(qhp
->wait
, !qhp
->ep
);
1594 remove_handle(rhp
, &rhp
->qpidr
, qhp
->wq
.sq
.qid
);
1595 atomic_dec(&qhp
->refcnt
);
1596 wait_event(qhp
->wait
, !atomic_read(&qhp
->refcnt
));
1598 spin_lock_irq(&rhp
->lock
);
1599 if (!list_empty(&qhp
->db_fc_entry
))
1600 list_del_init(&qhp
->db_fc_entry
);
1601 spin_unlock_irq(&rhp
->lock
);
1602 free_ird(rhp
, qhp
->attr
.max_ird
);
1604 ucontext
= ib_qp
->uobject
?
1605 to_c4iw_ucontext(ib_qp
->uobject
->context
) : NULL
;
1606 destroy_qp(&rhp
->rdev
, &qhp
->wq
,
1607 ucontext
? &ucontext
->uctx
: &rhp
->rdev
.uctx
);
1609 PDBG("%s ib_qp %p qpid 0x%0x\n", __func__
, ib_qp
, qhp
->wq
.sq
.qid
);
1614 struct ib_qp
*c4iw_create_qp(struct ib_pd
*pd
, struct ib_qp_init_attr
*attrs
,
1615 struct ib_udata
*udata
)
1617 struct c4iw_dev
*rhp
;
1618 struct c4iw_qp
*qhp
;
1619 struct c4iw_pd
*php
;
1620 struct c4iw_cq
*schp
;
1621 struct c4iw_cq
*rchp
;
1622 struct c4iw_create_qp_resp uresp
;
1623 unsigned int sqsize
, rqsize
;
1624 struct c4iw_ucontext
*ucontext
;
1626 struct c4iw_mm_entry
*sq_key_mm
, *rq_key_mm
= NULL
, *sq_db_key_mm
;
1627 struct c4iw_mm_entry
*rq_db_key_mm
= NULL
, *ma_sync_key_mm
= NULL
;
1629 PDBG("%s ib_pd %p\n", __func__
, pd
);
1631 if (attrs
->qp_type
!= IB_QPT_RC
)
1632 return ERR_PTR(-EINVAL
);
1634 php
= to_c4iw_pd(pd
);
1636 schp
= get_chp(rhp
, ((struct c4iw_cq
*)attrs
->send_cq
)->cq
.cqid
);
1637 rchp
= get_chp(rhp
, ((struct c4iw_cq
*)attrs
->recv_cq
)->cq
.cqid
);
1639 return ERR_PTR(-EINVAL
);
1641 if (attrs
->cap
.max_inline_data
> T4_MAX_SEND_INLINE
)
1642 return ERR_PTR(-EINVAL
);
1644 if (attrs
->cap
.max_recv_wr
> rhp
->rdev
.hw_queue
.t4_max_rq_size
)
1645 return ERR_PTR(-E2BIG
);
1646 rqsize
= attrs
->cap
.max_recv_wr
+ 1;
1650 if (attrs
->cap
.max_send_wr
> rhp
->rdev
.hw_queue
.t4_max_sq_size
)
1651 return ERR_PTR(-E2BIG
);
1652 sqsize
= attrs
->cap
.max_send_wr
+ 1;
1656 ucontext
= pd
->uobject
? to_c4iw_ucontext(pd
->uobject
->context
) : NULL
;
1658 qhp
= kzalloc(sizeof(*qhp
), GFP_KERNEL
);
1660 return ERR_PTR(-ENOMEM
);
1661 qhp
->wq
.sq
.size
= sqsize
;
1662 qhp
->wq
.sq
.memsize
=
1663 (sqsize
+ rhp
->rdev
.hw_queue
.t4_eq_status_entries
) *
1664 sizeof(*qhp
->wq
.sq
.queue
) + 16 * sizeof(__be64
);
1665 qhp
->wq
.sq
.flush_cidx
= -1;
1666 qhp
->wq
.rq
.size
= rqsize
;
1667 qhp
->wq
.rq
.memsize
=
1668 (rqsize
+ rhp
->rdev
.hw_queue
.t4_eq_status_entries
) *
1669 sizeof(*qhp
->wq
.rq
.queue
);
1672 qhp
->wq
.sq
.memsize
= roundup(qhp
->wq
.sq
.memsize
, PAGE_SIZE
);
1673 qhp
->wq
.rq
.memsize
= roundup(qhp
->wq
.rq
.memsize
, PAGE_SIZE
);
1676 ret
= create_qp(&rhp
->rdev
, &qhp
->wq
, &schp
->cq
, &rchp
->cq
,
1677 ucontext
? &ucontext
->uctx
: &rhp
->rdev
.uctx
);
1681 attrs
->cap
.max_recv_wr
= rqsize
- 1;
1682 attrs
->cap
.max_send_wr
= sqsize
- 1;
1683 attrs
->cap
.max_inline_data
= T4_MAX_SEND_INLINE
;
1686 qhp
->attr
.pd
= php
->pdid
;
1687 qhp
->attr
.scq
= ((struct c4iw_cq
*) attrs
->send_cq
)->cq
.cqid
;
1688 qhp
->attr
.rcq
= ((struct c4iw_cq
*) attrs
->recv_cq
)->cq
.cqid
;
1689 qhp
->attr
.sq_num_entries
= attrs
->cap
.max_send_wr
;
1690 qhp
->attr
.rq_num_entries
= attrs
->cap
.max_recv_wr
;
1691 qhp
->attr
.sq_max_sges
= attrs
->cap
.max_send_sge
;
1692 qhp
->attr
.sq_max_sges_rdma_write
= attrs
->cap
.max_send_sge
;
1693 qhp
->attr
.rq_max_sges
= attrs
->cap
.max_recv_sge
;
1694 qhp
->attr
.state
= C4IW_QP_STATE_IDLE
;
1695 qhp
->attr
.next_state
= C4IW_QP_STATE_IDLE
;
1696 qhp
->attr
.enable_rdma_read
= 1;
1697 qhp
->attr
.enable_rdma_write
= 1;
1698 qhp
->attr
.enable_bind
= 1;
1699 qhp
->attr
.max_ord
= 0;
1700 qhp
->attr
.max_ird
= 0;
1701 qhp
->sq_sig_all
= attrs
->sq_sig_type
== IB_SIGNAL_ALL_WR
;
1702 spin_lock_init(&qhp
->lock
);
1703 init_completion(&qhp
->sq_drained
);
1704 init_completion(&qhp
->rq_drained
);
1705 mutex_init(&qhp
->mutex
);
1706 init_waitqueue_head(&qhp
->wait
);
1707 atomic_set(&qhp
->refcnt
, 1);
1709 ret
= insert_handle(rhp
, &rhp
->qpidr
, qhp
, qhp
->wq
.sq
.qid
);
1714 sq_key_mm
= kmalloc(sizeof(*sq_key_mm
), GFP_KERNEL
);
1719 rq_key_mm
= kmalloc(sizeof(*rq_key_mm
), GFP_KERNEL
);
1724 sq_db_key_mm
= kmalloc(sizeof(*sq_db_key_mm
), GFP_KERNEL
);
1725 if (!sq_db_key_mm
) {
1729 rq_db_key_mm
= kmalloc(sizeof(*rq_db_key_mm
), GFP_KERNEL
);
1730 if (!rq_db_key_mm
) {
1734 if (t4_sq_onchip(&qhp
->wq
.sq
)) {
1735 ma_sync_key_mm
= kmalloc(sizeof(*ma_sync_key_mm
),
1737 if (!ma_sync_key_mm
) {
1741 uresp
.flags
= C4IW_QPF_ONCHIP
;
1744 uresp
.qid_mask
= rhp
->rdev
.qpmask
;
1745 uresp
.sqid
= qhp
->wq
.sq
.qid
;
1746 uresp
.sq_size
= qhp
->wq
.sq
.size
;
1747 uresp
.sq_memsize
= qhp
->wq
.sq
.memsize
;
1748 uresp
.rqid
= qhp
->wq
.rq
.qid
;
1749 uresp
.rq_size
= qhp
->wq
.rq
.size
;
1750 uresp
.rq_memsize
= qhp
->wq
.rq
.memsize
;
1751 spin_lock(&ucontext
->mmap_lock
);
1752 if (ma_sync_key_mm
) {
1753 uresp
.ma_sync_key
= ucontext
->key
;
1754 ucontext
->key
+= PAGE_SIZE
;
1756 uresp
.ma_sync_key
= 0;
1758 uresp
.sq_key
= ucontext
->key
;
1759 ucontext
->key
+= PAGE_SIZE
;
1760 uresp
.rq_key
= ucontext
->key
;
1761 ucontext
->key
+= PAGE_SIZE
;
1762 uresp
.sq_db_gts_key
= ucontext
->key
;
1763 ucontext
->key
+= PAGE_SIZE
;
1764 uresp
.rq_db_gts_key
= ucontext
->key
;
1765 ucontext
->key
+= PAGE_SIZE
;
1766 spin_unlock(&ucontext
->mmap_lock
);
1767 ret
= ib_copy_to_udata(udata
, &uresp
, sizeof uresp
);
1770 sq_key_mm
->key
= uresp
.sq_key
;
1771 sq_key_mm
->addr
= qhp
->wq
.sq
.phys_addr
;
1772 sq_key_mm
->len
= PAGE_ALIGN(qhp
->wq
.sq
.memsize
);
1773 insert_mmap(ucontext
, sq_key_mm
);
1774 rq_key_mm
->key
= uresp
.rq_key
;
1775 rq_key_mm
->addr
= virt_to_phys(qhp
->wq
.rq
.queue
);
1776 rq_key_mm
->len
= PAGE_ALIGN(qhp
->wq
.rq
.memsize
);
1777 insert_mmap(ucontext
, rq_key_mm
);
1778 sq_db_key_mm
->key
= uresp
.sq_db_gts_key
;
1779 sq_db_key_mm
->addr
= (u64
)(unsigned long)qhp
->wq
.sq
.bar2_pa
;
1780 sq_db_key_mm
->len
= PAGE_SIZE
;
1781 insert_mmap(ucontext
, sq_db_key_mm
);
1782 rq_db_key_mm
->key
= uresp
.rq_db_gts_key
;
1783 rq_db_key_mm
->addr
= (u64
)(unsigned long)qhp
->wq
.rq
.bar2_pa
;
1784 rq_db_key_mm
->len
= PAGE_SIZE
;
1785 insert_mmap(ucontext
, rq_db_key_mm
);
1786 if (ma_sync_key_mm
) {
1787 ma_sync_key_mm
->key
= uresp
.ma_sync_key
;
1788 ma_sync_key_mm
->addr
=
1789 (pci_resource_start(rhp
->rdev
.lldi
.pdev
, 0) +
1790 PCIE_MA_SYNC_A
) & PAGE_MASK
;
1791 ma_sync_key_mm
->len
= PAGE_SIZE
;
1792 insert_mmap(ucontext
, ma_sync_key_mm
);
1795 qhp
->ibqp
.qp_num
= qhp
->wq
.sq
.qid
;
1796 init_timer(&(qhp
->timer
));
1797 INIT_LIST_HEAD(&qhp
->db_fc_entry
);
1798 PDBG("%s sq id %u size %u memsize %zu num_entries %u "
1799 "rq id %u size %u memsize %zu num_entries %u\n", __func__
,
1800 qhp
->wq
.sq
.qid
, qhp
->wq
.sq
.size
, qhp
->wq
.sq
.memsize
,
1801 attrs
->cap
.max_send_wr
, qhp
->wq
.rq
.qid
, qhp
->wq
.rq
.size
,
1802 qhp
->wq
.rq
.memsize
, attrs
->cap
.max_recv_wr
);
1805 kfree(ma_sync_key_mm
);
1807 kfree(rq_db_key_mm
);
1809 kfree(sq_db_key_mm
);
1815 remove_handle(rhp
, &rhp
->qpidr
, qhp
->wq
.sq
.qid
);
1817 destroy_qp(&rhp
->rdev
, &qhp
->wq
,
1818 ucontext
? &ucontext
->uctx
: &rhp
->rdev
.uctx
);
1821 return ERR_PTR(ret
);
1824 int c4iw_ib_modify_qp(struct ib_qp
*ibqp
, struct ib_qp_attr
*attr
,
1825 int attr_mask
, struct ib_udata
*udata
)
1827 struct c4iw_dev
*rhp
;
1828 struct c4iw_qp
*qhp
;
1829 enum c4iw_qp_attr_mask mask
= 0;
1830 struct c4iw_qp_attributes attrs
;
1832 PDBG("%s ib_qp %p\n", __func__
, ibqp
);
1834 /* iwarp does not support the RTR state */
1835 if ((attr_mask
& IB_QP_STATE
) && (attr
->qp_state
== IB_QPS_RTR
))
1836 attr_mask
&= ~IB_QP_STATE
;
1838 /* Make sure we still have something left to do */
1842 memset(&attrs
, 0, sizeof attrs
);
1843 qhp
= to_c4iw_qp(ibqp
);
1846 attrs
.next_state
= c4iw_convert_state(attr
->qp_state
);
1847 attrs
.enable_rdma_read
= (attr
->qp_access_flags
&
1848 IB_ACCESS_REMOTE_READ
) ? 1 : 0;
1849 attrs
.enable_rdma_write
= (attr
->qp_access_flags
&
1850 IB_ACCESS_REMOTE_WRITE
) ? 1 : 0;
1851 attrs
.enable_bind
= (attr
->qp_access_flags
& IB_ACCESS_MW_BIND
) ? 1 : 0;
1854 mask
|= (attr_mask
& IB_QP_STATE
) ? C4IW_QP_ATTR_NEXT_STATE
: 0;
1855 mask
|= (attr_mask
& IB_QP_ACCESS_FLAGS
) ?
1856 (C4IW_QP_ATTR_ENABLE_RDMA_READ
|
1857 C4IW_QP_ATTR_ENABLE_RDMA_WRITE
|
1858 C4IW_QP_ATTR_ENABLE_RDMA_BIND
) : 0;
1861 * Use SQ_PSN and RQ_PSN to pass in IDX_INC values for
1862 * ringing the queue db when we're in DB_FULL mode.
1863 * Only allow this on T4 devices.
1865 attrs
.sq_db_inc
= attr
->sq_psn
;
1866 attrs
.rq_db_inc
= attr
->rq_psn
;
1867 mask
|= (attr_mask
& IB_QP_SQ_PSN
) ? C4IW_QP_ATTR_SQ_DB
: 0;
1868 mask
|= (attr_mask
& IB_QP_RQ_PSN
) ? C4IW_QP_ATTR_RQ_DB
: 0;
1869 if (!is_t4(to_c4iw_qp(ibqp
)->rhp
->rdev
.lldi
.adapter_type
) &&
1870 (mask
& (C4IW_QP_ATTR_SQ_DB
|C4IW_QP_ATTR_RQ_DB
)))
1873 return c4iw_modify_qp(rhp
, qhp
, mask
, &attrs
, 0);
1876 struct ib_qp
*c4iw_get_qp(struct ib_device
*dev
, int qpn
)
1878 PDBG("%s ib_dev %p qpn 0x%x\n", __func__
, dev
, qpn
);
1879 return (struct ib_qp
*)get_qhp(to_c4iw_dev(dev
), qpn
);
1882 int c4iw_ib_query_qp(struct ib_qp
*ibqp
, struct ib_qp_attr
*attr
,
1883 int attr_mask
, struct ib_qp_init_attr
*init_attr
)
1885 struct c4iw_qp
*qhp
= to_c4iw_qp(ibqp
);
1887 memset(attr
, 0, sizeof *attr
);
1888 memset(init_attr
, 0, sizeof *init_attr
);
1889 attr
->qp_state
= to_ib_qp_state(qhp
->attr
.state
);
1890 init_attr
->cap
.max_send_wr
= qhp
->attr
.sq_num_entries
;
1891 init_attr
->cap
.max_recv_wr
= qhp
->attr
.rq_num_entries
;
1892 init_attr
->cap
.max_send_sge
= qhp
->attr
.sq_max_sges
;
1893 init_attr
->cap
.max_recv_sge
= qhp
->attr
.sq_max_sges
;
1894 init_attr
->cap
.max_inline_data
= T4_MAX_SEND_INLINE
;
1895 init_attr
->sq_sig_type
= qhp
->sq_sig_all
? IB_SIGNAL_ALL_WR
: 0;
1899 void c4iw_drain_sq(struct ib_qp
*ibqp
)
1901 struct c4iw_qp
*qp
= to_c4iw_qp(ibqp
);
1905 spin_lock_irqsave(&qp
->lock
, flag
);
1906 need_to_wait
= !t4_sq_empty(&qp
->wq
);
1907 spin_unlock_irqrestore(&qp
->lock
, flag
);
1910 wait_for_completion(&qp
->sq_drained
);
1913 void c4iw_drain_rq(struct ib_qp
*ibqp
)
1915 struct c4iw_qp
*qp
= to_c4iw_qp(ibqp
);
1919 spin_lock_irqsave(&qp
->lock
, flag
);
1920 need_to_wait
= !t4_rq_empty(&qp
->wq
);
1921 spin_unlock_irqrestore(&qp
->lock
, flag
);
1924 wait_for_completion(&qp
->rq_drained
);