]> git.proxmox.com Git - mirror_ubuntu-focal-kernel.git/blob - drivers/infiniband/hw/cxgb4/t4.h
projects / mirror_ubuntu-focal-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
ASoC: pcm512x: add missing MODULE_DESCRIPTION/AUTHOR/LICENSE
[mirror_ubuntu-focal-kernel.git] / drivers / infiniband / hw / cxgb4 / t4.h
1 /*
2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 * - Redistributions in binary form must reproduce the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials
20 * provided with the distribution.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
23 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
25 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
26 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
27 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
28 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
29 * SOFTWARE.
30 */
31 #ifndef __T4_H__
32 #define __T4_H__
33
34 #include "t4_hw.h"
35 #include "t4_regs.h"
36 #include "t4_values.h"
37 #include "t4_msg.h"
38 #include "t4fw_ri_api.h"
39
40 #define T4_MAX_NUM_PD 65536
41 #define T4_MAX_MR_SIZE (~0ULL)
42 #define T4_PAGESIZE_MASK 0xffff000 /* 4KB-128MB */
43 #define T4_STAG_UNSET 0xffffffff
44 #define T4_FW_MAJ 0
45 #define PCIE_MA_SYNC_A 0x30b4
46
47 struct t4_status_page {
48 __be32 rsvd1; /* flit 0 - hw owns */
49 __be16 rsvd2;
50 __be16 qid;
51 __be16 cidx;
52 __be16 pidx;
53 u8 qp_err; /* flit 1 - sw owns */
54 u8 db_off;
55 u8 pad;
56 u16 host_wq_pidx;
57 u16 host_cidx;
58 u16 host_pidx;
59 };
60
61 #define T4_EQ_ENTRY_SIZE 64
62
63 #define T4_SQ_NUM_SLOTS 5
64 #define T4_SQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_SQ_NUM_SLOTS)
65 #define T4_MAX_SEND_SGE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
66 sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
67 #define T4_MAX_SEND_INLINE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
68 sizeof(struct fw_ri_immd)))
69 #define T4_MAX_WRITE_INLINE ((T4_SQ_NUM_BYTES - \
70 sizeof(struct fw_ri_rdma_write_wr) - \
71 sizeof(struct fw_ri_immd)))
72 #define T4_MAX_WRITE_SGE ((T4_SQ_NUM_BYTES - \
73 sizeof(struct fw_ri_rdma_write_wr) - \
74 sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
75 #define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - \
76 sizeof(struct fw_ri_immd)) & ~31UL)
77 #define T4_MAX_FR_IMMD_DEPTH (T4_MAX_FR_IMMD / sizeof(u64))
78 #define T4_MAX_FR_DSGL 1024
79 #define T4_MAX_FR_DSGL_DEPTH (T4_MAX_FR_DSGL / sizeof(u64))
80
81 static inline int t4_max_fr_depth(int use_dsgl)
82 {
83 return use_dsgl ? T4_MAX_FR_DSGL_DEPTH : T4_MAX_FR_IMMD_DEPTH;
84 }
85
86 #define T4_RQ_NUM_SLOTS 2
87 #define T4_RQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_RQ_NUM_SLOTS)
88 #define T4_MAX_RECV_SGE 4
89
90 union t4_wr {
91 struct fw_ri_res_wr res;
92 struct fw_ri_wr ri;
93 struct fw_ri_rdma_write_wr write;
94 struct fw_ri_send_wr send;
95 struct fw_ri_rdma_read_wr read;
96 struct fw_ri_bind_mw_wr bind;
97 struct fw_ri_fr_nsmr_wr fr;
98 struct fw_ri_fr_nsmr_tpte_wr fr_tpte;
99 struct fw_ri_inv_lstag_wr inv;
100 struct t4_status_page status;
101 __be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_SQ_NUM_SLOTS];
102 };
103
104 union t4_recv_wr {
105 struct fw_ri_recv_wr recv;
106 struct t4_status_page status;
107 __be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_RQ_NUM_SLOTS];
108 };
109
110 static inline void init_wr_hdr(union t4_wr *wqe, u16 wrid,
111 enum fw_wr_opcodes opcode, u8 flags, u8 len16)
112 {
113 wqe->send.opcode = (u8)opcode;
114 wqe->send.flags = flags;
115 wqe->send.wrid = wrid;
116 wqe->send.r1[0] = 0;
117 wqe->send.r1[1] = 0;
118 wqe->send.r1[2] = 0;
119 wqe->send.len16 = len16;
120 }
121
122 /* CQE/AE status codes */
123 #define T4_ERR_SUCCESS 0x0
124 #define T4_ERR_STAG 0x1 /* STAG invalid: either the */
125 /* STAG is offlimt, being 0, */
126 /* or STAG_key mismatch */
127 #define T4_ERR_PDID 0x2 /* PDID mismatch */
128 #define T4_ERR_QPID 0x3 /* QPID mismatch */
129 #define T4_ERR_ACCESS 0x4 /* Invalid access right */
130 #define T4_ERR_WRAP 0x5 /* Wrap error */
131 #define T4_ERR_BOUND 0x6 /* base and bounds voilation */
132 #define T4_ERR_INVALIDATE_SHARED_MR 0x7 /* attempt to invalidate a */
133 /* shared memory region */
134 #define T4_ERR_INVALIDATE_MR_WITH_MW_BOUND 0x8 /* attempt to invalidate a */
135 /* shared memory region */
136 #define T4_ERR_ECC 0x9 /* ECC error detected */
137 #define T4_ERR_ECC_PSTAG 0xA /* ECC error detected when */
138 /* reading PSTAG for a MW */
139 /* Invalidate */
140 #define T4_ERR_PBL_ADDR_BOUND 0xB /* pbl addr out of bounds: */
141 /* software error */
142 #define T4_ERR_SWFLUSH 0xC /* SW FLUSHED */
143 #define T4_ERR_CRC 0x10 /* CRC error */
144 #define T4_ERR_MARKER 0x11 /* Marker error */
145 #define T4_ERR_PDU_LEN_ERR 0x12 /* invalid PDU length */
146 #define T4_ERR_OUT_OF_RQE 0x13 /* out of RQE */
147 #define T4_ERR_DDP_VERSION 0x14 /* wrong DDP version */
148 #define T4_ERR_RDMA_VERSION 0x15 /* wrong RDMA version */
149 #define T4_ERR_OPCODE 0x16 /* invalid rdma opcode */
150 #define T4_ERR_DDP_QUEUE_NUM 0x17 /* invalid ddp queue number */
151 #define T4_ERR_MSN 0x18 /* MSN error */
152 #define T4_ERR_TBIT 0x19 /* tag bit not set correctly */
153 #define T4_ERR_MO 0x1A /* MO not 0 for TERMINATE */
154 /* or READ_REQ */
155 #define T4_ERR_MSN_GAP 0x1B
156 #define T4_ERR_MSN_RANGE 0x1C
157 #define T4_ERR_IRD_OVERFLOW 0x1D
158 #define T4_ERR_RQE_ADDR_BOUND 0x1E /* RQE addr out of bounds: */
159 /* software error */
160 #define T4_ERR_INTERNAL_ERR 0x1F /* internal error (opcode */
161 /* mismatch) */
162 /*
163 * CQE defs
164 */
165 struct t4_cqe {
166 __be32 header;
167 __be32 len;
168 union {
169 struct {
170 __be32 stag;
171 __be32 msn;
172 } rcqe;
173 struct {
174 __be32 stag;
175 u16 nada2;
176 u16 cidx;
177 } scqe;
178 struct {
179 __be32 wrid_hi;
180 __be32 wrid_low;
181 } gen;
182 u64 drain_cookie;
183 } u;
184 __be64 reserved;
185 __be64 bits_type_ts;
186 };
187
188 /* macros for flit 0 of the cqe */
189
190 #define CQE_QPID_S 12
191 #define CQE_QPID_M 0xFFFFF
192 #define CQE_QPID_G(x) ((((x) >> CQE_QPID_S)) & CQE_QPID_M)
193 #define CQE_QPID_V(x) ((x)<<CQE_QPID_S)
194
195 #define CQE_SWCQE_S 11
196 #define CQE_SWCQE_M 0x1
197 #define CQE_SWCQE_G(x) ((((x) >> CQE_SWCQE_S)) & CQE_SWCQE_M)
198 #define CQE_SWCQE_V(x) ((x)<<CQE_SWCQE_S)
199
200 #define CQE_STATUS_S 5
201 #define CQE_STATUS_M 0x1F
202 #define CQE_STATUS_G(x) ((((x) >> CQE_STATUS_S)) & CQE_STATUS_M)
203 #define CQE_STATUS_V(x) ((x)<<CQE_STATUS_S)
204
205 #define CQE_TYPE_S 4
206 #define CQE_TYPE_M 0x1
207 #define CQE_TYPE_G(x) ((((x) >> CQE_TYPE_S)) & CQE_TYPE_M)
208 #define CQE_TYPE_V(x) ((x)<<CQE_TYPE_S)
209
210 #define CQE_OPCODE_S 0
211 #define CQE_OPCODE_M 0xF
212 #define CQE_OPCODE_G(x) ((((x) >> CQE_OPCODE_S)) & CQE_OPCODE_M)
213 #define CQE_OPCODE_V(x) ((x)<<CQE_OPCODE_S)
214
215 #define SW_CQE(x) (CQE_SWCQE_G(be32_to_cpu((x)->header)))
216 #define CQE_QPID(x) (CQE_QPID_G(be32_to_cpu((x)->header)))
217 #define CQE_TYPE(x) (CQE_TYPE_G(be32_to_cpu((x)->header)))
218 #define SQ_TYPE(x) (CQE_TYPE((x)))
219 #define RQ_TYPE(x) (!CQE_TYPE((x)))
220 #define CQE_STATUS(x) (CQE_STATUS_G(be32_to_cpu((x)->header)))
221 #define CQE_OPCODE(x) (CQE_OPCODE_G(be32_to_cpu((x)->header)))
222
223 #define CQE_SEND_OPCODE(x)( \
224 (CQE_OPCODE_G(be32_to_cpu((x)->header)) == FW_RI_SEND) || \
225 (CQE_OPCODE_G(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE) || \
226 (CQE_OPCODE_G(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_INV) || \
227 (CQE_OPCODE_G(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE_INV))
228
229 #define CQE_LEN(x) (be32_to_cpu((x)->len))
230
231 /* used for RQ completion processing */
232 #define CQE_WRID_STAG(x) (be32_to_cpu((x)->u.rcqe.stag))
233 #define CQE_WRID_MSN(x) (be32_to_cpu((x)->u.rcqe.msn))
234
235 /* used for SQ completion processing */
236 #define CQE_WRID_SQ_IDX(x) ((x)->u.scqe.cidx)
237 #define CQE_WRID_FR_STAG(x) (be32_to_cpu((x)->u.scqe.stag))
238
239 /* generic accessor macros */
240 #define CQE_WRID_HI(x) (be32_to_cpu((x)->u.gen.wrid_hi))
241 #define CQE_WRID_LOW(x) (be32_to_cpu((x)->u.gen.wrid_low))
242 #define CQE_DRAIN_COOKIE(x) ((x)->u.drain_cookie)
243
244 /* macros for flit 3 of the cqe */
245 #define CQE_GENBIT_S 63
246 #define CQE_GENBIT_M 0x1
247 #define CQE_GENBIT_G(x) (((x) >> CQE_GENBIT_S) & CQE_GENBIT_M)
248 #define CQE_GENBIT_V(x) ((x)<<CQE_GENBIT_S)
249
250 #define CQE_OVFBIT_S 62
251 #define CQE_OVFBIT_M 0x1
252 #define CQE_OVFBIT_G(x) ((((x) >> CQE_OVFBIT_S)) & CQE_OVFBIT_M)
253
254 #define CQE_IQTYPE_S 60
255 #define CQE_IQTYPE_M 0x3
256 #define CQE_IQTYPE_G(x) ((((x) >> CQE_IQTYPE_S)) & CQE_IQTYPE_M)
257
258 #define CQE_TS_M 0x0fffffffffffffffULL
259 #define CQE_TS_G(x) ((x) & CQE_TS_M)
260
261 #define CQE_OVFBIT(x) ((unsigned)CQE_OVFBIT_G(be64_to_cpu((x)->bits_type_ts)))
262 #define CQE_GENBIT(x) ((unsigned)CQE_GENBIT_G(be64_to_cpu((x)->bits_type_ts)))
263 #define CQE_TS(x) (CQE_TS_G(be64_to_cpu((x)->bits_type_ts)))
264
265 struct t4_swsqe {
266 u64 wr_id;
267 struct t4_cqe cqe;
268 int read_len;
269 int opcode;
270 int complete;
271 int signaled;
272 u16 idx;
273 int flushed;
274 struct timespec host_ts;
275 u64 sge_ts;
276 };
277
278 static inline pgprot_t t4_pgprot_wc(pgprot_t prot)
279 {
280 #if defined(__i386__) || defined(__x86_64__) || defined(CONFIG_PPC64)
281 return pgprot_writecombine(prot);
282 #else
283 return pgprot_noncached(prot);
284 #endif
285 }
286
287 enum {
288 T4_SQ_ONCHIP = (1<<0),
289 };
290
291 struct t4_sq {
292 union t4_wr *queue;
293 dma_addr_t dma_addr;
294 DEFINE_DMA_UNMAP_ADDR(mapping);
295 unsigned long phys_addr;
296 struct t4_swsqe *sw_sq;
297 struct t4_swsqe *oldest_read;
298 void __iomem *bar2_va;
299 u64 bar2_pa;
300 size_t memsize;
301 u32 bar2_qid;
302 u32 qid;
303 u16 in_use;
304 u16 size;
305 u16 cidx;
306 u16 pidx;
307 u16 wq_pidx;
308 u16 wq_pidx_inc;
309 u16 flags;
310 short flush_cidx;
311 };
312
313 struct t4_swrqe {
314 u64 wr_id;
315 struct timespec host_ts;
316 u64 sge_ts;
317 };
318
319 struct t4_rq {
320 union t4_recv_wr *queue;
321 dma_addr_t dma_addr;
322 DEFINE_DMA_UNMAP_ADDR(mapping);
323 struct t4_swrqe *sw_rq;
324 void __iomem *bar2_va;
325 u64 bar2_pa;
326 size_t memsize;
327 u32 bar2_qid;
328 u32 qid;
329 u32 msn;
330 u32 rqt_hwaddr;
331 u16 rqt_size;
332 u16 in_use;
333 u16 size;
334 u16 cidx;
335 u16 pidx;
336 u16 wq_pidx;
337 u16 wq_pidx_inc;
338 };
339
340 struct t4_wq {
341 struct t4_sq sq;
342 struct t4_rq rq;
343 void __iomem *db;
344 struct c4iw_rdev *rdev;
345 int flushed;
346 };
347
348 static inline int t4_rqes_posted(struct t4_wq *wq)
349 {
350 return wq->rq.in_use;
351 }
352
353 static inline int t4_rq_empty(struct t4_wq *wq)
354 {
355 return wq->rq.in_use == 0;
356 }
357
358 static inline int t4_rq_full(struct t4_wq *wq)
359 {
360 return wq->rq.in_use == (wq->rq.size - 1);
361 }
362
363 static inline u32 t4_rq_avail(struct t4_wq *wq)
364 {
365 return wq->rq.size - 1 - wq->rq.in_use;
366 }
367
368 static inline void t4_rq_produce(struct t4_wq *wq, u8 len16)
369 {
370 wq->rq.in_use++;
371 if (++wq->rq.pidx == wq->rq.size)
372 wq->rq.pidx = 0;
373 wq->rq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
374 if (wq->rq.wq_pidx >= wq->rq.size * T4_RQ_NUM_SLOTS)
375 wq->rq.wq_pidx %= wq->rq.size * T4_RQ_NUM_SLOTS;
376 }
377
378 static inline void t4_rq_consume(struct t4_wq *wq)
379 {
380 wq->rq.in_use--;
381 wq->rq.msn++;
382 if (++wq->rq.cidx == wq->rq.size)
383 wq->rq.cidx = 0;
384 }
385
386 static inline u16 t4_rq_host_wq_pidx(struct t4_wq *wq)
387 {
388 return wq->rq.queue[wq->rq.size].status.host_wq_pidx;
389 }
390
391 static inline u16 t4_rq_wq_size(struct t4_wq *wq)
392 {
393 return wq->rq.size * T4_RQ_NUM_SLOTS;
394 }
395
396 static inline int t4_sq_onchip(struct t4_sq *sq)
397 {
398 return sq->flags & T4_SQ_ONCHIP;
399 }
400
401 static inline int t4_sq_empty(struct t4_wq *wq)
402 {
403 return wq->sq.in_use == 0;
404 }
405
406 static inline int t4_sq_full(struct t4_wq *wq)
407 {
408 return wq->sq.in_use == (wq->sq.size - 1);
409 }
410
411 static inline u32 t4_sq_avail(struct t4_wq *wq)
412 {
413 return wq->sq.size - 1 - wq->sq.in_use;
414 }
415
416 static inline void t4_sq_produce(struct t4_wq *wq, u8 len16)
417 {
418 wq->sq.in_use++;
419 if (++wq->sq.pidx == wq->sq.size)
420 wq->sq.pidx = 0;
421 wq->sq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
422 if (wq->sq.wq_pidx >= wq->sq.size * T4_SQ_NUM_SLOTS)
423 wq->sq.wq_pidx %= wq->sq.size * T4_SQ_NUM_SLOTS;
424 }
425
426 static inline void t4_sq_consume(struct t4_wq *wq)
427 {
428 if (wq->sq.cidx == wq->sq.flush_cidx)
429 wq->sq.flush_cidx = -1;
430 wq->sq.in_use--;
431 if (++wq->sq.cidx == wq->sq.size)
432 wq->sq.cidx = 0;
433 }
434
435 static inline u16 t4_sq_host_wq_pidx(struct t4_wq *wq)
436 {
437 return wq->sq.queue[wq->sq.size].status.host_wq_pidx;
438 }
439
440 static inline u16 t4_sq_wq_size(struct t4_wq *wq)
441 {
442 return wq->sq.size * T4_SQ_NUM_SLOTS;
443 }
444
445 /* This function copies 64 byte coalesced work request to memory
446 * mapped BAR2 space. For coalesced WRs, the SGE fetches data
447 * from the FIFO instead of from Host.
448 */
449 static inline void pio_copy(u64 __iomem *dst, u64 *src)
450 {
451 int count = 8;
452
453 while (count) {
454 writeq(*src, dst);
455 src++;
456 dst++;
457 count--;
458 }
459 }
460
461 static inline void t4_ring_sq_db(struct t4_wq *wq, u16 inc, union t4_wr *wqe)
462 {
463
464 /* Flush host queue memory writes. */
465 wmb();
466 if (wq->sq.bar2_va) {
467 if (inc == 1 && wq->sq.bar2_qid == 0 && wqe) {
468 pr_debug("WC wq->sq.pidx = %d\n", wq->sq.pidx);
469 pio_copy((u64 __iomem *)
470 (wq->sq.bar2_va + SGE_UDB_WCDOORBELL),
471 (u64 *)wqe);
472 } else {
473 pr_debug("DB wq->sq.pidx = %d\n", wq->sq.pidx);
474 writel(PIDX_T5_V(inc) | QID_V(wq->sq.bar2_qid),
475 wq->sq.bar2_va + SGE_UDB_KDOORBELL);
476 }
477
478 /* Flush user doorbell area writes. */
479 wmb();
480 return;
481 }
482 writel(QID_V(wq->sq.qid) | PIDX_V(inc), wq->db);
483 }
484
485 static inline void t4_ring_rq_db(struct t4_wq *wq, u16 inc,
486 union t4_recv_wr *wqe)
487 {
488
489 /* Flush host queue memory writes. */
490 wmb();
491 if (wq->rq.bar2_va) {
492 if (inc == 1 && wq->rq.bar2_qid == 0 && wqe) {
493 pr_debug("WC wq->rq.pidx = %d\n", wq->rq.pidx);
494 pio_copy((u64 __iomem *)
495 (wq->rq.bar2_va + SGE_UDB_WCDOORBELL),
496 (void *)wqe);
497 } else {
498 pr_debug("DB wq->rq.pidx = %d\n", wq->rq.pidx);
499 writel(PIDX_T5_V(inc) | QID_V(wq->rq.bar2_qid),
500 wq->rq.bar2_va + SGE_UDB_KDOORBELL);
501 }
502
503 /* Flush user doorbell area writes. */
504 wmb();
505 return;
506 }
507 writel(QID_V(wq->rq.qid) | PIDX_V(inc), wq->db);
508 }
509
510 static inline int t4_wq_in_error(struct t4_wq *wq)
511 {
512 return wq->rq.queue[wq->rq.size].status.qp_err;
513 }
514
515 static inline void t4_set_wq_in_error(struct t4_wq *wq)
516 {
517 wq->rq.queue[wq->rq.size].status.qp_err = 1;
518 }
519
520 static inline void t4_disable_wq_db(struct t4_wq *wq)
521 {
522 wq->rq.queue[wq->rq.size].status.db_off = 1;
523 }
524
525 static inline void t4_enable_wq_db(struct t4_wq *wq)
526 {
527 wq->rq.queue[wq->rq.size].status.db_off = 0;
528 }
529
530 static inline int t4_wq_db_enabled(struct t4_wq *wq)
531 {
532 return !wq->rq.queue[wq->rq.size].status.db_off;
533 }
534
535 enum t4_cq_flags {
536 CQ_ARMED = 1,
537 };
538
539 struct t4_cq {
540 struct t4_cqe *queue;
541 dma_addr_t dma_addr;
542 DEFINE_DMA_UNMAP_ADDR(mapping);
543 struct t4_cqe *sw_queue;
544 void __iomem *gts;
545 void __iomem *bar2_va;
546 u64 bar2_pa;
547 u32 bar2_qid;
548 struct c4iw_rdev *rdev;
549 size_t memsize;
550 __be64 bits_type_ts;
551 u32 cqid;
552 u32 qid_mask;
553 int vector;
554 u16 size; /* including status page */
555 u16 cidx;
556 u16 sw_pidx;
557 u16 sw_cidx;
558 u16 sw_in_use;
559 u16 cidx_inc;
560 u8 gen;
561 u8 error;
562 unsigned long flags;
563 };
564
565 static inline void write_gts(struct t4_cq *cq, u32 val)
566 {
567 if (cq->bar2_va)
568 writel(val | INGRESSQID_V(cq->bar2_qid),
569 cq->bar2_va + SGE_UDB_GTS);
570 else
571 writel(val | INGRESSQID_V(cq->cqid), cq->gts);
572 }
573
574 static inline int t4_clear_cq_armed(struct t4_cq *cq)
575 {
576 return test_and_clear_bit(CQ_ARMED, &cq->flags);
577 }
578
579 static inline int t4_arm_cq(struct t4_cq *cq, int se)
580 {
581 u32 val;
582
583 set_bit(CQ_ARMED, &cq->flags);
584 while (cq->cidx_inc > CIDXINC_M) {
585 val = SEINTARM_V(0) | CIDXINC_V(CIDXINC_M) | TIMERREG_V(7);
586 write_gts(cq, val);
587 cq->cidx_inc -= CIDXINC_M;
588 }
589 val = SEINTARM_V(se) | CIDXINC_V(cq->cidx_inc) | TIMERREG_V(6);
590 write_gts(cq, val);
591 cq->cidx_inc = 0;
592 return 0;
593 }
594
595 static inline void t4_swcq_produce(struct t4_cq *cq)
596 {
597 cq->sw_in_use++;
598 if (cq->sw_in_use == cq->size) {
599 pr_warn("%s cxgb4 sw cq overflow cqid %u\n",
600 __func__, cq->cqid);
601 cq->error = 1;
602 cq->sw_in_use--;
603 return;
604 }
605 if (++cq->sw_pidx == cq->size)
606 cq->sw_pidx = 0;
607 }
608
609 static inline void t4_swcq_consume(struct t4_cq *cq)
610 {
611 cq->sw_in_use--;
612 if (++cq->sw_cidx == cq->size)
613 cq->sw_cidx = 0;
614 }
615
616 static inline void t4_hwcq_consume(struct t4_cq *cq)
617 {
618 cq->bits_type_ts = cq->queue[cq->cidx].bits_type_ts;
619 if (++cq->cidx_inc == (cq->size >> 4) || cq->cidx_inc == CIDXINC_M) {
620 u32 val;
621
622 val = SEINTARM_V(0) | CIDXINC_V(cq->cidx_inc) | TIMERREG_V(7);
623 write_gts(cq, val);
624 cq->cidx_inc = 0;
625 }
626 if (++cq->cidx == cq->size) {
627 cq->cidx = 0;
628 cq->gen ^= 1;
629 }
630 }
631
632 static inline int t4_valid_cqe(struct t4_cq *cq, struct t4_cqe *cqe)
633 {
634 return (CQE_GENBIT(cqe) == cq->gen);
635 }
636
637 static inline int t4_cq_notempty(struct t4_cq *cq)
638 {
639 return cq->sw_in_use || t4_valid_cqe(cq, &cq->queue[cq->cidx]);
640 }
641
642 static inline int t4_next_hw_cqe(struct t4_cq *cq, struct t4_cqe **cqe)
643 {
644 int ret;
645 u16 prev_cidx;
646
647 if (cq->cidx == 0)
648 prev_cidx = cq->size - 1;
649 else
650 prev_cidx = cq->cidx - 1;
651
652 if (cq->queue[prev_cidx].bits_type_ts != cq->bits_type_ts) {
653 ret = -EOVERFLOW;
654 cq->error = 1;
655 pr_err("cq overflow cqid %u\n", cq->cqid);
656 } else if (t4_valid_cqe(cq, &cq->queue[cq->cidx])) {
657
658 /* Ensure CQE is flushed to memory */
659 rmb();
660 *cqe = &cq->queue[cq->cidx];
661 ret = 0;
662 } else
663 ret = -ENODATA;
664 return ret;
665 }
666
667 static inline struct t4_cqe *t4_next_sw_cqe(struct t4_cq *cq)
668 {
669 if (cq->sw_in_use == cq->size) {
670 pr_warn("%s cxgb4 sw cq overflow cqid %u\n",
671 __func__, cq->cqid);
672 cq->error = 1;
673 return NULL;
674 }
675 if (cq->sw_in_use)
676 return &cq->sw_queue[cq->sw_cidx];
677 return NULL;
678 }
679
680 static inline int t4_next_cqe(struct t4_cq *cq, struct t4_cqe **cqe)
681 {
682 int ret = 0;
683
684 if (cq->error)
685 ret = -ENODATA;
686 else if (cq->sw_in_use)
687 *cqe = &cq->sw_queue[cq->sw_cidx];
688 else
689 ret = t4_next_hw_cqe(cq, cqe);
690 return ret;
691 }
692
693 static inline int t4_cq_in_error(struct t4_cq *cq)
694 {
695 return ((struct t4_status_page *)&cq->queue[cq->size])->qp_err;
696 }
697
698 static inline void t4_set_cq_in_error(struct t4_cq *cq)
699 {
700 ((struct t4_status_page *)&cq->queue[cq->size])->qp_err = 1;
701 }
702 #endif
703
704 struct t4_dev_status_page {
705 u8 db_off;
706 u8 pad1;
707 u16 pad2;
708 u32 pad3;
709 u64 qp_start;
710 u64 qp_size;
711 u64 cq_start;
712 u64 cq_size;
713 };
Ubuntu Focal Linux kernel mirror