2 * Copyright(c) 2015 - 2017 Intel Corporation.
4 * This file is provided under a dual BSD/GPLv2 license. When using or
5 * redistributing this file, you may do so under either license.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions
24 * - Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * - Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in
28 * the documentation and/or other materials provided with the
30 * - Neither the name of Intel Corporation nor the names of its
31 * contributors may be used to endorse or promote products derived
32 * from this software without specific prior written permission.
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
49 * This file contains all of the code that is specific to the HFI chip
52 #include <linux/pci.h>
53 #include <linux/delay.h>
54 #include <linux/interrupt.h>
55 #include <linux/module.h>
69 #define NUM_IB_PORTS 1
72 module_param_named(kdeth_qp
, kdeth_qp
, uint
, S_IRUGO
);
73 MODULE_PARM_DESC(kdeth_qp
, "Set the KDETH queue pair prefix");
75 uint num_vls
= HFI1_MAX_VLS_SUPPORTED
;
76 module_param(num_vls
, uint
, S_IRUGO
);
77 MODULE_PARM_DESC(num_vls
, "Set number of Virtual Lanes to use (1-8)");
80 * Default time to aggregate two 10K packets from the idle state
81 * (timer not running). The timer starts at the end of the first packet,
82 * so only the time for one 10K packet and header plus a bit extra is needed.
83 * 10 * 1024 + 64 header byte = 10304 byte
84 * 10304 byte / 12.5 GB/s = 824.32ns
86 uint rcv_intr_timeout
= (824 + 16); /* 16 is for coalescing interrupt */
87 module_param(rcv_intr_timeout
, uint
, S_IRUGO
);
88 MODULE_PARM_DESC(rcv_intr_timeout
, "Receive interrupt mitigation timeout in ns");
90 uint rcv_intr_count
= 16; /* same as qib */
91 module_param(rcv_intr_count
, uint
, S_IRUGO
);
92 MODULE_PARM_DESC(rcv_intr_count
, "Receive interrupt mitigation count");
94 ushort link_crc_mask
= SUPPORTED_CRCS
;
95 module_param(link_crc_mask
, ushort
, S_IRUGO
);
96 MODULE_PARM_DESC(link_crc_mask
, "CRCs to use on the link");
99 module_param_named(loopback
, loopback
, uint
, S_IRUGO
);
100 MODULE_PARM_DESC(loopback
, "Put into loopback mode (1 = serdes, 3 = external cable");
102 /* Other driver tunables */
103 uint rcv_intr_dynamic
= 1; /* enable dynamic mode for rcv int mitigation*/
104 static ushort crc_14b_sideband
= 1;
105 static uint use_flr
= 1;
106 uint quick_linkup
; /* skip LNI */
109 u64 flag
; /* the flag */
110 char *str
; /* description string */
111 u16 extra
; /* extra information */
116 /* str must be a string constant */
117 #define FLAG_ENTRY(str, extra, flag) {flag, str, extra}
118 #define FLAG_ENTRY0(str, flag) {flag, str, 0}
120 /* Send Error Consequences */
121 #define SEC_WRITE_DROPPED 0x1
122 #define SEC_PACKET_DROPPED 0x2
123 #define SEC_SC_HALTED 0x4 /* per-context only */
124 #define SEC_SPC_FREEZE 0x8 /* per-HFI only */
126 #define DEFAULT_KRCVQS 2
127 #define MIN_KERNEL_KCTXTS 2
128 #define FIRST_KERNEL_KCTXT 1
131 * RSM instance allocation
133 * 1 - User Fecn Handling
136 #define RSM_INS_VERBS 0
137 #define RSM_INS_FECN 1
138 #define RSM_INS_VNIC 2
140 /* Bit offset into the GUID which carries HFI id information */
141 #define GUID_HFI_INDEX_SHIFT 39
143 /* extract the emulation revision */
144 #define emulator_rev(dd) ((dd)->irev >> 8)
145 /* parallel and serial emulation versions are 3 and 4 respectively */
146 #define is_emulator_p(dd) ((((dd)->irev) & 0xf) == 3)
147 #define is_emulator_s(dd) ((((dd)->irev) & 0xf) == 4)
149 /* RSM fields for Verbs */
151 #define IB_PACKET_TYPE 2ull
152 #define QW_SHIFT 6ull
154 #define QPN_WIDTH 7ull
156 /* LRH.BTH: QW 0, OFFSET 48 - for match */
157 #define LRH_BTH_QW 0ull
158 #define LRH_BTH_BIT_OFFSET 48ull
159 #define LRH_BTH_OFFSET(off) ((LRH_BTH_QW << QW_SHIFT) | (off))
160 #define LRH_BTH_MATCH_OFFSET LRH_BTH_OFFSET(LRH_BTH_BIT_OFFSET)
161 #define LRH_BTH_SELECT
162 #define LRH_BTH_MASK 3ull
163 #define LRH_BTH_VALUE 2ull
165 /* LRH.SC[3..0] QW 0, OFFSET 56 - for match */
166 #define LRH_SC_QW 0ull
167 #define LRH_SC_BIT_OFFSET 56ull
168 #define LRH_SC_OFFSET(off) ((LRH_SC_QW << QW_SHIFT) | (off))
169 #define LRH_SC_MATCH_OFFSET LRH_SC_OFFSET(LRH_SC_BIT_OFFSET)
170 #define LRH_SC_MASK 128ull
171 #define LRH_SC_VALUE 0ull
173 /* SC[n..0] QW 0, OFFSET 60 - for select */
174 #define LRH_SC_SELECT_OFFSET ((LRH_SC_QW << QW_SHIFT) | (60ull))
176 /* QPN[m+n:1] QW 1, OFFSET 1 */
177 #define QPN_SELECT_OFFSET ((1ull << QW_SHIFT) | (1ull))
179 /* RSM fields for Vnic */
180 /* L2_TYPE: QW 0, OFFSET 61 - for match */
181 #define L2_TYPE_QW 0ull
182 #define L2_TYPE_BIT_OFFSET 61ull
183 #define L2_TYPE_OFFSET(off) ((L2_TYPE_QW << QW_SHIFT) | (off))
184 #define L2_TYPE_MATCH_OFFSET L2_TYPE_OFFSET(L2_TYPE_BIT_OFFSET)
185 #define L2_TYPE_MASK 3ull
186 #define L2_16B_VALUE 2ull
188 /* L4_TYPE QW 1, OFFSET 0 - for match */
189 #define L4_TYPE_QW 1ull
190 #define L4_TYPE_BIT_OFFSET 0ull
191 #define L4_TYPE_OFFSET(off) ((L4_TYPE_QW << QW_SHIFT) | (off))
192 #define L4_TYPE_MATCH_OFFSET L4_TYPE_OFFSET(L4_TYPE_BIT_OFFSET)
193 #define L4_16B_TYPE_MASK 0xFFull
194 #define L4_16B_ETH_VALUE 0x78ull
196 /* 16B VESWID - for select */
197 #define L4_16B_HDR_VESWID_OFFSET ((2 << QW_SHIFT) | (16ull))
198 /* 16B ENTROPY - for select */
199 #define L2_16B_ENTROPY_OFFSET ((1 << QW_SHIFT) | (32ull))
201 /* defines to build power on SC2VL table */
213 ((u64)(sc0val) << SEND_SC2VLT##num##_SC##sc0##_SHIFT) | \
214 ((u64)(sc1val) << SEND_SC2VLT##num##_SC##sc1##_SHIFT) | \
215 ((u64)(sc2val) << SEND_SC2VLT##num##_SC##sc2##_SHIFT) | \
216 ((u64)(sc3val) << SEND_SC2VLT##num##_SC##sc3##_SHIFT) | \
217 ((u64)(sc4val) << SEND_SC2VLT##num##_SC##sc4##_SHIFT) | \
218 ((u64)(sc5val) << SEND_SC2VLT##num##_SC##sc5##_SHIFT) | \
219 ((u64)(sc6val) << SEND_SC2VLT##num##_SC##sc6##_SHIFT) | \
220 ((u64)(sc7val) << SEND_SC2VLT##num##_SC##sc7##_SHIFT) \
223 #define DC_SC_VL_VAL( \
242 ((u64)(e0val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e0##_SHIFT) | \
243 ((u64)(e1val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e1##_SHIFT) | \
244 ((u64)(e2val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e2##_SHIFT) | \
245 ((u64)(e3val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e3##_SHIFT) | \
246 ((u64)(e4val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e4##_SHIFT) | \
247 ((u64)(e5val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e5##_SHIFT) | \
248 ((u64)(e6val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e6##_SHIFT) | \
249 ((u64)(e7val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e7##_SHIFT) | \
250 ((u64)(e8val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e8##_SHIFT) | \
251 ((u64)(e9val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e9##_SHIFT) | \
252 ((u64)(e10val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e10##_SHIFT) | \
253 ((u64)(e11val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e11##_SHIFT) | \
254 ((u64)(e12val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e12##_SHIFT) | \
255 ((u64)(e13val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e13##_SHIFT) | \
256 ((u64)(e14val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e14##_SHIFT) | \
257 ((u64)(e15val) << DCC_CFG_SC_VL_TABLE_##range##_ENTRY##e15##_SHIFT) \
260 /* all CceStatus sub-block freeze bits */
261 #define ALL_FROZE (CCE_STATUS_SDMA_FROZE_SMASK \
262 | CCE_STATUS_RXE_FROZE_SMASK \
263 | CCE_STATUS_TXE_FROZE_SMASK \
264 | CCE_STATUS_TXE_PIO_FROZE_SMASK)
265 /* all CceStatus sub-block TXE pause bits */
266 #define ALL_TXE_PAUSE (CCE_STATUS_TXE_PIO_PAUSED_SMASK \
267 | CCE_STATUS_TXE_PAUSED_SMASK \
268 | CCE_STATUS_SDMA_PAUSED_SMASK)
269 /* all CceStatus sub-block RXE pause bits */
270 #define ALL_RXE_PAUSE CCE_STATUS_RXE_PAUSED_SMASK
272 #define CNTR_MAX 0xFFFFFFFFFFFFFFFFULL
273 #define CNTR_32BIT_MAX 0x00000000FFFFFFFF
278 static struct flag_table cce_err_status_flags
[] = {
279 /* 0*/ FLAG_ENTRY0("CceCsrParityErr",
280 CCE_ERR_STATUS_CCE_CSR_PARITY_ERR_SMASK
),
281 /* 1*/ FLAG_ENTRY0("CceCsrReadBadAddrErr",
282 CCE_ERR_STATUS_CCE_CSR_READ_BAD_ADDR_ERR_SMASK
),
283 /* 2*/ FLAG_ENTRY0("CceCsrWriteBadAddrErr",
284 CCE_ERR_STATUS_CCE_CSR_WRITE_BAD_ADDR_ERR_SMASK
),
285 /* 3*/ FLAG_ENTRY0("CceTrgtAsyncFifoParityErr",
286 CCE_ERR_STATUS_CCE_TRGT_ASYNC_FIFO_PARITY_ERR_SMASK
),
287 /* 4*/ FLAG_ENTRY0("CceTrgtAccessErr",
288 CCE_ERR_STATUS_CCE_TRGT_ACCESS_ERR_SMASK
),
289 /* 5*/ FLAG_ENTRY0("CceRspdDataParityErr",
290 CCE_ERR_STATUS_CCE_RSPD_DATA_PARITY_ERR_SMASK
),
291 /* 6*/ FLAG_ENTRY0("CceCli0AsyncFifoParityErr",
292 CCE_ERR_STATUS_CCE_CLI0_ASYNC_FIFO_PARITY_ERR_SMASK
),
293 /* 7*/ FLAG_ENTRY0("CceCsrCfgBusParityErr",
294 CCE_ERR_STATUS_CCE_CSR_CFG_BUS_PARITY_ERR_SMASK
),
295 /* 8*/ FLAG_ENTRY0("CceCli2AsyncFifoParityErr",
296 CCE_ERR_STATUS_CCE_CLI2_ASYNC_FIFO_PARITY_ERR_SMASK
),
297 /* 9*/ FLAG_ENTRY0("CceCli1AsyncFifoPioCrdtParityErr",
298 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_PIO_CRDT_PARITY_ERR_SMASK
),
299 /*10*/ FLAG_ENTRY0("CceCli1AsyncFifoPioCrdtParityErr",
300 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_SDMA_HD_PARITY_ERR_SMASK
),
301 /*11*/ FLAG_ENTRY0("CceCli1AsyncFifoRxdmaParityError",
302 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_RXDMA_PARITY_ERROR_SMASK
),
303 /*12*/ FLAG_ENTRY0("CceCli1AsyncFifoDbgParityError",
304 CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_DBG_PARITY_ERROR_SMASK
),
305 /*13*/ FLAG_ENTRY0("PcicRetryMemCorErr",
306 CCE_ERR_STATUS_PCIC_RETRY_MEM_COR_ERR_SMASK
),
307 /*14*/ FLAG_ENTRY0("PcicRetryMemCorErr",
308 CCE_ERR_STATUS_PCIC_RETRY_SOT_MEM_COR_ERR_SMASK
),
309 /*15*/ FLAG_ENTRY0("PcicPostHdQCorErr",
310 CCE_ERR_STATUS_PCIC_POST_HD_QCOR_ERR_SMASK
),
311 /*16*/ FLAG_ENTRY0("PcicPostHdQCorErr",
312 CCE_ERR_STATUS_PCIC_POST_DAT_QCOR_ERR_SMASK
),
313 /*17*/ FLAG_ENTRY0("PcicPostHdQCorErr",
314 CCE_ERR_STATUS_PCIC_CPL_HD_QCOR_ERR_SMASK
),
315 /*18*/ FLAG_ENTRY0("PcicCplDatQCorErr",
316 CCE_ERR_STATUS_PCIC_CPL_DAT_QCOR_ERR_SMASK
),
317 /*19*/ FLAG_ENTRY0("PcicNPostHQParityErr",
318 CCE_ERR_STATUS_PCIC_NPOST_HQ_PARITY_ERR_SMASK
),
319 /*20*/ FLAG_ENTRY0("PcicNPostDatQParityErr",
320 CCE_ERR_STATUS_PCIC_NPOST_DAT_QPARITY_ERR_SMASK
),
321 /*21*/ FLAG_ENTRY0("PcicRetryMemUncErr",
322 CCE_ERR_STATUS_PCIC_RETRY_MEM_UNC_ERR_SMASK
),
323 /*22*/ FLAG_ENTRY0("PcicRetrySotMemUncErr",
324 CCE_ERR_STATUS_PCIC_RETRY_SOT_MEM_UNC_ERR_SMASK
),
325 /*23*/ FLAG_ENTRY0("PcicPostHdQUncErr",
326 CCE_ERR_STATUS_PCIC_POST_HD_QUNC_ERR_SMASK
),
327 /*24*/ FLAG_ENTRY0("PcicPostDatQUncErr",
328 CCE_ERR_STATUS_PCIC_POST_DAT_QUNC_ERR_SMASK
),
329 /*25*/ FLAG_ENTRY0("PcicCplHdQUncErr",
330 CCE_ERR_STATUS_PCIC_CPL_HD_QUNC_ERR_SMASK
),
331 /*26*/ FLAG_ENTRY0("PcicCplDatQUncErr",
332 CCE_ERR_STATUS_PCIC_CPL_DAT_QUNC_ERR_SMASK
),
333 /*27*/ FLAG_ENTRY0("PcicTransmitFrontParityErr",
334 CCE_ERR_STATUS_PCIC_TRANSMIT_FRONT_PARITY_ERR_SMASK
),
335 /*28*/ FLAG_ENTRY0("PcicTransmitBackParityErr",
336 CCE_ERR_STATUS_PCIC_TRANSMIT_BACK_PARITY_ERR_SMASK
),
337 /*29*/ FLAG_ENTRY0("PcicReceiveParityErr",
338 CCE_ERR_STATUS_PCIC_RECEIVE_PARITY_ERR_SMASK
),
339 /*30*/ FLAG_ENTRY0("CceTrgtCplTimeoutErr",
340 CCE_ERR_STATUS_CCE_TRGT_CPL_TIMEOUT_ERR_SMASK
),
341 /*31*/ FLAG_ENTRY0("LATriggered",
342 CCE_ERR_STATUS_LA_TRIGGERED_SMASK
),
343 /*32*/ FLAG_ENTRY0("CceSegReadBadAddrErr",
344 CCE_ERR_STATUS_CCE_SEG_READ_BAD_ADDR_ERR_SMASK
),
345 /*33*/ FLAG_ENTRY0("CceSegWriteBadAddrErr",
346 CCE_ERR_STATUS_CCE_SEG_WRITE_BAD_ADDR_ERR_SMASK
),
347 /*34*/ FLAG_ENTRY0("CceRcplAsyncFifoParityErr",
348 CCE_ERR_STATUS_CCE_RCPL_ASYNC_FIFO_PARITY_ERR_SMASK
),
349 /*35*/ FLAG_ENTRY0("CceRxdmaConvFifoParityErr",
350 CCE_ERR_STATUS_CCE_RXDMA_CONV_FIFO_PARITY_ERR_SMASK
),
351 /*36*/ FLAG_ENTRY0("CceMsixTableCorErr",
352 CCE_ERR_STATUS_CCE_MSIX_TABLE_COR_ERR_SMASK
),
353 /*37*/ FLAG_ENTRY0("CceMsixTableUncErr",
354 CCE_ERR_STATUS_CCE_MSIX_TABLE_UNC_ERR_SMASK
),
355 /*38*/ FLAG_ENTRY0("CceIntMapCorErr",
356 CCE_ERR_STATUS_CCE_INT_MAP_COR_ERR_SMASK
),
357 /*39*/ FLAG_ENTRY0("CceIntMapUncErr",
358 CCE_ERR_STATUS_CCE_INT_MAP_UNC_ERR_SMASK
),
359 /*40*/ FLAG_ENTRY0("CceMsixCsrParityErr",
360 CCE_ERR_STATUS_CCE_MSIX_CSR_PARITY_ERR_SMASK
),
367 #define MES(text) MISC_ERR_STATUS_MISC_##text##_ERR_SMASK
368 static struct flag_table misc_err_status_flags
[] = {
369 /* 0*/ FLAG_ENTRY0("CSR_PARITY", MES(CSR_PARITY
)),
370 /* 1*/ FLAG_ENTRY0("CSR_READ_BAD_ADDR", MES(CSR_READ_BAD_ADDR
)),
371 /* 2*/ FLAG_ENTRY0("CSR_WRITE_BAD_ADDR", MES(CSR_WRITE_BAD_ADDR
)),
372 /* 3*/ FLAG_ENTRY0("SBUS_WRITE_FAILED", MES(SBUS_WRITE_FAILED
)),
373 /* 4*/ FLAG_ENTRY0("KEY_MISMATCH", MES(KEY_MISMATCH
)),
374 /* 5*/ FLAG_ENTRY0("FW_AUTH_FAILED", MES(FW_AUTH_FAILED
)),
375 /* 6*/ FLAG_ENTRY0("EFUSE_CSR_PARITY", MES(EFUSE_CSR_PARITY
)),
376 /* 7*/ FLAG_ENTRY0("EFUSE_READ_BAD_ADDR", MES(EFUSE_READ_BAD_ADDR
)),
377 /* 8*/ FLAG_ENTRY0("EFUSE_WRITE", MES(EFUSE_WRITE
)),
378 /* 9*/ FLAG_ENTRY0("EFUSE_DONE_PARITY", MES(EFUSE_DONE_PARITY
)),
379 /*10*/ FLAG_ENTRY0("INVALID_EEP_CMD", MES(INVALID_EEP_CMD
)),
380 /*11*/ FLAG_ENTRY0("MBIST_FAIL", MES(MBIST_FAIL
)),
381 /*12*/ FLAG_ENTRY0("PLL_LOCK_FAIL", MES(PLL_LOCK_FAIL
))
385 * TXE PIO Error flags and consequences
387 static struct flag_table pio_err_status_flags
[] = {
388 /* 0*/ FLAG_ENTRY("PioWriteBadCtxt",
390 SEND_PIO_ERR_STATUS_PIO_WRITE_BAD_CTXT_ERR_SMASK
),
391 /* 1*/ FLAG_ENTRY("PioWriteAddrParity",
393 SEND_PIO_ERR_STATUS_PIO_WRITE_ADDR_PARITY_ERR_SMASK
),
394 /* 2*/ FLAG_ENTRY("PioCsrParity",
396 SEND_PIO_ERR_STATUS_PIO_CSR_PARITY_ERR_SMASK
),
397 /* 3*/ FLAG_ENTRY("PioSbMemFifo0",
399 SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO0_ERR_SMASK
),
400 /* 4*/ FLAG_ENTRY("PioSbMemFifo1",
402 SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO1_ERR_SMASK
),
403 /* 5*/ FLAG_ENTRY("PioPccFifoParity",
405 SEND_PIO_ERR_STATUS_PIO_PCC_FIFO_PARITY_ERR_SMASK
),
406 /* 6*/ FLAG_ENTRY("PioPecFifoParity",
408 SEND_PIO_ERR_STATUS_PIO_PEC_FIFO_PARITY_ERR_SMASK
),
409 /* 7*/ FLAG_ENTRY("PioSbrdctlCrrelParity",
411 SEND_PIO_ERR_STATUS_PIO_SBRDCTL_CRREL_PARITY_ERR_SMASK
),
412 /* 8*/ FLAG_ENTRY("PioSbrdctrlCrrelFifoParity",
414 SEND_PIO_ERR_STATUS_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR_SMASK
),
415 /* 9*/ FLAG_ENTRY("PioPktEvictFifoParityErr",
417 SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_FIFO_PARITY_ERR_SMASK
),
418 /*10*/ FLAG_ENTRY("PioSmPktResetParity",
420 SEND_PIO_ERR_STATUS_PIO_SM_PKT_RESET_PARITY_ERR_SMASK
),
421 /*11*/ FLAG_ENTRY("PioVlLenMemBank0Unc",
423 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_UNC_ERR_SMASK
),
424 /*12*/ FLAG_ENTRY("PioVlLenMemBank1Unc",
426 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_UNC_ERR_SMASK
),
427 /*13*/ FLAG_ENTRY("PioVlLenMemBank0Cor",
429 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_COR_ERR_SMASK
),
430 /*14*/ FLAG_ENTRY("PioVlLenMemBank1Cor",
432 SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_COR_ERR_SMASK
),
433 /*15*/ FLAG_ENTRY("PioCreditRetFifoParity",
435 SEND_PIO_ERR_STATUS_PIO_CREDIT_RET_FIFO_PARITY_ERR_SMASK
),
436 /*16*/ FLAG_ENTRY("PioPpmcPblFifo",
438 SEND_PIO_ERR_STATUS_PIO_PPMC_PBL_FIFO_ERR_SMASK
),
439 /*17*/ FLAG_ENTRY("PioInitSmIn",
441 SEND_PIO_ERR_STATUS_PIO_INIT_SM_IN_ERR_SMASK
),
442 /*18*/ FLAG_ENTRY("PioPktEvictSmOrArbSm",
444 SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_SM_OR_ARB_SM_ERR_SMASK
),
445 /*19*/ FLAG_ENTRY("PioHostAddrMemUnc",
447 SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_UNC_ERR_SMASK
),
448 /*20*/ FLAG_ENTRY("PioHostAddrMemCor",
450 SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_COR_ERR_SMASK
),
451 /*21*/ FLAG_ENTRY("PioWriteDataParity",
453 SEND_PIO_ERR_STATUS_PIO_WRITE_DATA_PARITY_ERR_SMASK
),
454 /*22*/ FLAG_ENTRY("PioStateMachine",
456 SEND_PIO_ERR_STATUS_PIO_STATE_MACHINE_ERR_SMASK
),
457 /*23*/ FLAG_ENTRY("PioWriteQwValidParity",
458 SEC_WRITE_DROPPED
| SEC_SPC_FREEZE
,
459 SEND_PIO_ERR_STATUS_PIO_WRITE_QW_VALID_PARITY_ERR_SMASK
),
460 /*24*/ FLAG_ENTRY("PioBlockQwCountParity",
461 SEC_WRITE_DROPPED
| SEC_SPC_FREEZE
,
462 SEND_PIO_ERR_STATUS_PIO_BLOCK_QW_COUNT_PARITY_ERR_SMASK
),
463 /*25*/ FLAG_ENTRY("PioVlfVlLenParity",
465 SEND_PIO_ERR_STATUS_PIO_VLF_VL_LEN_PARITY_ERR_SMASK
),
466 /*26*/ FLAG_ENTRY("PioVlfSopParity",
468 SEND_PIO_ERR_STATUS_PIO_VLF_SOP_PARITY_ERR_SMASK
),
469 /*27*/ FLAG_ENTRY("PioVlFifoParity",
471 SEND_PIO_ERR_STATUS_PIO_VL_FIFO_PARITY_ERR_SMASK
),
472 /*28*/ FLAG_ENTRY("PioPpmcBqcMemParity",
474 SEND_PIO_ERR_STATUS_PIO_PPMC_BQC_MEM_PARITY_ERR_SMASK
),
475 /*29*/ FLAG_ENTRY("PioPpmcSopLen",
477 SEND_PIO_ERR_STATUS_PIO_PPMC_SOP_LEN_ERR_SMASK
),
479 /*32*/ FLAG_ENTRY("PioCurrentFreeCntParity",
481 SEND_PIO_ERR_STATUS_PIO_CURRENT_FREE_CNT_PARITY_ERR_SMASK
),
482 /*33*/ FLAG_ENTRY("PioLastReturnedCntParity",
484 SEND_PIO_ERR_STATUS_PIO_LAST_RETURNED_CNT_PARITY_ERR_SMASK
),
485 /*34*/ FLAG_ENTRY("PioPccSopHeadParity",
487 SEND_PIO_ERR_STATUS_PIO_PCC_SOP_HEAD_PARITY_ERR_SMASK
),
488 /*35*/ FLAG_ENTRY("PioPecSopHeadParityErr",
490 SEND_PIO_ERR_STATUS_PIO_PEC_SOP_HEAD_PARITY_ERR_SMASK
),
494 /* TXE PIO errors that cause an SPC freeze */
495 #define ALL_PIO_FREEZE_ERR \
496 (SEND_PIO_ERR_STATUS_PIO_WRITE_ADDR_PARITY_ERR_SMASK \
497 | SEND_PIO_ERR_STATUS_PIO_CSR_PARITY_ERR_SMASK \
498 | SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO0_ERR_SMASK \
499 | SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO1_ERR_SMASK \
500 | SEND_PIO_ERR_STATUS_PIO_PCC_FIFO_PARITY_ERR_SMASK \
501 | SEND_PIO_ERR_STATUS_PIO_PEC_FIFO_PARITY_ERR_SMASK \
502 | SEND_PIO_ERR_STATUS_PIO_SBRDCTL_CRREL_PARITY_ERR_SMASK \
503 | SEND_PIO_ERR_STATUS_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR_SMASK \
504 | SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_FIFO_PARITY_ERR_SMASK \
505 | SEND_PIO_ERR_STATUS_PIO_SM_PKT_RESET_PARITY_ERR_SMASK \
506 | SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_UNC_ERR_SMASK \
507 | SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_UNC_ERR_SMASK \
508 | SEND_PIO_ERR_STATUS_PIO_CREDIT_RET_FIFO_PARITY_ERR_SMASK \
509 | SEND_PIO_ERR_STATUS_PIO_PPMC_PBL_FIFO_ERR_SMASK \
510 | SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_SM_OR_ARB_SM_ERR_SMASK \
511 | SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_UNC_ERR_SMASK \
512 | SEND_PIO_ERR_STATUS_PIO_WRITE_DATA_PARITY_ERR_SMASK \
513 | SEND_PIO_ERR_STATUS_PIO_STATE_MACHINE_ERR_SMASK \
514 | SEND_PIO_ERR_STATUS_PIO_WRITE_QW_VALID_PARITY_ERR_SMASK \
515 | SEND_PIO_ERR_STATUS_PIO_BLOCK_QW_COUNT_PARITY_ERR_SMASK \
516 | SEND_PIO_ERR_STATUS_PIO_VLF_VL_LEN_PARITY_ERR_SMASK \
517 | SEND_PIO_ERR_STATUS_PIO_VLF_SOP_PARITY_ERR_SMASK \
518 | SEND_PIO_ERR_STATUS_PIO_VL_FIFO_PARITY_ERR_SMASK \
519 | SEND_PIO_ERR_STATUS_PIO_PPMC_BQC_MEM_PARITY_ERR_SMASK \
520 | SEND_PIO_ERR_STATUS_PIO_PPMC_SOP_LEN_ERR_SMASK \
521 | SEND_PIO_ERR_STATUS_PIO_CURRENT_FREE_CNT_PARITY_ERR_SMASK \
522 | SEND_PIO_ERR_STATUS_PIO_LAST_RETURNED_CNT_PARITY_ERR_SMASK \
523 | SEND_PIO_ERR_STATUS_PIO_PCC_SOP_HEAD_PARITY_ERR_SMASK \
524 | SEND_PIO_ERR_STATUS_PIO_PEC_SOP_HEAD_PARITY_ERR_SMASK)
527 * TXE SDMA Error flags
529 static struct flag_table sdma_err_status_flags
[] = {
530 /* 0*/ FLAG_ENTRY0("SDmaRpyTagErr",
531 SEND_DMA_ERR_STATUS_SDMA_RPY_TAG_ERR_SMASK
),
532 /* 1*/ FLAG_ENTRY0("SDmaCsrParityErr",
533 SEND_DMA_ERR_STATUS_SDMA_CSR_PARITY_ERR_SMASK
),
534 /* 2*/ FLAG_ENTRY0("SDmaPcieReqTrackingUncErr",
535 SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_UNC_ERR_SMASK
),
536 /* 3*/ FLAG_ENTRY0("SDmaPcieReqTrackingCorErr",
537 SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_COR_ERR_SMASK
),
541 /* TXE SDMA errors that cause an SPC freeze */
542 #define ALL_SDMA_FREEZE_ERR \
543 (SEND_DMA_ERR_STATUS_SDMA_RPY_TAG_ERR_SMASK \
544 | SEND_DMA_ERR_STATUS_SDMA_CSR_PARITY_ERR_SMASK \
545 | SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_UNC_ERR_SMASK)
547 /* SendEgressErrInfo bits that correspond to a PortXmitDiscard counter */
548 #define PORT_DISCARD_EGRESS_ERRS \
549 (SEND_EGRESS_ERR_INFO_TOO_LONG_IB_PACKET_ERR_SMASK \
550 | SEND_EGRESS_ERR_INFO_VL_MAPPING_ERR_SMASK \
551 | SEND_EGRESS_ERR_INFO_VL_ERR_SMASK)
554 * TXE Egress Error flags
556 #define SEES(text) SEND_EGRESS_ERR_STATUS_##text##_ERR_SMASK
557 static struct flag_table egress_err_status_flags
[] = {
558 /* 0*/ FLAG_ENTRY0("TxPktIntegrityMemCorErr", SEES(TX_PKT_INTEGRITY_MEM_COR
)),
559 /* 1*/ FLAG_ENTRY0("TxPktIntegrityMemUncErr", SEES(TX_PKT_INTEGRITY_MEM_UNC
)),
561 /* 3*/ FLAG_ENTRY0("TxEgressFifoUnderrunOrParityErr",
562 SEES(TX_EGRESS_FIFO_UNDERRUN_OR_PARITY
)),
563 /* 4*/ FLAG_ENTRY0("TxLinkdownErr", SEES(TX_LINKDOWN
)),
564 /* 5*/ FLAG_ENTRY0("TxIncorrectLinkStateErr", SEES(TX_INCORRECT_LINK_STATE
)),
566 /* 7*/ FLAG_ENTRY0("TxPioLaunchIntfParityErr",
567 SEES(TX_PIO_LAUNCH_INTF_PARITY
)),
568 /* 8*/ FLAG_ENTRY0("TxSdmaLaunchIntfParityErr",
569 SEES(TX_SDMA_LAUNCH_INTF_PARITY
)),
571 /*11*/ FLAG_ENTRY0("TxSbrdCtlStateMachineParityErr",
572 SEES(TX_SBRD_CTL_STATE_MACHINE_PARITY
)),
573 /*12*/ FLAG_ENTRY0("TxIllegalVLErr", SEES(TX_ILLEGAL_VL
)),
574 /*13*/ FLAG_ENTRY0("TxLaunchCsrParityErr", SEES(TX_LAUNCH_CSR_PARITY
)),
575 /*14*/ FLAG_ENTRY0("TxSbrdCtlCsrParityErr", SEES(TX_SBRD_CTL_CSR_PARITY
)),
576 /*15*/ FLAG_ENTRY0("TxConfigParityErr", SEES(TX_CONFIG_PARITY
)),
577 /*16*/ FLAG_ENTRY0("TxSdma0DisallowedPacketErr",
578 SEES(TX_SDMA0_DISALLOWED_PACKET
)),
579 /*17*/ FLAG_ENTRY0("TxSdma1DisallowedPacketErr",
580 SEES(TX_SDMA1_DISALLOWED_PACKET
)),
581 /*18*/ FLAG_ENTRY0("TxSdma2DisallowedPacketErr",
582 SEES(TX_SDMA2_DISALLOWED_PACKET
)),
583 /*19*/ FLAG_ENTRY0("TxSdma3DisallowedPacketErr",
584 SEES(TX_SDMA3_DISALLOWED_PACKET
)),
585 /*20*/ FLAG_ENTRY0("TxSdma4DisallowedPacketErr",
586 SEES(TX_SDMA4_DISALLOWED_PACKET
)),
587 /*21*/ FLAG_ENTRY0("TxSdma5DisallowedPacketErr",
588 SEES(TX_SDMA5_DISALLOWED_PACKET
)),
589 /*22*/ FLAG_ENTRY0("TxSdma6DisallowedPacketErr",
590 SEES(TX_SDMA6_DISALLOWED_PACKET
)),
591 /*23*/ FLAG_ENTRY0("TxSdma7DisallowedPacketErr",
592 SEES(TX_SDMA7_DISALLOWED_PACKET
)),
593 /*24*/ FLAG_ENTRY0("TxSdma8DisallowedPacketErr",
594 SEES(TX_SDMA8_DISALLOWED_PACKET
)),
595 /*25*/ FLAG_ENTRY0("TxSdma9DisallowedPacketErr",
596 SEES(TX_SDMA9_DISALLOWED_PACKET
)),
597 /*26*/ FLAG_ENTRY0("TxSdma10DisallowedPacketErr",
598 SEES(TX_SDMA10_DISALLOWED_PACKET
)),
599 /*27*/ FLAG_ENTRY0("TxSdma11DisallowedPacketErr",
600 SEES(TX_SDMA11_DISALLOWED_PACKET
)),
601 /*28*/ FLAG_ENTRY0("TxSdma12DisallowedPacketErr",
602 SEES(TX_SDMA12_DISALLOWED_PACKET
)),
603 /*29*/ FLAG_ENTRY0("TxSdma13DisallowedPacketErr",
604 SEES(TX_SDMA13_DISALLOWED_PACKET
)),
605 /*30*/ FLAG_ENTRY0("TxSdma14DisallowedPacketErr",
606 SEES(TX_SDMA14_DISALLOWED_PACKET
)),
607 /*31*/ FLAG_ENTRY0("TxSdma15DisallowedPacketErr",
608 SEES(TX_SDMA15_DISALLOWED_PACKET
)),
609 /*32*/ FLAG_ENTRY0("TxLaunchFifo0UncOrParityErr",
610 SEES(TX_LAUNCH_FIFO0_UNC_OR_PARITY
)),
611 /*33*/ FLAG_ENTRY0("TxLaunchFifo1UncOrParityErr",
612 SEES(TX_LAUNCH_FIFO1_UNC_OR_PARITY
)),
613 /*34*/ FLAG_ENTRY0("TxLaunchFifo2UncOrParityErr",
614 SEES(TX_LAUNCH_FIFO2_UNC_OR_PARITY
)),
615 /*35*/ FLAG_ENTRY0("TxLaunchFifo3UncOrParityErr",
616 SEES(TX_LAUNCH_FIFO3_UNC_OR_PARITY
)),
617 /*36*/ FLAG_ENTRY0("TxLaunchFifo4UncOrParityErr",
618 SEES(TX_LAUNCH_FIFO4_UNC_OR_PARITY
)),
619 /*37*/ FLAG_ENTRY0("TxLaunchFifo5UncOrParityErr",
620 SEES(TX_LAUNCH_FIFO5_UNC_OR_PARITY
)),
621 /*38*/ FLAG_ENTRY0("TxLaunchFifo6UncOrParityErr",
622 SEES(TX_LAUNCH_FIFO6_UNC_OR_PARITY
)),
623 /*39*/ FLAG_ENTRY0("TxLaunchFifo7UncOrParityErr",
624 SEES(TX_LAUNCH_FIFO7_UNC_OR_PARITY
)),
625 /*40*/ FLAG_ENTRY0("TxLaunchFifo8UncOrParityErr",
626 SEES(TX_LAUNCH_FIFO8_UNC_OR_PARITY
)),
627 /*41*/ FLAG_ENTRY0("TxCreditReturnParityErr", SEES(TX_CREDIT_RETURN_PARITY
)),
628 /*42*/ FLAG_ENTRY0("TxSbHdrUncErr", SEES(TX_SB_HDR_UNC
)),
629 /*43*/ FLAG_ENTRY0("TxReadSdmaMemoryUncErr", SEES(TX_READ_SDMA_MEMORY_UNC
)),
630 /*44*/ FLAG_ENTRY0("TxReadPioMemoryUncErr", SEES(TX_READ_PIO_MEMORY_UNC
)),
631 /*45*/ FLAG_ENTRY0("TxEgressFifoUncErr", SEES(TX_EGRESS_FIFO_UNC
)),
632 /*46*/ FLAG_ENTRY0("TxHcrcInsertionErr", SEES(TX_HCRC_INSERTION
)),
633 /*47*/ FLAG_ENTRY0("TxCreditReturnVLErr", SEES(TX_CREDIT_RETURN_VL
)),
634 /*48*/ FLAG_ENTRY0("TxLaunchFifo0CorErr", SEES(TX_LAUNCH_FIFO0_COR
)),
635 /*49*/ FLAG_ENTRY0("TxLaunchFifo1CorErr", SEES(TX_LAUNCH_FIFO1_COR
)),
636 /*50*/ FLAG_ENTRY0("TxLaunchFifo2CorErr", SEES(TX_LAUNCH_FIFO2_COR
)),
637 /*51*/ FLAG_ENTRY0("TxLaunchFifo3CorErr", SEES(TX_LAUNCH_FIFO3_COR
)),
638 /*52*/ FLAG_ENTRY0("TxLaunchFifo4CorErr", SEES(TX_LAUNCH_FIFO4_COR
)),
639 /*53*/ FLAG_ENTRY0("TxLaunchFifo5CorErr", SEES(TX_LAUNCH_FIFO5_COR
)),
640 /*54*/ FLAG_ENTRY0("TxLaunchFifo6CorErr", SEES(TX_LAUNCH_FIFO6_COR
)),
641 /*55*/ FLAG_ENTRY0("TxLaunchFifo7CorErr", SEES(TX_LAUNCH_FIFO7_COR
)),
642 /*56*/ FLAG_ENTRY0("TxLaunchFifo8CorErr", SEES(TX_LAUNCH_FIFO8_COR
)),
643 /*57*/ FLAG_ENTRY0("TxCreditOverrunErr", SEES(TX_CREDIT_OVERRUN
)),
644 /*58*/ FLAG_ENTRY0("TxSbHdrCorErr", SEES(TX_SB_HDR_COR
)),
645 /*59*/ FLAG_ENTRY0("TxReadSdmaMemoryCorErr", SEES(TX_READ_SDMA_MEMORY_COR
)),
646 /*60*/ FLAG_ENTRY0("TxReadPioMemoryCorErr", SEES(TX_READ_PIO_MEMORY_COR
)),
647 /*61*/ FLAG_ENTRY0("TxEgressFifoCorErr", SEES(TX_EGRESS_FIFO_COR
)),
648 /*62*/ FLAG_ENTRY0("TxReadSdmaMemoryCsrUncErr",
649 SEES(TX_READ_SDMA_MEMORY_CSR_UNC
)),
650 /*63*/ FLAG_ENTRY0("TxReadPioMemoryCsrUncErr",
651 SEES(TX_READ_PIO_MEMORY_CSR_UNC
)),
655 * TXE Egress Error Info flags
657 #define SEEI(text) SEND_EGRESS_ERR_INFO_##text##_ERR_SMASK
658 static struct flag_table egress_err_info_flags
[] = {
659 /* 0*/ FLAG_ENTRY0("Reserved", 0ull),
660 /* 1*/ FLAG_ENTRY0("VLErr", SEEI(VL
)),
661 /* 2*/ FLAG_ENTRY0("JobKeyErr", SEEI(JOB_KEY
)),
662 /* 3*/ FLAG_ENTRY0("JobKeyErr", SEEI(JOB_KEY
)),
663 /* 4*/ FLAG_ENTRY0("PartitionKeyErr", SEEI(PARTITION_KEY
)),
664 /* 5*/ FLAG_ENTRY0("SLIDErr", SEEI(SLID
)),
665 /* 6*/ FLAG_ENTRY0("OpcodeErr", SEEI(OPCODE
)),
666 /* 7*/ FLAG_ENTRY0("VLMappingErr", SEEI(VL_MAPPING
)),
667 /* 8*/ FLAG_ENTRY0("RawErr", SEEI(RAW
)),
668 /* 9*/ FLAG_ENTRY0("RawIPv6Err", SEEI(RAW_IPV6
)),
669 /*10*/ FLAG_ENTRY0("GRHErr", SEEI(GRH
)),
670 /*11*/ FLAG_ENTRY0("BypassErr", SEEI(BYPASS
)),
671 /*12*/ FLAG_ENTRY0("KDETHPacketsErr", SEEI(KDETH_PACKETS
)),
672 /*13*/ FLAG_ENTRY0("NonKDETHPacketsErr", SEEI(NON_KDETH_PACKETS
)),
673 /*14*/ FLAG_ENTRY0("TooSmallIBPacketsErr", SEEI(TOO_SMALL_IB_PACKETS
)),
674 /*15*/ FLAG_ENTRY0("TooSmallBypassPacketsErr", SEEI(TOO_SMALL_BYPASS_PACKETS
)),
675 /*16*/ FLAG_ENTRY0("PbcTestErr", SEEI(PBC_TEST
)),
676 /*17*/ FLAG_ENTRY0("BadPktLenErr", SEEI(BAD_PKT_LEN
)),
677 /*18*/ FLAG_ENTRY0("TooLongIBPacketErr", SEEI(TOO_LONG_IB_PACKET
)),
678 /*19*/ FLAG_ENTRY0("TooLongBypassPacketsErr", SEEI(TOO_LONG_BYPASS_PACKETS
)),
679 /*20*/ FLAG_ENTRY0("PbcStaticRateControlErr", SEEI(PBC_STATIC_RATE_CONTROL
)),
680 /*21*/ FLAG_ENTRY0("BypassBadPktLenErr", SEEI(BAD_PKT_LEN
)),
683 /* TXE Egress errors that cause an SPC freeze */
684 #define ALL_TXE_EGRESS_FREEZE_ERR \
685 (SEES(TX_EGRESS_FIFO_UNDERRUN_OR_PARITY) \
686 | SEES(TX_PIO_LAUNCH_INTF_PARITY) \
687 | SEES(TX_SDMA_LAUNCH_INTF_PARITY) \
688 | SEES(TX_SBRD_CTL_STATE_MACHINE_PARITY) \
689 | SEES(TX_LAUNCH_CSR_PARITY) \
690 | SEES(TX_SBRD_CTL_CSR_PARITY) \
691 | SEES(TX_CONFIG_PARITY) \
692 | SEES(TX_LAUNCH_FIFO0_UNC_OR_PARITY) \
693 | SEES(TX_LAUNCH_FIFO1_UNC_OR_PARITY) \
694 | SEES(TX_LAUNCH_FIFO2_UNC_OR_PARITY) \
695 | SEES(TX_LAUNCH_FIFO3_UNC_OR_PARITY) \
696 | SEES(TX_LAUNCH_FIFO4_UNC_OR_PARITY) \
697 | SEES(TX_LAUNCH_FIFO5_UNC_OR_PARITY) \
698 | SEES(TX_LAUNCH_FIFO6_UNC_OR_PARITY) \
699 | SEES(TX_LAUNCH_FIFO7_UNC_OR_PARITY) \
700 | SEES(TX_LAUNCH_FIFO8_UNC_OR_PARITY) \
701 | SEES(TX_CREDIT_RETURN_PARITY))
704 * TXE Send error flags
706 #define SES(name) SEND_ERR_STATUS_SEND_##name##_ERR_SMASK
707 static struct flag_table send_err_status_flags
[] = {
708 /* 0*/ FLAG_ENTRY0("SendCsrParityErr", SES(CSR_PARITY
)),
709 /* 1*/ FLAG_ENTRY0("SendCsrReadBadAddrErr", SES(CSR_READ_BAD_ADDR
)),
710 /* 2*/ FLAG_ENTRY0("SendCsrWriteBadAddrErr", SES(CSR_WRITE_BAD_ADDR
))
714 * TXE Send Context Error flags and consequences
716 static struct flag_table sc_err_status_flags
[] = {
717 /* 0*/ FLAG_ENTRY("InconsistentSop",
718 SEC_PACKET_DROPPED
| SEC_SC_HALTED
,
719 SEND_CTXT_ERR_STATUS_PIO_INCONSISTENT_SOP_ERR_SMASK
),
720 /* 1*/ FLAG_ENTRY("DisallowedPacket",
721 SEC_PACKET_DROPPED
| SEC_SC_HALTED
,
722 SEND_CTXT_ERR_STATUS_PIO_DISALLOWED_PACKET_ERR_SMASK
),
723 /* 2*/ FLAG_ENTRY("WriteCrossesBoundary",
724 SEC_WRITE_DROPPED
| SEC_SC_HALTED
,
725 SEND_CTXT_ERR_STATUS_PIO_WRITE_CROSSES_BOUNDARY_ERR_SMASK
),
726 /* 3*/ FLAG_ENTRY("WriteOverflow",
727 SEC_WRITE_DROPPED
| SEC_SC_HALTED
,
728 SEND_CTXT_ERR_STATUS_PIO_WRITE_OVERFLOW_ERR_SMASK
),
729 /* 4*/ FLAG_ENTRY("WriteOutOfBounds",
730 SEC_WRITE_DROPPED
| SEC_SC_HALTED
,
731 SEND_CTXT_ERR_STATUS_PIO_WRITE_OUT_OF_BOUNDS_ERR_SMASK
),
736 * RXE Receive Error flags
738 #define RXES(name) RCV_ERR_STATUS_RX_##name##_ERR_SMASK
739 static struct flag_table rxe_err_status_flags
[] = {
740 /* 0*/ FLAG_ENTRY0("RxDmaCsrCorErr", RXES(DMA_CSR_COR
)),
741 /* 1*/ FLAG_ENTRY0("RxDcIntfParityErr", RXES(DC_INTF_PARITY
)),
742 /* 2*/ FLAG_ENTRY0("RxRcvHdrUncErr", RXES(RCV_HDR_UNC
)),
743 /* 3*/ FLAG_ENTRY0("RxRcvHdrCorErr", RXES(RCV_HDR_COR
)),
744 /* 4*/ FLAG_ENTRY0("RxRcvDataUncErr", RXES(RCV_DATA_UNC
)),
745 /* 5*/ FLAG_ENTRY0("RxRcvDataCorErr", RXES(RCV_DATA_COR
)),
746 /* 6*/ FLAG_ENTRY0("RxRcvQpMapTableUncErr", RXES(RCV_QP_MAP_TABLE_UNC
)),
747 /* 7*/ FLAG_ENTRY0("RxRcvQpMapTableCorErr", RXES(RCV_QP_MAP_TABLE_COR
)),
748 /* 8*/ FLAG_ENTRY0("RxRcvCsrParityErr", RXES(RCV_CSR_PARITY
)),
749 /* 9*/ FLAG_ENTRY0("RxDcSopEopParityErr", RXES(DC_SOP_EOP_PARITY
)),
750 /*10*/ FLAG_ENTRY0("RxDmaFlagUncErr", RXES(DMA_FLAG_UNC
)),
751 /*11*/ FLAG_ENTRY0("RxDmaFlagCorErr", RXES(DMA_FLAG_COR
)),
752 /*12*/ FLAG_ENTRY0("RxRcvFsmEncodingErr", RXES(RCV_FSM_ENCODING
)),
753 /*13*/ FLAG_ENTRY0("RxRbufFreeListUncErr", RXES(RBUF_FREE_LIST_UNC
)),
754 /*14*/ FLAG_ENTRY0("RxRbufFreeListCorErr", RXES(RBUF_FREE_LIST_COR
)),
755 /*15*/ FLAG_ENTRY0("RxRbufLookupDesRegUncErr", RXES(RBUF_LOOKUP_DES_REG_UNC
)),
756 /*16*/ FLAG_ENTRY0("RxRbufLookupDesRegUncCorErr",
757 RXES(RBUF_LOOKUP_DES_REG_UNC_COR
)),
758 /*17*/ FLAG_ENTRY0("RxRbufLookupDesUncErr", RXES(RBUF_LOOKUP_DES_UNC
)),
759 /*18*/ FLAG_ENTRY0("RxRbufLookupDesCorErr", RXES(RBUF_LOOKUP_DES_COR
)),
760 /*19*/ FLAG_ENTRY0("RxRbufBlockListReadUncErr",
761 RXES(RBUF_BLOCK_LIST_READ_UNC
)),
762 /*20*/ FLAG_ENTRY0("RxRbufBlockListReadCorErr",
763 RXES(RBUF_BLOCK_LIST_READ_COR
)),
764 /*21*/ FLAG_ENTRY0("RxRbufCsrQHeadBufNumParityErr",
765 RXES(RBUF_CSR_QHEAD_BUF_NUM_PARITY
)),
766 /*22*/ FLAG_ENTRY0("RxRbufCsrQEntCntParityErr",
767 RXES(RBUF_CSR_QENT_CNT_PARITY
)),
768 /*23*/ FLAG_ENTRY0("RxRbufCsrQNextBufParityErr",
769 RXES(RBUF_CSR_QNEXT_BUF_PARITY
)),
770 /*24*/ FLAG_ENTRY0("RxRbufCsrQVldBitParityErr",
771 RXES(RBUF_CSR_QVLD_BIT_PARITY
)),
772 /*25*/ FLAG_ENTRY0("RxRbufCsrQHdPtrParityErr", RXES(RBUF_CSR_QHD_PTR_PARITY
)),
773 /*26*/ FLAG_ENTRY0("RxRbufCsrQTlPtrParityErr", RXES(RBUF_CSR_QTL_PTR_PARITY
)),
774 /*27*/ FLAG_ENTRY0("RxRbufCsrQNumOfPktParityErr",
775 RXES(RBUF_CSR_QNUM_OF_PKT_PARITY
)),
776 /*28*/ FLAG_ENTRY0("RxRbufCsrQEOPDWParityErr", RXES(RBUF_CSR_QEOPDW_PARITY
)),
777 /*29*/ FLAG_ENTRY0("RxRbufCtxIdParityErr", RXES(RBUF_CTX_ID_PARITY
)),
778 /*30*/ FLAG_ENTRY0("RxRBufBadLookupErr", RXES(RBUF_BAD_LOOKUP
)),
779 /*31*/ FLAG_ENTRY0("RxRbufFullErr", RXES(RBUF_FULL
)),
780 /*32*/ FLAG_ENTRY0("RxRbufEmptyErr", RXES(RBUF_EMPTY
)),
781 /*33*/ FLAG_ENTRY0("RxRbufFlRdAddrParityErr", RXES(RBUF_FL_RD_ADDR_PARITY
)),
782 /*34*/ FLAG_ENTRY0("RxRbufFlWrAddrParityErr", RXES(RBUF_FL_WR_ADDR_PARITY
)),
783 /*35*/ FLAG_ENTRY0("RxRbufFlInitdoneParityErr",
784 RXES(RBUF_FL_INITDONE_PARITY
)),
785 /*36*/ FLAG_ENTRY0("RxRbufFlInitWrAddrParityErr",
786 RXES(RBUF_FL_INIT_WR_ADDR_PARITY
)),
787 /*37*/ FLAG_ENTRY0("RxRbufNextFreeBufUncErr", RXES(RBUF_NEXT_FREE_BUF_UNC
)),
788 /*38*/ FLAG_ENTRY0("RxRbufNextFreeBufCorErr", RXES(RBUF_NEXT_FREE_BUF_COR
)),
789 /*39*/ FLAG_ENTRY0("RxLookupDesPart1UncErr", RXES(LOOKUP_DES_PART1_UNC
)),
790 /*40*/ FLAG_ENTRY0("RxLookupDesPart1UncCorErr",
791 RXES(LOOKUP_DES_PART1_UNC_COR
)),
792 /*41*/ FLAG_ENTRY0("RxLookupDesPart2ParityErr",
793 RXES(LOOKUP_DES_PART2_PARITY
)),
794 /*42*/ FLAG_ENTRY0("RxLookupRcvArrayUncErr", RXES(LOOKUP_RCV_ARRAY_UNC
)),
795 /*43*/ FLAG_ENTRY0("RxLookupRcvArrayCorErr", RXES(LOOKUP_RCV_ARRAY_COR
)),
796 /*44*/ FLAG_ENTRY0("RxLookupCsrParityErr", RXES(LOOKUP_CSR_PARITY
)),
797 /*45*/ FLAG_ENTRY0("RxHqIntrCsrParityErr", RXES(HQ_INTR_CSR_PARITY
)),
798 /*46*/ FLAG_ENTRY0("RxHqIntrFsmErr", RXES(HQ_INTR_FSM
)),
799 /*47*/ FLAG_ENTRY0("RxRbufDescPart1UncErr", RXES(RBUF_DESC_PART1_UNC
)),
800 /*48*/ FLAG_ENTRY0("RxRbufDescPart1CorErr", RXES(RBUF_DESC_PART1_COR
)),
801 /*49*/ FLAG_ENTRY0("RxRbufDescPart2UncErr", RXES(RBUF_DESC_PART2_UNC
)),
802 /*50*/ FLAG_ENTRY0("RxRbufDescPart2CorErr", RXES(RBUF_DESC_PART2_COR
)),
803 /*51*/ FLAG_ENTRY0("RxDmaHdrFifoRdUncErr", RXES(DMA_HDR_FIFO_RD_UNC
)),
804 /*52*/ FLAG_ENTRY0("RxDmaHdrFifoRdCorErr", RXES(DMA_HDR_FIFO_RD_COR
)),
805 /*53*/ FLAG_ENTRY0("RxDmaDataFifoRdUncErr", RXES(DMA_DATA_FIFO_RD_UNC
)),
806 /*54*/ FLAG_ENTRY0("RxDmaDataFifoRdCorErr", RXES(DMA_DATA_FIFO_RD_COR
)),
807 /*55*/ FLAG_ENTRY0("RxRbufDataUncErr", RXES(RBUF_DATA_UNC
)),
808 /*56*/ FLAG_ENTRY0("RxRbufDataCorErr", RXES(RBUF_DATA_COR
)),
809 /*57*/ FLAG_ENTRY0("RxDmaCsrParityErr", RXES(DMA_CSR_PARITY
)),
810 /*58*/ FLAG_ENTRY0("RxDmaEqFsmEncodingErr", RXES(DMA_EQ_FSM_ENCODING
)),
811 /*59*/ FLAG_ENTRY0("RxDmaDqFsmEncodingErr", RXES(DMA_DQ_FSM_ENCODING
)),
812 /*60*/ FLAG_ENTRY0("RxDmaCsrUncErr", RXES(DMA_CSR_UNC
)),
813 /*61*/ FLAG_ENTRY0("RxCsrReadBadAddrErr", RXES(CSR_READ_BAD_ADDR
)),
814 /*62*/ FLAG_ENTRY0("RxCsrWriteBadAddrErr", RXES(CSR_WRITE_BAD_ADDR
)),
815 /*63*/ FLAG_ENTRY0("RxCsrParityErr", RXES(CSR_PARITY
))
818 /* RXE errors that will trigger an SPC freeze */
819 #define ALL_RXE_FREEZE_ERR \
820 (RCV_ERR_STATUS_RX_RCV_QP_MAP_TABLE_UNC_ERR_SMASK \
821 | RCV_ERR_STATUS_RX_RCV_CSR_PARITY_ERR_SMASK \
822 | RCV_ERR_STATUS_RX_DMA_FLAG_UNC_ERR_SMASK \
823 | RCV_ERR_STATUS_RX_RCV_FSM_ENCODING_ERR_SMASK \
824 | RCV_ERR_STATUS_RX_RBUF_FREE_LIST_UNC_ERR_SMASK \
825 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_ERR_SMASK \
826 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_COR_ERR_SMASK \
827 | RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_UNC_ERR_SMASK \
828 | RCV_ERR_STATUS_RX_RBUF_BLOCK_LIST_READ_UNC_ERR_SMASK \
829 | RCV_ERR_STATUS_RX_RBUF_CSR_QHEAD_BUF_NUM_PARITY_ERR_SMASK \
830 | RCV_ERR_STATUS_RX_RBUF_CSR_QENT_CNT_PARITY_ERR_SMASK \
831 | RCV_ERR_STATUS_RX_RBUF_CSR_QNEXT_BUF_PARITY_ERR_SMASK \
832 | RCV_ERR_STATUS_RX_RBUF_CSR_QVLD_BIT_PARITY_ERR_SMASK \
833 | RCV_ERR_STATUS_RX_RBUF_CSR_QHD_PTR_PARITY_ERR_SMASK \
834 | RCV_ERR_STATUS_RX_RBUF_CSR_QTL_PTR_PARITY_ERR_SMASK \
835 | RCV_ERR_STATUS_RX_RBUF_CSR_QNUM_OF_PKT_PARITY_ERR_SMASK \
836 | RCV_ERR_STATUS_RX_RBUF_CSR_QEOPDW_PARITY_ERR_SMASK \
837 | RCV_ERR_STATUS_RX_RBUF_CTX_ID_PARITY_ERR_SMASK \
838 | RCV_ERR_STATUS_RX_RBUF_BAD_LOOKUP_ERR_SMASK \
839 | RCV_ERR_STATUS_RX_RBUF_FULL_ERR_SMASK \
840 | RCV_ERR_STATUS_RX_RBUF_EMPTY_ERR_SMASK \
841 | RCV_ERR_STATUS_RX_RBUF_FL_RD_ADDR_PARITY_ERR_SMASK \
842 | RCV_ERR_STATUS_RX_RBUF_FL_WR_ADDR_PARITY_ERR_SMASK \
843 | RCV_ERR_STATUS_RX_RBUF_FL_INITDONE_PARITY_ERR_SMASK \
844 | RCV_ERR_STATUS_RX_RBUF_FL_INIT_WR_ADDR_PARITY_ERR_SMASK \
845 | RCV_ERR_STATUS_RX_RBUF_NEXT_FREE_BUF_UNC_ERR_SMASK \
846 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_ERR_SMASK \
847 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_COR_ERR_SMASK \
848 | RCV_ERR_STATUS_RX_LOOKUP_DES_PART2_PARITY_ERR_SMASK \
849 | RCV_ERR_STATUS_RX_LOOKUP_RCV_ARRAY_UNC_ERR_SMASK \
850 | RCV_ERR_STATUS_RX_LOOKUP_CSR_PARITY_ERR_SMASK \
851 | RCV_ERR_STATUS_RX_HQ_INTR_CSR_PARITY_ERR_SMASK \
852 | RCV_ERR_STATUS_RX_HQ_INTR_FSM_ERR_SMASK \
853 | RCV_ERR_STATUS_RX_RBUF_DESC_PART1_UNC_ERR_SMASK \
854 | RCV_ERR_STATUS_RX_RBUF_DESC_PART1_COR_ERR_SMASK \
855 | RCV_ERR_STATUS_RX_RBUF_DESC_PART2_UNC_ERR_SMASK \
856 | RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_UNC_ERR_SMASK \
857 | RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_UNC_ERR_SMASK \
858 | RCV_ERR_STATUS_RX_RBUF_DATA_UNC_ERR_SMASK \
859 | RCV_ERR_STATUS_RX_DMA_CSR_PARITY_ERR_SMASK \
860 | RCV_ERR_STATUS_RX_DMA_EQ_FSM_ENCODING_ERR_SMASK \
861 | RCV_ERR_STATUS_RX_DMA_DQ_FSM_ENCODING_ERR_SMASK \
862 | RCV_ERR_STATUS_RX_DMA_CSR_UNC_ERR_SMASK \
863 | RCV_ERR_STATUS_RX_CSR_PARITY_ERR_SMASK)
865 #define RXE_FREEZE_ABORT_MASK \
866 (RCV_ERR_STATUS_RX_DMA_CSR_UNC_ERR_SMASK | \
867 RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_UNC_ERR_SMASK | \
868 RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_UNC_ERR_SMASK)
873 #define DCCE(name) DCC_ERR_FLG_##name##_SMASK
874 static struct flag_table dcc_err_flags
[] = {
875 FLAG_ENTRY0("bad_l2_err", DCCE(BAD_L2_ERR
)),
876 FLAG_ENTRY0("bad_sc_err", DCCE(BAD_SC_ERR
)),
877 FLAG_ENTRY0("bad_mid_tail_err", DCCE(BAD_MID_TAIL_ERR
)),
878 FLAG_ENTRY0("bad_preemption_err", DCCE(BAD_PREEMPTION_ERR
)),
879 FLAG_ENTRY0("preemption_err", DCCE(PREEMPTION_ERR
)),
880 FLAG_ENTRY0("preemptionvl15_err", DCCE(PREEMPTIONVL15_ERR
)),
881 FLAG_ENTRY0("bad_vl_marker_err", DCCE(BAD_VL_MARKER_ERR
)),
882 FLAG_ENTRY0("bad_dlid_target_err", DCCE(BAD_DLID_TARGET_ERR
)),
883 FLAG_ENTRY0("bad_lver_err", DCCE(BAD_LVER_ERR
)),
884 FLAG_ENTRY0("uncorrectable_err", DCCE(UNCORRECTABLE_ERR
)),
885 FLAG_ENTRY0("bad_crdt_ack_err", DCCE(BAD_CRDT_ACK_ERR
)),
886 FLAG_ENTRY0("unsup_pkt_type", DCCE(UNSUP_PKT_TYPE
)),
887 FLAG_ENTRY0("bad_ctrl_flit_err", DCCE(BAD_CTRL_FLIT_ERR
)),
888 FLAG_ENTRY0("event_cntr_parity_err", DCCE(EVENT_CNTR_PARITY_ERR
)),
889 FLAG_ENTRY0("event_cntr_rollover_err", DCCE(EVENT_CNTR_ROLLOVER_ERR
)),
890 FLAG_ENTRY0("link_err", DCCE(LINK_ERR
)),
891 FLAG_ENTRY0("misc_cntr_rollover_err", DCCE(MISC_CNTR_ROLLOVER_ERR
)),
892 FLAG_ENTRY0("bad_ctrl_dist_err", DCCE(BAD_CTRL_DIST_ERR
)),
893 FLAG_ENTRY0("bad_tail_dist_err", DCCE(BAD_TAIL_DIST_ERR
)),
894 FLAG_ENTRY0("bad_head_dist_err", DCCE(BAD_HEAD_DIST_ERR
)),
895 FLAG_ENTRY0("nonvl15_state_err", DCCE(NONVL15_STATE_ERR
)),
896 FLAG_ENTRY0("vl15_multi_err", DCCE(VL15_MULTI_ERR
)),
897 FLAG_ENTRY0("bad_pkt_length_err", DCCE(BAD_PKT_LENGTH_ERR
)),
898 FLAG_ENTRY0("unsup_vl_err", DCCE(UNSUP_VL_ERR
)),
899 FLAG_ENTRY0("perm_nvl15_err", DCCE(PERM_NVL15_ERR
)),
900 FLAG_ENTRY0("slid_zero_err", DCCE(SLID_ZERO_ERR
)),
901 FLAG_ENTRY0("dlid_zero_err", DCCE(DLID_ZERO_ERR
)),
902 FLAG_ENTRY0("length_mtu_err", DCCE(LENGTH_MTU_ERR
)),
903 FLAG_ENTRY0("rx_early_drop_err", DCCE(RX_EARLY_DROP_ERR
)),
904 FLAG_ENTRY0("late_short_err", DCCE(LATE_SHORT_ERR
)),
905 FLAG_ENTRY0("late_long_err", DCCE(LATE_LONG_ERR
)),
906 FLAG_ENTRY0("late_ebp_err", DCCE(LATE_EBP_ERR
)),
907 FLAG_ENTRY0("fpe_tx_fifo_ovflw_err", DCCE(FPE_TX_FIFO_OVFLW_ERR
)),
908 FLAG_ENTRY0("fpe_tx_fifo_unflw_err", DCCE(FPE_TX_FIFO_UNFLW_ERR
)),
909 FLAG_ENTRY0("csr_access_blocked_host", DCCE(CSR_ACCESS_BLOCKED_HOST
)),
910 FLAG_ENTRY0("csr_access_blocked_uc", DCCE(CSR_ACCESS_BLOCKED_UC
)),
911 FLAG_ENTRY0("tx_ctrl_parity_err", DCCE(TX_CTRL_PARITY_ERR
)),
912 FLAG_ENTRY0("tx_ctrl_parity_mbe_err", DCCE(TX_CTRL_PARITY_MBE_ERR
)),
913 FLAG_ENTRY0("tx_sc_parity_err", DCCE(TX_SC_PARITY_ERR
)),
914 FLAG_ENTRY0("rx_ctrl_parity_mbe_err", DCCE(RX_CTRL_PARITY_MBE_ERR
)),
915 FLAG_ENTRY0("csr_parity_err", DCCE(CSR_PARITY_ERR
)),
916 FLAG_ENTRY0("csr_inval_addr", DCCE(CSR_INVAL_ADDR
)),
917 FLAG_ENTRY0("tx_byte_shft_parity_err", DCCE(TX_BYTE_SHFT_PARITY_ERR
)),
918 FLAG_ENTRY0("rx_byte_shft_parity_err", DCCE(RX_BYTE_SHFT_PARITY_ERR
)),
919 FLAG_ENTRY0("fmconfig_err", DCCE(FMCONFIG_ERR
)),
920 FLAG_ENTRY0("rcvport_err", DCCE(RCVPORT_ERR
)),
926 #define LCBE(name) DC_LCB_ERR_FLG_##name##_SMASK
927 static struct flag_table lcb_err_flags
[] = {
928 /* 0*/ FLAG_ENTRY0("CSR_PARITY_ERR", LCBE(CSR_PARITY_ERR
)),
929 /* 1*/ FLAG_ENTRY0("INVALID_CSR_ADDR", LCBE(INVALID_CSR_ADDR
)),
930 /* 2*/ FLAG_ENTRY0("RST_FOR_FAILED_DESKEW", LCBE(RST_FOR_FAILED_DESKEW
)),
931 /* 3*/ FLAG_ENTRY0("ALL_LNS_FAILED_REINIT_TEST",
932 LCBE(ALL_LNS_FAILED_REINIT_TEST
)),
933 /* 4*/ FLAG_ENTRY0("LOST_REINIT_STALL_OR_TOS", LCBE(LOST_REINIT_STALL_OR_TOS
)),
934 /* 5*/ FLAG_ENTRY0("TX_LESS_THAN_FOUR_LNS", LCBE(TX_LESS_THAN_FOUR_LNS
)),
935 /* 6*/ FLAG_ENTRY0("RX_LESS_THAN_FOUR_LNS", LCBE(RX_LESS_THAN_FOUR_LNS
)),
936 /* 7*/ FLAG_ENTRY0("SEQ_CRC_ERR", LCBE(SEQ_CRC_ERR
)),
937 /* 8*/ FLAG_ENTRY0("REINIT_FROM_PEER", LCBE(REINIT_FROM_PEER
)),
938 /* 9*/ FLAG_ENTRY0("REINIT_FOR_LN_DEGRADE", LCBE(REINIT_FOR_LN_DEGRADE
)),
939 /*10*/ FLAG_ENTRY0("CRC_ERR_CNT_HIT_LIMIT", LCBE(CRC_ERR_CNT_HIT_LIMIT
)),
940 /*11*/ FLAG_ENTRY0("RCLK_STOPPED", LCBE(RCLK_STOPPED
)),
941 /*12*/ FLAG_ENTRY0("UNEXPECTED_REPLAY_MARKER", LCBE(UNEXPECTED_REPLAY_MARKER
)),
942 /*13*/ FLAG_ENTRY0("UNEXPECTED_ROUND_TRIP_MARKER",
943 LCBE(UNEXPECTED_ROUND_TRIP_MARKER
)),
944 /*14*/ FLAG_ENTRY0("ILLEGAL_NULL_LTP", LCBE(ILLEGAL_NULL_LTP
)),
945 /*15*/ FLAG_ENTRY0("ILLEGAL_FLIT_ENCODING", LCBE(ILLEGAL_FLIT_ENCODING
)),
946 /*16*/ FLAG_ENTRY0("FLIT_INPUT_BUF_OFLW", LCBE(FLIT_INPUT_BUF_OFLW
)),
947 /*17*/ FLAG_ENTRY0("VL_ACK_INPUT_BUF_OFLW", LCBE(VL_ACK_INPUT_BUF_OFLW
)),
948 /*18*/ FLAG_ENTRY0("VL_ACK_INPUT_PARITY_ERR", LCBE(VL_ACK_INPUT_PARITY_ERR
)),
949 /*19*/ FLAG_ENTRY0("VL_ACK_INPUT_WRONG_CRC_MODE",
950 LCBE(VL_ACK_INPUT_WRONG_CRC_MODE
)),
951 /*20*/ FLAG_ENTRY0("FLIT_INPUT_BUF_MBE", LCBE(FLIT_INPUT_BUF_MBE
)),
952 /*21*/ FLAG_ENTRY0("FLIT_INPUT_BUF_SBE", LCBE(FLIT_INPUT_BUF_SBE
)),
953 /*22*/ FLAG_ENTRY0("REPLAY_BUF_MBE", LCBE(REPLAY_BUF_MBE
)),
954 /*23*/ FLAG_ENTRY0("REPLAY_BUF_SBE", LCBE(REPLAY_BUF_SBE
)),
955 /*24*/ FLAG_ENTRY0("CREDIT_RETURN_FLIT_MBE", LCBE(CREDIT_RETURN_FLIT_MBE
)),
956 /*25*/ FLAG_ENTRY0("RST_FOR_LINK_TIMEOUT", LCBE(RST_FOR_LINK_TIMEOUT
)),
957 /*26*/ FLAG_ENTRY0("RST_FOR_INCOMPLT_RND_TRIP",
958 LCBE(RST_FOR_INCOMPLT_RND_TRIP
)),
959 /*27*/ FLAG_ENTRY0("HOLD_REINIT", LCBE(HOLD_REINIT
)),
960 /*28*/ FLAG_ENTRY0("NEG_EDGE_LINK_TRANSFER_ACTIVE",
961 LCBE(NEG_EDGE_LINK_TRANSFER_ACTIVE
)),
962 /*29*/ FLAG_ENTRY0("REDUNDANT_FLIT_PARITY_ERR",
963 LCBE(REDUNDANT_FLIT_PARITY_ERR
))
969 #define D8E(name) DC_DC8051_ERR_FLG_##name##_SMASK
970 static struct flag_table dc8051_err_flags
[] = {
971 FLAG_ENTRY0("SET_BY_8051", D8E(SET_BY_8051
)),
972 FLAG_ENTRY0("LOST_8051_HEART_BEAT", D8E(LOST_8051_HEART_BEAT
)),
973 FLAG_ENTRY0("CRAM_MBE", D8E(CRAM_MBE
)),
974 FLAG_ENTRY0("CRAM_SBE", D8E(CRAM_SBE
)),
975 FLAG_ENTRY0("DRAM_MBE", D8E(DRAM_MBE
)),
976 FLAG_ENTRY0("DRAM_SBE", D8E(DRAM_SBE
)),
977 FLAG_ENTRY0("IRAM_MBE", D8E(IRAM_MBE
)),
978 FLAG_ENTRY0("IRAM_SBE", D8E(IRAM_SBE
)),
979 FLAG_ENTRY0("UNMATCHED_SECURE_MSG_ACROSS_BCC_LANES",
980 D8E(UNMATCHED_SECURE_MSG_ACROSS_BCC_LANES
)),
981 FLAG_ENTRY0("INVALID_CSR_ADDR", D8E(INVALID_CSR_ADDR
)),
985 * DC8051 Information Error flags
987 * Flags in DC8051_DBG_ERR_INFO_SET_BY_8051.ERROR field.
989 static struct flag_table dc8051_info_err_flags
[] = {
990 FLAG_ENTRY0("Spico ROM check failed", SPICO_ROM_FAILED
),
991 FLAG_ENTRY0("Unknown frame received", UNKNOWN_FRAME
),
992 FLAG_ENTRY0("Target BER not met", TARGET_BER_NOT_MET
),
993 FLAG_ENTRY0("Serdes internal loopback failure",
994 FAILED_SERDES_INTERNAL_LOOPBACK
),
995 FLAG_ENTRY0("Failed SerDes init", FAILED_SERDES_INIT
),
996 FLAG_ENTRY0("Failed LNI(Polling)", FAILED_LNI_POLLING
),
997 FLAG_ENTRY0("Failed LNI(Debounce)", FAILED_LNI_DEBOUNCE
),
998 FLAG_ENTRY0("Failed LNI(EstbComm)", FAILED_LNI_ESTBCOMM
),
999 FLAG_ENTRY0("Failed LNI(OptEq)", FAILED_LNI_OPTEQ
),
1000 FLAG_ENTRY0("Failed LNI(VerifyCap_1)", FAILED_LNI_VERIFY_CAP1
),
1001 FLAG_ENTRY0("Failed LNI(VerifyCap_2)", FAILED_LNI_VERIFY_CAP2
),
1002 FLAG_ENTRY0("Failed LNI(ConfigLT)", FAILED_LNI_CONFIGLT
),
1003 FLAG_ENTRY0("Host Handshake Timeout", HOST_HANDSHAKE_TIMEOUT
),
1004 FLAG_ENTRY0("External Device Request Timeout",
1005 EXTERNAL_DEVICE_REQ_TIMEOUT
),
1009 * DC8051 Information Host Information flags
1011 * Flags in DC8051_DBG_ERR_INFO_SET_BY_8051.HOST_MSG field.
1013 static struct flag_table dc8051_info_host_msg_flags
[] = {
1014 FLAG_ENTRY0("Host request done", 0x0001),
1015 FLAG_ENTRY0("BC SMA message", 0x0002),
1016 FLAG_ENTRY0("BC PWR_MGM message", 0x0004),
1017 FLAG_ENTRY0("BC Unknown message (BCC)", 0x0008),
1018 FLAG_ENTRY0("BC Unknown message (LCB)", 0x0010),
1019 FLAG_ENTRY0("External device config request", 0x0020),
1020 FLAG_ENTRY0("VerifyCap all frames received", 0x0040),
1021 FLAG_ENTRY0("LinkUp achieved", 0x0080),
1022 FLAG_ENTRY0("Link going down", 0x0100),
1025 static u32
encoded_size(u32 size
);
1026 static u32
chip_to_opa_lstate(struct hfi1_devdata
*dd
, u32 chip_lstate
);
1027 static int set_physical_link_state(struct hfi1_devdata
*dd
, u64 state
);
1028 static void read_vc_remote_phy(struct hfi1_devdata
*dd
, u8
*power_management
,
1030 static void read_vc_remote_fabric(struct hfi1_devdata
*dd
, u8
*vau
, u8
*z
,
1031 u8
*vcu
, u16
*vl15buf
, u8
*crc_sizes
);
1032 static void read_vc_remote_link_width(struct hfi1_devdata
*dd
,
1033 u8
*remote_tx_rate
, u16
*link_widths
);
1034 static void read_vc_local_link_width(struct hfi1_devdata
*dd
, u8
*misc_bits
,
1035 u8
*flag_bits
, u16
*link_widths
);
1036 static void read_remote_device_id(struct hfi1_devdata
*dd
, u16
*device_id
,
1038 static void read_mgmt_allowed(struct hfi1_devdata
*dd
, u8
*mgmt_allowed
);
1039 static void read_local_lni(struct hfi1_devdata
*dd
, u8
*enable_lane_rx
);
1040 static int read_tx_settings(struct hfi1_devdata
*dd
, u8
*enable_lane_tx
,
1041 u8
*tx_polarity_inversion
,
1042 u8
*rx_polarity_inversion
, u8
*max_rate
);
1043 static void handle_sdma_eng_err(struct hfi1_devdata
*dd
,
1044 unsigned int context
, u64 err_status
);
1045 static void handle_qsfp_int(struct hfi1_devdata
*dd
, u32 source
, u64 reg
);
1046 static void handle_dcc_err(struct hfi1_devdata
*dd
,
1047 unsigned int context
, u64 err_status
);
1048 static void handle_lcb_err(struct hfi1_devdata
*dd
,
1049 unsigned int context
, u64 err_status
);
1050 static void handle_8051_interrupt(struct hfi1_devdata
*dd
, u32 unused
, u64 reg
);
1051 static void handle_cce_err(struct hfi1_devdata
*dd
, u32 unused
, u64 reg
);
1052 static void handle_rxe_err(struct hfi1_devdata
*dd
, u32 unused
, u64 reg
);
1053 static void handle_misc_err(struct hfi1_devdata
*dd
, u32 unused
, u64 reg
);
1054 static void handle_pio_err(struct hfi1_devdata
*dd
, u32 unused
, u64 reg
);
1055 static void handle_sdma_err(struct hfi1_devdata
*dd
, u32 unused
, u64 reg
);
1056 static void handle_egress_err(struct hfi1_devdata
*dd
, u32 unused
, u64 reg
);
1057 static void handle_txe_err(struct hfi1_devdata
*dd
, u32 unused
, u64 reg
);
1058 static void set_partition_keys(struct hfi1_pportdata
*ppd
);
1059 static const char *link_state_name(u32 state
);
1060 static const char *link_state_reason_name(struct hfi1_pportdata
*ppd
,
1062 static int do_8051_command(struct hfi1_devdata
*dd
, u32 type
, u64 in_data
,
1064 static int read_idle_sma(struct hfi1_devdata
*dd
, u64
*data
);
1065 static int thermal_init(struct hfi1_devdata
*dd
);
1067 static int wait_logical_linkstate(struct hfi1_pportdata
*ppd
, u32 state
,
1069 static void read_planned_down_reason_code(struct hfi1_devdata
*dd
, u8
*pdrrc
);
1070 static void read_link_down_reason(struct hfi1_devdata
*dd
, u8
*ldr
);
1071 static void handle_temp_err(struct hfi1_devdata
*dd
);
1072 static void dc_shutdown(struct hfi1_devdata
*dd
);
1073 static void dc_start(struct hfi1_devdata
*dd
);
1074 static int qos_rmt_entries(struct hfi1_devdata
*dd
, unsigned int *mp
,
1076 static void clear_full_mgmt_pkey(struct hfi1_pportdata
*ppd
);
1077 static int wait_link_transfer_active(struct hfi1_devdata
*dd
, int wait_ms
);
1078 static void clear_rsm_rule(struct hfi1_devdata
*dd
, u8 rule_index
);
1081 * Error interrupt table entry. This is used as input to the interrupt
1082 * "clear down" routine used for all second tier error interrupt register.
1083 * Second tier interrupt registers have a single bit representing them
1084 * in the top-level CceIntStatus.
1086 struct err_reg_info
{
1087 u32 status
; /* status CSR offset */
1088 u32 clear
; /* clear CSR offset */
1089 u32 mask
; /* mask CSR offset */
1090 void (*handler
)(struct hfi1_devdata
*dd
, u32 source
, u64 reg
);
1094 #define NUM_MISC_ERRS (IS_GENERAL_ERR_END - IS_GENERAL_ERR_START)
1095 #define NUM_DC_ERRS (IS_DC_END - IS_DC_START)
1096 #define NUM_VARIOUS (IS_VARIOUS_END - IS_VARIOUS_START)
1099 * Helpers for building HFI and DC error interrupt table entries. Different
1100 * helpers are needed because of inconsistent register names.
1102 #define EE(reg, handler, desc) \
1103 { reg##_STATUS, reg##_CLEAR, reg##_MASK, \
1105 #define DC_EE1(reg, handler, desc) \
1106 { reg##_FLG, reg##_FLG_CLR, reg##_FLG_EN, handler, desc }
1107 #define DC_EE2(reg, handler, desc) \
1108 { reg##_FLG, reg##_CLR, reg##_EN, handler, desc }
1111 * Table of the "misc" grouping of error interrupts. Each entry refers to
1112 * another register containing more information.
1114 static const struct err_reg_info misc_errs
[NUM_MISC_ERRS
] = {
1115 /* 0*/ EE(CCE_ERR
, handle_cce_err
, "CceErr"),
1116 /* 1*/ EE(RCV_ERR
, handle_rxe_err
, "RxeErr"),
1117 /* 2*/ EE(MISC_ERR
, handle_misc_err
, "MiscErr"),
1118 /* 3*/ { 0, 0, 0, NULL
}, /* reserved */
1119 /* 4*/ EE(SEND_PIO_ERR
, handle_pio_err
, "PioErr"),
1120 /* 5*/ EE(SEND_DMA_ERR
, handle_sdma_err
, "SDmaErr"),
1121 /* 6*/ EE(SEND_EGRESS_ERR
, handle_egress_err
, "EgressErr"),
1122 /* 7*/ EE(SEND_ERR
, handle_txe_err
, "TxeErr")
1123 /* the rest are reserved */
1127 * Index into the Various section of the interrupt sources
1128 * corresponding to the Critical Temperature interrupt.
1130 #define TCRIT_INT_SOURCE 4
1133 * SDMA error interrupt entry - refers to another register containing more
1136 static const struct err_reg_info sdma_eng_err
=
1137 EE(SEND_DMA_ENG_ERR
, handle_sdma_eng_err
, "SDmaEngErr");
1139 static const struct err_reg_info various_err
[NUM_VARIOUS
] = {
1140 /* 0*/ { 0, 0, 0, NULL
}, /* PbcInt */
1141 /* 1*/ { 0, 0, 0, NULL
}, /* GpioAssertInt */
1142 /* 2*/ EE(ASIC_QSFP1
, handle_qsfp_int
, "QSFP1"),
1143 /* 3*/ EE(ASIC_QSFP2
, handle_qsfp_int
, "QSFP2"),
1144 /* 4*/ { 0, 0, 0, NULL
}, /* TCritInt */
1145 /* rest are reserved */
1149 * The DC encoding of mtu_cap for 10K MTU in the DCC_CFG_PORT_CONFIG
1150 * register can not be derived from the MTU value because 10K is not
1151 * a power of 2. Therefore, we need a constant. Everything else can
1154 #define DCC_CFG_PORT_MTU_CAP_10240 7
1157 * Table of the DC grouping of error interrupts. Each entry refers to
1158 * another register containing more information.
1160 static const struct err_reg_info dc_errs
[NUM_DC_ERRS
] = {
1161 /* 0*/ DC_EE1(DCC_ERR
, handle_dcc_err
, "DCC Err"),
1162 /* 1*/ DC_EE2(DC_LCB_ERR
, handle_lcb_err
, "LCB Err"),
1163 /* 2*/ DC_EE2(DC_DC8051_ERR
, handle_8051_interrupt
, "DC8051 Interrupt"),
1164 /* 3*/ /* dc_lbm_int - special, see is_dc_int() */
1165 /* the rest are reserved */
1175 * csr to read for name (if applicable)
1180 * offset into dd or ppd to store the counter's value
1190 * accessor for stat element, context either dd or ppd
1192 u64 (*rw_cntr
)(const struct cntr_entry
*, void *context
, int vl
,
1193 int mode
, u64 data
);
1196 #define C_RCV_HDR_OVF_FIRST C_RCV_HDR_OVF_0
1197 #define C_RCV_HDR_OVF_LAST C_RCV_HDR_OVF_159
1199 #define CNTR_ELEM(name, csr, offset, flags, accessor) \
1209 #define RXE32_PORT_CNTR_ELEM(name, counter, flags) \
1211 (counter * 8 + RCV_COUNTER_ARRAY32), \
1212 0, flags | CNTR_32BIT, \
1213 port_access_u32_csr)
1215 #define RXE32_DEV_CNTR_ELEM(name, counter, flags) \
1217 (counter * 8 + RCV_COUNTER_ARRAY32), \
1218 0, flags | CNTR_32BIT, \
1222 #define RXE64_PORT_CNTR_ELEM(name, counter, flags) \
1224 (counter * 8 + RCV_COUNTER_ARRAY64), \
1226 port_access_u64_csr)
1228 #define RXE64_DEV_CNTR_ELEM(name, counter, flags) \
1230 (counter * 8 + RCV_COUNTER_ARRAY64), \
1234 #define OVR_LBL(ctx) C_RCV_HDR_OVF_ ## ctx
1235 #define OVR_ELM(ctx) \
1236 CNTR_ELEM("RcvHdrOvr" #ctx, \
1237 (RCV_HDR_OVFL_CNT + ctx * 0x100), \
1238 0, CNTR_NORMAL, port_access_u64_csr)
1241 #define TXE32_PORT_CNTR_ELEM(name, counter, flags) \
1243 (counter * 8 + SEND_COUNTER_ARRAY32), \
1244 0, flags | CNTR_32BIT, \
1245 port_access_u32_csr)
1248 #define TXE64_PORT_CNTR_ELEM(name, counter, flags) \
1250 (counter * 8 + SEND_COUNTER_ARRAY64), \
1252 port_access_u64_csr)
1254 # define TX64_DEV_CNTR_ELEM(name, counter, flags) \
1256 counter * 8 + SEND_COUNTER_ARRAY64, \
1262 #define CCE_PERF_DEV_CNTR_ELEM(name, counter, flags) \
1264 (counter * 8 + CCE_COUNTER_ARRAY32), \
1265 0, flags | CNTR_32BIT, \
1268 #define CCE_INT_DEV_CNTR_ELEM(name, counter, flags) \
1270 (counter * 8 + CCE_INT_COUNTER_ARRAY32), \
1271 0, flags | CNTR_32BIT, \
1275 #define DC_PERF_CNTR(name, counter, flags) \
1282 #define DC_PERF_CNTR_LCB(name, counter, flags) \
1290 #define SW_IBP_CNTR(name, cntr) \
1297 u64
read_csr(const struct hfi1_devdata
*dd
, u32 offset
)
1299 if (dd
->flags
& HFI1_PRESENT
) {
1300 return readq((void __iomem
*)dd
->kregbase
+ offset
);
1305 void write_csr(const struct hfi1_devdata
*dd
, u32 offset
, u64 value
)
1307 if (dd
->flags
& HFI1_PRESENT
)
1308 writeq(value
, (void __iomem
*)dd
->kregbase
+ offset
);
1311 void __iomem
*get_csr_addr(
1312 struct hfi1_devdata
*dd
,
1315 return (void __iomem
*)dd
->kregbase
+ offset
;
1318 static inline u64
read_write_csr(const struct hfi1_devdata
*dd
, u32 csr
,
1319 int mode
, u64 value
)
1323 if (mode
== CNTR_MODE_R
) {
1324 ret
= read_csr(dd
, csr
);
1325 } else if (mode
== CNTR_MODE_W
) {
1326 write_csr(dd
, csr
, value
);
1329 dd_dev_err(dd
, "Invalid cntr register access mode");
1333 hfi1_cdbg(CNTR
, "csr 0x%x val 0x%llx mode %d", csr
, ret
, mode
);
1338 static u64
dev_access_u32_csr(const struct cntr_entry
*entry
,
1339 void *context
, int vl
, int mode
, u64 data
)
1341 struct hfi1_devdata
*dd
= context
;
1342 u64 csr
= entry
->csr
;
1344 if (entry
->flags
& CNTR_SDMA
) {
1345 if (vl
== CNTR_INVALID_VL
)
1349 if (vl
!= CNTR_INVALID_VL
)
1352 return read_write_csr(dd
, csr
, mode
, data
);
1355 static u64
access_sde_err_cnt(const struct cntr_entry
*entry
,
1356 void *context
, int idx
, int mode
, u64 data
)
1358 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
1360 if (dd
->per_sdma
&& idx
< dd
->num_sdma
)
1361 return dd
->per_sdma
[idx
].err_cnt
;
1365 static u64
access_sde_int_cnt(const struct cntr_entry
*entry
,
1366 void *context
, int idx
, int mode
, u64 data
)
1368 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
1370 if (dd
->per_sdma
&& idx
< dd
->num_sdma
)
1371 return dd
->per_sdma
[idx
].sdma_int_cnt
;
1375 static u64
access_sde_idle_int_cnt(const struct cntr_entry
*entry
,
1376 void *context
, int idx
, int mode
, u64 data
)
1378 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
1380 if (dd
->per_sdma
&& idx
< dd
->num_sdma
)
1381 return dd
->per_sdma
[idx
].idle_int_cnt
;
1385 static u64
access_sde_progress_int_cnt(const struct cntr_entry
*entry
,
1386 void *context
, int idx
, int mode
,
1389 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
1391 if (dd
->per_sdma
&& idx
< dd
->num_sdma
)
1392 return dd
->per_sdma
[idx
].progress_int_cnt
;
1396 static u64
dev_access_u64_csr(const struct cntr_entry
*entry
, void *context
,
1397 int vl
, int mode
, u64 data
)
1399 struct hfi1_devdata
*dd
= context
;
1402 u64 csr
= entry
->csr
;
1404 if (entry
->flags
& CNTR_VL
) {
1405 if (vl
== CNTR_INVALID_VL
)
1409 if (vl
!= CNTR_INVALID_VL
)
1413 val
= read_write_csr(dd
, csr
, mode
, data
);
1417 static u64
dc_access_lcb_cntr(const struct cntr_entry
*entry
, void *context
,
1418 int vl
, int mode
, u64 data
)
1420 struct hfi1_devdata
*dd
= context
;
1421 u32 csr
= entry
->csr
;
1424 if (vl
!= CNTR_INVALID_VL
)
1426 if (mode
== CNTR_MODE_R
)
1427 ret
= read_lcb_csr(dd
, csr
, &data
);
1428 else if (mode
== CNTR_MODE_W
)
1429 ret
= write_lcb_csr(dd
, csr
, data
);
1432 dd_dev_err(dd
, "Could not acquire LCB for counter 0x%x", csr
);
1436 hfi1_cdbg(CNTR
, "csr 0x%x val 0x%llx mode %d", csr
, data
, mode
);
1441 static u64
port_access_u32_csr(const struct cntr_entry
*entry
, void *context
,
1442 int vl
, int mode
, u64 data
)
1444 struct hfi1_pportdata
*ppd
= context
;
1446 if (vl
!= CNTR_INVALID_VL
)
1448 return read_write_csr(ppd
->dd
, entry
->csr
, mode
, data
);
1451 static u64
port_access_u64_csr(const struct cntr_entry
*entry
,
1452 void *context
, int vl
, int mode
, u64 data
)
1454 struct hfi1_pportdata
*ppd
= context
;
1456 u64 csr
= entry
->csr
;
1458 if (entry
->flags
& CNTR_VL
) {
1459 if (vl
== CNTR_INVALID_VL
)
1463 if (vl
!= CNTR_INVALID_VL
)
1466 val
= read_write_csr(ppd
->dd
, csr
, mode
, data
);
1470 /* Software defined */
1471 static inline u64
read_write_sw(struct hfi1_devdata
*dd
, u64
*cntr
, int mode
,
1476 if (mode
== CNTR_MODE_R
) {
1478 } else if (mode
== CNTR_MODE_W
) {
1482 dd_dev_err(dd
, "Invalid cntr sw access mode");
1486 hfi1_cdbg(CNTR
, "val 0x%llx mode %d", ret
, mode
);
1491 static u64
access_sw_link_dn_cnt(const struct cntr_entry
*entry
, void *context
,
1492 int vl
, int mode
, u64 data
)
1494 struct hfi1_pportdata
*ppd
= context
;
1496 if (vl
!= CNTR_INVALID_VL
)
1498 return read_write_sw(ppd
->dd
, &ppd
->link_downed
, mode
, data
);
1501 static u64
access_sw_link_up_cnt(const struct cntr_entry
*entry
, void *context
,
1502 int vl
, int mode
, u64 data
)
1504 struct hfi1_pportdata
*ppd
= context
;
1506 if (vl
!= CNTR_INVALID_VL
)
1508 return read_write_sw(ppd
->dd
, &ppd
->link_up
, mode
, data
);
1511 static u64
access_sw_unknown_frame_cnt(const struct cntr_entry
*entry
,
1512 void *context
, int vl
, int mode
,
1515 struct hfi1_pportdata
*ppd
= (struct hfi1_pportdata
*)context
;
1517 if (vl
!= CNTR_INVALID_VL
)
1519 return read_write_sw(ppd
->dd
, &ppd
->unknown_frame_count
, mode
, data
);
1522 static u64
access_sw_xmit_discards(const struct cntr_entry
*entry
,
1523 void *context
, int vl
, int mode
, u64 data
)
1525 struct hfi1_pportdata
*ppd
= (struct hfi1_pportdata
*)context
;
1529 if (vl
== CNTR_INVALID_VL
)
1530 counter
= &ppd
->port_xmit_discards
;
1531 else if (vl
>= 0 && vl
< C_VL_COUNT
)
1532 counter
= &ppd
->port_xmit_discards_vl
[vl
];
1536 return read_write_sw(ppd
->dd
, counter
, mode
, data
);
1539 static u64
access_xmit_constraint_errs(const struct cntr_entry
*entry
,
1540 void *context
, int vl
, int mode
,
1543 struct hfi1_pportdata
*ppd
= context
;
1545 if (vl
!= CNTR_INVALID_VL
)
1548 return read_write_sw(ppd
->dd
, &ppd
->port_xmit_constraint_errors
,
1552 static u64
access_rcv_constraint_errs(const struct cntr_entry
*entry
,
1553 void *context
, int vl
, int mode
, u64 data
)
1555 struct hfi1_pportdata
*ppd
= context
;
1557 if (vl
!= CNTR_INVALID_VL
)
1560 return read_write_sw(ppd
->dd
, &ppd
->port_rcv_constraint_errors
,
1564 u64
get_all_cpu_total(u64 __percpu
*cntr
)
1569 for_each_possible_cpu(cpu
)
1570 counter
+= *per_cpu_ptr(cntr
, cpu
);
1574 static u64
read_write_cpu(struct hfi1_devdata
*dd
, u64
*z_val
,
1576 int vl
, int mode
, u64 data
)
1580 if (vl
!= CNTR_INVALID_VL
)
1583 if (mode
== CNTR_MODE_R
) {
1584 ret
= get_all_cpu_total(cntr
) - *z_val
;
1585 } else if (mode
== CNTR_MODE_W
) {
1586 /* A write can only zero the counter */
1588 *z_val
= get_all_cpu_total(cntr
);
1590 dd_dev_err(dd
, "Per CPU cntrs can only be zeroed");
1592 dd_dev_err(dd
, "Invalid cntr sw cpu access mode");
1599 static u64
access_sw_cpu_intr(const struct cntr_entry
*entry
,
1600 void *context
, int vl
, int mode
, u64 data
)
1602 struct hfi1_devdata
*dd
= context
;
1604 return read_write_cpu(dd
, &dd
->z_int_counter
, dd
->int_counter
, vl
,
1608 static u64
access_sw_cpu_rcv_limit(const struct cntr_entry
*entry
,
1609 void *context
, int vl
, int mode
, u64 data
)
1611 struct hfi1_devdata
*dd
= context
;
1613 return read_write_cpu(dd
, &dd
->z_rcv_limit
, dd
->rcv_limit
, vl
,
1617 static u64
access_sw_pio_wait(const struct cntr_entry
*entry
,
1618 void *context
, int vl
, int mode
, u64 data
)
1620 struct hfi1_devdata
*dd
= context
;
1622 return dd
->verbs_dev
.n_piowait
;
1625 static u64
access_sw_pio_drain(const struct cntr_entry
*entry
,
1626 void *context
, int vl
, int mode
, u64 data
)
1628 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
1630 return dd
->verbs_dev
.n_piodrain
;
1633 static u64
access_sw_vtx_wait(const struct cntr_entry
*entry
,
1634 void *context
, int vl
, int mode
, u64 data
)
1636 struct hfi1_devdata
*dd
= context
;
1638 return dd
->verbs_dev
.n_txwait
;
1641 static u64
access_sw_kmem_wait(const struct cntr_entry
*entry
,
1642 void *context
, int vl
, int mode
, u64 data
)
1644 struct hfi1_devdata
*dd
= context
;
1646 return dd
->verbs_dev
.n_kmem_wait
;
1649 static u64
access_sw_send_schedule(const struct cntr_entry
*entry
,
1650 void *context
, int vl
, int mode
, u64 data
)
1652 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
1654 return read_write_cpu(dd
, &dd
->z_send_schedule
, dd
->send_schedule
, vl
,
1658 /* Software counters for the error status bits within MISC_ERR_STATUS */
1659 static u64
access_misc_pll_lock_fail_err_cnt(const struct cntr_entry
*entry
,
1660 void *context
, int vl
, int mode
,
1663 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
1665 return dd
->misc_err_status_cnt
[12];
1668 static u64
access_misc_mbist_fail_err_cnt(const struct cntr_entry
*entry
,
1669 void *context
, int vl
, int mode
,
1672 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
1674 return dd
->misc_err_status_cnt
[11];
1677 static u64
access_misc_invalid_eep_cmd_err_cnt(const struct cntr_entry
*entry
,
1678 void *context
, int vl
, int mode
,
1681 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
1683 return dd
->misc_err_status_cnt
[10];
1686 static u64
access_misc_efuse_done_parity_err_cnt(const struct cntr_entry
*entry
,
1687 void *context
, int vl
,
1690 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
1692 return dd
->misc_err_status_cnt
[9];
1695 static u64
access_misc_efuse_write_err_cnt(const struct cntr_entry
*entry
,
1696 void *context
, int vl
, int mode
,
1699 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
1701 return dd
->misc_err_status_cnt
[8];
1704 static u64
access_misc_efuse_read_bad_addr_err_cnt(
1705 const struct cntr_entry
*entry
,
1706 void *context
, int vl
, int mode
, u64 data
)
1708 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
1710 return dd
->misc_err_status_cnt
[7];
1713 static u64
access_misc_efuse_csr_parity_err_cnt(const struct cntr_entry
*entry
,
1714 void *context
, int vl
,
1717 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
1719 return dd
->misc_err_status_cnt
[6];
1722 static u64
access_misc_fw_auth_failed_err_cnt(const struct cntr_entry
*entry
,
1723 void *context
, int vl
, int mode
,
1726 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
1728 return dd
->misc_err_status_cnt
[5];
1731 static u64
access_misc_key_mismatch_err_cnt(const struct cntr_entry
*entry
,
1732 void *context
, int vl
, int mode
,
1735 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
1737 return dd
->misc_err_status_cnt
[4];
1740 static u64
access_misc_sbus_write_failed_err_cnt(const struct cntr_entry
*entry
,
1741 void *context
, int vl
,
1744 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
1746 return dd
->misc_err_status_cnt
[3];
1749 static u64
access_misc_csr_write_bad_addr_err_cnt(
1750 const struct cntr_entry
*entry
,
1751 void *context
, int vl
, int mode
, u64 data
)
1753 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
1755 return dd
->misc_err_status_cnt
[2];
1758 static u64
access_misc_csr_read_bad_addr_err_cnt(const struct cntr_entry
*entry
,
1759 void *context
, int vl
,
1762 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
1764 return dd
->misc_err_status_cnt
[1];
1767 static u64
access_misc_csr_parity_err_cnt(const struct cntr_entry
*entry
,
1768 void *context
, int vl
, int mode
,
1771 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
1773 return dd
->misc_err_status_cnt
[0];
1777 * Software counter for the aggregate of
1778 * individual CceErrStatus counters
1780 static u64
access_sw_cce_err_status_aggregated_cnt(
1781 const struct cntr_entry
*entry
,
1782 void *context
, int vl
, int mode
, u64 data
)
1784 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
1786 return dd
->sw_cce_err_status_aggregate
;
1790 * Software counters corresponding to each of the
1791 * error status bits within CceErrStatus
1793 static u64
access_cce_msix_csr_parity_err_cnt(const struct cntr_entry
*entry
,
1794 void *context
, int vl
, int mode
,
1797 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
1799 return dd
->cce_err_status_cnt
[40];
1802 static u64
access_cce_int_map_unc_err_cnt(const struct cntr_entry
*entry
,
1803 void *context
, int vl
, int mode
,
1806 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
1808 return dd
->cce_err_status_cnt
[39];
1811 static u64
access_cce_int_map_cor_err_cnt(const struct cntr_entry
*entry
,
1812 void *context
, int vl
, int mode
,
1815 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
1817 return dd
->cce_err_status_cnt
[38];
1820 static u64
access_cce_msix_table_unc_err_cnt(const struct cntr_entry
*entry
,
1821 void *context
, int vl
, int mode
,
1824 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
1826 return dd
->cce_err_status_cnt
[37];
1829 static u64
access_cce_msix_table_cor_err_cnt(const struct cntr_entry
*entry
,
1830 void *context
, int vl
, int mode
,
1833 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
1835 return dd
->cce_err_status_cnt
[36];
1838 static u64
access_cce_rxdma_conv_fifo_parity_err_cnt(
1839 const struct cntr_entry
*entry
,
1840 void *context
, int vl
, int mode
, u64 data
)
1842 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
1844 return dd
->cce_err_status_cnt
[35];
1847 static u64
access_cce_rcpl_async_fifo_parity_err_cnt(
1848 const struct cntr_entry
*entry
,
1849 void *context
, int vl
, int mode
, u64 data
)
1851 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
1853 return dd
->cce_err_status_cnt
[34];
1856 static u64
access_cce_seg_write_bad_addr_err_cnt(const struct cntr_entry
*entry
,
1857 void *context
, int vl
,
1860 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
1862 return dd
->cce_err_status_cnt
[33];
1865 static u64
access_cce_seg_read_bad_addr_err_cnt(const struct cntr_entry
*entry
,
1866 void *context
, int vl
, int mode
,
1869 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
1871 return dd
->cce_err_status_cnt
[32];
1874 static u64
access_la_triggered_cnt(const struct cntr_entry
*entry
,
1875 void *context
, int vl
, int mode
, u64 data
)
1877 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
1879 return dd
->cce_err_status_cnt
[31];
1882 static u64
access_cce_trgt_cpl_timeout_err_cnt(const struct cntr_entry
*entry
,
1883 void *context
, int vl
, int mode
,
1886 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
1888 return dd
->cce_err_status_cnt
[30];
1891 static u64
access_pcic_receive_parity_err_cnt(const struct cntr_entry
*entry
,
1892 void *context
, int vl
, int mode
,
1895 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
1897 return dd
->cce_err_status_cnt
[29];
1900 static u64
access_pcic_transmit_back_parity_err_cnt(
1901 const struct cntr_entry
*entry
,
1902 void *context
, int vl
, int mode
, u64 data
)
1904 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
1906 return dd
->cce_err_status_cnt
[28];
1909 static u64
access_pcic_transmit_front_parity_err_cnt(
1910 const struct cntr_entry
*entry
,
1911 void *context
, int vl
, int mode
, u64 data
)
1913 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
1915 return dd
->cce_err_status_cnt
[27];
1918 static u64
access_pcic_cpl_dat_q_unc_err_cnt(const struct cntr_entry
*entry
,
1919 void *context
, int vl
, int mode
,
1922 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
1924 return dd
->cce_err_status_cnt
[26];
1927 static u64
access_pcic_cpl_hd_q_unc_err_cnt(const struct cntr_entry
*entry
,
1928 void *context
, int vl
, int mode
,
1931 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
1933 return dd
->cce_err_status_cnt
[25];
1936 static u64
access_pcic_post_dat_q_unc_err_cnt(const struct cntr_entry
*entry
,
1937 void *context
, int vl
, int mode
,
1940 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
1942 return dd
->cce_err_status_cnt
[24];
1945 static u64
access_pcic_post_hd_q_unc_err_cnt(const struct cntr_entry
*entry
,
1946 void *context
, int vl
, int mode
,
1949 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
1951 return dd
->cce_err_status_cnt
[23];
1954 static u64
access_pcic_retry_sot_mem_unc_err_cnt(const struct cntr_entry
*entry
,
1955 void *context
, int vl
,
1958 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
1960 return dd
->cce_err_status_cnt
[22];
1963 static u64
access_pcic_retry_mem_unc_err(const struct cntr_entry
*entry
,
1964 void *context
, int vl
, int mode
,
1967 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
1969 return dd
->cce_err_status_cnt
[21];
1972 static u64
access_pcic_n_post_dat_q_parity_err_cnt(
1973 const struct cntr_entry
*entry
,
1974 void *context
, int vl
, int mode
, u64 data
)
1976 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
1978 return dd
->cce_err_status_cnt
[20];
1981 static u64
access_pcic_n_post_h_q_parity_err_cnt(const struct cntr_entry
*entry
,
1982 void *context
, int vl
,
1985 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
1987 return dd
->cce_err_status_cnt
[19];
1990 static u64
access_pcic_cpl_dat_q_cor_err_cnt(const struct cntr_entry
*entry
,
1991 void *context
, int vl
, int mode
,
1994 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
1996 return dd
->cce_err_status_cnt
[18];
1999 static u64
access_pcic_cpl_hd_q_cor_err_cnt(const struct cntr_entry
*entry
,
2000 void *context
, int vl
, int mode
,
2003 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2005 return dd
->cce_err_status_cnt
[17];
2008 static u64
access_pcic_post_dat_q_cor_err_cnt(const struct cntr_entry
*entry
,
2009 void *context
, int vl
, int mode
,
2012 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2014 return dd
->cce_err_status_cnt
[16];
2017 static u64
access_pcic_post_hd_q_cor_err_cnt(const struct cntr_entry
*entry
,
2018 void *context
, int vl
, int mode
,
2021 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2023 return dd
->cce_err_status_cnt
[15];
2026 static u64
access_pcic_retry_sot_mem_cor_err_cnt(const struct cntr_entry
*entry
,
2027 void *context
, int vl
,
2030 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2032 return dd
->cce_err_status_cnt
[14];
2035 static u64
access_pcic_retry_mem_cor_err_cnt(const struct cntr_entry
*entry
,
2036 void *context
, int vl
, int mode
,
2039 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2041 return dd
->cce_err_status_cnt
[13];
2044 static u64
access_cce_cli1_async_fifo_dbg_parity_err_cnt(
2045 const struct cntr_entry
*entry
,
2046 void *context
, int vl
, int mode
, u64 data
)
2048 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2050 return dd
->cce_err_status_cnt
[12];
2053 static u64
access_cce_cli1_async_fifo_rxdma_parity_err_cnt(
2054 const struct cntr_entry
*entry
,
2055 void *context
, int vl
, int mode
, u64 data
)
2057 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2059 return dd
->cce_err_status_cnt
[11];
2062 static u64
access_cce_cli1_async_fifo_sdma_hd_parity_err_cnt(
2063 const struct cntr_entry
*entry
,
2064 void *context
, int vl
, int mode
, u64 data
)
2066 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2068 return dd
->cce_err_status_cnt
[10];
2071 static u64
access_cce_cl1_async_fifo_pio_crdt_parity_err_cnt(
2072 const struct cntr_entry
*entry
,
2073 void *context
, int vl
, int mode
, u64 data
)
2075 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2077 return dd
->cce_err_status_cnt
[9];
2080 static u64
access_cce_cli2_async_fifo_parity_err_cnt(
2081 const struct cntr_entry
*entry
,
2082 void *context
, int vl
, int mode
, u64 data
)
2084 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2086 return dd
->cce_err_status_cnt
[8];
2089 static u64
access_cce_csr_cfg_bus_parity_err_cnt(const struct cntr_entry
*entry
,
2090 void *context
, int vl
,
2093 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2095 return dd
->cce_err_status_cnt
[7];
2098 static u64
access_cce_cli0_async_fifo_parity_err_cnt(
2099 const struct cntr_entry
*entry
,
2100 void *context
, int vl
, int mode
, u64 data
)
2102 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2104 return dd
->cce_err_status_cnt
[6];
2107 static u64
access_cce_rspd_data_parity_err_cnt(const struct cntr_entry
*entry
,
2108 void *context
, int vl
, int mode
,
2111 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2113 return dd
->cce_err_status_cnt
[5];
2116 static u64
access_cce_trgt_access_err_cnt(const struct cntr_entry
*entry
,
2117 void *context
, int vl
, int mode
,
2120 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2122 return dd
->cce_err_status_cnt
[4];
2125 static u64
access_cce_trgt_async_fifo_parity_err_cnt(
2126 const struct cntr_entry
*entry
,
2127 void *context
, int vl
, int mode
, u64 data
)
2129 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2131 return dd
->cce_err_status_cnt
[3];
2134 static u64
access_cce_csr_write_bad_addr_err_cnt(const struct cntr_entry
*entry
,
2135 void *context
, int vl
,
2138 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2140 return dd
->cce_err_status_cnt
[2];
2143 static u64
access_cce_csr_read_bad_addr_err_cnt(const struct cntr_entry
*entry
,
2144 void *context
, int vl
,
2147 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2149 return dd
->cce_err_status_cnt
[1];
2152 static u64
access_ccs_csr_parity_err_cnt(const struct cntr_entry
*entry
,
2153 void *context
, int vl
, int mode
,
2156 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2158 return dd
->cce_err_status_cnt
[0];
2162 * Software counters corresponding to each of the
2163 * error status bits within RcvErrStatus
2165 static u64
access_rx_csr_parity_err_cnt(const struct cntr_entry
*entry
,
2166 void *context
, int vl
, int mode
,
2169 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2171 return dd
->rcv_err_status_cnt
[63];
2174 static u64
access_rx_csr_write_bad_addr_err_cnt(const struct cntr_entry
*entry
,
2175 void *context
, int vl
,
2178 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2180 return dd
->rcv_err_status_cnt
[62];
2183 static u64
access_rx_csr_read_bad_addr_err_cnt(const struct cntr_entry
*entry
,
2184 void *context
, int vl
, int mode
,
2187 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2189 return dd
->rcv_err_status_cnt
[61];
2192 static u64
access_rx_dma_csr_unc_err_cnt(const struct cntr_entry
*entry
,
2193 void *context
, int vl
, int mode
,
2196 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2198 return dd
->rcv_err_status_cnt
[60];
2201 static u64
access_rx_dma_dq_fsm_encoding_err_cnt(const struct cntr_entry
*entry
,
2202 void *context
, int vl
,
2205 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2207 return dd
->rcv_err_status_cnt
[59];
2210 static u64
access_rx_dma_eq_fsm_encoding_err_cnt(const struct cntr_entry
*entry
,
2211 void *context
, int vl
,
2214 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2216 return dd
->rcv_err_status_cnt
[58];
2219 static u64
access_rx_dma_csr_parity_err_cnt(const struct cntr_entry
*entry
,
2220 void *context
, int vl
, int mode
,
2223 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2225 return dd
->rcv_err_status_cnt
[57];
2228 static u64
access_rx_rbuf_data_cor_err_cnt(const struct cntr_entry
*entry
,
2229 void *context
, int vl
, int mode
,
2232 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2234 return dd
->rcv_err_status_cnt
[56];
2237 static u64
access_rx_rbuf_data_unc_err_cnt(const struct cntr_entry
*entry
,
2238 void *context
, int vl
, int mode
,
2241 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2243 return dd
->rcv_err_status_cnt
[55];
2246 static u64
access_rx_dma_data_fifo_rd_cor_err_cnt(
2247 const struct cntr_entry
*entry
,
2248 void *context
, int vl
, int mode
, u64 data
)
2250 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2252 return dd
->rcv_err_status_cnt
[54];
2255 static u64
access_rx_dma_data_fifo_rd_unc_err_cnt(
2256 const struct cntr_entry
*entry
,
2257 void *context
, int vl
, int mode
, u64 data
)
2259 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2261 return dd
->rcv_err_status_cnt
[53];
2264 static u64
access_rx_dma_hdr_fifo_rd_cor_err_cnt(const struct cntr_entry
*entry
,
2265 void *context
, int vl
,
2268 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2270 return dd
->rcv_err_status_cnt
[52];
2273 static u64
access_rx_dma_hdr_fifo_rd_unc_err_cnt(const struct cntr_entry
*entry
,
2274 void *context
, int vl
,
2277 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2279 return dd
->rcv_err_status_cnt
[51];
2282 static u64
access_rx_rbuf_desc_part2_cor_err_cnt(const struct cntr_entry
*entry
,
2283 void *context
, int vl
,
2286 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2288 return dd
->rcv_err_status_cnt
[50];
2291 static u64
access_rx_rbuf_desc_part2_unc_err_cnt(const struct cntr_entry
*entry
,
2292 void *context
, int vl
,
2295 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2297 return dd
->rcv_err_status_cnt
[49];
2300 static u64
access_rx_rbuf_desc_part1_cor_err_cnt(const struct cntr_entry
*entry
,
2301 void *context
, int vl
,
2304 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2306 return dd
->rcv_err_status_cnt
[48];
2309 static u64
access_rx_rbuf_desc_part1_unc_err_cnt(const struct cntr_entry
*entry
,
2310 void *context
, int vl
,
2313 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2315 return dd
->rcv_err_status_cnt
[47];
2318 static u64
access_rx_hq_intr_fsm_err_cnt(const struct cntr_entry
*entry
,
2319 void *context
, int vl
, int mode
,
2322 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2324 return dd
->rcv_err_status_cnt
[46];
2327 static u64
access_rx_hq_intr_csr_parity_err_cnt(
2328 const struct cntr_entry
*entry
,
2329 void *context
, int vl
, int mode
, u64 data
)
2331 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2333 return dd
->rcv_err_status_cnt
[45];
2336 static u64
access_rx_lookup_csr_parity_err_cnt(
2337 const struct cntr_entry
*entry
,
2338 void *context
, int vl
, int mode
, u64 data
)
2340 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2342 return dd
->rcv_err_status_cnt
[44];
2345 static u64
access_rx_lookup_rcv_array_cor_err_cnt(
2346 const struct cntr_entry
*entry
,
2347 void *context
, int vl
, int mode
, u64 data
)
2349 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2351 return dd
->rcv_err_status_cnt
[43];
2354 static u64
access_rx_lookup_rcv_array_unc_err_cnt(
2355 const struct cntr_entry
*entry
,
2356 void *context
, int vl
, int mode
, u64 data
)
2358 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2360 return dd
->rcv_err_status_cnt
[42];
2363 static u64
access_rx_lookup_des_part2_parity_err_cnt(
2364 const struct cntr_entry
*entry
,
2365 void *context
, int vl
, int mode
, u64 data
)
2367 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2369 return dd
->rcv_err_status_cnt
[41];
2372 static u64
access_rx_lookup_des_part1_unc_cor_err_cnt(
2373 const struct cntr_entry
*entry
,
2374 void *context
, int vl
, int mode
, u64 data
)
2376 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2378 return dd
->rcv_err_status_cnt
[40];
2381 static u64
access_rx_lookup_des_part1_unc_err_cnt(
2382 const struct cntr_entry
*entry
,
2383 void *context
, int vl
, int mode
, u64 data
)
2385 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2387 return dd
->rcv_err_status_cnt
[39];
2390 static u64
access_rx_rbuf_next_free_buf_cor_err_cnt(
2391 const struct cntr_entry
*entry
,
2392 void *context
, int vl
, int mode
, u64 data
)
2394 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2396 return dd
->rcv_err_status_cnt
[38];
2399 static u64
access_rx_rbuf_next_free_buf_unc_err_cnt(
2400 const struct cntr_entry
*entry
,
2401 void *context
, int vl
, int mode
, u64 data
)
2403 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2405 return dd
->rcv_err_status_cnt
[37];
2408 static u64
access_rbuf_fl_init_wr_addr_parity_err_cnt(
2409 const struct cntr_entry
*entry
,
2410 void *context
, int vl
, int mode
, u64 data
)
2412 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2414 return dd
->rcv_err_status_cnt
[36];
2417 static u64
access_rx_rbuf_fl_initdone_parity_err_cnt(
2418 const struct cntr_entry
*entry
,
2419 void *context
, int vl
, int mode
, u64 data
)
2421 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2423 return dd
->rcv_err_status_cnt
[35];
2426 static u64
access_rx_rbuf_fl_write_addr_parity_err_cnt(
2427 const struct cntr_entry
*entry
,
2428 void *context
, int vl
, int mode
, u64 data
)
2430 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2432 return dd
->rcv_err_status_cnt
[34];
2435 static u64
access_rx_rbuf_fl_rd_addr_parity_err_cnt(
2436 const struct cntr_entry
*entry
,
2437 void *context
, int vl
, int mode
, u64 data
)
2439 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2441 return dd
->rcv_err_status_cnt
[33];
2444 static u64
access_rx_rbuf_empty_err_cnt(const struct cntr_entry
*entry
,
2445 void *context
, int vl
, int mode
,
2448 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2450 return dd
->rcv_err_status_cnt
[32];
2453 static u64
access_rx_rbuf_full_err_cnt(const struct cntr_entry
*entry
,
2454 void *context
, int vl
, int mode
,
2457 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2459 return dd
->rcv_err_status_cnt
[31];
2462 static u64
access_rbuf_bad_lookup_err_cnt(const struct cntr_entry
*entry
,
2463 void *context
, int vl
, int mode
,
2466 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2468 return dd
->rcv_err_status_cnt
[30];
2471 static u64
access_rbuf_ctx_id_parity_err_cnt(const struct cntr_entry
*entry
,
2472 void *context
, int vl
, int mode
,
2475 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2477 return dd
->rcv_err_status_cnt
[29];
2480 static u64
access_rbuf_csr_qeopdw_parity_err_cnt(const struct cntr_entry
*entry
,
2481 void *context
, int vl
,
2484 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2486 return dd
->rcv_err_status_cnt
[28];
2489 static u64
access_rx_rbuf_csr_q_num_of_pkt_parity_err_cnt(
2490 const struct cntr_entry
*entry
,
2491 void *context
, int vl
, int mode
, u64 data
)
2493 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2495 return dd
->rcv_err_status_cnt
[27];
2498 static u64
access_rx_rbuf_csr_q_t1_ptr_parity_err_cnt(
2499 const struct cntr_entry
*entry
,
2500 void *context
, int vl
, int mode
, u64 data
)
2502 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2504 return dd
->rcv_err_status_cnt
[26];
2507 static u64
access_rx_rbuf_csr_q_hd_ptr_parity_err_cnt(
2508 const struct cntr_entry
*entry
,
2509 void *context
, int vl
, int mode
, u64 data
)
2511 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2513 return dd
->rcv_err_status_cnt
[25];
2516 static u64
access_rx_rbuf_csr_q_vld_bit_parity_err_cnt(
2517 const struct cntr_entry
*entry
,
2518 void *context
, int vl
, int mode
, u64 data
)
2520 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2522 return dd
->rcv_err_status_cnt
[24];
2525 static u64
access_rx_rbuf_csr_q_next_buf_parity_err_cnt(
2526 const struct cntr_entry
*entry
,
2527 void *context
, int vl
, int mode
, u64 data
)
2529 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2531 return dd
->rcv_err_status_cnt
[23];
2534 static u64
access_rx_rbuf_csr_q_ent_cnt_parity_err_cnt(
2535 const struct cntr_entry
*entry
,
2536 void *context
, int vl
, int mode
, u64 data
)
2538 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2540 return dd
->rcv_err_status_cnt
[22];
2543 static u64
access_rx_rbuf_csr_q_head_buf_num_parity_err_cnt(
2544 const struct cntr_entry
*entry
,
2545 void *context
, int vl
, int mode
, u64 data
)
2547 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2549 return dd
->rcv_err_status_cnt
[21];
2552 static u64
access_rx_rbuf_block_list_read_cor_err_cnt(
2553 const struct cntr_entry
*entry
,
2554 void *context
, int vl
, int mode
, u64 data
)
2556 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2558 return dd
->rcv_err_status_cnt
[20];
2561 static u64
access_rx_rbuf_block_list_read_unc_err_cnt(
2562 const struct cntr_entry
*entry
,
2563 void *context
, int vl
, int mode
, u64 data
)
2565 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2567 return dd
->rcv_err_status_cnt
[19];
2570 static u64
access_rx_rbuf_lookup_des_cor_err_cnt(const struct cntr_entry
*entry
,
2571 void *context
, int vl
,
2574 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2576 return dd
->rcv_err_status_cnt
[18];
2579 static u64
access_rx_rbuf_lookup_des_unc_err_cnt(const struct cntr_entry
*entry
,
2580 void *context
, int vl
,
2583 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2585 return dd
->rcv_err_status_cnt
[17];
2588 static u64
access_rx_rbuf_lookup_des_reg_unc_cor_err_cnt(
2589 const struct cntr_entry
*entry
,
2590 void *context
, int vl
, int mode
, u64 data
)
2592 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2594 return dd
->rcv_err_status_cnt
[16];
2597 static u64
access_rx_rbuf_lookup_des_reg_unc_err_cnt(
2598 const struct cntr_entry
*entry
,
2599 void *context
, int vl
, int mode
, u64 data
)
2601 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2603 return dd
->rcv_err_status_cnt
[15];
2606 static u64
access_rx_rbuf_free_list_cor_err_cnt(const struct cntr_entry
*entry
,
2607 void *context
, int vl
,
2610 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2612 return dd
->rcv_err_status_cnt
[14];
2615 static u64
access_rx_rbuf_free_list_unc_err_cnt(const struct cntr_entry
*entry
,
2616 void *context
, int vl
,
2619 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2621 return dd
->rcv_err_status_cnt
[13];
2624 static u64
access_rx_rcv_fsm_encoding_err_cnt(const struct cntr_entry
*entry
,
2625 void *context
, int vl
, int mode
,
2628 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2630 return dd
->rcv_err_status_cnt
[12];
2633 static u64
access_rx_dma_flag_cor_err_cnt(const struct cntr_entry
*entry
,
2634 void *context
, int vl
, int mode
,
2637 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2639 return dd
->rcv_err_status_cnt
[11];
2642 static u64
access_rx_dma_flag_unc_err_cnt(const struct cntr_entry
*entry
,
2643 void *context
, int vl
, int mode
,
2646 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2648 return dd
->rcv_err_status_cnt
[10];
2651 static u64
access_rx_dc_sop_eop_parity_err_cnt(const struct cntr_entry
*entry
,
2652 void *context
, int vl
, int mode
,
2655 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2657 return dd
->rcv_err_status_cnt
[9];
2660 static u64
access_rx_rcv_csr_parity_err_cnt(const struct cntr_entry
*entry
,
2661 void *context
, int vl
, int mode
,
2664 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2666 return dd
->rcv_err_status_cnt
[8];
2669 static u64
access_rx_rcv_qp_map_table_cor_err_cnt(
2670 const struct cntr_entry
*entry
,
2671 void *context
, int vl
, int mode
, u64 data
)
2673 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2675 return dd
->rcv_err_status_cnt
[7];
2678 static u64
access_rx_rcv_qp_map_table_unc_err_cnt(
2679 const struct cntr_entry
*entry
,
2680 void *context
, int vl
, int mode
, u64 data
)
2682 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2684 return dd
->rcv_err_status_cnt
[6];
2687 static u64
access_rx_rcv_data_cor_err_cnt(const struct cntr_entry
*entry
,
2688 void *context
, int vl
, int mode
,
2691 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2693 return dd
->rcv_err_status_cnt
[5];
2696 static u64
access_rx_rcv_data_unc_err_cnt(const struct cntr_entry
*entry
,
2697 void *context
, int vl
, int mode
,
2700 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2702 return dd
->rcv_err_status_cnt
[4];
2705 static u64
access_rx_rcv_hdr_cor_err_cnt(const struct cntr_entry
*entry
,
2706 void *context
, int vl
, int mode
,
2709 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2711 return dd
->rcv_err_status_cnt
[3];
2714 static u64
access_rx_rcv_hdr_unc_err_cnt(const struct cntr_entry
*entry
,
2715 void *context
, int vl
, int mode
,
2718 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2720 return dd
->rcv_err_status_cnt
[2];
2723 static u64
access_rx_dc_intf_parity_err_cnt(const struct cntr_entry
*entry
,
2724 void *context
, int vl
, int mode
,
2727 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2729 return dd
->rcv_err_status_cnt
[1];
2732 static u64
access_rx_dma_csr_cor_err_cnt(const struct cntr_entry
*entry
,
2733 void *context
, int vl
, int mode
,
2736 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2738 return dd
->rcv_err_status_cnt
[0];
2742 * Software counters corresponding to each of the
2743 * error status bits within SendPioErrStatus
2745 static u64
access_pio_pec_sop_head_parity_err_cnt(
2746 const struct cntr_entry
*entry
,
2747 void *context
, int vl
, int mode
, u64 data
)
2749 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2751 return dd
->send_pio_err_status_cnt
[35];
2754 static u64
access_pio_pcc_sop_head_parity_err_cnt(
2755 const struct cntr_entry
*entry
,
2756 void *context
, int vl
, int mode
, u64 data
)
2758 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2760 return dd
->send_pio_err_status_cnt
[34];
2763 static u64
access_pio_last_returned_cnt_parity_err_cnt(
2764 const struct cntr_entry
*entry
,
2765 void *context
, int vl
, int mode
, u64 data
)
2767 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2769 return dd
->send_pio_err_status_cnt
[33];
2772 static u64
access_pio_current_free_cnt_parity_err_cnt(
2773 const struct cntr_entry
*entry
,
2774 void *context
, int vl
, int mode
, u64 data
)
2776 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2778 return dd
->send_pio_err_status_cnt
[32];
2781 static u64
access_pio_reserved_31_err_cnt(const struct cntr_entry
*entry
,
2782 void *context
, int vl
, int mode
,
2785 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2787 return dd
->send_pio_err_status_cnt
[31];
2790 static u64
access_pio_reserved_30_err_cnt(const struct cntr_entry
*entry
,
2791 void *context
, int vl
, int mode
,
2794 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2796 return dd
->send_pio_err_status_cnt
[30];
2799 static u64
access_pio_ppmc_sop_len_err_cnt(const struct cntr_entry
*entry
,
2800 void *context
, int vl
, int mode
,
2803 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2805 return dd
->send_pio_err_status_cnt
[29];
2808 static u64
access_pio_ppmc_bqc_mem_parity_err_cnt(
2809 const struct cntr_entry
*entry
,
2810 void *context
, int vl
, int mode
, u64 data
)
2812 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2814 return dd
->send_pio_err_status_cnt
[28];
2817 static u64
access_pio_vl_fifo_parity_err_cnt(const struct cntr_entry
*entry
,
2818 void *context
, int vl
, int mode
,
2821 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2823 return dd
->send_pio_err_status_cnt
[27];
2826 static u64
access_pio_vlf_sop_parity_err_cnt(const struct cntr_entry
*entry
,
2827 void *context
, int vl
, int mode
,
2830 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2832 return dd
->send_pio_err_status_cnt
[26];
2835 static u64
access_pio_vlf_v1_len_parity_err_cnt(const struct cntr_entry
*entry
,
2836 void *context
, int vl
,
2839 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2841 return dd
->send_pio_err_status_cnt
[25];
2844 static u64
access_pio_block_qw_count_parity_err_cnt(
2845 const struct cntr_entry
*entry
,
2846 void *context
, int vl
, int mode
, u64 data
)
2848 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2850 return dd
->send_pio_err_status_cnt
[24];
2853 static u64
access_pio_write_qw_valid_parity_err_cnt(
2854 const struct cntr_entry
*entry
,
2855 void *context
, int vl
, int mode
, u64 data
)
2857 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2859 return dd
->send_pio_err_status_cnt
[23];
2862 static u64
access_pio_state_machine_err_cnt(const struct cntr_entry
*entry
,
2863 void *context
, int vl
, int mode
,
2866 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2868 return dd
->send_pio_err_status_cnt
[22];
2871 static u64
access_pio_write_data_parity_err_cnt(const struct cntr_entry
*entry
,
2872 void *context
, int vl
,
2875 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2877 return dd
->send_pio_err_status_cnt
[21];
2880 static u64
access_pio_host_addr_mem_cor_err_cnt(const struct cntr_entry
*entry
,
2881 void *context
, int vl
,
2884 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2886 return dd
->send_pio_err_status_cnt
[20];
2889 static u64
access_pio_host_addr_mem_unc_err_cnt(const struct cntr_entry
*entry
,
2890 void *context
, int vl
,
2893 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2895 return dd
->send_pio_err_status_cnt
[19];
2898 static u64
access_pio_pkt_evict_sm_or_arb_sm_err_cnt(
2899 const struct cntr_entry
*entry
,
2900 void *context
, int vl
, int mode
, u64 data
)
2902 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2904 return dd
->send_pio_err_status_cnt
[18];
2907 static u64
access_pio_init_sm_in_err_cnt(const struct cntr_entry
*entry
,
2908 void *context
, int vl
, int mode
,
2911 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2913 return dd
->send_pio_err_status_cnt
[17];
2916 static u64
access_pio_ppmc_pbl_fifo_err_cnt(const struct cntr_entry
*entry
,
2917 void *context
, int vl
, int mode
,
2920 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2922 return dd
->send_pio_err_status_cnt
[16];
2925 static u64
access_pio_credit_ret_fifo_parity_err_cnt(
2926 const struct cntr_entry
*entry
,
2927 void *context
, int vl
, int mode
, u64 data
)
2929 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2931 return dd
->send_pio_err_status_cnt
[15];
2934 static u64
access_pio_v1_len_mem_bank1_cor_err_cnt(
2935 const struct cntr_entry
*entry
,
2936 void *context
, int vl
, int mode
, u64 data
)
2938 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2940 return dd
->send_pio_err_status_cnt
[14];
2943 static u64
access_pio_v1_len_mem_bank0_cor_err_cnt(
2944 const struct cntr_entry
*entry
,
2945 void *context
, int vl
, int mode
, u64 data
)
2947 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2949 return dd
->send_pio_err_status_cnt
[13];
2952 static u64
access_pio_v1_len_mem_bank1_unc_err_cnt(
2953 const struct cntr_entry
*entry
,
2954 void *context
, int vl
, int mode
, u64 data
)
2956 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2958 return dd
->send_pio_err_status_cnt
[12];
2961 static u64
access_pio_v1_len_mem_bank0_unc_err_cnt(
2962 const struct cntr_entry
*entry
,
2963 void *context
, int vl
, int mode
, u64 data
)
2965 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2967 return dd
->send_pio_err_status_cnt
[11];
2970 static u64
access_pio_sm_pkt_reset_parity_err_cnt(
2971 const struct cntr_entry
*entry
,
2972 void *context
, int vl
, int mode
, u64 data
)
2974 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2976 return dd
->send_pio_err_status_cnt
[10];
2979 static u64
access_pio_pkt_evict_fifo_parity_err_cnt(
2980 const struct cntr_entry
*entry
,
2981 void *context
, int vl
, int mode
, u64 data
)
2983 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2985 return dd
->send_pio_err_status_cnt
[9];
2988 static u64
access_pio_sbrdctrl_crrel_fifo_parity_err_cnt(
2989 const struct cntr_entry
*entry
,
2990 void *context
, int vl
, int mode
, u64 data
)
2992 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
2994 return dd
->send_pio_err_status_cnt
[8];
2997 static u64
access_pio_sbrdctl_crrel_parity_err_cnt(
2998 const struct cntr_entry
*entry
,
2999 void *context
, int vl
, int mode
, u64 data
)
3001 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3003 return dd
->send_pio_err_status_cnt
[7];
3006 static u64
access_pio_pec_fifo_parity_err_cnt(const struct cntr_entry
*entry
,
3007 void *context
, int vl
, int mode
,
3010 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3012 return dd
->send_pio_err_status_cnt
[6];
3015 static u64
access_pio_pcc_fifo_parity_err_cnt(const struct cntr_entry
*entry
,
3016 void *context
, int vl
, int mode
,
3019 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3021 return dd
->send_pio_err_status_cnt
[5];
3024 static u64
access_pio_sb_mem_fifo1_err_cnt(const struct cntr_entry
*entry
,
3025 void *context
, int vl
, int mode
,
3028 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3030 return dd
->send_pio_err_status_cnt
[4];
3033 static u64
access_pio_sb_mem_fifo0_err_cnt(const struct cntr_entry
*entry
,
3034 void *context
, int vl
, int mode
,
3037 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3039 return dd
->send_pio_err_status_cnt
[3];
3042 static u64
access_pio_csr_parity_err_cnt(const struct cntr_entry
*entry
,
3043 void *context
, int vl
, int mode
,
3046 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3048 return dd
->send_pio_err_status_cnt
[2];
3051 static u64
access_pio_write_addr_parity_err_cnt(const struct cntr_entry
*entry
,
3052 void *context
, int vl
,
3055 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3057 return dd
->send_pio_err_status_cnt
[1];
3060 static u64
access_pio_write_bad_ctxt_err_cnt(const struct cntr_entry
*entry
,
3061 void *context
, int vl
, int mode
,
3064 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3066 return dd
->send_pio_err_status_cnt
[0];
3070 * Software counters corresponding to each of the
3071 * error status bits within SendDmaErrStatus
3073 static u64
access_sdma_pcie_req_tracking_cor_err_cnt(
3074 const struct cntr_entry
*entry
,
3075 void *context
, int vl
, int mode
, u64 data
)
3077 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3079 return dd
->send_dma_err_status_cnt
[3];
3082 static u64
access_sdma_pcie_req_tracking_unc_err_cnt(
3083 const struct cntr_entry
*entry
,
3084 void *context
, int vl
, int mode
, u64 data
)
3086 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3088 return dd
->send_dma_err_status_cnt
[2];
3091 static u64
access_sdma_csr_parity_err_cnt(const struct cntr_entry
*entry
,
3092 void *context
, int vl
, int mode
,
3095 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3097 return dd
->send_dma_err_status_cnt
[1];
3100 static u64
access_sdma_rpy_tag_err_cnt(const struct cntr_entry
*entry
,
3101 void *context
, int vl
, int mode
,
3104 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3106 return dd
->send_dma_err_status_cnt
[0];
3110 * Software counters corresponding to each of the
3111 * error status bits within SendEgressErrStatus
3113 static u64
access_tx_read_pio_memory_csr_unc_err_cnt(
3114 const struct cntr_entry
*entry
,
3115 void *context
, int vl
, int mode
, u64 data
)
3117 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3119 return dd
->send_egress_err_status_cnt
[63];
3122 static u64
access_tx_read_sdma_memory_csr_err_cnt(
3123 const struct cntr_entry
*entry
,
3124 void *context
, int vl
, int mode
, u64 data
)
3126 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3128 return dd
->send_egress_err_status_cnt
[62];
3131 static u64
access_tx_egress_fifo_cor_err_cnt(const struct cntr_entry
*entry
,
3132 void *context
, int vl
, int mode
,
3135 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3137 return dd
->send_egress_err_status_cnt
[61];
3140 static u64
access_tx_read_pio_memory_cor_err_cnt(const struct cntr_entry
*entry
,
3141 void *context
, int vl
,
3144 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3146 return dd
->send_egress_err_status_cnt
[60];
3149 static u64
access_tx_read_sdma_memory_cor_err_cnt(
3150 const struct cntr_entry
*entry
,
3151 void *context
, int vl
, int mode
, u64 data
)
3153 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3155 return dd
->send_egress_err_status_cnt
[59];
3158 static u64
access_tx_sb_hdr_cor_err_cnt(const struct cntr_entry
*entry
,
3159 void *context
, int vl
, int mode
,
3162 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3164 return dd
->send_egress_err_status_cnt
[58];
3167 static u64
access_tx_credit_overrun_err_cnt(const struct cntr_entry
*entry
,
3168 void *context
, int vl
, int mode
,
3171 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3173 return dd
->send_egress_err_status_cnt
[57];
3176 static u64
access_tx_launch_fifo8_cor_err_cnt(const struct cntr_entry
*entry
,
3177 void *context
, int vl
, int mode
,
3180 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3182 return dd
->send_egress_err_status_cnt
[56];
3185 static u64
access_tx_launch_fifo7_cor_err_cnt(const struct cntr_entry
*entry
,
3186 void *context
, int vl
, int mode
,
3189 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3191 return dd
->send_egress_err_status_cnt
[55];
3194 static u64
access_tx_launch_fifo6_cor_err_cnt(const struct cntr_entry
*entry
,
3195 void *context
, int vl
, int mode
,
3198 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3200 return dd
->send_egress_err_status_cnt
[54];
3203 static u64
access_tx_launch_fifo5_cor_err_cnt(const struct cntr_entry
*entry
,
3204 void *context
, int vl
, int mode
,
3207 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3209 return dd
->send_egress_err_status_cnt
[53];
3212 static u64
access_tx_launch_fifo4_cor_err_cnt(const struct cntr_entry
*entry
,
3213 void *context
, int vl
, int mode
,
3216 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3218 return dd
->send_egress_err_status_cnt
[52];
3221 static u64
access_tx_launch_fifo3_cor_err_cnt(const struct cntr_entry
*entry
,
3222 void *context
, int vl
, int mode
,
3225 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3227 return dd
->send_egress_err_status_cnt
[51];
3230 static u64
access_tx_launch_fifo2_cor_err_cnt(const struct cntr_entry
*entry
,
3231 void *context
, int vl
, int mode
,
3234 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3236 return dd
->send_egress_err_status_cnt
[50];
3239 static u64
access_tx_launch_fifo1_cor_err_cnt(const struct cntr_entry
*entry
,
3240 void *context
, int vl
, int mode
,
3243 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3245 return dd
->send_egress_err_status_cnt
[49];
3248 static u64
access_tx_launch_fifo0_cor_err_cnt(const struct cntr_entry
*entry
,
3249 void *context
, int vl
, int mode
,
3252 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3254 return dd
->send_egress_err_status_cnt
[48];
3257 static u64
access_tx_credit_return_vl_err_cnt(const struct cntr_entry
*entry
,
3258 void *context
, int vl
, int mode
,
3261 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3263 return dd
->send_egress_err_status_cnt
[47];
3266 static u64
access_tx_hcrc_insertion_err_cnt(const struct cntr_entry
*entry
,
3267 void *context
, int vl
, int mode
,
3270 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3272 return dd
->send_egress_err_status_cnt
[46];
3275 static u64
access_tx_egress_fifo_unc_err_cnt(const struct cntr_entry
*entry
,
3276 void *context
, int vl
, int mode
,
3279 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3281 return dd
->send_egress_err_status_cnt
[45];
3284 static u64
access_tx_read_pio_memory_unc_err_cnt(const struct cntr_entry
*entry
,
3285 void *context
, int vl
,
3288 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3290 return dd
->send_egress_err_status_cnt
[44];
3293 static u64
access_tx_read_sdma_memory_unc_err_cnt(
3294 const struct cntr_entry
*entry
,
3295 void *context
, int vl
, int mode
, u64 data
)
3297 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3299 return dd
->send_egress_err_status_cnt
[43];
3302 static u64
access_tx_sb_hdr_unc_err_cnt(const struct cntr_entry
*entry
,
3303 void *context
, int vl
, int mode
,
3306 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3308 return dd
->send_egress_err_status_cnt
[42];
3311 static u64
access_tx_credit_return_partiy_err_cnt(
3312 const struct cntr_entry
*entry
,
3313 void *context
, int vl
, int mode
, u64 data
)
3315 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3317 return dd
->send_egress_err_status_cnt
[41];
3320 static u64
access_tx_launch_fifo8_unc_or_parity_err_cnt(
3321 const struct cntr_entry
*entry
,
3322 void *context
, int vl
, int mode
, u64 data
)
3324 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3326 return dd
->send_egress_err_status_cnt
[40];
3329 static u64
access_tx_launch_fifo7_unc_or_parity_err_cnt(
3330 const struct cntr_entry
*entry
,
3331 void *context
, int vl
, int mode
, u64 data
)
3333 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3335 return dd
->send_egress_err_status_cnt
[39];
3338 static u64
access_tx_launch_fifo6_unc_or_parity_err_cnt(
3339 const struct cntr_entry
*entry
,
3340 void *context
, int vl
, int mode
, u64 data
)
3342 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3344 return dd
->send_egress_err_status_cnt
[38];
3347 static u64
access_tx_launch_fifo5_unc_or_parity_err_cnt(
3348 const struct cntr_entry
*entry
,
3349 void *context
, int vl
, int mode
, u64 data
)
3351 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3353 return dd
->send_egress_err_status_cnt
[37];
3356 static u64
access_tx_launch_fifo4_unc_or_parity_err_cnt(
3357 const struct cntr_entry
*entry
,
3358 void *context
, int vl
, int mode
, u64 data
)
3360 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3362 return dd
->send_egress_err_status_cnt
[36];
3365 static u64
access_tx_launch_fifo3_unc_or_parity_err_cnt(
3366 const struct cntr_entry
*entry
,
3367 void *context
, int vl
, int mode
, u64 data
)
3369 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3371 return dd
->send_egress_err_status_cnt
[35];
3374 static u64
access_tx_launch_fifo2_unc_or_parity_err_cnt(
3375 const struct cntr_entry
*entry
,
3376 void *context
, int vl
, int mode
, u64 data
)
3378 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3380 return dd
->send_egress_err_status_cnt
[34];
3383 static u64
access_tx_launch_fifo1_unc_or_parity_err_cnt(
3384 const struct cntr_entry
*entry
,
3385 void *context
, int vl
, int mode
, u64 data
)
3387 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3389 return dd
->send_egress_err_status_cnt
[33];
3392 static u64
access_tx_launch_fifo0_unc_or_parity_err_cnt(
3393 const struct cntr_entry
*entry
,
3394 void *context
, int vl
, int mode
, u64 data
)
3396 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3398 return dd
->send_egress_err_status_cnt
[32];
3401 static u64
access_tx_sdma15_disallowed_packet_err_cnt(
3402 const struct cntr_entry
*entry
,
3403 void *context
, int vl
, int mode
, u64 data
)
3405 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3407 return dd
->send_egress_err_status_cnt
[31];
3410 static u64
access_tx_sdma14_disallowed_packet_err_cnt(
3411 const struct cntr_entry
*entry
,
3412 void *context
, int vl
, int mode
, u64 data
)
3414 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3416 return dd
->send_egress_err_status_cnt
[30];
3419 static u64
access_tx_sdma13_disallowed_packet_err_cnt(
3420 const struct cntr_entry
*entry
,
3421 void *context
, int vl
, int mode
, u64 data
)
3423 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3425 return dd
->send_egress_err_status_cnt
[29];
3428 static u64
access_tx_sdma12_disallowed_packet_err_cnt(
3429 const struct cntr_entry
*entry
,
3430 void *context
, int vl
, int mode
, u64 data
)
3432 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3434 return dd
->send_egress_err_status_cnt
[28];
3437 static u64
access_tx_sdma11_disallowed_packet_err_cnt(
3438 const struct cntr_entry
*entry
,
3439 void *context
, int vl
, int mode
, u64 data
)
3441 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3443 return dd
->send_egress_err_status_cnt
[27];
3446 static u64
access_tx_sdma10_disallowed_packet_err_cnt(
3447 const struct cntr_entry
*entry
,
3448 void *context
, int vl
, int mode
, u64 data
)
3450 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3452 return dd
->send_egress_err_status_cnt
[26];
3455 static u64
access_tx_sdma9_disallowed_packet_err_cnt(
3456 const struct cntr_entry
*entry
,
3457 void *context
, int vl
, int mode
, u64 data
)
3459 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3461 return dd
->send_egress_err_status_cnt
[25];
3464 static u64
access_tx_sdma8_disallowed_packet_err_cnt(
3465 const struct cntr_entry
*entry
,
3466 void *context
, int vl
, int mode
, u64 data
)
3468 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3470 return dd
->send_egress_err_status_cnt
[24];
3473 static u64
access_tx_sdma7_disallowed_packet_err_cnt(
3474 const struct cntr_entry
*entry
,
3475 void *context
, int vl
, int mode
, u64 data
)
3477 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3479 return dd
->send_egress_err_status_cnt
[23];
3482 static u64
access_tx_sdma6_disallowed_packet_err_cnt(
3483 const struct cntr_entry
*entry
,
3484 void *context
, int vl
, int mode
, u64 data
)
3486 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3488 return dd
->send_egress_err_status_cnt
[22];
3491 static u64
access_tx_sdma5_disallowed_packet_err_cnt(
3492 const struct cntr_entry
*entry
,
3493 void *context
, int vl
, int mode
, u64 data
)
3495 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3497 return dd
->send_egress_err_status_cnt
[21];
3500 static u64
access_tx_sdma4_disallowed_packet_err_cnt(
3501 const struct cntr_entry
*entry
,
3502 void *context
, int vl
, int mode
, u64 data
)
3504 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3506 return dd
->send_egress_err_status_cnt
[20];
3509 static u64
access_tx_sdma3_disallowed_packet_err_cnt(
3510 const struct cntr_entry
*entry
,
3511 void *context
, int vl
, int mode
, u64 data
)
3513 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3515 return dd
->send_egress_err_status_cnt
[19];
3518 static u64
access_tx_sdma2_disallowed_packet_err_cnt(
3519 const struct cntr_entry
*entry
,
3520 void *context
, int vl
, int mode
, u64 data
)
3522 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3524 return dd
->send_egress_err_status_cnt
[18];
3527 static u64
access_tx_sdma1_disallowed_packet_err_cnt(
3528 const struct cntr_entry
*entry
,
3529 void *context
, int vl
, int mode
, u64 data
)
3531 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3533 return dd
->send_egress_err_status_cnt
[17];
3536 static u64
access_tx_sdma0_disallowed_packet_err_cnt(
3537 const struct cntr_entry
*entry
,
3538 void *context
, int vl
, int mode
, u64 data
)
3540 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3542 return dd
->send_egress_err_status_cnt
[16];
3545 static u64
access_tx_config_parity_err_cnt(const struct cntr_entry
*entry
,
3546 void *context
, int vl
, int mode
,
3549 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3551 return dd
->send_egress_err_status_cnt
[15];
3554 static u64
access_tx_sbrd_ctl_csr_parity_err_cnt(const struct cntr_entry
*entry
,
3555 void *context
, int vl
,
3558 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3560 return dd
->send_egress_err_status_cnt
[14];
3563 static u64
access_tx_launch_csr_parity_err_cnt(const struct cntr_entry
*entry
,
3564 void *context
, int vl
, int mode
,
3567 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3569 return dd
->send_egress_err_status_cnt
[13];
3572 static u64
access_tx_illegal_vl_err_cnt(const struct cntr_entry
*entry
,
3573 void *context
, int vl
, int mode
,
3576 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3578 return dd
->send_egress_err_status_cnt
[12];
3581 static u64
access_tx_sbrd_ctl_state_machine_parity_err_cnt(
3582 const struct cntr_entry
*entry
,
3583 void *context
, int vl
, int mode
, u64 data
)
3585 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3587 return dd
->send_egress_err_status_cnt
[11];
3590 static u64
access_egress_reserved_10_err_cnt(const struct cntr_entry
*entry
,
3591 void *context
, int vl
, int mode
,
3594 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3596 return dd
->send_egress_err_status_cnt
[10];
3599 static u64
access_egress_reserved_9_err_cnt(const struct cntr_entry
*entry
,
3600 void *context
, int vl
, int mode
,
3603 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3605 return dd
->send_egress_err_status_cnt
[9];
3608 static u64
access_tx_sdma_launch_intf_parity_err_cnt(
3609 const struct cntr_entry
*entry
,
3610 void *context
, int vl
, int mode
, u64 data
)
3612 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3614 return dd
->send_egress_err_status_cnt
[8];
3617 static u64
access_tx_pio_launch_intf_parity_err_cnt(
3618 const struct cntr_entry
*entry
,
3619 void *context
, int vl
, int mode
, u64 data
)
3621 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3623 return dd
->send_egress_err_status_cnt
[7];
3626 static u64
access_egress_reserved_6_err_cnt(const struct cntr_entry
*entry
,
3627 void *context
, int vl
, int mode
,
3630 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3632 return dd
->send_egress_err_status_cnt
[6];
3635 static u64
access_tx_incorrect_link_state_err_cnt(
3636 const struct cntr_entry
*entry
,
3637 void *context
, int vl
, int mode
, u64 data
)
3639 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3641 return dd
->send_egress_err_status_cnt
[5];
3644 static u64
access_tx_linkdown_err_cnt(const struct cntr_entry
*entry
,
3645 void *context
, int vl
, int mode
,
3648 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3650 return dd
->send_egress_err_status_cnt
[4];
3653 static u64
access_tx_egress_fifi_underrun_or_parity_err_cnt(
3654 const struct cntr_entry
*entry
,
3655 void *context
, int vl
, int mode
, u64 data
)
3657 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3659 return dd
->send_egress_err_status_cnt
[3];
3662 static u64
access_egress_reserved_2_err_cnt(const struct cntr_entry
*entry
,
3663 void *context
, int vl
, int mode
,
3666 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3668 return dd
->send_egress_err_status_cnt
[2];
3671 static u64
access_tx_pkt_integrity_mem_unc_err_cnt(
3672 const struct cntr_entry
*entry
,
3673 void *context
, int vl
, int mode
, u64 data
)
3675 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3677 return dd
->send_egress_err_status_cnt
[1];
3680 static u64
access_tx_pkt_integrity_mem_cor_err_cnt(
3681 const struct cntr_entry
*entry
,
3682 void *context
, int vl
, int mode
, u64 data
)
3684 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3686 return dd
->send_egress_err_status_cnt
[0];
3690 * Software counters corresponding to each of the
3691 * error status bits within SendErrStatus
3693 static u64
access_send_csr_write_bad_addr_err_cnt(
3694 const struct cntr_entry
*entry
,
3695 void *context
, int vl
, int mode
, u64 data
)
3697 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3699 return dd
->send_err_status_cnt
[2];
3702 static u64
access_send_csr_read_bad_addr_err_cnt(const struct cntr_entry
*entry
,
3703 void *context
, int vl
,
3706 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3708 return dd
->send_err_status_cnt
[1];
3711 static u64
access_send_csr_parity_cnt(const struct cntr_entry
*entry
,
3712 void *context
, int vl
, int mode
,
3715 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3717 return dd
->send_err_status_cnt
[0];
3721 * Software counters corresponding to each of the
3722 * error status bits within SendCtxtErrStatus
3724 static u64
access_pio_write_out_of_bounds_err_cnt(
3725 const struct cntr_entry
*entry
,
3726 void *context
, int vl
, int mode
, u64 data
)
3728 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3730 return dd
->sw_ctxt_err_status_cnt
[4];
3733 static u64
access_pio_write_overflow_err_cnt(const struct cntr_entry
*entry
,
3734 void *context
, int vl
, int mode
,
3737 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3739 return dd
->sw_ctxt_err_status_cnt
[3];
3742 static u64
access_pio_write_crosses_boundary_err_cnt(
3743 const struct cntr_entry
*entry
,
3744 void *context
, int vl
, int mode
, u64 data
)
3746 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3748 return dd
->sw_ctxt_err_status_cnt
[2];
3751 static u64
access_pio_disallowed_packet_err_cnt(const struct cntr_entry
*entry
,
3752 void *context
, int vl
,
3755 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3757 return dd
->sw_ctxt_err_status_cnt
[1];
3760 static u64
access_pio_inconsistent_sop_err_cnt(const struct cntr_entry
*entry
,
3761 void *context
, int vl
, int mode
,
3764 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3766 return dd
->sw_ctxt_err_status_cnt
[0];
3770 * Software counters corresponding to each of the
3771 * error status bits within SendDmaEngErrStatus
3773 static u64
access_sdma_header_request_fifo_cor_err_cnt(
3774 const struct cntr_entry
*entry
,
3775 void *context
, int vl
, int mode
, u64 data
)
3777 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3779 return dd
->sw_send_dma_eng_err_status_cnt
[23];
3782 static u64
access_sdma_header_storage_cor_err_cnt(
3783 const struct cntr_entry
*entry
,
3784 void *context
, int vl
, int mode
, u64 data
)
3786 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3788 return dd
->sw_send_dma_eng_err_status_cnt
[22];
3791 static u64
access_sdma_packet_tracking_cor_err_cnt(
3792 const struct cntr_entry
*entry
,
3793 void *context
, int vl
, int mode
, u64 data
)
3795 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3797 return dd
->sw_send_dma_eng_err_status_cnt
[21];
3800 static u64
access_sdma_assembly_cor_err_cnt(const struct cntr_entry
*entry
,
3801 void *context
, int vl
, int mode
,
3804 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3806 return dd
->sw_send_dma_eng_err_status_cnt
[20];
3809 static u64
access_sdma_desc_table_cor_err_cnt(const struct cntr_entry
*entry
,
3810 void *context
, int vl
, int mode
,
3813 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3815 return dd
->sw_send_dma_eng_err_status_cnt
[19];
3818 static u64
access_sdma_header_request_fifo_unc_err_cnt(
3819 const struct cntr_entry
*entry
,
3820 void *context
, int vl
, int mode
, u64 data
)
3822 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3824 return dd
->sw_send_dma_eng_err_status_cnt
[18];
3827 static u64
access_sdma_header_storage_unc_err_cnt(
3828 const struct cntr_entry
*entry
,
3829 void *context
, int vl
, int mode
, u64 data
)
3831 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3833 return dd
->sw_send_dma_eng_err_status_cnt
[17];
3836 static u64
access_sdma_packet_tracking_unc_err_cnt(
3837 const struct cntr_entry
*entry
,
3838 void *context
, int vl
, int mode
, u64 data
)
3840 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3842 return dd
->sw_send_dma_eng_err_status_cnt
[16];
3845 static u64
access_sdma_assembly_unc_err_cnt(const struct cntr_entry
*entry
,
3846 void *context
, int vl
, int mode
,
3849 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3851 return dd
->sw_send_dma_eng_err_status_cnt
[15];
3854 static u64
access_sdma_desc_table_unc_err_cnt(const struct cntr_entry
*entry
,
3855 void *context
, int vl
, int mode
,
3858 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3860 return dd
->sw_send_dma_eng_err_status_cnt
[14];
3863 static u64
access_sdma_timeout_err_cnt(const struct cntr_entry
*entry
,
3864 void *context
, int vl
, int mode
,
3867 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3869 return dd
->sw_send_dma_eng_err_status_cnt
[13];
3872 static u64
access_sdma_header_length_err_cnt(const struct cntr_entry
*entry
,
3873 void *context
, int vl
, int mode
,
3876 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3878 return dd
->sw_send_dma_eng_err_status_cnt
[12];
3881 static u64
access_sdma_header_address_err_cnt(const struct cntr_entry
*entry
,
3882 void *context
, int vl
, int mode
,
3885 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3887 return dd
->sw_send_dma_eng_err_status_cnt
[11];
3890 static u64
access_sdma_header_select_err_cnt(const struct cntr_entry
*entry
,
3891 void *context
, int vl
, int mode
,
3894 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3896 return dd
->sw_send_dma_eng_err_status_cnt
[10];
3899 static u64
access_sdma_reserved_9_err_cnt(const struct cntr_entry
*entry
,
3900 void *context
, int vl
, int mode
,
3903 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3905 return dd
->sw_send_dma_eng_err_status_cnt
[9];
3908 static u64
access_sdma_packet_desc_overflow_err_cnt(
3909 const struct cntr_entry
*entry
,
3910 void *context
, int vl
, int mode
, u64 data
)
3912 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3914 return dd
->sw_send_dma_eng_err_status_cnt
[8];
3917 static u64
access_sdma_length_mismatch_err_cnt(const struct cntr_entry
*entry
,
3918 void *context
, int vl
,
3921 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3923 return dd
->sw_send_dma_eng_err_status_cnt
[7];
3926 static u64
access_sdma_halt_err_cnt(const struct cntr_entry
*entry
,
3927 void *context
, int vl
, int mode
, u64 data
)
3929 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3931 return dd
->sw_send_dma_eng_err_status_cnt
[6];
3934 static u64
access_sdma_mem_read_err_cnt(const struct cntr_entry
*entry
,
3935 void *context
, int vl
, int mode
,
3938 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3940 return dd
->sw_send_dma_eng_err_status_cnt
[5];
3943 static u64
access_sdma_first_desc_err_cnt(const struct cntr_entry
*entry
,
3944 void *context
, int vl
, int mode
,
3947 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3949 return dd
->sw_send_dma_eng_err_status_cnt
[4];
3952 static u64
access_sdma_tail_out_of_bounds_err_cnt(
3953 const struct cntr_entry
*entry
,
3954 void *context
, int vl
, int mode
, u64 data
)
3956 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3958 return dd
->sw_send_dma_eng_err_status_cnt
[3];
3961 static u64
access_sdma_too_long_err_cnt(const struct cntr_entry
*entry
,
3962 void *context
, int vl
, int mode
,
3965 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3967 return dd
->sw_send_dma_eng_err_status_cnt
[2];
3970 static u64
access_sdma_gen_mismatch_err_cnt(const struct cntr_entry
*entry
,
3971 void *context
, int vl
, int mode
,
3974 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3976 return dd
->sw_send_dma_eng_err_status_cnt
[1];
3979 static u64
access_sdma_wrong_dw_err_cnt(const struct cntr_entry
*entry
,
3980 void *context
, int vl
, int mode
,
3983 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3985 return dd
->sw_send_dma_eng_err_status_cnt
[0];
3988 static u64
access_dc_rcv_err_cnt(const struct cntr_entry
*entry
,
3989 void *context
, int vl
, int mode
,
3992 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)context
;
3995 u64 csr
= entry
->csr
;
3997 val
= read_write_csr(dd
, csr
, mode
, data
);
3998 if (mode
== CNTR_MODE_R
) {
3999 val
= val
> CNTR_MAX
- dd
->sw_rcv_bypass_packet_errors
?
4000 CNTR_MAX
: val
+ dd
->sw_rcv_bypass_packet_errors
;
4001 } else if (mode
== CNTR_MODE_W
) {
4002 dd
->sw_rcv_bypass_packet_errors
= 0;
4004 dd_dev_err(dd
, "Invalid cntr register access mode");
4010 #define def_access_sw_cpu(cntr) \
4011 static u64 access_sw_cpu_##cntr(const struct cntr_entry *entry, \
4012 void *context, int vl, int mode, u64 data) \
4014 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context; \
4015 return read_write_cpu(ppd->dd, &ppd->ibport_data.rvp.z_ ##cntr, \
4016 ppd->ibport_data.rvp.cntr, vl, \
4020 def_access_sw_cpu(rc_acks
);
4021 def_access_sw_cpu(rc_qacks
);
4022 def_access_sw_cpu(rc_delayed_comp
);
4024 #define def_access_ibp_counter(cntr) \
4025 static u64 access_ibp_##cntr(const struct cntr_entry *entry, \
4026 void *context, int vl, int mode, u64 data) \
4028 struct hfi1_pportdata *ppd = (struct hfi1_pportdata *)context; \
4030 if (vl != CNTR_INVALID_VL) \
4033 return read_write_sw(ppd->dd, &ppd->ibport_data.rvp.n_ ##cntr, \
4037 def_access_ibp_counter(loop_pkts
);
4038 def_access_ibp_counter(rc_resends
);
4039 def_access_ibp_counter(rnr_naks
);
4040 def_access_ibp_counter(other_naks
);
4041 def_access_ibp_counter(rc_timeouts
);
4042 def_access_ibp_counter(pkt_drops
);
4043 def_access_ibp_counter(dmawait
);
4044 def_access_ibp_counter(rc_seqnak
);
4045 def_access_ibp_counter(rc_dupreq
);
4046 def_access_ibp_counter(rdma_seq
);
4047 def_access_ibp_counter(unaligned
);
4048 def_access_ibp_counter(seq_naks
);
4050 static struct cntr_entry dev_cntrs
[DEV_CNTR_LAST
] = {
4051 [C_RCV_OVF
] = RXE32_DEV_CNTR_ELEM(RcvOverflow
, RCV_BUF_OVFL_CNT
, CNTR_SYNTH
),
4052 [C_RX_TID_FULL
] = RXE32_DEV_CNTR_ELEM(RxTIDFullEr
, RCV_TID_FULL_ERR_CNT
,
4054 [C_RX_TID_INVALID
] = RXE32_DEV_CNTR_ELEM(RxTIDInvalid
, RCV_TID_VALID_ERR_CNT
,
4056 [C_RX_TID_FLGMS
] = RXE32_DEV_CNTR_ELEM(RxTidFLGMs
,
4057 RCV_TID_FLOW_GEN_MISMATCH_CNT
,
4059 [C_RX_CTX_EGRS
] = RXE32_DEV_CNTR_ELEM(RxCtxEgrS
, RCV_CONTEXT_EGR_STALL
,
4061 [C_RCV_TID_FLSMS
] = RXE32_DEV_CNTR_ELEM(RxTidFLSMs
,
4062 RCV_TID_FLOW_SEQ_MISMATCH_CNT
, CNTR_NORMAL
),
4063 [C_CCE_PCI_CR_ST
] = CCE_PERF_DEV_CNTR_ELEM(CcePciCrSt
,
4064 CCE_PCIE_POSTED_CRDT_STALL_CNT
, CNTR_NORMAL
),
4065 [C_CCE_PCI_TR_ST
] = CCE_PERF_DEV_CNTR_ELEM(CcePciTrSt
, CCE_PCIE_TRGT_STALL_CNT
,
4067 [C_CCE_PIO_WR_ST
] = CCE_PERF_DEV_CNTR_ELEM(CcePioWrSt
, CCE_PIO_WR_STALL_CNT
,
4069 [C_CCE_ERR_INT
] = CCE_INT_DEV_CNTR_ELEM(CceErrInt
, CCE_ERR_INT_CNT
,
4071 [C_CCE_SDMA_INT
] = CCE_INT_DEV_CNTR_ELEM(CceSdmaInt
, CCE_SDMA_INT_CNT
,
4073 [C_CCE_MISC_INT
] = CCE_INT_DEV_CNTR_ELEM(CceMiscInt
, CCE_MISC_INT_CNT
,
4075 [C_CCE_RCV_AV_INT
] = CCE_INT_DEV_CNTR_ELEM(CceRcvAvInt
, CCE_RCV_AVAIL_INT_CNT
,
4077 [C_CCE_RCV_URG_INT
] = CCE_INT_DEV_CNTR_ELEM(CceRcvUrgInt
,
4078 CCE_RCV_URGENT_INT_CNT
, CNTR_NORMAL
),
4079 [C_CCE_SEND_CR_INT
] = CCE_INT_DEV_CNTR_ELEM(CceSndCrInt
,
4080 CCE_SEND_CREDIT_INT_CNT
, CNTR_NORMAL
),
4081 [C_DC_UNC_ERR
] = DC_PERF_CNTR(DcUnctblErr
, DCC_ERR_UNCORRECTABLE_CNT
,
4083 [C_DC_RCV_ERR
] = CNTR_ELEM("DcRecvErr", DCC_ERR_PORTRCV_ERR_CNT
, 0, CNTR_SYNTH
,
4084 access_dc_rcv_err_cnt
),
4085 [C_DC_FM_CFG_ERR
] = DC_PERF_CNTR(DcFmCfgErr
, DCC_ERR_FMCONFIG_ERR_CNT
,
4087 [C_DC_RMT_PHY_ERR
] = DC_PERF_CNTR(DcRmtPhyErr
, DCC_ERR_RCVREMOTE_PHY_ERR_CNT
,
4089 [C_DC_DROPPED_PKT
] = DC_PERF_CNTR(DcDroppedPkt
, DCC_ERR_DROPPED_PKT_CNT
,
4091 [C_DC_MC_XMIT_PKTS
] = DC_PERF_CNTR(DcMcXmitPkts
,
4092 DCC_PRF_PORT_XMIT_MULTICAST_CNT
, CNTR_SYNTH
),
4093 [C_DC_MC_RCV_PKTS
] = DC_PERF_CNTR(DcMcRcvPkts
,
4094 DCC_PRF_PORT_RCV_MULTICAST_PKT_CNT
,
4096 [C_DC_XMIT_CERR
] = DC_PERF_CNTR(DcXmitCorr
,
4097 DCC_PRF_PORT_XMIT_CORRECTABLE_CNT
, CNTR_SYNTH
),
4098 [C_DC_RCV_CERR
] = DC_PERF_CNTR(DcRcvCorrCnt
, DCC_PRF_PORT_RCV_CORRECTABLE_CNT
,
4100 [C_DC_RCV_FCC
] = DC_PERF_CNTR(DcRxFCntl
, DCC_PRF_RX_FLOW_CRTL_CNT
,
4102 [C_DC_XMIT_FCC
] = DC_PERF_CNTR(DcXmitFCntl
, DCC_PRF_TX_FLOW_CRTL_CNT
,
4104 [C_DC_XMIT_FLITS
] = DC_PERF_CNTR(DcXmitFlits
, DCC_PRF_PORT_XMIT_DATA_CNT
,
4106 [C_DC_RCV_FLITS
] = DC_PERF_CNTR(DcRcvFlits
, DCC_PRF_PORT_RCV_DATA_CNT
,
4108 [C_DC_XMIT_PKTS
] = DC_PERF_CNTR(DcXmitPkts
, DCC_PRF_PORT_XMIT_PKTS_CNT
,
4110 [C_DC_RCV_PKTS
] = DC_PERF_CNTR(DcRcvPkts
, DCC_PRF_PORT_RCV_PKTS_CNT
,
4112 [C_DC_RX_FLIT_VL
] = DC_PERF_CNTR(DcRxFlitVl
, DCC_PRF_PORT_VL_RCV_DATA_CNT
,
4113 CNTR_SYNTH
| CNTR_VL
),
4114 [C_DC_RX_PKT_VL
] = DC_PERF_CNTR(DcRxPktVl
, DCC_PRF_PORT_VL_RCV_PKTS_CNT
,
4115 CNTR_SYNTH
| CNTR_VL
),
4116 [C_DC_RCV_FCN
] = DC_PERF_CNTR(DcRcvFcn
, DCC_PRF_PORT_RCV_FECN_CNT
, CNTR_SYNTH
),
4117 [C_DC_RCV_FCN_VL
] = DC_PERF_CNTR(DcRcvFcnVl
, DCC_PRF_PORT_VL_RCV_FECN_CNT
,
4118 CNTR_SYNTH
| CNTR_VL
),
4119 [C_DC_RCV_BCN
] = DC_PERF_CNTR(DcRcvBcn
, DCC_PRF_PORT_RCV_BECN_CNT
, CNTR_SYNTH
),
4120 [C_DC_RCV_BCN_VL
] = DC_PERF_CNTR(DcRcvBcnVl
, DCC_PRF_PORT_VL_RCV_BECN_CNT
,
4121 CNTR_SYNTH
| CNTR_VL
),
4122 [C_DC_RCV_BBL
] = DC_PERF_CNTR(DcRcvBbl
, DCC_PRF_PORT_RCV_BUBBLE_CNT
,
4124 [C_DC_RCV_BBL_VL
] = DC_PERF_CNTR(DcRcvBblVl
, DCC_PRF_PORT_VL_RCV_BUBBLE_CNT
,
4125 CNTR_SYNTH
| CNTR_VL
),
4126 [C_DC_MARK_FECN
] = DC_PERF_CNTR(DcMarkFcn
, DCC_PRF_PORT_MARK_FECN_CNT
,
4128 [C_DC_MARK_FECN_VL
] = DC_PERF_CNTR(DcMarkFcnVl
, DCC_PRF_PORT_VL_MARK_FECN_CNT
,
4129 CNTR_SYNTH
| CNTR_VL
),
4131 DC_PERF_CNTR_LCB(DcTotCrc
, DC_LCB_ERR_INFO_TOTAL_CRC_ERR
,
4133 [C_DC_CRC_LN0
] = DC_PERF_CNTR_LCB(DcCrcLn0
, DC_LCB_ERR_INFO_CRC_ERR_LN0
,
4135 [C_DC_CRC_LN1
] = DC_PERF_CNTR_LCB(DcCrcLn1
, DC_LCB_ERR_INFO_CRC_ERR_LN1
,
4137 [C_DC_CRC_LN2
] = DC_PERF_CNTR_LCB(DcCrcLn2
, DC_LCB_ERR_INFO_CRC_ERR_LN2
,
4139 [C_DC_CRC_LN3
] = DC_PERF_CNTR_LCB(DcCrcLn3
, DC_LCB_ERR_INFO_CRC_ERR_LN3
,
4141 [C_DC_CRC_MULT_LN
] =
4142 DC_PERF_CNTR_LCB(DcMultLn
, DC_LCB_ERR_INFO_CRC_ERR_MULTI_LN
,
4144 [C_DC_TX_REPLAY
] = DC_PERF_CNTR_LCB(DcTxReplay
, DC_LCB_ERR_INFO_TX_REPLAY_CNT
,
4146 [C_DC_RX_REPLAY
] = DC_PERF_CNTR_LCB(DcRxReplay
, DC_LCB_ERR_INFO_RX_REPLAY_CNT
,
4148 [C_DC_SEQ_CRC_CNT
] =
4149 DC_PERF_CNTR_LCB(DcLinkSeqCrc
, DC_LCB_ERR_INFO_SEQ_CRC_CNT
,
4151 [C_DC_ESC0_ONLY_CNT
] =
4152 DC_PERF_CNTR_LCB(DcEsc0
, DC_LCB_ERR_INFO_ESCAPE_0_ONLY_CNT
,
4154 [C_DC_ESC0_PLUS1_CNT
] =
4155 DC_PERF_CNTR_LCB(DcEsc1
, DC_LCB_ERR_INFO_ESCAPE_0_PLUS1_CNT
,
4157 [C_DC_ESC0_PLUS2_CNT
] =
4158 DC_PERF_CNTR_LCB(DcEsc0Plus2
, DC_LCB_ERR_INFO_ESCAPE_0_PLUS2_CNT
,
4160 [C_DC_REINIT_FROM_PEER_CNT
] =
4161 DC_PERF_CNTR_LCB(DcReinitPeer
, DC_LCB_ERR_INFO_REINIT_FROM_PEER_CNT
,
4163 [C_DC_SBE_CNT
] = DC_PERF_CNTR_LCB(DcSbe
, DC_LCB_ERR_INFO_SBE_CNT
,
4165 [C_DC_MISC_FLG_CNT
] =
4166 DC_PERF_CNTR_LCB(DcMiscFlg
, DC_LCB_ERR_INFO_MISC_FLG_CNT
,
4168 [C_DC_PRF_GOOD_LTP_CNT
] =
4169 DC_PERF_CNTR_LCB(DcGoodLTP
, DC_LCB_PRF_GOOD_LTP_CNT
, CNTR_SYNTH
),
4170 [C_DC_PRF_ACCEPTED_LTP_CNT
] =
4171 DC_PERF_CNTR_LCB(DcAccLTP
, DC_LCB_PRF_ACCEPTED_LTP_CNT
,
4173 [C_DC_PRF_RX_FLIT_CNT
] =
4174 DC_PERF_CNTR_LCB(DcPrfRxFlit
, DC_LCB_PRF_RX_FLIT_CNT
, CNTR_SYNTH
),
4175 [C_DC_PRF_TX_FLIT_CNT
] =
4176 DC_PERF_CNTR_LCB(DcPrfTxFlit
, DC_LCB_PRF_TX_FLIT_CNT
, CNTR_SYNTH
),
4177 [C_DC_PRF_CLK_CNTR
] =
4178 DC_PERF_CNTR_LCB(DcPrfClk
, DC_LCB_PRF_CLK_CNTR
, CNTR_SYNTH
),
4179 [C_DC_PG_DBG_FLIT_CRDTS_CNT
] =
4180 DC_PERF_CNTR_LCB(DcFltCrdts
, DC_LCB_PG_DBG_FLIT_CRDTS_CNT
, CNTR_SYNTH
),
4181 [C_DC_PG_STS_PAUSE_COMPLETE_CNT
] =
4182 DC_PERF_CNTR_LCB(DcPauseComp
, DC_LCB_PG_STS_PAUSE_COMPLETE_CNT
,
4184 [C_DC_PG_STS_TX_SBE_CNT
] =
4185 DC_PERF_CNTR_LCB(DcStsTxSbe
, DC_LCB_PG_STS_TX_SBE_CNT
, CNTR_SYNTH
),
4186 [C_DC_PG_STS_TX_MBE_CNT
] =
4187 DC_PERF_CNTR_LCB(DcStsTxMbe
, DC_LCB_PG_STS_TX_MBE_CNT
,
4189 [C_SW_CPU_INTR
] = CNTR_ELEM("Intr", 0, 0, CNTR_NORMAL
,
4190 access_sw_cpu_intr
),
4191 [C_SW_CPU_RCV_LIM
] = CNTR_ELEM("RcvLimit", 0, 0, CNTR_NORMAL
,
4192 access_sw_cpu_rcv_limit
),
4193 [C_SW_VTX_WAIT
] = CNTR_ELEM("vTxWait", 0, 0, CNTR_NORMAL
,
4194 access_sw_vtx_wait
),
4195 [C_SW_PIO_WAIT
] = CNTR_ELEM("PioWait", 0, 0, CNTR_NORMAL
,
4196 access_sw_pio_wait
),
4197 [C_SW_PIO_DRAIN
] = CNTR_ELEM("PioDrain", 0, 0, CNTR_NORMAL
,
4198 access_sw_pio_drain
),
4199 [C_SW_KMEM_WAIT
] = CNTR_ELEM("KmemWait", 0, 0, CNTR_NORMAL
,
4200 access_sw_kmem_wait
),
4201 [C_SW_SEND_SCHED
] = CNTR_ELEM("SendSched", 0, 0, CNTR_NORMAL
,
4202 access_sw_send_schedule
),
4203 [C_SDMA_DESC_FETCHED_CNT
] = CNTR_ELEM("SDEDscFdCn",
4204 SEND_DMA_DESC_FETCHED_CNT
, 0,
4205 CNTR_NORMAL
| CNTR_32BIT
| CNTR_SDMA
,
4206 dev_access_u32_csr
),
4207 [C_SDMA_INT_CNT
] = CNTR_ELEM("SDMAInt", 0, 0,
4208 CNTR_NORMAL
| CNTR_32BIT
| CNTR_SDMA
,
4209 access_sde_int_cnt
),
4210 [C_SDMA_ERR_CNT
] = CNTR_ELEM("SDMAErrCt", 0, 0,
4211 CNTR_NORMAL
| CNTR_32BIT
| CNTR_SDMA
,
4212 access_sde_err_cnt
),
4213 [C_SDMA_IDLE_INT_CNT
] = CNTR_ELEM("SDMAIdInt", 0, 0,
4214 CNTR_NORMAL
| CNTR_32BIT
| CNTR_SDMA
,
4215 access_sde_idle_int_cnt
),
4216 [C_SDMA_PROGRESS_INT_CNT
] = CNTR_ELEM("SDMAPrIntCn", 0, 0,
4217 CNTR_NORMAL
| CNTR_32BIT
| CNTR_SDMA
,
4218 access_sde_progress_int_cnt
),
4219 /* MISC_ERR_STATUS */
4220 [C_MISC_PLL_LOCK_FAIL_ERR
] = CNTR_ELEM("MISC_PLL_LOCK_FAIL_ERR", 0, 0,
4222 access_misc_pll_lock_fail_err_cnt
),
4223 [C_MISC_MBIST_FAIL_ERR
] = CNTR_ELEM("MISC_MBIST_FAIL_ERR", 0, 0,
4225 access_misc_mbist_fail_err_cnt
),
4226 [C_MISC_INVALID_EEP_CMD_ERR
] = CNTR_ELEM("MISC_INVALID_EEP_CMD_ERR", 0, 0,
4228 access_misc_invalid_eep_cmd_err_cnt
),
4229 [C_MISC_EFUSE_DONE_PARITY_ERR
] = CNTR_ELEM("MISC_EFUSE_DONE_PARITY_ERR", 0, 0,
4231 access_misc_efuse_done_parity_err_cnt
),
4232 [C_MISC_EFUSE_WRITE_ERR
] = CNTR_ELEM("MISC_EFUSE_WRITE_ERR", 0, 0,
4234 access_misc_efuse_write_err_cnt
),
4235 [C_MISC_EFUSE_READ_BAD_ADDR_ERR
] = CNTR_ELEM("MISC_EFUSE_READ_BAD_ADDR_ERR", 0,
4237 access_misc_efuse_read_bad_addr_err_cnt
),
4238 [C_MISC_EFUSE_CSR_PARITY_ERR
] = CNTR_ELEM("MISC_EFUSE_CSR_PARITY_ERR", 0, 0,
4240 access_misc_efuse_csr_parity_err_cnt
),
4241 [C_MISC_FW_AUTH_FAILED_ERR
] = CNTR_ELEM("MISC_FW_AUTH_FAILED_ERR", 0, 0,
4243 access_misc_fw_auth_failed_err_cnt
),
4244 [C_MISC_KEY_MISMATCH_ERR
] = CNTR_ELEM("MISC_KEY_MISMATCH_ERR", 0, 0,
4246 access_misc_key_mismatch_err_cnt
),
4247 [C_MISC_SBUS_WRITE_FAILED_ERR
] = CNTR_ELEM("MISC_SBUS_WRITE_FAILED_ERR", 0, 0,
4249 access_misc_sbus_write_failed_err_cnt
),
4250 [C_MISC_CSR_WRITE_BAD_ADDR_ERR
] = CNTR_ELEM("MISC_CSR_WRITE_BAD_ADDR_ERR", 0, 0,
4252 access_misc_csr_write_bad_addr_err_cnt
),
4253 [C_MISC_CSR_READ_BAD_ADDR_ERR
] = CNTR_ELEM("MISC_CSR_READ_BAD_ADDR_ERR", 0, 0,
4255 access_misc_csr_read_bad_addr_err_cnt
),
4256 [C_MISC_CSR_PARITY_ERR
] = CNTR_ELEM("MISC_CSR_PARITY_ERR", 0, 0,
4258 access_misc_csr_parity_err_cnt
),
4260 [C_CCE_ERR_STATUS_AGGREGATED_CNT
] = CNTR_ELEM("CceErrStatusAggregatedCnt", 0, 0,
4262 access_sw_cce_err_status_aggregated_cnt
),
4263 [C_CCE_MSIX_CSR_PARITY_ERR
] = CNTR_ELEM("CceMsixCsrParityErr", 0, 0,
4265 access_cce_msix_csr_parity_err_cnt
),
4266 [C_CCE_INT_MAP_UNC_ERR
] = CNTR_ELEM("CceIntMapUncErr", 0, 0,
4268 access_cce_int_map_unc_err_cnt
),
4269 [C_CCE_INT_MAP_COR_ERR
] = CNTR_ELEM("CceIntMapCorErr", 0, 0,
4271 access_cce_int_map_cor_err_cnt
),
4272 [C_CCE_MSIX_TABLE_UNC_ERR
] = CNTR_ELEM("CceMsixTableUncErr", 0, 0,
4274 access_cce_msix_table_unc_err_cnt
),
4275 [C_CCE_MSIX_TABLE_COR_ERR
] = CNTR_ELEM("CceMsixTableCorErr", 0, 0,
4277 access_cce_msix_table_cor_err_cnt
),
4278 [C_CCE_RXDMA_CONV_FIFO_PARITY_ERR
] = CNTR_ELEM("CceRxdmaConvFifoParityErr", 0,
4280 access_cce_rxdma_conv_fifo_parity_err_cnt
),
4281 [C_CCE_RCPL_ASYNC_FIFO_PARITY_ERR
] = CNTR_ELEM("CceRcplAsyncFifoParityErr", 0,
4283 access_cce_rcpl_async_fifo_parity_err_cnt
),
4284 [C_CCE_SEG_WRITE_BAD_ADDR_ERR
] = CNTR_ELEM("CceSegWriteBadAddrErr", 0, 0,
4286 access_cce_seg_write_bad_addr_err_cnt
),
4287 [C_CCE_SEG_READ_BAD_ADDR_ERR
] = CNTR_ELEM("CceSegReadBadAddrErr", 0, 0,
4289 access_cce_seg_read_bad_addr_err_cnt
),
4290 [C_LA_TRIGGERED
] = CNTR_ELEM("Cce LATriggered", 0, 0,
4292 access_la_triggered_cnt
),
4293 [C_CCE_TRGT_CPL_TIMEOUT_ERR
] = CNTR_ELEM("CceTrgtCplTimeoutErr", 0, 0,
4295 access_cce_trgt_cpl_timeout_err_cnt
),
4296 [C_PCIC_RECEIVE_PARITY_ERR
] = CNTR_ELEM("PcicReceiveParityErr", 0, 0,
4298 access_pcic_receive_parity_err_cnt
),
4299 [C_PCIC_TRANSMIT_BACK_PARITY_ERR
] = CNTR_ELEM("PcicTransmitBackParityErr", 0, 0,
4301 access_pcic_transmit_back_parity_err_cnt
),
4302 [C_PCIC_TRANSMIT_FRONT_PARITY_ERR
] = CNTR_ELEM("PcicTransmitFrontParityErr", 0,
4304 access_pcic_transmit_front_parity_err_cnt
),
4305 [C_PCIC_CPL_DAT_Q_UNC_ERR
] = CNTR_ELEM("PcicCplDatQUncErr", 0, 0,
4307 access_pcic_cpl_dat_q_unc_err_cnt
),
4308 [C_PCIC_CPL_HD_Q_UNC_ERR
] = CNTR_ELEM("PcicCplHdQUncErr", 0, 0,
4310 access_pcic_cpl_hd_q_unc_err_cnt
),
4311 [C_PCIC_POST_DAT_Q_UNC_ERR
] = CNTR_ELEM("PcicPostDatQUncErr", 0, 0,
4313 access_pcic_post_dat_q_unc_err_cnt
),
4314 [C_PCIC_POST_HD_Q_UNC_ERR
] = CNTR_ELEM("PcicPostHdQUncErr", 0, 0,
4316 access_pcic_post_hd_q_unc_err_cnt
),
4317 [C_PCIC_RETRY_SOT_MEM_UNC_ERR
] = CNTR_ELEM("PcicRetrySotMemUncErr", 0, 0,
4319 access_pcic_retry_sot_mem_unc_err_cnt
),
4320 [C_PCIC_RETRY_MEM_UNC_ERR
] = CNTR_ELEM("PcicRetryMemUncErr", 0, 0,
4322 access_pcic_retry_mem_unc_err
),
4323 [C_PCIC_N_POST_DAT_Q_PARITY_ERR
] = CNTR_ELEM("PcicNPostDatQParityErr", 0, 0,
4325 access_pcic_n_post_dat_q_parity_err_cnt
),
4326 [C_PCIC_N_POST_H_Q_PARITY_ERR
] = CNTR_ELEM("PcicNPostHQParityErr", 0, 0,
4328 access_pcic_n_post_h_q_parity_err_cnt
),
4329 [C_PCIC_CPL_DAT_Q_COR_ERR
] = CNTR_ELEM("PcicCplDatQCorErr", 0, 0,
4331 access_pcic_cpl_dat_q_cor_err_cnt
),
4332 [C_PCIC_CPL_HD_Q_COR_ERR
] = CNTR_ELEM("PcicCplHdQCorErr", 0, 0,
4334 access_pcic_cpl_hd_q_cor_err_cnt
),
4335 [C_PCIC_POST_DAT_Q_COR_ERR
] = CNTR_ELEM("PcicPostDatQCorErr", 0, 0,
4337 access_pcic_post_dat_q_cor_err_cnt
),
4338 [C_PCIC_POST_HD_Q_COR_ERR
] = CNTR_ELEM("PcicPostHdQCorErr", 0, 0,
4340 access_pcic_post_hd_q_cor_err_cnt
),
4341 [C_PCIC_RETRY_SOT_MEM_COR_ERR
] = CNTR_ELEM("PcicRetrySotMemCorErr", 0, 0,
4343 access_pcic_retry_sot_mem_cor_err_cnt
),
4344 [C_PCIC_RETRY_MEM_COR_ERR
] = CNTR_ELEM("PcicRetryMemCorErr", 0, 0,
4346 access_pcic_retry_mem_cor_err_cnt
),
4347 [C_CCE_CLI1_ASYNC_FIFO_DBG_PARITY_ERR
] = CNTR_ELEM(
4348 "CceCli1AsyncFifoDbgParityError", 0, 0,
4350 access_cce_cli1_async_fifo_dbg_parity_err_cnt
),
4351 [C_CCE_CLI1_ASYNC_FIFO_RXDMA_PARITY_ERR
] = CNTR_ELEM(
4352 "CceCli1AsyncFifoRxdmaParityError", 0, 0,
4354 access_cce_cli1_async_fifo_rxdma_parity_err_cnt
4356 [C_CCE_CLI1_ASYNC_FIFO_SDMA_HD_PARITY_ERR
] = CNTR_ELEM(
4357 "CceCli1AsyncFifoSdmaHdParityErr", 0, 0,
4359 access_cce_cli1_async_fifo_sdma_hd_parity_err_cnt
),
4360 [C_CCE_CLI1_ASYNC_FIFO_PIO_CRDT_PARITY_ERR
] = CNTR_ELEM(
4361 "CceCli1AsyncFifoPioCrdtParityErr", 0, 0,
4363 access_cce_cl1_async_fifo_pio_crdt_parity_err_cnt
),
4364 [C_CCE_CLI2_ASYNC_FIFO_PARITY_ERR
] = CNTR_ELEM("CceCli2AsyncFifoParityErr", 0,
4366 access_cce_cli2_async_fifo_parity_err_cnt
),
4367 [C_CCE_CSR_CFG_BUS_PARITY_ERR
] = CNTR_ELEM("CceCsrCfgBusParityErr", 0, 0,
4369 access_cce_csr_cfg_bus_parity_err_cnt
),
4370 [C_CCE_CLI0_ASYNC_FIFO_PARTIY_ERR
] = CNTR_ELEM("CceCli0AsyncFifoParityErr", 0,
4372 access_cce_cli0_async_fifo_parity_err_cnt
),
4373 [C_CCE_RSPD_DATA_PARITY_ERR
] = CNTR_ELEM("CceRspdDataParityErr", 0, 0,
4375 access_cce_rspd_data_parity_err_cnt
),
4376 [C_CCE_TRGT_ACCESS_ERR
] = CNTR_ELEM("CceTrgtAccessErr", 0, 0,
4378 access_cce_trgt_access_err_cnt
),
4379 [C_CCE_TRGT_ASYNC_FIFO_PARITY_ERR
] = CNTR_ELEM("CceTrgtAsyncFifoParityErr", 0,
4381 access_cce_trgt_async_fifo_parity_err_cnt
),
4382 [C_CCE_CSR_WRITE_BAD_ADDR_ERR
] = CNTR_ELEM("CceCsrWriteBadAddrErr", 0, 0,
4384 access_cce_csr_write_bad_addr_err_cnt
),
4385 [C_CCE_CSR_READ_BAD_ADDR_ERR
] = CNTR_ELEM("CceCsrReadBadAddrErr", 0, 0,
4387 access_cce_csr_read_bad_addr_err_cnt
),
4388 [C_CCE_CSR_PARITY_ERR
] = CNTR_ELEM("CceCsrParityErr", 0, 0,
4390 access_ccs_csr_parity_err_cnt
),
4393 [C_RX_CSR_PARITY_ERR
] = CNTR_ELEM("RxCsrParityErr", 0, 0,
4395 access_rx_csr_parity_err_cnt
),
4396 [C_RX_CSR_WRITE_BAD_ADDR_ERR
] = CNTR_ELEM("RxCsrWriteBadAddrErr", 0, 0,
4398 access_rx_csr_write_bad_addr_err_cnt
),
4399 [C_RX_CSR_READ_BAD_ADDR_ERR
] = CNTR_ELEM("RxCsrReadBadAddrErr", 0, 0,
4401 access_rx_csr_read_bad_addr_err_cnt
),
4402 [C_RX_DMA_CSR_UNC_ERR
] = CNTR_ELEM("RxDmaCsrUncErr", 0, 0,
4404 access_rx_dma_csr_unc_err_cnt
),
4405 [C_RX_DMA_DQ_FSM_ENCODING_ERR
] = CNTR_ELEM("RxDmaDqFsmEncodingErr", 0, 0,
4407 access_rx_dma_dq_fsm_encoding_err_cnt
),
4408 [C_RX_DMA_EQ_FSM_ENCODING_ERR
] = CNTR_ELEM("RxDmaEqFsmEncodingErr", 0, 0,
4410 access_rx_dma_eq_fsm_encoding_err_cnt
),
4411 [C_RX_DMA_CSR_PARITY_ERR
] = CNTR_ELEM("RxDmaCsrParityErr", 0, 0,
4413 access_rx_dma_csr_parity_err_cnt
),
4414 [C_RX_RBUF_DATA_COR_ERR
] = CNTR_ELEM("RxRbufDataCorErr", 0, 0,
4416 access_rx_rbuf_data_cor_err_cnt
),
4417 [C_RX_RBUF_DATA_UNC_ERR
] = CNTR_ELEM("RxRbufDataUncErr", 0, 0,
4419 access_rx_rbuf_data_unc_err_cnt
),
4420 [C_RX_DMA_DATA_FIFO_RD_COR_ERR
] = CNTR_ELEM("RxDmaDataFifoRdCorErr", 0, 0,
4422 access_rx_dma_data_fifo_rd_cor_err_cnt
),
4423 [C_RX_DMA_DATA_FIFO_RD_UNC_ERR
] = CNTR_ELEM("RxDmaDataFifoRdUncErr", 0, 0,
4425 access_rx_dma_data_fifo_rd_unc_err_cnt
),
4426 [C_RX_DMA_HDR_FIFO_RD_COR_ERR
] = CNTR_ELEM("RxDmaHdrFifoRdCorErr", 0, 0,
4428 access_rx_dma_hdr_fifo_rd_cor_err_cnt
),
4429 [C_RX_DMA_HDR_FIFO_RD_UNC_ERR
] = CNTR_ELEM("RxDmaHdrFifoRdUncErr", 0, 0,
4431 access_rx_dma_hdr_fifo_rd_unc_err_cnt
),
4432 [C_RX_RBUF_DESC_PART2_COR_ERR
] = CNTR_ELEM("RxRbufDescPart2CorErr", 0, 0,
4434 access_rx_rbuf_desc_part2_cor_err_cnt
),
4435 [C_RX_RBUF_DESC_PART2_UNC_ERR
] = CNTR_ELEM("RxRbufDescPart2UncErr", 0, 0,
4437 access_rx_rbuf_desc_part2_unc_err_cnt
),
4438 [C_RX_RBUF_DESC_PART1_COR_ERR
] = CNTR_ELEM("RxRbufDescPart1CorErr", 0, 0,
4440 access_rx_rbuf_desc_part1_cor_err_cnt
),
4441 [C_RX_RBUF_DESC_PART1_UNC_ERR
] = CNTR_ELEM("RxRbufDescPart1UncErr", 0, 0,
4443 access_rx_rbuf_desc_part1_unc_err_cnt
),
4444 [C_RX_HQ_INTR_FSM_ERR
] = CNTR_ELEM("RxHqIntrFsmErr", 0, 0,
4446 access_rx_hq_intr_fsm_err_cnt
),
4447 [C_RX_HQ_INTR_CSR_PARITY_ERR
] = CNTR_ELEM("RxHqIntrCsrParityErr", 0, 0,
4449 access_rx_hq_intr_csr_parity_err_cnt
),
4450 [C_RX_LOOKUP_CSR_PARITY_ERR
] = CNTR_ELEM("RxLookupCsrParityErr", 0, 0,
4452 access_rx_lookup_csr_parity_err_cnt
),
4453 [C_RX_LOOKUP_RCV_ARRAY_COR_ERR
] = CNTR_ELEM("RxLookupRcvArrayCorErr", 0, 0,
4455 access_rx_lookup_rcv_array_cor_err_cnt
),
4456 [C_RX_LOOKUP_RCV_ARRAY_UNC_ERR
] = CNTR_ELEM("RxLookupRcvArrayUncErr", 0, 0,
4458 access_rx_lookup_rcv_array_unc_err_cnt
),
4459 [C_RX_LOOKUP_DES_PART2_PARITY_ERR
] = CNTR_ELEM("RxLookupDesPart2ParityErr", 0,
4461 access_rx_lookup_des_part2_parity_err_cnt
),
4462 [C_RX_LOOKUP_DES_PART1_UNC_COR_ERR
] = CNTR_ELEM("RxLookupDesPart1UncCorErr", 0,
4464 access_rx_lookup_des_part1_unc_cor_err_cnt
),
4465 [C_RX_LOOKUP_DES_PART1_UNC_ERR
] = CNTR_ELEM("RxLookupDesPart1UncErr", 0, 0,
4467 access_rx_lookup_des_part1_unc_err_cnt
),
4468 [C_RX_RBUF_NEXT_FREE_BUF_COR_ERR
] = CNTR_ELEM("RxRbufNextFreeBufCorErr", 0, 0,
4470 access_rx_rbuf_next_free_buf_cor_err_cnt
),
4471 [C_RX_RBUF_NEXT_FREE_BUF_UNC_ERR
] = CNTR_ELEM("RxRbufNextFreeBufUncErr", 0, 0,
4473 access_rx_rbuf_next_free_buf_unc_err_cnt
),
4474 [C_RX_RBUF_FL_INIT_WR_ADDR_PARITY_ERR
] = CNTR_ELEM(
4475 "RxRbufFlInitWrAddrParityErr", 0, 0,
4477 access_rbuf_fl_init_wr_addr_parity_err_cnt
),
4478 [C_RX_RBUF_FL_INITDONE_PARITY_ERR
] = CNTR_ELEM("RxRbufFlInitdoneParityErr", 0,
4480 access_rx_rbuf_fl_initdone_parity_err_cnt
),
4481 [C_RX_RBUF_FL_WRITE_ADDR_PARITY_ERR
] = CNTR_ELEM("RxRbufFlWrAddrParityErr", 0,
4483 access_rx_rbuf_fl_write_addr_parity_err_cnt
),
4484 [C_RX_RBUF_FL_RD_ADDR_PARITY_ERR
] = CNTR_ELEM("RxRbufFlRdAddrParityErr", 0, 0,
4486 access_rx_rbuf_fl_rd_addr_parity_err_cnt
),
4487 [C_RX_RBUF_EMPTY_ERR
] = CNTR_ELEM("RxRbufEmptyErr", 0, 0,
4489 access_rx_rbuf_empty_err_cnt
),
4490 [C_RX_RBUF_FULL_ERR
] = CNTR_ELEM("RxRbufFullErr", 0, 0,
4492 access_rx_rbuf_full_err_cnt
),
4493 [C_RX_RBUF_BAD_LOOKUP_ERR
] = CNTR_ELEM("RxRBufBadLookupErr", 0, 0,
4495 access_rbuf_bad_lookup_err_cnt
),
4496 [C_RX_RBUF_CTX_ID_PARITY_ERR
] = CNTR_ELEM("RxRbufCtxIdParityErr", 0, 0,
4498 access_rbuf_ctx_id_parity_err_cnt
),
4499 [C_RX_RBUF_CSR_QEOPDW_PARITY_ERR
] = CNTR_ELEM("RxRbufCsrQEOPDWParityErr", 0, 0,
4501 access_rbuf_csr_qeopdw_parity_err_cnt
),
4502 [C_RX_RBUF_CSR_Q_NUM_OF_PKT_PARITY_ERR
] = CNTR_ELEM(
4503 "RxRbufCsrQNumOfPktParityErr", 0, 0,
4505 access_rx_rbuf_csr_q_num_of_pkt_parity_err_cnt
),
4506 [C_RX_RBUF_CSR_Q_T1_PTR_PARITY_ERR
] = CNTR_ELEM(
4507 "RxRbufCsrQTlPtrParityErr", 0, 0,
4509 access_rx_rbuf_csr_q_t1_ptr_parity_err_cnt
),
4510 [C_RX_RBUF_CSR_Q_HD_PTR_PARITY_ERR
] = CNTR_ELEM("RxRbufCsrQHdPtrParityErr", 0,
4512 access_rx_rbuf_csr_q_hd_ptr_parity_err_cnt
),
4513 [C_RX_RBUF_CSR_Q_VLD_BIT_PARITY_ERR
] = CNTR_ELEM("RxRbufCsrQVldBitParityErr", 0,
4515 access_rx_rbuf_csr_q_vld_bit_parity_err_cnt
),
4516 [C_RX_RBUF_CSR_Q_NEXT_BUF_PARITY_ERR
] = CNTR_ELEM("RxRbufCsrQNextBufParityErr",
4518 access_rx_rbuf_csr_q_next_buf_parity_err_cnt
),
4519 [C_RX_RBUF_CSR_Q_ENT_CNT_PARITY_ERR
] = CNTR_ELEM("RxRbufCsrQEntCntParityErr", 0,
4521 access_rx_rbuf_csr_q_ent_cnt_parity_err_cnt
),
4522 [C_RX_RBUF_CSR_Q_HEAD_BUF_NUM_PARITY_ERR
] = CNTR_ELEM(
4523 "RxRbufCsrQHeadBufNumParityErr", 0, 0,
4525 access_rx_rbuf_csr_q_head_buf_num_parity_err_cnt
),
4526 [C_RX_RBUF_BLOCK_LIST_READ_COR_ERR
] = CNTR_ELEM("RxRbufBlockListReadCorErr", 0,
4528 access_rx_rbuf_block_list_read_cor_err_cnt
),
4529 [C_RX_RBUF_BLOCK_LIST_READ_UNC_ERR
] = CNTR_ELEM("RxRbufBlockListReadUncErr", 0,
4531 access_rx_rbuf_block_list_read_unc_err_cnt
),
4532 [C_RX_RBUF_LOOKUP_DES_COR_ERR
] = CNTR_ELEM("RxRbufLookupDesCorErr", 0, 0,
4534 access_rx_rbuf_lookup_des_cor_err_cnt
),
4535 [C_RX_RBUF_LOOKUP_DES_UNC_ERR
] = CNTR_ELEM("RxRbufLookupDesUncErr", 0, 0,
4537 access_rx_rbuf_lookup_des_unc_err_cnt
),
4538 [C_RX_RBUF_LOOKUP_DES_REG_UNC_COR_ERR
] = CNTR_ELEM(
4539 "RxRbufLookupDesRegUncCorErr", 0, 0,
4541 access_rx_rbuf_lookup_des_reg_unc_cor_err_cnt
),
4542 [C_RX_RBUF_LOOKUP_DES_REG_UNC_ERR
] = CNTR_ELEM("RxRbufLookupDesRegUncErr", 0, 0,
4544 access_rx_rbuf_lookup_des_reg_unc_err_cnt
),
4545 [C_RX_RBUF_FREE_LIST_COR_ERR
] = CNTR_ELEM("RxRbufFreeListCorErr", 0, 0,
4547 access_rx_rbuf_free_list_cor_err_cnt
),
4548 [C_RX_RBUF_FREE_LIST_UNC_ERR
] = CNTR_ELEM("RxRbufFreeListUncErr", 0, 0,
4550 access_rx_rbuf_free_list_unc_err_cnt
),
4551 [C_RX_RCV_FSM_ENCODING_ERR
] = CNTR_ELEM("RxRcvFsmEncodingErr", 0, 0,
4553 access_rx_rcv_fsm_encoding_err_cnt
),
4554 [C_RX_DMA_FLAG_COR_ERR
] = CNTR_ELEM("RxDmaFlagCorErr", 0, 0,
4556 access_rx_dma_flag_cor_err_cnt
),
4557 [C_RX_DMA_FLAG_UNC_ERR
] = CNTR_ELEM("RxDmaFlagUncErr", 0, 0,
4559 access_rx_dma_flag_unc_err_cnt
),
4560 [C_RX_DC_SOP_EOP_PARITY_ERR
] = CNTR_ELEM("RxDcSopEopParityErr", 0, 0,
4562 access_rx_dc_sop_eop_parity_err_cnt
),
4563 [C_RX_RCV_CSR_PARITY_ERR
] = CNTR_ELEM("RxRcvCsrParityErr", 0, 0,
4565 access_rx_rcv_csr_parity_err_cnt
),
4566 [C_RX_RCV_QP_MAP_TABLE_COR_ERR
] = CNTR_ELEM("RxRcvQpMapTableCorErr", 0, 0,
4568 access_rx_rcv_qp_map_table_cor_err_cnt
),
4569 [C_RX_RCV_QP_MAP_TABLE_UNC_ERR
] = CNTR_ELEM("RxRcvQpMapTableUncErr", 0, 0,
4571 access_rx_rcv_qp_map_table_unc_err_cnt
),
4572 [C_RX_RCV_DATA_COR_ERR
] = CNTR_ELEM("RxRcvDataCorErr", 0, 0,
4574 access_rx_rcv_data_cor_err_cnt
),
4575 [C_RX_RCV_DATA_UNC_ERR
] = CNTR_ELEM("RxRcvDataUncErr", 0, 0,
4577 access_rx_rcv_data_unc_err_cnt
),
4578 [C_RX_RCV_HDR_COR_ERR
] = CNTR_ELEM("RxRcvHdrCorErr", 0, 0,
4580 access_rx_rcv_hdr_cor_err_cnt
),
4581 [C_RX_RCV_HDR_UNC_ERR
] = CNTR_ELEM("RxRcvHdrUncErr", 0, 0,
4583 access_rx_rcv_hdr_unc_err_cnt
),
4584 [C_RX_DC_INTF_PARITY_ERR
] = CNTR_ELEM("RxDcIntfParityErr", 0, 0,
4586 access_rx_dc_intf_parity_err_cnt
),
4587 [C_RX_DMA_CSR_COR_ERR
] = CNTR_ELEM("RxDmaCsrCorErr", 0, 0,
4589 access_rx_dma_csr_cor_err_cnt
),
4590 /* SendPioErrStatus */
4591 [C_PIO_PEC_SOP_HEAD_PARITY_ERR
] = CNTR_ELEM("PioPecSopHeadParityErr", 0, 0,
4593 access_pio_pec_sop_head_parity_err_cnt
),
4594 [C_PIO_PCC_SOP_HEAD_PARITY_ERR
] = CNTR_ELEM("PioPccSopHeadParityErr", 0, 0,
4596 access_pio_pcc_sop_head_parity_err_cnt
),
4597 [C_PIO_LAST_RETURNED_CNT_PARITY_ERR
] = CNTR_ELEM("PioLastReturnedCntParityErr",
4599 access_pio_last_returned_cnt_parity_err_cnt
),
4600 [C_PIO_CURRENT_FREE_CNT_PARITY_ERR
] = CNTR_ELEM("PioCurrentFreeCntParityErr", 0,
4602 access_pio_current_free_cnt_parity_err_cnt
),
4603 [C_PIO_RSVD_31_ERR
] = CNTR_ELEM("Pio Reserved 31", 0, 0,
4605 access_pio_reserved_31_err_cnt
),
4606 [C_PIO_RSVD_30_ERR
] = CNTR_ELEM("Pio Reserved 30", 0, 0,
4608 access_pio_reserved_30_err_cnt
),
4609 [C_PIO_PPMC_SOP_LEN_ERR
] = CNTR_ELEM("PioPpmcSopLenErr", 0, 0,
4611 access_pio_ppmc_sop_len_err_cnt
),
4612 [C_PIO_PPMC_BQC_MEM_PARITY_ERR
] = CNTR_ELEM("PioPpmcBqcMemParityErr", 0, 0,
4614 access_pio_ppmc_bqc_mem_parity_err_cnt
),
4615 [C_PIO_VL_FIFO_PARITY_ERR
] = CNTR_ELEM("PioVlFifoParityErr", 0, 0,
4617 access_pio_vl_fifo_parity_err_cnt
),
4618 [C_PIO_VLF_SOP_PARITY_ERR
] = CNTR_ELEM("PioVlfSopParityErr", 0, 0,
4620 access_pio_vlf_sop_parity_err_cnt
),
4621 [C_PIO_VLF_V1_LEN_PARITY_ERR
] = CNTR_ELEM("PioVlfVlLenParityErr", 0, 0,
4623 access_pio_vlf_v1_len_parity_err_cnt
),
4624 [C_PIO_BLOCK_QW_COUNT_PARITY_ERR
] = CNTR_ELEM("PioBlockQwCountParityErr", 0, 0,
4626 access_pio_block_qw_count_parity_err_cnt
),
4627 [C_PIO_WRITE_QW_VALID_PARITY_ERR
] = CNTR_ELEM("PioWriteQwValidParityErr", 0, 0,
4629 access_pio_write_qw_valid_parity_err_cnt
),
4630 [C_PIO_STATE_MACHINE_ERR
] = CNTR_ELEM("PioStateMachineErr", 0, 0,
4632 access_pio_state_machine_err_cnt
),
4633 [C_PIO_WRITE_DATA_PARITY_ERR
] = CNTR_ELEM("PioWriteDataParityErr", 0, 0,
4635 access_pio_write_data_parity_err_cnt
),
4636 [C_PIO_HOST_ADDR_MEM_COR_ERR
] = CNTR_ELEM("PioHostAddrMemCorErr", 0, 0,
4638 access_pio_host_addr_mem_cor_err_cnt
),
4639 [C_PIO_HOST_ADDR_MEM_UNC_ERR
] = CNTR_ELEM("PioHostAddrMemUncErr", 0, 0,
4641 access_pio_host_addr_mem_unc_err_cnt
),
4642 [C_PIO_PKT_EVICT_SM_OR_ARM_SM_ERR
] = CNTR_ELEM("PioPktEvictSmOrArbSmErr", 0, 0,
4644 access_pio_pkt_evict_sm_or_arb_sm_err_cnt
),
4645 [C_PIO_INIT_SM_IN_ERR
] = CNTR_ELEM("PioInitSmInErr", 0, 0,
4647 access_pio_init_sm_in_err_cnt
),
4648 [C_PIO_PPMC_PBL_FIFO_ERR
] = CNTR_ELEM("PioPpmcPblFifoErr", 0, 0,
4650 access_pio_ppmc_pbl_fifo_err_cnt
),
4651 [C_PIO_CREDIT_RET_FIFO_PARITY_ERR
] = CNTR_ELEM("PioCreditRetFifoParityErr", 0,
4653 access_pio_credit_ret_fifo_parity_err_cnt
),
4654 [C_PIO_V1_LEN_MEM_BANK1_COR_ERR
] = CNTR_ELEM("PioVlLenMemBank1CorErr", 0, 0,
4656 access_pio_v1_len_mem_bank1_cor_err_cnt
),
4657 [C_PIO_V1_LEN_MEM_BANK0_COR_ERR
] = CNTR_ELEM("PioVlLenMemBank0CorErr", 0, 0,
4659 access_pio_v1_len_mem_bank0_cor_err_cnt
),
4660 [C_PIO_V1_LEN_MEM_BANK1_UNC_ERR
] = CNTR_ELEM("PioVlLenMemBank1UncErr", 0, 0,
4662 access_pio_v1_len_mem_bank1_unc_err_cnt
),
4663 [C_PIO_V1_LEN_MEM_BANK0_UNC_ERR
] = CNTR_ELEM("PioVlLenMemBank0UncErr", 0, 0,
4665 access_pio_v1_len_mem_bank0_unc_err_cnt
),
4666 [C_PIO_SM_PKT_RESET_PARITY_ERR
] = CNTR_ELEM("PioSmPktResetParityErr", 0, 0,
4668 access_pio_sm_pkt_reset_parity_err_cnt
),
4669 [C_PIO_PKT_EVICT_FIFO_PARITY_ERR
] = CNTR_ELEM("PioPktEvictFifoParityErr", 0, 0,
4671 access_pio_pkt_evict_fifo_parity_err_cnt
),
4672 [C_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR
] = CNTR_ELEM(
4673 "PioSbrdctrlCrrelFifoParityErr", 0, 0,
4675 access_pio_sbrdctrl_crrel_fifo_parity_err_cnt
),
4676 [C_PIO_SBRDCTL_CRREL_PARITY_ERR
] = CNTR_ELEM("PioSbrdctlCrrelParityErr", 0, 0,
4678 access_pio_sbrdctl_crrel_parity_err_cnt
),
4679 [C_PIO_PEC_FIFO_PARITY_ERR
] = CNTR_ELEM("PioPecFifoParityErr", 0, 0,
4681 access_pio_pec_fifo_parity_err_cnt
),
4682 [C_PIO_PCC_FIFO_PARITY_ERR
] = CNTR_ELEM("PioPccFifoParityErr", 0, 0,
4684 access_pio_pcc_fifo_parity_err_cnt
),
4685 [C_PIO_SB_MEM_FIFO1_ERR
] = CNTR_ELEM("PioSbMemFifo1Err", 0, 0,
4687 access_pio_sb_mem_fifo1_err_cnt
),
4688 [C_PIO_SB_MEM_FIFO0_ERR
] = CNTR_ELEM("PioSbMemFifo0Err", 0, 0,
4690 access_pio_sb_mem_fifo0_err_cnt
),
4691 [C_PIO_CSR_PARITY_ERR
] = CNTR_ELEM("PioCsrParityErr", 0, 0,
4693 access_pio_csr_parity_err_cnt
),
4694 [C_PIO_WRITE_ADDR_PARITY_ERR
] = CNTR_ELEM("PioWriteAddrParityErr", 0, 0,
4696 access_pio_write_addr_parity_err_cnt
),
4697 [C_PIO_WRITE_BAD_CTXT_ERR
] = CNTR_ELEM("PioWriteBadCtxtErr", 0, 0,
4699 access_pio_write_bad_ctxt_err_cnt
),
4700 /* SendDmaErrStatus */
4701 [C_SDMA_PCIE_REQ_TRACKING_COR_ERR
] = CNTR_ELEM("SDmaPcieReqTrackingCorErr", 0,
4703 access_sdma_pcie_req_tracking_cor_err_cnt
),
4704 [C_SDMA_PCIE_REQ_TRACKING_UNC_ERR
] = CNTR_ELEM("SDmaPcieReqTrackingUncErr", 0,
4706 access_sdma_pcie_req_tracking_unc_err_cnt
),
4707 [C_SDMA_CSR_PARITY_ERR
] = CNTR_ELEM("SDmaCsrParityErr", 0, 0,
4709 access_sdma_csr_parity_err_cnt
),
4710 [C_SDMA_RPY_TAG_ERR
] = CNTR_ELEM("SDmaRpyTagErr", 0, 0,
4712 access_sdma_rpy_tag_err_cnt
),
4713 /* SendEgressErrStatus */
4714 [C_TX_READ_PIO_MEMORY_CSR_UNC_ERR
] = CNTR_ELEM("TxReadPioMemoryCsrUncErr", 0, 0,
4716 access_tx_read_pio_memory_csr_unc_err_cnt
),
4717 [C_TX_READ_SDMA_MEMORY_CSR_UNC_ERR
] = CNTR_ELEM("TxReadSdmaMemoryCsrUncErr", 0,
4719 access_tx_read_sdma_memory_csr_err_cnt
),
4720 [C_TX_EGRESS_FIFO_COR_ERR
] = CNTR_ELEM("TxEgressFifoCorErr", 0, 0,
4722 access_tx_egress_fifo_cor_err_cnt
),
4723 [C_TX_READ_PIO_MEMORY_COR_ERR
] = CNTR_ELEM("TxReadPioMemoryCorErr", 0, 0,
4725 access_tx_read_pio_memory_cor_err_cnt
),
4726 [C_TX_READ_SDMA_MEMORY_COR_ERR
] = CNTR_ELEM("TxReadSdmaMemoryCorErr", 0, 0,
4728 access_tx_read_sdma_memory_cor_err_cnt
),
4729 [C_TX_SB_HDR_COR_ERR
] = CNTR_ELEM("TxSbHdrCorErr", 0, 0,
4731 access_tx_sb_hdr_cor_err_cnt
),
4732 [C_TX_CREDIT_OVERRUN_ERR
] = CNTR_ELEM("TxCreditOverrunErr", 0, 0,
4734 access_tx_credit_overrun_err_cnt
),
4735 [C_TX_LAUNCH_FIFO8_COR_ERR
] = CNTR_ELEM("TxLaunchFifo8CorErr", 0, 0,
4737 access_tx_launch_fifo8_cor_err_cnt
),
4738 [C_TX_LAUNCH_FIFO7_COR_ERR
] = CNTR_ELEM("TxLaunchFifo7CorErr", 0, 0,
4740 access_tx_launch_fifo7_cor_err_cnt
),
4741 [C_TX_LAUNCH_FIFO6_COR_ERR
] = CNTR_ELEM("TxLaunchFifo6CorErr", 0, 0,
4743 access_tx_launch_fifo6_cor_err_cnt
),
4744 [C_TX_LAUNCH_FIFO5_COR_ERR
] = CNTR_ELEM("TxLaunchFifo5CorErr", 0, 0,
4746 access_tx_launch_fifo5_cor_err_cnt
),
4747 [C_TX_LAUNCH_FIFO4_COR_ERR
] = CNTR_ELEM("TxLaunchFifo4CorErr", 0, 0,
4749 access_tx_launch_fifo4_cor_err_cnt
),
4750 [C_TX_LAUNCH_FIFO3_COR_ERR
] = CNTR_ELEM("TxLaunchFifo3CorErr", 0, 0,
4752 access_tx_launch_fifo3_cor_err_cnt
),
4753 [C_TX_LAUNCH_FIFO2_COR_ERR
] = CNTR_ELEM("TxLaunchFifo2CorErr", 0, 0,
4755 access_tx_launch_fifo2_cor_err_cnt
),
4756 [C_TX_LAUNCH_FIFO1_COR_ERR
] = CNTR_ELEM("TxLaunchFifo1CorErr", 0, 0,
4758 access_tx_launch_fifo1_cor_err_cnt
),
4759 [C_TX_LAUNCH_FIFO0_COR_ERR
] = CNTR_ELEM("TxLaunchFifo0CorErr", 0, 0,
4761 access_tx_launch_fifo0_cor_err_cnt
),
4762 [C_TX_CREDIT_RETURN_VL_ERR
] = CNTR_ELEM("TxCreditReturnVLErr", 0, 0,
4764 access_tx_credit_return_vl_err_cnt
),
4765 [C_TX_HCRC_INSERTION_ERR
] = CNTR_ELEM("TxHcrcInsertionErr", 0, 0,
4767 access_tx_hcrc_insertion_err_cnt
),
4768 [C_TX_EGRESS_FIFI_UNC_ERR
] = CNTR_ELEM("TxEgressFifoUncErr", 0, 0,
4770 access_tx_egress_fifo_unc_err_cnt
),
4771 [C_TX_READ_PIO_MEMORY_UNC_ERR
] = CNTR_ELEM("TxReadPioMemoryUncErr", 0, 0,
4773 access_tx_read_pio_memory_unc_err_cnt
),
4774 [C_TX_READ_SDMA_MEMORY_UNC_ERR
] = CNTR_ELEM("TxReadSdmaMemoryUncErr", 0, 0,
4776 access_tx_read_sdma_memory_unc_err_cnt
),
4777 [C_TX_SB_HDR_UNC_ERR
] = CNTR_ELEM("TxSbHdrUncErr", 0, 0,
4779 access_tx_sb_hdr_unc_err_cnt
),
4780 [C_TX_CREDIT_RETURN_PARITY_ERR
] = CNTR_ELEM("TxCreditReturnParityErr", 0, 0,
4782 access_tx_credit_return_partiy_err_cnt
),
4783 [C_TX_LAUNCH_FIFO8_UNC_OR_PARITY_ERR
] = CNTR_ELEM("TxLaunchFifo8UncOrParityErr",
4785 access_tx_launch_fifo8_unc_or_parity_err_cnt
),
4786 [C_TX_LAUNCH_FIFO7_UNC_OR_PARITY_ERR
] = CNTR_ELEM("TxLaunchFifo7UncOrParityErr",
4788 access_tx_launch_fifo7_unc_or_parity_err_cnt
),
4789 [C_TX_LAUNCH_FIFO6_UNC_OR_PARITY_ERR
] = CNTR_ELEM("TxLaunchFifo6UncOrParityErr",
4791 access_tx_launch_fifo6_unc_or_parity_err_cnt
),
4792 [C_TX_LAUNCH_FIFO5_UNC_OR_PARITY_ERR
] = CNTR_ELEM("TxLaunchFifo5UncOrParityErr",
4794 access_tx_launch_fifo5_unc_or_parity_err_cnt
),
4795 [C_TX_LAUNCH_FIFO4_UNC_OR_PARITY_ERR
] = CNTR_ELEM("TxLaunchFifo4UncOrParityErr",
4797 access_tx_launch_fifo4_unc_or_parity_err_cnt
),
4798 [C_TX_LAUNCH_FIFO3_UNC_OR_PARITY_ERR
] = CNTR_ELEM("TxLaunchFifo3UncOrParityErr",
4800 access_tx_launch_fifo3_unc_or_parity_err_cnt
),
4801 [C_TX_LAUNCH_FIFO2_UNC_OR_PARITY_ERR
] = CNTR_ELEM("TxLaunchFifo2UncOrParityErr",
4803 access_tx_launch_fifo2_unc_or_parity_err_cnt
),
4804 [C_TX_LAUNCH_FIFO1_UNC_OR_PARITY_ERR
] = CNTR_ELEM("TxLaunchFifo1UncOrParityErr",
4806 access_tx_launch_fifo1_unc_or_parity_err_cnt
),
4807 [C_TX_LAUNCH_FIFO0_UNC_OR_PARITY_ERR
] = CNTR_ELEM("TxLaunchFifo0UncOrParityErr",
4809 access_tx_launch_fifo0_unc_or_parity_err_cnt
),
4810 [C_TX_SDMA15_DISALLOWED_PACKET_ERR
] = CNTR_ELEM("TxSdma15DisallowedPacketErr",
4812 access_tx_sdma15_disallowed_packet_err_cnt
),
4813 [C_TX_SDMA14_DISALLOWED_PACKET_ERR
] = CNTR_ELEM("TxSdma14DisallowedPacketErr",
4815 access_tx_sdma14_disallowed_packet_err_cnt
),
4816 [C_TX_SDMA13_DISALLOWED_PACKET_ERR
] = CNTR_ELEM("TxSdma13DisallowedPacketErr",
4818 access_tx_sdma13_disallowed_packet_err_cnt
),
4819 [C_TX_SDMA12_DISALLOWED_PACKET_ERR
] = CNTR_ELEM("TxSdma12DisallowedPacketErr",
4821 access_tx_sdma12_disallowed_packet_err_cnt
),
4822 [C_TX_SDMA11_DISALLOWED_PACKET_ERR
] = CNTR_ELEM("TxSdma11DisallowedPacketErr",
4824 access_tx_sdma11_disallowed_packet_err_cnt
),
4825 [C_TX_SDMA10_DISALLOWED_PACKET_ERR
] = CNTR_ELEM("TxSdma10DisallowedPacketErr",
4827 access_tx_sdma10_disallowed_packet_err_cnt
),
4828 [C_TX_SDMA9_DISALLOWED_PACKET_ERR
] = CNTR_ELEM("TxSdma9DisallowedPacketErr",
4830 access_tx_sdma9_disallowed_packet_err_cnt
),
4831 [C_TX_SDMA8_DISALLOWED_PACKET_ERR
] = CNTR_ELEM("TxSdma8DisallowedPacketErr",
4833 access_tx_sdma8_disallowed_packet_err_cnt
),
4834 [C_TX_SDMA7_DISALLOWED_PACKET_ERR
] = CNTR_ELEM("TxSdma7DisallowedPacketErr",
4836 access_tx_sdma7_disallowed_packet_err_cnt
),
4837 [C_TX_SDMA6_DISALLOWED_PACKET_ERR
] = CNTR_ELEM("TxSdma6DisallowedPacketErr",
4839 access_tx_sdma6_disallowed_packet_err_cnt
),
4840 [C_TX_SDMA5_DISALLOWED_PACKET_ERR
] = CNTR_ELEM("TxSdma5DisallowedPacketErr",
4842 access_tx_sdma5_disallowed_packet_err_cnt
),
4843 [C_TX_SDMA4_DISALLOWED_PACKET_ERR
] = CNTR_ELEM("TxSdma4DisallowedPacketErr",
4845 access_tx_sdma4_disallowed_packet_err_cnt
),
4846 [C_TX_SDMA3_DISALLOWED_PACKET_ERR
] = CNTR_ELEM("TxSdma3DisallowedPacketErr",
4848 access_tx_sdma3_disallowed_packet_err_cnt
),
4849 [C_TX_SDMA2_DISALLOWED_PACKET_ERR
] = CNTR_ELEM("TxSdma2DisallowedPacketErr",
4851 access_tx_sdma2_disallowed_packet_err_cnt
),
4852 [C_TX_SDMA1_DISALLOWED_PACKET_ERR
] = CNTR_ELEM("TxSdma1DisallowedPacketErr",
4854 access_tx_sdma1_disallowed_packet_err_cnt
),
4855 [C_TX_SDMA0_DISALLOWED_PACKET_ERR
] = CNTR_ELEM("TxSdma0DisallowedPacketErr",
4857 access_tx_sdma0_disallowed_packet_err_cnt
),
4858 [C_TX_CONFIG_PARITY_ERR
] = CNTR_ELEM("TxConfigParityErr", 0, 0,
4860 access_tx_config_parity_err_cnt
),
4861 [C_TX_SBRD_CTL_CSR_PARITY_ERR
] = CNTR_ELEM("TxSbrdCtlCsrParityErr", 0, 0,
4863 access_tx_sbrd_ctl_csr_parity_err_cnt
),
4864 [C_TX_LAUNCH_CSR_PARITY_ERR
] = CNTR_ELEM("TxLaunchCsrParityErr", 0, 0,
4866 access_tx_launch_csr_parity_err_cnt
),
4867 [C_TX_ILLEGAL_CL_ERR
] = CNTR_ELEM("TxIllegalVLErr", 0, 0,
4869 access_tx_illegal_vl_err_cnt
),
4870 [C_TX_SBRD_CTL_STATE_MACHINE_PARITY_ERR
] = CNTR_ELEM(
4871 "TxSbrdCtlStateMachineParityErr", 0, 0,
4873 access_tx_sbrd_ctl_state_machine_parity_err_cnt
),
4874 [C_TX_RESERVED_10
] = CNTR_ELEM("Tx Egress Reserved 10", 0, 0,
4876 access_egress_reserved_10_err_cnt
),
4877 [C_TX_RESERVED_9
] = CNTR_ELEM("Tx Egress Reserved 9", 0, 0,
4879 access_egress_reserved_9_err_cnt
),
4880 [C_TX_SDMA_LAUNCH_INTF_PARITY_ERR
] = CNTR_ELEM("TxSdmaLaunchIntfParityErr",
4882 access_tx_sdma_launch_intf_parity_err_cnt
),
4883 [C_TX_PIO_LAUNCH_INTF_PARITY_ERR
] = CNTR_ELEM("TxPioLaunchIntfParityErr", 0, 0,
4885 access_tx_pio_launch_intf_parity_err_cnt
),
4886 [C_TX_RESERVED_6
] = CNTR_ELEM("Tx Egress Reserved 6", 0, 0,
4888 access_egress_reserved_6_err_cnt
),
4889 [C_TX_INCORRECT_LINK_STATE_ERR
] = CNTR_ELEM("TxIncorrectLinkStateErr", 0, 0,
4891 access_tx_incorrect_link_state_err_cnt
),
4892 [C_TX_LINK_DOWN_ERR
] = CNTR_ELEM("TxLinkdownErr", 0, 0,
4894 access_tx_linkdown_err_cnt
),
4895 [C_TX_EGRESS_FIFO_UNDERRUN_OR_PARITY_ERR
] = CNTR_ELEM(
4896 "EgressFifoUnderrunOrParityErr", 0, 0,
4898 access_tx_egress_fifi_underrun_or_parity_err_cnt
),
4899 [C_TX_RESERVED_2
] = CNTR_ELEM("Tx Egress Reserved 2", 0, 0,
4901 access_egress_reserved_2_err_cnt
),
4902 [C_TX_PKT_INTEGRITY_MEM_UNC_ERR
] = CNTR_ELEM("TxPktIntegrityMemUncErr", 0, 0,
4904 access_tx_pkt_integrity_mem_unc_err_cnt
),
4905 [C_TX_PKT_INTEGRITY_MEM_COR_ERR
] = CNTR_ELEM("TxPktIntegrityMemCorErr", 0, 0,
4907 access_tx_pkt_integrity_mem_cor_err_cnt
),
4909 [C_SEND_CSR_WRITE_BAD_ADDR_ERR
] = CNTR_ELEM("SendCsrWriteBadAddrErr", 0, 0,
4911 access_send_csr_write_bad_addr_err_cnt
),
4912 [C_SEND_CSR_READ_BAD_ADD_ERR
] = CNTR_ELEM("SendCsrReadBadAddrErr", 0, 0,
4914 access_send_csr_read_bad_addr_err_cnt
),
4915 [C_SEND_CSR_PARITY_ERR
] = CNTR_ELEM("SendCsrParityErr", 0, 0,
4917 access_send_csr_parity_cnt
),
4918 /* SendCtxtErrStatus */
4919 [C_PIO_WRITE_OUT_OF_BOUNDS_ERR
] = CNTR_ELEM("PioWriteOutOfBoundsErr", 0, 0,
4921 access_pio_write_out_of_bounds_err_cnt
),
4922 [C_PIO_WRITE_OVERFLOW_ERR
] = CNTR_ELEM("PioWriteOverflowErr", 0, 0,
4924 access_pio_write_overflow_err_cnt
),
4925 [C_PIO_WRITE_CROSSES_BOUNDARY_ERR
] = CNTR_ELEM("PioWriteCrossesBoundaryErr",
4927 access_pio_write_crosses_boundary_err_cnt
),
4928 [C_PIO_DISALLOWED_PACKET_ERR
] = CNTR_ELEM("PioDisallowedPacketErr", 0, 0,
4930 access_pio_disallowed_packet_err_cnt
),
4931 [C_PIO_INCONSISTENT_SOP_ERR
] = CNTR_ELEM("PioInconsistentSopErr", 0, 0,
4933 access_pio_inconsistent_sop_err_cnt
),
4934 /* SendDmaEngErrStatus */
4935 [C_SDMA_HEADER_REQUEST_FIFO_COR_ERR
] = CNTR_ELEM("SDmaHeaderRequestFifoCorErr",
4937 access_sdma_header_request_fifo_cor_err_cnt
),
4938 [C_SDMA_HEADER_STORAGE_COR_ERR
] = CNTR_ELEM("SDmaHeaderStorageCorErr", 0, 0,
4940 access_sdma_header_storage_cor_err_cnt
),
4941 [C_SDMA_PACKET_TRACKING_COR_ERR
] = CNTR_ELEM("SDmaPacketTrackingCorErr", 0, 0,
4943 access_sdma_packet_tracking_cor_err_cnt
),
4944 [C_SDMA_ASSEMBLY_COR_ERR
] = CNTR_ELEM("SDmaAssemblyCorErr", 0, 0,
4946 access_sdma_assembly_cor_err_cnt
),
4947 [C_SDMA_DESC_TABLE_COR_ERR
] = CNTR_ELEM("SDmaDescTableCorErr", 0, 0,
4949 access_sdma_desc_table_cor_err_cnt
),
4950 [C_SDMA_HEADER_REQUEST_FIFO_UNC_ERR
] = CNTR_ELEM("SDmaHeaderRequestFifoUncErr",
4952 access_sdma_header_request_fifo_unc_err_cnt
),
4953 [C_SDMA_HEADER_STORAGE_UNC_ERR
] = CNTR_ELEM("SDmaHeaderStorageUncErr", 0, 0,
4955 access_sdma_header_storage_unc_err_cnt
),
4956 [C_SDMA_PACKET_TRACKING_UNC_ERR
] = CNTR_ELEM("SDmaPacketTrackingUncErr", 0, 0,
4958 access_sdma_packet_tracking_unc_err_cnt
),
4959 [C_SDMA_ASSEMBLY_UNC_ERR
] = CNTR_ELEM("SDmaAssemblyUncErr", 0, 0,
4961 access_sdma_assembly_unc_err_cnt
),
4962 [C_SDMA_DESC_TABLE_UNC_ERR
] = CNTR_ELEM("SDmaDescTableUncErr", 0, 0,
4964 access_sdma_desc_table_unc_err_cnt
),
4965 [C_SDMA_TIMEOUT_ERR
] = CNTR_ELEM("SDmaTimeoutErr", 0, 0,
4967 access_sdma_timeout_err_cnt
),
4968 [C_SDMA_HEADER_LENGTH_ERR
] = CNTR_ELEM("SDmaHeaderLengthErr", 0, 0,
4970 access_sdma_header_length_err_cnt
),
4971 [C_SDMA_HEADER_ADDRESS_ERR
] = CNTR_ELEM("SDmaHeaderAddressErr", 0, 0,
4973 access_sdma_header_address_err_cnt
),
4974 [C_SDMA_HEADER_SELECT_ERR
] = CNTR_ELEM("SDmaHeaderSelectErr", 0, 0,
4976 access_sdma_header_select_err_cnt
),
4977 [C_SMDA_RESERVED_9
] = CNTR_ELEM("SDma Reserved 9", 0, 0,
4979 access_sdma_reserved_9_err_cnt
),
4980 [C_SDMA_PACKET_DESC_OVERFLOW_ERR
] = CNTR_ELEM("SDmaPacketDescOverflowErr", 0, 0,
4982 access_sdma_packet_desc_overflow_err_cnt
),
4983 [C_SDMA_LENGTH_MISMATCH_ERR
] = CNTR_ELEM("SDmaLengthMismatchErr", 0, 0,
4985 access_sdma_length_mismatch_err_cnt
),
4986 [C_SDMA_HALT_ERR
] = CNTR_ELEM("SDmaHaltErr", 0, 0,
4988 access_sdma_halt_err_cnt
),
4989 [C_SDMA_MEM_READ_ERR
] = CNTR_ELEM("SDmaMemReadErr", 0, 0,
4991 access_sdma_mem_read_err_cnt
),
4992 [C_SDMA_FIRST_DESC_ERR
] = CNTR_ELEM("SDmaFirstDescErr", 0, 0,
4994 access_sdma_first_desc_err_cnt
),
4995 [C_SDMA_TAIL_OUT_OF_BOUNDS_ERR
] = CNTR_ELEM("SDmaTailOutOfBoundsErr", 0, 0,
4997 access_sdma_tail_out_of_bounds_err_cnt
),
4998 [C_SDMA_TOO_LONG_ERR
] = CNTR_ELEM("SDmaTooLongErr", 0, 0,
5000 access_sdma_too_long_err_cnt
),
5001 [C_SDMA_GEN_MISMATCH_ERR
] = CNTR_ELEM("SDmaGenMismatchErr", 0, 0,
5003 access_sdma_gen_mismatch_err_cnt
),
5004 [C_SDMA_WRONG_DW_ERR
] = CNTR_ELEM("SDmaWrongDwErr", 0, 0,
5006 access_sdma_wrong_dw_err_cnt
),
5009 static struct cntr_entry port_cntrs
[PORT_CNTR_LAST
] = {
5010 [C_TX_UNSUP_VL
] = TXE32_PORT_CNTR_ELEM(TxUnVLErr
, SEND_UNSUP_VL_ERR_CNT
,
5012 [C_TX_INVAL_LEN
] = TXE32_PORT_CNTR_ELEM(TxInvalLen
, SEND_LEN_ERR_CNT
,
5014 [C_TX_MM_LEN_ERR
] = TXE32_PORT_CNTR_ELEM(TxMMLenErr
, SEND_MAX_MIN_LEN_ERR_CNT
,
5016 [C_TX_UNDERRUN
] = TXE32_PORT_CNTR_ELEM(TxUnderrun
, SEND_UNDERRUN_CNT
,
5018 [C_TX_FLOW_STALL
] = TXE32_PORT_CNTR_ELEM(TxFlowStall
, SEND_FLOW_STALL_CNT
,
5020 [C_TX_DROPPED
] = TXE32_PORT_CNTR_ELEM(TxDropped
, SEND_DROPPED_PKT_CNT
,
5022 [C_TX_HDR_ERR
] = TXE32_PORT_CNTR_ELEM(TxHdrErr
, SEND_HEADERS_ERR_CNT
,
5024 [C_TX_PKT
] = TXE64_PORT_CNTR_ELEM(TxPkt
, SEND_DATA_PKT_CNT
, CNTR_NORMAL
),
5025 [C_TX_WORDS
] = TXE64_PORT_CNTR_ELEM(TxWords
, SEND_DWORD_CNT
, CNTR_NORMAL
),
5026 [C_TX_WAIT
] = TXE64_PORT_CNTR_ELEM(TxWait
, SEND_WAIT_CNT
, CNTR_SYNTH
),
5027 [C_TX_FLIT_VL
] = TXE64_PORT_CNTR_ELEM(TxFlitVL
, SEND_DATA_VL0_CNT
,
5028 CNTR_SYNTH
| CNTR_VL
),
5029 [C_TX_PKT_VL
] = TXE64_PORT_CNTR_ELEM(TxPktVL
, SEND_DATA_PKT_VL0_CNT
,
5030 CNTR_SYNTH
| CNTR_VL
),
5031 [C_TX_WAIT_VL
] = TXE64_PORT_CNTR_ELEM(TxWaitVL
, SEND_WAIT_VL0_CNT
,
5032 CNTR_SYNTH
| CNTR_VL
),
5033 [C_RX_PKT
] = RXE64_PORT_CNTR_ELEM(RxPkt
, RCV_DATA_PKT_CNT
, CNTR_NORMAL
),
5034 [C_RX_WORDS
] = RXE64_PORT_CNTR_ELEM(RxWords
, RCV_DWORD_CNT
, CNTR_NORMAL
),
5035 [C_SW_LINK_DOWN
] = CNTR_ELEM("SwLinkDown", 0, 0, CNTR_SYNTH
| CNTR_32BIT
,
5036 access_sw_link_dn_cnt
),
5037 [C_SW_LINK_UP
] = CNTR_ELEM("SwLinkUp", 0, 0, CNTR_SYNTH
| CNTR_32BIT
,
5038 access_sw_link_up_cnt
),
5039 [C_SW_UNKNOWN_FRAME
] = CNTR_ELEM("UnknownFrame", 0, 0, CNTR_NORMAL
,
5040 access_sw_unknown_frame_cnt
),
5041 [C_SW_XMIT_DSCD
] = CNTR_ELEM("XmitDscd", 0, 0, CNTR_SYNTH
| CNTR_32BIT
,
5042 access_sw_xmit_discards
),
5043 [C_SW_XMIT_DSCD_VL
] = CNTR_ELEM("XmitDscdVl", 0, 0,
5044 CNTR_SYNTH
| CNTR_32BIT
| CNTR_VL
,
5045 access_sw_xmit_discards
),
5046 [C_SW_XMIT_CSTR_ERR
] = CNTR_ELEM("XmitCstrErr", 0, 0, CNTR_SYNTH
,
5047 access_xmit_constraint_errs
),
5048 [C_SW_RCV_CSTR_ERR
] = CNTR_ELEM("RcvCstrErr", 0, 0, CNTR_SYNTH
,
5049 access_rcv_constraint_errs
),
5050 [C_SW_IBP_LOOP_PKTS
] = SW_IBP_CNTR(LoopPkts
, loop_pkts
),
5051 [C_SW_IBP_RC_RESENDS
] = SW_IBP_CNTR(RcResend
, rc_resends
),
5052 [C_SW_IBP_RNR_NAKS
] = SW_IBP_CNTR(RnrNak
, rnr_naks
),
5053 [C_SW_IBP_OTHER_NAKS
] = SW_IBP_CNTR(OtherNak
, other_naks
),
5054 [C_SW_IBP_RC_TIMEOUTS
] = SW_IBP_CNTR(RcTimeOut
, rc_timeouts
),
5055 [C_SW_IBP_PKT_DROPS
] = SW_IBP_CNTR(PktDrop
, pkt_drops
),
5056 [C_SW_IBP_DMA_WAIT
] = SW_IBP_CNTR(DmaWait
, dmawait
),
5057 [C_SW_IBP_RC_SEQNAK
] = SW_IBP_CNTR(RcSeqNak
, rc_seqnak
),
5058 [C_SW_IBP_RC_DUPREQ
] = SW_IBP_CNTR(RcDupRew
, rc_dupreq
),
5059 [C_SW_IBP_RDMA_SEQ
] = SW_IBP_CNTR(RdmaSeq
, rdma_seq
),
5060 [C_SW_IBP_UNALIGNED
] = SW_IBP_CNTR(Unaligned
, unaligned
),
5061 [C_SW_IBP_SEQ_NAK
] = SW_IBP_CNTR(SeqNak
, seq_naks
),
5062 [C_SW_CPU_RC_ACKS
] = CNTR_ELEM("RcAcks", 0, 0, CNTR_NORMAL
,
5063 access_sw_cpu_rc_acks
),
5064 [C_SW_CPU_RC_QACKS
] = CNTR_ELEM("RcQacks", 0, 0, CNTR_NORMAL
,
5065 access_sw_cpu_rc_qacks
),
5066 [C_SW_CPU_RC_DELAYED_COMP
] = CNTR_ELEM("RcDelayComp", 0, 0, CNTR_NORMAL
,
5067 access_sw_cpu_rc_delayed_comp
),
5068 [OVR_LBL(0)] = OVR_ELM(0), [OVR_LBL(1)] = OVR_ELM(1),
5069 [OVR_LBL(2)] = OVR_ELM(2), [OVR_LBL(3)] = OVR_ELM(3),
5070 [OVR_LBL(4)] = OVR_ELM(4), [OVR_LBL(5)] = OVR_ELM(5),
5071 [OVR_LBL(6)] = OVR_ELM(6), [OVR_LBL(7)] = OVR_ELM(7),
5072 [OVR_LBL(8)] = OVR_ELM(8), [OVR_LBL(9)] = OVR_ELM(9),
5073 [OVR_LBL(10)] = OVR_ELM(10), [OVR_LBL(11)] = OVR_ELM(11),
5074 [OVR_LBL(12)] = OVR_ELM(12), [OVR_LBL(13)] = OVR_ELM(13),
5075 [OVR_LBL(14)] = OVR_ELM(14), [OVR_LBL(15)] = OVR_ELM(15),
5076 [OVR_LBL(16)] = OVR_ELM(16), [OVR_LBL(17)] = OVR_ELM(17),
5077 [OVR_LBL(18)] = OVR_ELM(18), [OVR_LBL(19)] = OVR_ELM(19),
5078 [OVR_LBL(20)] = OVR_ELM(20), [OVR_LBL(21)] = OVR_ELM(21),
5079 [OVR_LBL(22)] = OVR_ELM(22), [OVR_LBL(23)] = OVR_ELM(23),
5080 [OVR_LBL(24)] = OVR_ELM(24), [OVR_LBL(25)] = OVR_ELM(25),
5081 [OVR_LBL(26)] = OVR_ELM(26), [OVR_LBL(27)] = OVR_ELM(27),
5082 [OVR_LBL(28)] = OVR_ELM(28), [OVR_LBL(29)] = OVR_ELM(29),
5083 [OVR_LBL(30)] = OVR_ELM(30), [OVR_LBL(31)] = OVR_ELM(31),
5084 [OVR_LBL(32)] = OVR_ELM(32), [OVR_LBL(33)] = OVR_ELM(33),
5085 [OVR_LBL(34)] = OVR_ELM(34), [OVR_LBL(35)] = OVR_ELM(35),
5086 [OVR_LBL(36)] = OVR_ELM(36), [OVR_LBL(37)] = OVR_ELM(37),
5087 [OVR_LBL(38)] = OVR_ELM(38), [OVR_LBL(39)] = OVR_ELM(39),
5088 [OVR_LBL(40)] = OVR_ELM(40), [OVR_LBL(41)] = OVR_ELM(41),
5089 [OVR_LBL(42)] = OVR_ELM(42), [OVR_LBL(43)] = OVR_ELM(43),
5090 [OVR_LBL(44)] = OVR_ELM(44), [OVR_LBL(45)] = OVR_ELM(45),
5091 [OVR_LBL(46)] = OVR_ELM(46), [OVR_LBL(47)] = OVR_ELM(47),
5092 [OVR_LBL(48)] = OVR_ELM(48), [OVR_LBL(49)] = OVR_ELM(49),
5093 [OVR_LBL(50)] = OVR_ELM(50), [OVR_LBL(51)] = OVR_ELM(51),
5094 [OVR_LBL(52)] = OVR_ELM(52), [OVR_LBL(53)] = OVR_ELM(53),
5095 [OVR_LBL(54)] = OVR_ELM(54), [OVR_LBL(55)] = OVR_ELM(55),
5096 [OVR_LBL(56)] = OVR_ELM(56), [OVR_LBL(57)] = OVR_ELM(57),
5097 [OVR_LBL(58)] = OVR_ELM(58), [OVR_LBL(59)] = OVR_ELM(59),
5098 [OVR_LBL(60)] = OVR_ELM(60), [OVR_LBL(61)] = OVR_ELM(61),
5099 [OVR_LBL(62)] = OVR_ELM(62), [OVR_LBL(63)] = OVR_ELM(63),
5100 [OVR_LBL(64)] = OVR_ELM(64), [OVR_LBL(65)] = OVR_ELM(65),
5101 [OVR_LBL(66)] = OVR_ELM(66), [OVR_LBL(67)] = OVR_ELM(67),
5102 [OVR_LBL(68)] = OVR_ELM(68), [OVR_LBL(69)] = OVR_ELM(69),
5103 [OVR_LBL(70)] = OVR_ELM(70), [OVR_LBL(71)] = OVR_ELM(71),
5104 [OVR_LBL(72)] = OVR_ELM(72), [OVR_LBL(73)] = OVR_ELM(73),
5105 [OVR_LBL(74)] = OVR_ELM(74), [OVR_LBL(75)] = OVR_ELM(75),
5106 [OVR_LBL(76)] = OVR_ELM(76), [OVR_LBL(77)] = OVR_ELM(77),
5107 [OVR_LBL(78)] = OVR_ELM(78), [OVR_LBL(79)] = OVR_ELM(79),
5108 [OVR_LBL(80)] = OVR_ELM(80), [OVR_LBL(81)] = OVR_ELM(81),
5109 [OVR_LBL(82)] = OVR_ELM(82), [OVR_LBL(83)] = OVR_ELM(83),
5110 [OVR_LBL(84)] = OVR_ELM(84), [OVR_LBL(85)] = OVR_ELM(85),
5111 [OVR_LBL(86)] = OVR_ELM(86), [OVR_LBL(87)] = OVR_ELM(87),
5112 [OVR_LBL(88)] = OVR_ELM(88), [OVR_LBL(89)] = OVR_ELM(89),
5113 [OVR_LBL(90)] = OVR_ELM(90), [OVR_LBL(91)] = OVR_ELM(91),
5114 [OVR_LBL(92)] = OVR_ELM(92), [OVR_LBL(93)] = OVR_ELM(93),
5115 [OVR_LBL(94)] = OVR_ELM(94), [OVR_LBL(95)] = OVR_ELM(95),
5116 [OVR_LBL(96)] = OVR_ELM(96), [OVR_LBL(97)] = OVR_ELM(97),
5117 [OVR_LBL(98)] = OVR_ELM(98), [OVR_LBL(99)] = OVR_ELM(99),
5118 [OVR_LBL(100)] = OVR_ELM(100), [OVR_LBL(101)] = OVR_ELM(101),
5119 [OVR_LBL(102)] = OVR_ELM(102), [OVR_LBL(103)] = OVR_ELM(103),
5120 [OVR_LBL(104)] = OVR_ELM(104), [OVR_LBL(105)] = OVR_ELM(105),
5121 [OVR_LBL(106)] = OVR_ELM(106), [OVR_LBL(107)] = OVR_ELM(107),
5122 [OVR_LBL(108)] = OVR_ELM(108), [OVR_LBL(109)] = OVR_ELM(109),
5123 [OVR_LBL(110)] = OVR_ELM(110), [OVR_LBL(111)] = OVR_ELM(111),
5124 [OVR_LBL(112)] = OVR_ELM(112), [OVR_LBL(113)] = OVR_ELM(113),
5125 [OVR_LBL(114)] = OVR_ELM(114), [OVR_LBL(115)] = OVR_ELM(115),
5126 [OVR_LBL(116)] = OVR_ELM(116), [OVR_LBL(117)] = OVR_ELM(117),
5127 [OVR_LBL(118)] = OVR_ELM(118), [OVR_LBL(119)] = OVR_ELM(119),
5128 [OVR_LBL(120)] = OVR_ELM(120), [OVR_LBL(121)] = OVR_ELM(121),
5129 [OVR_LBL(122)] = OVR_ELM(122), [OVR_LBL(123)] = OVR_ELM(123),
5130 [OVR_LBL(124)] = OVR_ELM(124), [OVR_LBL(125)] = OVR_ELM(125),
5131 [OVR_LBL(126)] = OVR_ELM(126), [OVR_LBL(127)] = OVR_ELM(127),
5132 [OVR_LBL(128)] = OVR_ELM(128), [OVR_LBL(129)] = OVR_ELM(129),
5133 [OVR_LBL(130)] = OVR_ELM(130), [OVR_LBL(131)] = OVR_ELM(131),
5134 [OVR_LBL(132)] = OVR_ELM(132), [OVR_LBL(133)] = OVR_ELM(133),
5135 [OVR_LBL(134)] = OVR_ELM(134), [OVR_LBL(135)] = OVR_ELM(135),
5136 [OVR_LBL(136)] = OVR_ELM(136), [OVR_LBL(137)] = OVR_ELM(137),
5137 [OVR_LBL(138)] = OVR_ELM(138), [OVR_LBL(139)] = OVR_ELM(139),
5138 [OVR_LBL(140)] = OVR_ELM(140), [OVR_LBL(141)] = OVR_ELM(141),
5139 [OVR_LBL(142)] = OVR_ELM(142), [OVR_LBL(143)] = OVR_ELM(143),
5140 [OVR_LBL(144)] = OVR_ELM(144), [OVR_LBL(145)] = OVR_ELM(145),
5141 [OVR_LBL(146)] = OVR_ELM(146), [OVR_LBL(147)] = OVR_ELM(147),
5142 [OVR_LBL(148)] = OVR_ELM(148), [OVR_LBL(149)] = OVR_ELM(149),
5143 [OVR_LBL(150)] = OVR_ELM(150), [OVR_LBL(151)] = OVR_ELM(151),
5144 [OVR_LBL(152)] = OVR_ELM(152), [OVR_LBL(153)] = OVR_ELM(153),
5145 [OVR_LBL(154)] = OVR_ELM(154), [OVR_LBL(155)] = OVR_ELM(155),
5146 [OVR_LBL(156)] = OVR_ELM(156), [OVR_LBL(157)] = OVR_ELM(157),
5147 [OVR_LBL(158)] = OVR_ELM(158), [OVR_LBL(159)] = OVR_ELM(159),
5150 /* ======================================================================== */
5152 /* return true if this is chip revision revision a */
5153 int is_ax(struct hfi1_devdata
*dd
)
5156 dd
->revision
>> CCE_REVISION_CHIP_REV_MINOR_SHIFT
5157 & CCE_REVISION_CHIP_REV_MINOR_MASK
;
5158 return (chip_rev_minor
& 0xf0) == 0;
5161 /* return true if this is chip revision revision b */
5162 int is_bx(struct hfi1_devdata
*dd
)
5165 dd
->revision
>> CCE_REVISION_CHIP_REV_MINOR_SHIFT
5166 & CCE_REVISION_CHIP_REV_MINOR_MASK
;
5167 return (chip_rev_minor
& 0xF0) == 0x10;
5171 * Append string s to buffer buf. Arguments curp and len are the current
5172 * position and remaining length, respectively.
5174 * return 0 on success, 1 on out of room
5176 static int append_str(char *buf
, char **curp
, int *lenp
, const char *s
)
5180 int result
= 0; /* success */
5183 /* add a comma, if first in the buffer */
5186 result
= 1; /* out of room */
5193 /* copy the string */
5194 while ((c
= *s
++) != 0) {
5196 result
= 1; /* out of room */
5204 /* write return values */
5212 * Using the given flag table, print a comma separated string into
5213 * the buffer. End in '*' if the buffer is too short.
5215 static char *flag_string(char *buf
, int buf_len
, u64 flags
,
5216 struct flag_table
*table
, int table_size
)
5224 /* make sure there is at least 2 so we can form "*" */
5228 len
--; /* leave room for a nul */
5229 for (i
= 0; i
< table_size
; i
++) {
5230 if (flags
& table
[i
].flag
) {
5231 no_room
= append_str(buf
, &p
, &len
, table
[i
].str
);
5234 flags
&= ~table
[i
].flag
;
5238 /* any undocumented bits left? */
5239 if (!no_room
&& flags
) {
5240 snprintf(extra
, sizeof(extra
), "bits 0x%llx", flags
);
5241 no_room
= append_str(buf
, &p
, &len
, extra
);
5244 /* add * if ran out of room */
5246 /* may need to back up to add space for a '*' */
5252 /* add final nul - space already allocated above */
5257 /* first 8 CCE error interrupt source names */
5258 static const char * const cce_misc_names
[] = {
5259 "CceErrInt", /* 0 */
5260 "RxeErrInt", /* 1 */
5261 "MiscErrInt", /* 2 */
5262 "Reserved3", /* 3 */
5263 "PioErrInt", /* 4 */
5264 "SDmaErrInt", /* 5 */
5265 "EgressErrInt", /* 6 */
5270 * Return the miscellaneous error interrupt name.
5272 static char *is_misc_err_name(char *buf
, size_t bsize
, unsigned int source
)
5274 if (source
< ARRAY_SIZE(cce_misc_names
))
5275 strncpy(buf
, cce_misc_names
[source
], bsize
);
5277 snprintf(buf
, bsize
, "Reserved%u",
5278 source
+ IS_GENERAL_ERR_START
);
5284 * Return the SDMA engine error interrupt name.
5286 static char *is_sdma_eng_err_name(char *buf
, size_t bsize
, unsigned int source
)
5288 snprintf(buf
, bsize
, "SDmaEngErrInt%u", source
);
5293 * Return the send context error interrupt name.
5295 static char *is_sendctxt_err_name(char *buf
, size_t bsize
, unsigned int source
)
5297 snprintf(buf
, bsize
, "SendCtxtErrInt%u", source
);
5301 static const char * const various_names
[] = {
5310 * Return the various interrupt name.
5312 static char *is_various_name(char *buf
, size_t bsize
, unsigned int source
)
5314 if (source
< ARRAY_SIZE(various_names
))
5315 strncpy(buf
, various_names
[source
], bsize
);
5317 snprintf(buf
, bsize
, "Reserved%u", source
+ IS_VARIOUS_START
);
5322 * Return the DC interrupt name.
5324 static char *is_dc_name(char *buf
, size_t bsize
, unsigned int source
)
5326 static const char * const dc_int_names
[] = {
5330 "lbm" /* local block merge */
5333 if (source
< ARRAY_SIZE(dc_int_names
))
5334 snprintf(buf
, bsize
, "dc_%s_int", dc_int_names
[source
]);
5336 snprintf(buf
, bsize
, "DCInt%u", source
);
5340 static const char * const sdma_int_names
[] = {
5347 * Return the SDMA engine interrupt name.
5349 static char *is_sdma_eng_name(char *buf
, size_t bsize
, unsigned int source
)
5351 /* what interrupt */
5352 unsigned int what
= source
/ TXE_NUM_SDMA_ENGINES
;
5354 unsigned int which
= source
% TXE_NUM_SDMA_ENGINES
;
5356 if (likely(what
< 3))
5357 snprintf(buf
, bsize
, "%s%u", sdma_int_names
[what
], which
);
5359 snprintf(buf
, bsize
, "Invalid SDMA interrupt %u", source
);
5364 * Return the receive available interrupt name.
5366 static char *is_rcv_avail_name(char *buf
, size_t bsize
, unsigned int source
)
5368 snprintf(buf
, bsize
, "RcvAvailInt%u", source
);
5373 * Return the receive urgent interrupt name.
5375 static char *is_rcv_urgent_name(char *buf
, size_t bsize
, unsigned int source
)
5377 snprintf(buf
, bsize
, "RcvUrgentInt%u", source
);
5382 * Return the send credit interrupt name.
5384 static char *is_send_credit_name(char *buf
, size_t bsize
, unsigned int source
)
5386 snprintf(buf
, bsize
, "SendCreditInt%u", source
);
5391 * Return the reserved interrupt name.
5393 static char *is_reserved_name(char *buf
, size_t bsize
, unsigned int source
)
5395 snprintf(buf
, bsize
, "Reserved%u", source
+ IS_RESERVED_START
);
5399 static char *cce_err_status_string(char *buf
, int buf_len
, u64 flags
)
5401 return flag_string(buf
, buf_len
, flags
,
5402 cce_err_status_flags
,
5403 ARRAY_SIZE(cce_err_status_flags
));
5406 static char *rxe_err_status_string(char *buf
, int buf_len
, u64 flags
)
5408 return flag_string(buf
, buf_len
, flags
,
5409 rxe_err_status_flags
,
5410 ARRAY_SIZE(rxe_err_status_flags
));
5413 static char *misc_err_status_string(char *buf
, int buf_len
, u64 flags
)
5415 return flag_string(buf
, buf_len
, flags
, misc_err_status_flags
,
5416 ARRAY_SIZE(misc_err_status_flags
));
5419 static char *pio_err_status_string(char *buf
, int buf_len
, u64 flags
)
5421 return flag_string(buf
, buf_len
, flags
,
5422 pio_err_status_flags
,
5423 ARRAY_SIZE(pio_err_status_flags
));
5426 static char *sdma_err_status_string(char *buf
, int buf_len
, u64 flags
)
5428 return flag_string(buf
, buf_len
, flags
,
5429 sdma_err_status_flags
,
5430 ARRAY_SIZE(sdma_err_status_flags
));
5433 static char *egress_err_status_string(char *buf
, int buf_len
, u64 flags
)
5435 return flag_string(buf
, buf_len
, flags
,
5436 egress_err_status_flags
,
5437 ARRAY_SIZE(egress_err_status_flags
));
5440 static char *egress_err_info_string(char *buf
, int buf_len
, u64 flags
)
5442 return flag_string(buf
, buf_len
, flags
,
5443 egress_err_info_flags
,
5444 ARRAY_SIZE(egress_err_info_flags
));
5447 static char *send_err_status_string(char *buf
, int buf_len
, u64 flags
)
5449 return flag_string(buf
, buf_len
, flags
,
5450 send_err_status_flags
,
5451 ARRAY_SIZE(send_err_status_flags
));
5454 static void handle_cce_err(struct hfi1_devdata
*dd
, u32 unused
, u64 reg
)
5460 * For most these errors, there is nothing that can be done except
5461 * report or record it.
5463 dd_dev_info(dd
, "CCE Error: %s\n",
5464 cce_err_status_string(buf
, sizeof(buf
), reg
));
5466 if ((reg
& CCE_ERR_STATUS_CCE_CLI2_ASYNC_FIFO_PARITY_ERR_SMASK
) &&
5467 is_ax(dd
) && (dd
->icode
!= ICODE_FUNCTIONAL_SIMULATOR
)) {
5468 /* this error requires a manual drop into SPC freeze mode */
5470 start_freeze_handling(dd
->pport
, FREEZE_SELF
);
5473 for (i
= 0; i
< NUM_CCE_ERR_STATUS_COUNTERS
; i
++) {
5474 if (reg
& (1ull << i
)) {
5475 incr_cntr64(&dd
->cce_err_status_cnt
[i
]);
5476 /* maintain a counter over all cce_err_status errors */
5477 incr_cntr64(&dd
->sw_cce_err_status_aggregate
);
5483 * Check counters for receive errors that do not have an interrupt
5484 * associated with them.
5486 #define RCVERR_CHECK_TIME 10
5487 static void update_rcverr_timer(unsigned long opaque
)
5489 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)opaque
;
5490 struct hfi1_pportdata
*ppd
= dd
->pport
;
5491 u32 cur_ovfl_cnt
= read_dev_cntr(dd
, C_RCV_OVF
, CNTR_INVALID_VL
);
5493 if (dd
->rcv_ovfl_cnt
< cur_ovfl_cnt
&&
5494 ppd
->port_error_action
& OPA_PI_MASK_EX_BUFFER_OVERRUN
) {
5495 dd_dev_info(dd
, "%s: PortErrorAction bounce\n", __func__
);
5496 set_link_down_reason(
5497 ppd
, OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN
, 0,
5498 OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN
);
5499 queue_work(ppd
->hfi1_wq
, &ppd
->link_bounce_work
);
5501 dd
->rcv_ovfl_cnt
= (u32
)cur_ovfl_cnt
;
5503 mod_timer(&dd
->rcverr_timer
, jiffies
+ HZ
* RCVERR_CHECK_TIME
);
5506 static int init_rcverr(struct hfi1_devdata
*dd
)
5508 setup_timer(&dd
->rcverr_timer
, update_rcverr_timer
, (unsigned long)dd
);
5509 /* Assume the hardware counter has been reset */
5510 dd
->rcv_ovfl_cnt
= 0;
5511 return mod_timer(&dd
->rcverr_timer
, jiffies
+ HZ
* RCVERR_CHECK_TIME
);
5514 static void free_rcverr(struct hfi1_devdata
*dd
)
5516 if (dd
->rcverr_timer
.data
)
5517 del_timer_sync(&dd
->rcverr_timer
);
5518 dd
->rcverr_timer
.data
= 0;
5521 static void handle_rxe_err(struct hfi1_devdata
*dd
, u32 unused
, u64 reg
)
5526 dd_dev_info(dd
, "Receive Error: %s\n",
5527 rxe_err_status_string(buf
, sizeof(buf
), reg
));
5529 if (reg
& ALL_RXE_FREEZE_ERR
) {
5533 * Freeze mode recovery is disabled for the errors
5534 * in RXE_FREEZE_ABORT_MASK
5536 if (is_ax(dd
) && (reg
& RXE_FREEZE_ABORT_MASK
))
5537 flags
= FREEZE_ABORT
;
5539 start_freeze_handling(dd
->pport
, flags
);
5542 for (i
= 0; i
< NUM_RCV_ERR_STATUS_COUNTERS
; i
++) {
5543 if (reg
& (1ull << i
))
5544 incr_cntr64(&dd
->rcv_err_status_cnt
[i
]);
5548 static void handle_misc_err(struct hfi1_devdata
*dd
, u32 unused
, u64 reg
)
5553 dd_dev_info(dd
, "Misc Error: %s",
5554 misc_err_status_string(buf
, sizeof(buf
), reg
));
5555 for (i
= 0; i
< NUM_MISC_ERR_STATUS_COUNTERS
; i
++) {
5556 if (reg
& (1ull << i
))
5557 incr_cntr64(&dd
->misc_err_status_cnt
[i
]);
5561 static void handle_pio_err(struct hfi1_devdata
*dd
, u32 unused
, u64 reg
)
5566 dd_dev_info(dd
, "PIO Error: %s\n",
5567 pio_err_status_string(buf
, sizeof(buf
), reg
));
5569 if (reg
& ALL_PIO_FREEZE_ERR
)
5570 start_freeze_handling(dd
->pport
, 0);
5572 for (i
= 0; i
< NUM_SEND_PIO_ERR_STATUS_COUNTERS
; i
++) {
5573 if (reg
& (1ull << i
))
5574 incr_cntr64(&dd
->send_pio_err_status_cnt
[i
]);
5578 static void handle_sdma_err(struct hfi1_devdata
*dd
, u32 unused
, u64 reg
)
5583 dd_dev_info(dd
, "SDMA Error: %s\n",
5584 sdma_err_status_string(buf
, sizeof(buf
), reg
));
5586 if (reg
& ALL_SDMA_FREEZE_ERR
)
5587 start_freeze_handling(dd
->pport
, 0);
5589 for (i
= 0; i
< NUM_SEND_DMA_ERR_STATUS_COUNTERS
; i
++) {
5590 if (reg
& (1ull << i
))
5591 incr_cntr64(&dd
->send_dma_err_status_cnt
[i
]);
5595 static inline void __count_port_discards(struct hfi1_pportdata
*ppd
)
5597 incr_cntr64(&ppd
->port_xmit_discards
);
5600 static void count_port_inactive(struct hfi1_devdata
*dd
)
5602 __count_port_discards(dd
->pport
);
5606 * We have had a "disallowed packet" error during egress. Determine the
5607 * integrity check which failed, and update relevant error counter, etc.
5609 * Note that the SEND_EGRESS_ERR_INFO register has only a single
5610 * bit of state per integrity check, and so we can miss the reason for an
5611 * egress error if more than one packet fails the same integrity check
5612 * since we cleared the corresponding bit in SEND_EGRESS_ERR_INFO.
5614 static void handle_send_egress_err_info(struct hfi1_devdata
*dd
,
5617 struct hfi1_pportdata
*ppd
= dd
->pport
;
5618 u64 src
= read_csr(dd
, SEND_EGRESS_ERR_SOURCE
); /* read first */
5619 u64 info
= read_csr(dd
, SEND_EGRESS_ERR_INFO
);
5622 /* clear down all observed info as quickly as possible after read */
5623 write_csr(dd
, SEND_EGRESS_ERR_INFO
, info
);
5626 "Egress Error Info: 0x%llx, %s Egress Error Src 0x%llx\n",
5627 info
, egress_err_info_string(buf
, sizeof(buf
), info
), src
);
5629 /* Eventually add other counters for each bit */
5630 if (info
& PORT_DISCARD_EGRESS_ERRS
) {
5634 * Count all applicable bits as individual errors and
5635 * attribute them to the packet that triggered this handler.
5636 * This may not be completely accurate due to limitations
5637 * on the available hardware error information. There is
5638 * a single information register and any number of error
5639 * packets may have occurred and contributed to it before
5640 * this routine is called. This means that:
5641 * a) If multiple packets with the same error occur before
5642 * this routine is called, earlier packets are missed.
5643 * There is only a single bit for each error type.
5644 * b) Errors may not be attributed to the correct VL.
5645 * The driver is attributing all bits in the info register
5646 * to the packet that triggered this call, but bits
5647 * could be an accumulation of different packets with
5649 * c) A single error packet may have multiple counts attached
5650 * to it. There is no way for the driver to know if
5651 * multiple bits set in the info register are due to a
5652 * single packet or multiple packets. The driver assumes
5655 weight
= hweight64(info
& PORT_DISCARD_EGRESS_ERRS
);
5656 for (i
= 0; i
< weight
; i
++) {
5657 __count_port_discards(ppd
);
5658 if (vl
>= 0 && vl
< TXE_NUM_DATA_VL
)
5659 incr_cntr64(&ppd
->port_xmit_discards_vl
[vl
]);
5661 incr_cntr64(&ppd
->port_xmit_discards_vl
5668 * Input value is a bit position within the SEND_EGRESS_ERR_STATUS
5669 * register. Does it represent a 'port inactive' error?
5671 static inline int port_inactive_err(u64 posn
)
5673 return (posn
>= SEES(TX_LINKDOWN
) &&
5674 posn
<= SEES(TX_INCORRECT_LINK_STATE
));
5678 * Input value is a bit position within the SEND_EGRESS_ERR_STATUS
5679 * register. Does it represent a 'disallowed packet' error?
5681 static inline int disallowed_pkt_err(int posn
)
5683 return (posn
>= SEES(TX_SDMA0_DISALLOWED_PACKET
) &&
5684 posn
<= SEES(TX_SDMA15_DISALLOWED_PACKET
));
5688 * Input value is a bit position of one of the SDMA engine disallowed
5689 * packet errors. Return which engine. Use of this must be guarded by
5690 * disallowed_pkt_err().
5692 static inline int disallowed_pkt_engine(int posn
)
5694 return posn
- SEES(TX_SDMA0_DISALLOWED_PACKET
);
5698 * Translate an SDMA engine to a VL. Return -1 if the tranlation cannot
5701 static int engine_to_vl(struct hfi1_devdata
*dd
, int engine
)
5703 struct sdma_vl_map
*m
;
5707 if (engine
< 0 || engine
>= TXE_NUM_SDMA_ENGINES
)
5711 m
= rcu_dereference(dd
->sdma_map
);
5712 vl
= m
->engine_to_vl
[engine
];
5719 * Translate the send context (sofware index) into a VL. Return -1 if the
5720 * translation cannot be done.
5722 static int sc_to_vl(struct hfi1_devdata
*dd
, int sw_index
)
5724 struct send_context_info
*sci
;
5725 struct send_context
*sc
;
5728 sci
= &dd
->send_contexts
[sw_index
];
5730 /* there is no information for user (PSM) and ack contexts */
5731 if ((sci
->type
!= SC_KERNEL
) && (sci
->type
!= SC_VL15
))
5737 if (dd
->vld
[15].sc
== sc
)
5739 for (i
= 0; i
< num_vls
; i
++)
5740 if (dd
->vld
[i
].sc
== sc
)
5746 static void handle_egress_err(struct hfi1_devdata
*dd
, u32 unused
, u64 reg
)
5748 u64 reg_copy
= reg
, handled
= 0;
5752 if (reg
& ALL_TXE_EGRESS_FREEZE_ERR
)
5753 start_freeze_handling(dd
->pport
, 0);
5754 else if (is_ax(dd
) &&
5755 (reg
& SEND_EGRESS_ERR_STATUS_TX_CREDIT_RETURN_VL_ERR_SMASK
) &&
5756 (dd
->icode
!= ICODE_FUNCTIONAL_SIMULATOR
))
5757 start_freeze_handling(dd
->pport
, 0);
5760 int posn
= fls64(reg_copy
);
5761 /* fls64() returns a 1-based offset, we want it zero based */
5762 int shift
= posn
- 1;
5763 u64 mask
= 1ULL << shift
;
5765 if (port_inactive_err(shift
)) {
5766 count_port_inactive(dd
);
5768 } else if (disallowed_pkt_err(shift
)) {
5769 int vl
= engine_to_vl(dd
, disallowed_pkt_engine(shift
));
5771 handle_send_egress_err_info(dd
, vl
);
5780 dd_dev_info(dd
, "Egress Error: %s\n",
5781 egress_err_status_string(buf
, sizeof(buf
), reg
));
5783 for (i
= 0; i
< NUM_SEND_EGRESS_ERR_STATUS_COUNTERS
; i
++) {
5784 if (reg
& (1ull << i
))
5785 incr_cntr64(&dd
->send_egress_err_status_cnt
[i
]);
5789 static void handle_txe_err(struct hfi1_devdata
*dd
, u32 unused
, u64 reg
)
5794 dd_dev_info(dd
, "Send Error: %s\n",
5795 send_err_status_string(buf
, sizeof(buf
), reg
));
5797 for (i
= 0; i
< NUM_SEND_ERR_STATUS_COUNTERS
; i
++) {
5798 if (reg
& (1ull << i
))
5799 incr_cntr64(&dd
->send_err_status_cnt
[i
]);
5804 * The maximum number of times the error clear down will loop before
5805 * blocking a repeating error. This value is arbitrary.
5807 #define MAX_CLEAR_COUNT 20
5810 * Clear and handle an error register. All error interrupts are funneled
5811 * through here to have a central location to correctly handle single-
5812 * or multi-shot errors.
5814 * For non per-context registers, call this routine with a context value
5815 * of 0 so the per-context offset is zero.
5817 * If the handler loops too many times, assume that something is wrong
5818 * and can't be fixed, so mask the error bits.
5820 static void interrupt_clear_down(struct hfi1_devdata
*dd
,
5822 const struct err_reg_info
*eri
)
5827 /* read in a loop until no more errors are seen */
5830 reg
= read_kctxt_csr(dd
, context
, eri
->status
);
5833 write_kctxt_csr(dd
, context
, eri
->clear
, reg
);
5834 if (likely(eri
->handler
))
5835 eri
->handler(dd
, context
, reg
);
5837 if (count
> MAX_CLEAR_COUNT
) {
5840 dd_dev_err(dd
, "Repeating %s bits 0x%llx - masking\n",
5843 * Read-modify-write so any other masked bits
5846 mask
= read_kctxt_csr(dd
, context
, eri
->mask
);
5848 write_kctxt_csr(dd
, context
, eri
->mask
, mask
);
5855 * CCE block "misc" interrupt. Source is < 16.
5857 static void is_misc_err_int(struct hfi1_devdata
*dd
, unsigned int source
)
5859 const struct err_reg_info
*eri
= &misc_errs
[source
];
5862 interrupt_clear_down(dd
, 0, eri
);
5864 dd_dev_err(dd
, "Unexpected misc interrupt (%u) - reserved\n",
5869 static char *send_context_err_status_string(char *buf
, int buf_len
, u64 flags
)
5871 return flag_string(buf
, buf_len
, flags
,
5872 sc_err_status_flags
,
5873 ARRAY_SIZE(sc_err_status_flags
));
5877 * Send context error interrupt. Source (hw_context) is < 160.
5879 * All send context errors cause the send context to halt. The normal
5880 * clear-down mechanism cannot be used because we cannot clear the
5881 * error bits until several other long-running items are done first.
5882 * This is OK because with the context halted, nothing else is going
5883 * to happen on it anyway.
5885 static void is_sendctxt_err_int(struct hfi1_devdata
*dd
,
5886 unsigned int hw_context
)
5888 struct send_context_info
*sci
;
5889 struct send_context
*sc
;
5895 sw_index
= dd
->hw_to_sw
[hw_context
];
5896 if (sw_index
>= dd
->num_send_contexts
) {
5898 "out of range sw index %u for send context %u\n",
5899 sw_index
, hw_context
);
5902 sci
= &dd
->send_contexts
[sw_index
];
5905 dd_dev_err(dd
, "%s: context %u(%u): no sc?\n", __func__
,
5906 sw_index
, hw_context
);
5910 /* tell the software that a halt has begun */
5911 sc_stop(sc
, SCF_HALTED
);
5913 status
= read_kctxt_csr(dd
, hw_context
, SEND_CTXT_ERR_STATUS
);
5915 dd_dev_info(dd
, "Send Context %u(%u) Error: %s\n", sw_index
, hw_context
,
5916 send_context_err_status_string(flags
, sizeof(flags
),
5919 if (status
& SEND_CTXT_ERR_STATUS_PIO_DISALLOWED_PACKET_ERR_SMASK
)
5920 handle_send_egress_err_info(dd
, sc_to_vl(dd
, sw_index
));
5923 * Automatically restart halted kernel contexts out of interrupt
5924 * context. User contexts must ask the driver to restart the context.
5926 if (sc
->type
!= SC_USER
)
5927 queue_work(dd
->pport
->hfi1_wq
, &sc
->halt_work
);
5930 * Update the counters for the corresponding status bits.
5931 * Note that these particular counters are aggregated over all
5934 for (i
= 0; i
< NUM_SEND_CTXT_ERR_STATUS_COUNTERS
; i
++) {
5935 if (status
& (1ull << i
))
5936 incr_cntr64(&dd
->sw_ctxt_err_status_cnt
[i
]);
5940 static void handle_sdma_eng_err(struct hfi1_devdata
*dd
,
5941 unsigned int source
, u64 status
)
5943 struct sdma_engine
*sde
;
5946 sde
= &dd
->per_sdma
[source
];
5947 #ifdef CONFIG_SDMA_VERBOSITY
5948 dd_dev_err(sde
->dd
, "CONFIG SDMA(%u) %s:%d %s()\n", sde
->this_idx
,
5949 slashstrip(__FILE__
), __LINE__
, __func__
);
5950 dd_dev_err(sde
->dd
, "CONFIG SDMA(%u) source: %u status 0x%llx\n",
5951 sde
->this_idx
, source
, (unsigned long long)status
);
5954 sdma_engine_error(sde
, status
);
5957 * Update the counters for the corresponding status bits.
5958 * Note that these particular counters are aggregated over
5959 * all 16 DMA engines.
5961 for (i
= 0; i
< NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS
; i
++) {
5962 if (status
& (1ull << i
))
5963 incr_cntr64(&dd
->sw_send_dma_eng_err_status_cnt
[i
]);
5968 * CCE block SDMA error interrupt. Source is < 16.
5970 static void is_sdma_eng_err_int(struct hfi1_devdata
*dd
, unsigned int source
)
5972 #ifdef CONFIG_SDMA_VERBOSITY
5973 struct sdma_engine
*sde
= &dd
->per_sdma
[source
];
5975 dd_dev_err(dd
, "CONFIG SDMA(%u) %s:%d %s()\n", sde
->this_idx
,
5976 slashstrip(__FILE__
), __LINE__
, __func__
);
5977 dd_dev_err(dd
, "CONFIG SDMA(%u) source: %u\n", sde
->this_idx
,
5979 sdma_dumpstate(sde
);
5981 interrupt_clear_down(dd
, source
, &sdma_eng_err
);
5985 * CCE block "various" interrupt. Source is < 8.
5987 static void is_various_int(struct hfi1_devdata
*dd
, unsigned int source
)
5989 const struct err_reg_info
*eri
= &various_err
[source
];
5992 * TCritInt cannot go through interrupt_clear_down()
5993 * because it is not a second tier interrupt. The handler
5994 * should be called directly.
5996 if (source
== TCRIT_INT_SOURCE
)
5997 handle_temp_err(dd
);
5998 else if (eri
->handler
)
5999 interrupt_clear_down(dd
, 0, eri
);
6002 "%s: Unimplemented/reserved interrupt %d\n",
6006 static void handle_qsfp_int(struct hfi1_devdata
*dd
, u32 src_ctx
, u64 reg
)
6008 /* src_ctx is always zero */
6009 struct hfi1_pportdata
*ppd
= dd
->pport
;
6010 unsigned long flags
;
6011 u64 qsfp_int_mgmt
= (u64
)(QSFP_HFI0_INT_N
| QSFP_HFI0_MODPRST_N
);
6013 if (reg
& QSFP_HFI0_MODPRST_N
) {
6014 if (!qsfp_mod_present(ppd
)) {
6015 dd_dev_info(dd
, "%s: QSFP module removed\n",
6018 ppd
->driver_link_ready
= 0;
6020 * Cable removed, reset all our information about the
6021 * cache and cable capabilities
6024 spin_lock_irqsave(&ppd
->qsfp_info
.qsfp_lock
, flags
);
6026 * We don't set cache_refresh_required here as we expect
6027 * an interrupt when a cable is inserted
6029 ppd
->qsfp_info
.cache_valid
= 0;
6030 ppd
->qsfp_info
.reset_needed
= 0;
6031 ppd
->qsfp_info
.limiting_active
= 0;
6032 spin_unlock_irqrestore(&ppd
->qsfp_info
.qsfp_lock
,
6034 /* Invert the ModPresent pin now to detect plug-in */
6035 write_csr(dd
, dd
->hfi1_id
? ASIC_QSFP2_INVERT
:
6036 ASIC_QSFP1_INVERT
, qsfp_int_mgmt
);
6038 if ((ppd
->offline_disabled_reason
>
6040 OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED
)) ||
6041 (ppd
->offline_disabled_reason
==
6042 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE
)))
6043 ppd
->offline_disabled_reason
=
6045 OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED
);
6047 if (ppd
->host_link_state
== HLS_DN_POLL
) {
6049 * The link is still in POLL. This means
6050 * that the normal link down processing
6051 * will not happen. We have to do it here
6052 * before turning the DC off.
6054 queue_work(ppd
->hfi1_wq
, &ppd
->link_down_work
);
6057 dd_dev_info(dd
, "%s: QSFP module inserted\n",
6060 spin_lock_irqsave(&ppd
->qsfp_info
.qsfp_lock
, flags
);
6061 ppd
->qsfp_info
.cache_valid
= 0;
6062 ppd
->qsfp_info
.cache_refresh_required
= 1;
6063 spin_unlock_irqrestore(&ppd
->qsfp_info
.qsfp_lock
,
6067 * Stop inversion of ModPresent pin to detect
6068 * removal of the cable
6070 qsfp_int_mgmt
&= ~(u64
)QSFP_HFI0_MODPRST_N
;
6071 write_csr(dd
, dd
->hfi1_id
? ASIC_QSFP2_INVERT
:
6072 ASIC_QSFP1_INVERT
, qsfp_int_mgmt
);
6074 ppd
->offline_disabled_reason
=
6075 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_TRANSIENT
);
6079 if (reg
& QSFP_HFI0_INT_N
) {
6080 dd_dev_info(dd
, "%s: Interrupt received from QSFP module\n",
6082 spin_lock_irqsave(&ppd
->qsfp_info
.qsfp_lock
, flags
);
6083 ppd
->qsfp_info
.check_interrupt_flags
= 1;
6084 spin_unlock_irqrestore(&ppd
->qsfp_info
.qsfp_lock
, flags
);
6087 /* Schedule the QSFP work only if there is a cable attached. */
6088 if (qsfp_mod_present(ppd
))
6089 queue_work(ppd
->hfi1_wq
, &ppd
->qsfp_info
.qsfp_work
);
6092 static int request_host_lcb_access(struct hfi1_devdata
*dd
)
6096 ret
= do_8051_command(dd
, HCMD_MISC
,
6097 (u64
)HCMD_MISC_REQUEST_LCB_ACCESS
<<
6098 LOAD_DATA_FIELD_ID_SHIFT
, NULL
);
6099 if (ret
!= HCMD_SUCCESS
) {
6100 dd_dev_err(dd
, "%s: command failed with error %d\n",
6103 return ret
== HCMD_SUCCESS
? 0 : -EBUSY
;
6106 static int request_8051_lcb_access(struct hfi1_devdata
*dd
)
6110 ret
= do_8051_command(dd
, HCMD_MISC
,
6111 (u64
)HCMD_MISC_GRANT_LCB_ACCESS
<<
6112 LOAD_DATA_FIELD_ID_SHIFT
, NULL
);
6113 if (ret
!= HCMD_SUCCESS
) {
6114 dd_dev_err(dd
, "%s: command failed with error %d\n",
6117 return ret
== HCMD_SUCCESS
? 0 : -EBUSY
;
6121 * Set the LCB selector - allow host access. The DCC selector always
6122 * points to the host.
6124 static inline void set_host_lcb_access(struct hfi1_devdata
*dd
)
6126 write_csr(dd
, DC_DC8051_CFG_CSR_ACCESS_SEL
,
6127 DC_DC8051_CFG_CSR_ACCESS_SEL_DCC_SMASK
|
6128 DC_DC8051_CFG_CSR_ACCESS_SEL_LCB_SMASK
);
6132 * Clear the LCB selector - allow 8051 access. The DCC selector always
6133 * points to the host.
6135 static inline void set_8051_lcb_access(struct hfi1_devdata
*dd
)
6137 write_csr(dd
, DC_DC8051_CFG_CSR_ACCESS_SEL
,
6138 DC_DC8051_CFG_CSR_ACCESS_SEL_DCC_SMASK
);
6142 * Acquire LCB access from the 8051. If the host already has access,
6143 * just increment a counter. Otherwise, inform the 8051 that the
6144 * host is taking access.
6148 * -EBUSY if the 8051 has control and cannot be disturbed
6149 * -errno if unable to acquire access from the 8051
6151 int acquire_lcb_access(struct hfi1_devdata
*dd
, int sleep_ok
)
6153 struct hfi1_pportdata
*ppd
= dd
->pport
;
6157 * Use the host link state lock so the operation of this routine
6158 * { link state check, selector change, count increment } can occur
6159 * as a unit against a link state change. Otherwise there is a
6160 * race between the state change and the count increment.
6163 mutex_lock(&ppd
->hls_lock
);
6165 while (!mutex_trylock(&ppd
->hls_lock
))
6169 /* this access is valid only when the link is up */
6170 if (ppd
->host_link_state
& HLS_DOWN
) {
6171 dd_dev_info(dd
, "%s: link state %s not up\n",
6172 __func__
, link_state_name(ppd
->host_link_state
));
6177 if (dd
->lcb_access_count
== 0) {
6178 ret
= request_host_lcb_access(dd
);
6181 "%s: unable to acquire LCB access, err %d\n",
6185 set_host_lcb_access(dd
);
6187 dd
->lcb_access_count
++;
6189 mutex_unlock(&ppd
->hls_lock
);
6194 * Release LCB access by decrementing the use count. If the count is moving
6195 * from 1 to 0, inform 8051 that it has control back.
6199 * -errno if unable to release access to the 8051
6201 int release_lcb_access(struct hfi1_devdata
*dd
, int sleep_ok
)
6206 * Use the host link state lock because the acquire needed it.
6207 * Here, we only need to keep { selector change, count decrement }
6211 mutex_lock(&dd
->pport
->hls_lock
);
6213 while (!mutex_trylock(&dd
->pport
->hls_lock
))
6217 if (dd
->lcb_access_count
== 0) {
6218 dd_dev_err(dd
, "%s: LCB access count is zero. Skipping.\n",
6223 if (dd
->lcb_access_count
== 1) {
6224 set_8051_lcb_access(dd
);
6225 ret
= request_8051_lcb_access(dd
);
6228 "%s: unable to release LCB access, err %d\n",
6230 /* restore host access if the grant didn't work */
6231 set_host_lcb_access(dd
);
6235 dd
->lcb_access_count
--;
6237 mutex_unlock(&dd
->pport
->hls_lock
);
6242 * Initialize LCB access variables and state. Called during driver load,
6243 * after most of the initialization is finished.
6245 * The DC default is LCB access on for the host. The driver defaults to
6246 * leaving access to the 8051. Assign access now - this constrains the call
6247 * to this routine to be after all LCB set-up is done. In particular, after
6248 * hf1_init_dd() -> set_up_interrupts() -> clear_all_interrupts()
6250 static void init_lcb_access(struct hfi1_devdata
*dd
)
6252 dd
->lcb_access_count
= 0;
6256 * Write a response back to a 8051 request.
6258 static void hreq_response(struct hfi1_devdata
*dd
, u8 return_code
, u16 rsp_data
)
6260 write_csr(dd
, DC_DC8051_CFG_EXT_DEV_0
,
6261 DC_DC8051_CFG_EXT_DEV_0_COMPLETED_SMASK
|
6263 DC_DC8051_CFG_EXT_DEV_0_RETURN_CODE_SHIFT
|
6264 (u64
)rsp_data
<< DC_DC8051_CFG_EXT_DEV_0_RSP_DATA_SHIFT
);
6268 * Handle host requests from the 8051.
6270 static void handle_8051_request(struct hfi1_pportdata
*ppd
)
6272 struct hfi1_devdata
*dd
= ppd
->dd
;
6277 reg
= read_csr(dd
, DC_DC8051_CFG_EXT_DEV_1
);
6278 if ((reg
& DC_DC8051_CFG_EXT_DEV_1_REQ_NEW_SMASK
) == 0)
6279 return; /* no request */
6281 /* zero out COMPLETED so the response is seen */
6282 write_csr(dd
, DC_DC8051_CFG_EXT_DEV_0
, 0);
6284 /* extract request details */
6285 type
= (reg
>> DC_DC8051_CFG_EXT_DEV_1_REQ_TYPE_SHIFT
)
6286 & DC_DC8051_CFG_EXT_DEV_1_REQ_TYPE_MASK
;
6287 data
= (reg
>> DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SHIFT
)
6288 & DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_MASK
;
6291 case HREQ_LOAD_CONFIG
:
6292 case HREQ_SAVE_CONFIG
:
6293 case HREQ_READ_CONFIG
:
6294 case HREQ_SET_TX_EQ_ABS
:
6295 case HREQ_SET_TX_EQ_REL
:
6297 dd_dev_info(dd
, "8051 request: request 0x%x not supported\n",
6299 hreq_response(dd
, HREQ_NOT_SUPPORTED
, 0);
6301 case HREQ_CONFIG_DONE
:
6302 hreq_response(dd
, HREQ_SUCCESS
, 0);
6305 case HREQ_INTERFACE_TEST
:
6306 hreq_response(dd
, HREQ_SUCCESS
, data
);
6309 dd_dev_err(dd
, "8051 request: unknown request 0x%x\n", type
);
6310 hreq_response(dd
, HREQ_NOT_SUPPORTED
, 0);
6316 * Set up allocation unit vaulue.
6318 void set_up_vau(struct hfi1_devdata
*dd
, u8 vau
)
6320 u64 reg
= read_csr(dd
, SEND_CM_GLOBAL_CREDIT
);
6322 /* do not modify other values in the register */
6323 reg
&= ~SEND_CM_GLOBAL_CREDIT_AU_SMASK
;
6324 reg
|= (u64
)vau
<< SEND_CM_GLOBAL_CREDIT_AU_SHIFT
;
6325 write_csr(dd
, SEND_CM_GLOBAL_CREDIT
, reg
);
6329 * Set up initial VL15 credits of the remote. Assumes the rest of
6330 * the CM credit registers are zero from a previous global or credit reset.
6331 * Shared limit for VL15 will always be 0.
6333 void set_up_vl15(struct hfi1_devdata
*dd
, u16 vl15buf
)
6335 u64 reg
= read_csr(dd
, SEND_CM_GLOBAL_CREDIT
);
6337 /* set initial values for total and shared credit limit */
6338 reg
&= ~(SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SMASK
|
6339 SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SMASK
);
6342 * Set total limit to be equal to VL15 credits.
6343 * Leave shared limit at 0.
6345 reg
|= (u64
)vl15buf
<< SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT
;
6346 write_csr(dd
, SEND_CM_GLOBAL_CREDIT
, reg
);
6348 write_csr(dd
, SEND_CM_CREDIT_VL15
, (u64
)vl15buf
6349 << SEND_CM_CREDIT_VL15_DEDICATED_LIMIT_VL_SHIFT
);
6353 * Zero all credit details from the previous connection and
6354 * reset the CM manager's internal counters.
6356 void reset_link_credits(struct hfi1_devdata
*dd
)
6360 /* remove all previous VL credit limits */
6361 for (i
= 0; i
< TXE_NUM_DATA_VL
; i
++)
6362 write_csr(dd
, SEND_CM_CREDIT_VL
+ (8 * i
), 0);
6363 write_csr(dd
, SEND_CM_CREDIT_VL15
, 0);
6364 write_csr(dd
, SEND_CM_GLOBAL_CREDIT
, 0);
6365 /* reset the CM block */
6366 pio_send_control(dd
, PSC_CM_RESET
);
6367 /* reset cached value */
6368 dd
->vl15buf_cached
= 0;
6371 /* convert a vCU to a CU */
6372 static u32
vcu_to_cu(u8 vcu
)
6377 /* convert a CU to a vCU */
6378 static u8
cu_to_vcu(u32 cu
)
6383 /* convert a vAU to an AU */
6384 static u32
vau_to_au(u8 vau
)
6386 return 8 * (1 << vau
);
6389 static void set_linkup_defaults(struct hfi1_pportdata
*ppd
)
6391 ppd
->sm_trap_qp
= 0x0;
6396 * Graceful LCB shutdown. This leaves the LCB FIFOs in reset.
6398 static void lcb_shutdown(struct hfi1_devdata
*dd
, int abort
)
6402 /* clear lcb run: LCB_CFG_RUN.EN = 0 */
6403 write_csr(dd
, DC_LCB_CFG_RUN
, 0);
6404 /* set tx fifo reset: LCB_CFG_TX_FIFOS_RESET.VAL = 1 */
6405 write_csr(dd
, DC_LCB_CFG_TX_FIFOS_RESET
,
6406 1ull << DC_LCB_CFG_TX_FIFOS_RESET_VAL_SHIFT
);
6407 /* set dcc reset csr: DCC_CFG_RESET.{reset_lcb,reset_rx_fpe} = 1 */
6408 dd
->lcb_err_en
= read_csr(dd
, DC_LCB_ERR_EN
);
6409 reg
= read_csr(dd
, DCC_CFG_RESET
);
6410 write_csr(dd
, DCC_CFG_RESET
, reg
|
6411 (1ull << DCC_CFG_RESET_RESET_LCB_SHIFT
) |
6412 (1ull << DCC_CFG_RESET_RESET_RX_FPE_SHIFT
));
6413 (void)read_csr(dd
, DCC_CFG_RESET
); /* make sure the write completed */
6415 udelay(1); /* must hold for the longer of 16cclks or 20ns */
6416 write_csr(dd
, DCC_CFG_RESET
, reg
);
6417 write_csr(dd
, DC_LCB_ERR_EN
, dd
->lcb_err_en
);
6422 * This routine should be called after the link has been transitioned to
6423 * OFFLINE (OFFLINE state has the side effect of putting the SerDes into
6426 * The expectation is that the caller of this routine would have taken
6427 * care of properly transitioning the link into the correct state.
6428 * NOTE: the caller needs to acquire the dd->dc8051_lock lock
6429 * before calling this function.
6431 static void _dc_shutdown(struct hfi1_devdata
*dd
)
6433 lockdep_assert_held(&dd
->dc8051_lock
);
6435 if (dd
->dc_shutdown
)
6438 dd
->dc_shutdown
= 1;
6439 /* Shutdown the LCB */
6440 lcb_shutdown(dd
, 1);
6442 * Going to OFFLINE would have causes the 8051 to put the
6443 * SerDes into reset already. Just need to shut down the 8051,
6446 write_csr(dd
, DC_DC8051_CFG_RST
, 0x1);
6449 static void dc_shutdown(struct hfi1_devdata
*dd
)
6451 mutex_lock(&dd
->dc8051_lock
);
6453 mutex_unlock(&dd
->dc8051_lock
);
6457 * Calling this after the DC has been brought out of reset should not
6459 * NOTE: the caller needs to acquire the dd->dc8051_lock lock
6460 * before calling this function.
6462 static void _dc_start(struct hfi1_devdata
*dd
)
6464 lockdep_assert_held(&dd
->dc8051_lock
);
6466 if (!dd
->dc_shutdown
)
6469 /* Take the 8051 out of reset */
6470 write_csr(dd
, DC_DC8051_CFG_RST
, 0ull);
6471 /* Wait until 8051 is ready */
6472 if (wait_fm_ready(dd
, TIMEOUT_8051_START
))
6473 dd_dev_err(dd
, "%s: timeout starting 8051 firmware\n",
6476 /* Take away reset for LCB and RX FPE (set in lcb_shutdown). */
6477 write_csr(dd
, DCC_CFG_RESET
, 0x10);
6478 /* lcb_shutdown() with abort=1 does not restore these */
6479 write_csr(dd
, DC_LCB_ERR_EN
, dd
->lcb_err_en
);
6480 dd
->dc_shutdown
= 0;
6483 static void dc_start(struct hfi1_devdata
*dd
)
6485 mutex_lock(&dd
->dc8051_lock
);
6487 mutex_unlock(&dd
->dc8051_lock
);
6491 * These LCB adjustments are for the Aurora SerDes core in the FPGA.
6493 static void adjust_lcb_for_fpga_serdes(struct hfi1_devdata
*dd
)
6495 u64 rx_radr
, tx_radr
;
6498 if (dd
->icode
!= ICODE_FPGA_EMULATION
)
6502 * These LCB defaults on emulator _s are good, nothing to do here:
6503 * LCB_CFG_TX_FIFOS_RADR
6504 * LCB_CFG_RX_FIFOS_RADR
6506 * LCB_CFG_IGNORE_LOST_RCLK
6508 if (is_emulator_s(dd
))
6510 /* else this is _p */
6512 version
= emulator_rev(dd
);
6514 version
= 0x2d; /* all B0 use 0x2d or higher settings */
6516 if (version
<= 0x12) {
6517 /* release 0x12 and below */
6520 * LCB_CFG_RX_FIFOS_RADR.RST_VAL = 0x9
6521 * LCB_CFG_RX_FIFOS_RADR.OK_TO_JUMP_VAL = 0x9
6522 * LCB_CFG_RX_FIFOS_RADR.DO_NOT_JUMP_VAL = 0xa
6525 0xaull
<< DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6526 | 0x9ull
<< DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6527 | 0x9ull
<< DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT
;
6529 * LCB_CFG_TX_FIFOS_RADR.ON_REINIT = 0 (default)
6530 * LCB_CFG_TX_FIFOS_RADR.RST_VAL = 6
6532 tx_radr
= 6ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT
;
6533 } else if (version
<= 0x18) {
6534 /* release 0x13 up to 0x18 */
6535 /* LCB_CFG_RX_FIFOS_RADR = 0x988 */
6537 0x9ull
<< DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6538 | 0x8ull
<< DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6539 | 0x8ull
<< DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT
;
6540 tx_radr
= 7ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT
;
6541 } else if (version
== 0x19) {
6543 /* LCB_CFG_RX_FIFOS_RADR = 0xa99 */
6545 0xAull
<< DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6546 | 0x9ull
<< DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6547 | 0x9ull
<< DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT
;
6548 tx_radr
= 3ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT
;
6549 } else if (version
== 0x1a) {
6551 /* LCB_CFG_RX_FIFOS_RADR = 0x988 */
6553 0x9ull
<< DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6554 | 0x8ull
<< DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6555 | 0x8ull
<< DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT
;
6556 tx_radr
= 7ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT
;
6557 write_csr(dd
, DC_LCB_CFG_LN_DCLK
, 1ull);
6559 /* release 0x1b and higher */
6560 /* LCB_CFG_RX_FIFOS_RADR = 0x877 */
6562 0x8ull
<< DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT
6563 | 0x7ull
<< DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT
6564 | 0x7ull
<< DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT
;
6565 tx_radr
= 3ull << DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT
;
6568 write_csr(dd
, DC_LCB_CFG_RX_FIFOS_RADR
, rx_radr
);
6569 /* LCB_CFG_IGNORE_LOST_RCLK.EN = 1 */
6570 write_csr(dd
, DC_LCB_CFG_IGNORE_LOST_RCLK
,
6571 DC_LCB_CFG_IGNORE_LOST_RCLK_EN_SMASK
);
6572 write_csr(dd
, DC_LCB_CFG_TX_FIFOS_RADR
, tx_radr
);
6576 * Handle a SMA idle message
6578 * This is a work-queue function outside of the interrupt.
6580 void handle_sma_message(struct work_struct
*work
)
6582 struct hfi1_pportdata
*ppd
= container_of(work
, struct hfi1_pportdata
,
6584 struct hfi1_devdata
*dd
= ppd
->dd
;
6589 * msg is bytes 1-4 of the 40-bit idle message - the command code
6592 ret
= read_idle_sma(dd
, &msg
);
6595 dd_dev_info(dd
, "%s: SMA message 0x%llx\n", __func__
, msg
);
6597 * React to the SMA message. Byte[1] (0 for us) is the command.
6599 switch (msg
& 0xff) {
6602 * See OPAv1 table 9-14 - HFI and External Switch Ports Key
6605 * Only expected in INIT or ARMED, discard otherwise.
6607 if (ppd
->host_link_state
& (HLS_UP_INIT
| HLS_UP_ARMED
))
6608 ppd
->neighbor_normal
= 1;
6610 case SMA_IDLE_ACTIVE
:
6612 * See OPAv1 table 9-14 - HFI and External Switch Ports Key
6615 * Can activate the node. Discard otherwise.
6617 if (ppd
->host_link_state
== HLS_UP_ARMED
&&
6618 ppd
->is_active_optimize_enabled
) {
6619 ppd
->neighbor_normal
= 1;
6620 ret
= set_link_state(ppd
, HLS_UP_ACTIVE
);
6624 "%s: received Active SMA idle message, couldn't set link to Active\n",
6630 "%s: received unexpected SMA idle message 0x%llx\n",
6636 static void adjust_rcvctrl(struct hfi1_devdata
*dd
, u64 add
, u64 clear
)
6639 unsigned long flags
;
6641 spin_lock_irqsave(&dd
->rcvctrl_lock
, flags
);
6642 rcvctrl
= read_csr(dd
, RCV_CTRL
);
6645 write_csr(dd
, RCV_CTRL
, rcvctrl
);
6646 spin_unlock_irqrestore(&dd
->rcvctrl_lock
, flags
);
6649 static inline void add_rcvctrl(struct hfi1_devdata
*dd
, u64 add
)
6651 adjust_rcvctrl(dd
, add
, 0);
6654 static inline void clear_rcvctrl(struct hfi1_devdata
*dd
, u64 clear
)
6656 adjust_rcvctrl(dd
, 0, clear
);
6660 * Called from all interrupt handlers to start handling an SPC freeze.
6662 void start_freeze_handling(struct hfi1_pportdata
*ppd
, int flags
)
6664 struct hfi1_devdata
*dd
= ppd
->dd
;
6665 struct send_context
*sc
;
6668 if (flags
& FREEZE_SELF
)
6669 write_csr(dd
, CCE_CTRL
, CCE_CTRL_SPC_FREEZE_SMASK
);
6671 /* enter frozen mode */
6672 dd
->flags
|= HFI1_FROZEN
;
6674 /* notify all SDMA engines that they are going into a freeze */
6675 sdma_freeze_notify(dd
, !!(flags
& FREEZE_LINK_DOWN
));
6677 /* do halt pre-handling on all enabled send contexts */
6678 for (i
= 0; i
< dd
->num_send_contexts
; i
++) {
6679 sc
= dd
->send_contexts
[i
].sc
;
6680 if (sc
&& (sc
->flags
& SCF_ENABLED
))
6681 sc_stop(sc
, SCF_FROZEN
| SCF_HALTED
);
6684 /* Send context are frozen. Notify user space */
6685 hfi1_set_uevent_bits(ppd
, _HFI1_EVENT_FROZEN_BIT
);
6687 if (flags
& FREEZE_ABORT
) {
6689 "Aborted freeze recovery. Please REBOOT system\n");
6692 /* queue non-interrupt handler */
6693 queue_work(ppd
->hfi1_wq
, &ppd
->freeze_work
);
6697 * Wait until all 4 sub-blocks indicate that they have frozen or unfrozen,
6698 * depending on the "freeze" parameter.
6700 * No need to return an error if it times out, our only option
6701 * is to proceed anyway.
6703 static void wait_for_freeze_status(struct hfi1_devdata
*dd
, int freeze
)
6705 unsigned long timeout
;
6708 timeout
= jiffies
+ msecs_to_jiffies(FREEZE_STATUS_TIMEOUT
);
6710 reg
= read_csr(dd
, CCE_STATUS
);
6712 /* waiting until all indicators are set */
6713 if ((reg
& ALL_FROZE
) == ALL_FROZE
)
6714 return; /* all done */
6716 /* waiting until all indicators are clear */
6717 if ((reg
& ALL_FROZE
) == 0)
6718 return; /* all done */
6721 if (time_after(jiffies
, timeout
)) {
6723 "Time out waiting for SPC %sfreeze, bits 0x%llx, expecting 0x%llx, continuing",
6724 freeze
? "" : "un", reg
& ALL_FROZE
,
6725 freeze
? ALL_FROZE
: 0ull);
6728 usleep_range(80, 120);
6733 * Do all freeze handling for the RXE block.
6735 static void rxe_freeze(struct hfi1_devdata
*dd
)
6740 clear_rcvctrl(dd
, RCV_CTRL_RCV_PORT_ENABLE_SMASK
);
6742 /* disable all receive contexts */
6743 for (i
= 0; i
< dd
->num_rcv_contexts
; i
++)
6744 hfi1_rcvctrl(dd
, HFI1_RCVCTRL_CTXT_DIS
, i
);
6748 * Unfreeze handling for the RXE block - kernel contexts only.
6749 * This will also enable the port. User contexts will do unfreeze
6750 * handling on a per-context basis as they call into the driver.
6753 static void rxe_kernel_unfreeze(struct hfi1_devdata
*dd
)
6758 /* enable all kernel contexts */
6759 for (i
= 0; i
< dd
->num_rcv_contexts
; i
++) {
6760 struct hfi1_ctxtdata
*rcd
= dd
->rcd
[i
];
6762 /* Ensure all non-user contexts(including vnic) are enabled */
6763 if (!rcd
|| !rcd
->sc
|| (rcd
->sc
->type
== SC_USER
))
6766 rcvmask
= HFI1_RCVCTRL_CTXT_ENB
;
6767 /* HFI1_RCVCTRL_TAILUPD_[ENB|DIS] needs to be set explicitly */
6768 rcvmask
|= HFI1_CAP_KGET_MASK(dd
->rcd
[i
]->flags
, DMA_RTAIL
) ?
6769 HFI1_RCVCTRL_TAILUPD_ENB
: HFI1_RCVCTRL_TAILUPD_DIS
;
6770 hfi1_rcvctrl(dd
, rcvmask
, i
);
6774 add_rcvctrl(dd
, RCV_CTRL_RCV_PORT_ENABLE_SMASK
);
6778 * Non-interrupt SPC freeze handling.
6780 * This is a work-queue function outside of the triggering interrupt.
6782 void handle_freeze(struct work_struct
*work
)
6784 struct hfi1_pportdata
*ppd
= container_of(work
, struct hfi1_pportdata
,
6786 struct hfi1_devdata
*dd
= ppd
->dd
;
6788 /* wait for freeze indicators on all affected blocks */
6789 wait_for_freeze_status(dd
, 1);
6791 /* SPC is now frozen */
6793 /* do send PIO freeze steps */
6796 /* do send DMA freeze steps */
6799 /* do send egress freeze steps - nothing to do */
6801 /* do receive freeze steps */
6805 * Unfreeze the hardware - clear the freeze, wait for each
6806 * block's frozen bit to clear, then clear the frozen flag.
6808 write_csr(dd
, CCE_CTRL
, CCE_CTRL_SPC_UNFREEZE_SMASK
);
6809 wait_for_freeze_status(dd
, 0);
6812 write_csr(dd
, CCE_CTRL
, CCE_CTRL_SPC_FREEZE_SMASK
);
6813 wait_for_freeze_status(dd
, 1);
6814 write_csr(dd
, CCE_CTRL
, CCE_CTRL_SPC_UNFREEZE_SMASK
);
6815 wait_for_freeze_status(dd
, 0);
6818 /* do send PIO unfreeze steps for kernel contexts */
6819 pio_kernel_unfreeze(dd
);
6821 /* do send DMA unfreeze steps */
6824 /* do send egress unfreeze steps - nothing to do */
6826 /* do receive unfreeze steps for kernel contexts */
6827 rxe_kernel_unfreeze(dd
);
6830 * The unfreeze procedure touches global device registers when
6831 * it disables and re-enables RXE. Mark the device unfrozen
6832 * after all that is done so other parts of the driver waiting
6833 * for the device to unfreeze don't do things out of order.
6835 * The above implies that the meaning of HFI1_FROZEN flag is
6836 * "Device has gone into freeze mode and freeze mode handling
6837 * is still in progress."
6839 * The flag will be removed when freeze mode processing has
6842 dd
->flags
&= ~HFI1_FROZEN
;
6843 wake_up(&dd
->event_queue
);
6845 /* no longer frozen */
6849 * Handle a link up interrupt from the 8051.
6851 * This is a work-queue function outside of the interrupt.
6853 void handle_link_up(struct work_struct
*work
)
6855 struct hfi1_pportdata
*ppd
= container_of(work
, struct hfi1_pportdata
,
6857 struct hfi1_devdata
*dd
= ppd
->dd
;
6859 set_link_state(ppd
, HLS_UP_INIT
);
6861 /* cache the read of DC_LCB_STS_ROUND_TRIP_LTP_CNT */
6864 * OPA specifies that certain counters are cleared on a transition
6865 * to link up, so do that.
6867 clear_linkup_counters(dd
);
6869 * And (re)set link up default values.
6871 set_linkup_defaults(ppd
);
6874 * Set VL15 credits. Use cached value from verify cap interrupt.
6875 * In case of quick linkup or simulator, vl15 value will be set by
6876 * handle_linkup_change. VerifyCap interrupt handler will not be
6877 * called in those scenarios.
6879 if (!(quick_linkup
|| dd
->icode
== ICODE_FUNCTIONAL_SIMULATOR
))
6880 set_up_vl15(dd
, dd
->vl15buf_cached
);
6882 /* enforce link speed enabled */
6883 if ((ppd
->link_speed_active
& ppd
->link_speed_enabled
) == 0) {
6884 /* oops - current speed is not enabled, bounce */
6886 "Link speed active 0x%x is outside enabled 0x%x, downing link\n",
6887 ppd
->link_speed_active
, ppd
->link_speed_enabled
);
6888 set_link_down_reason(ppd
, OPA_LINKDOWN_REASON_SPEED_POLICY
, 0,
6889 OPA_LINKDOWN_REASON_SPEED_POLICY
);
6890 set_link_state(ppd
, HLS_DN_OFFLINE
);
6896 * Several pieces of LNI information were cached for SMA in ppd.
6897 * Reset these on link down
6899 static void reset_neighbor_info(struct hfi1_pportdata
*ppd
)
6901 ppd
->neighbor_guid
= 0;
6902 ppd
->neighbor_port_number
= 0;
6903 ppd
->neighbor_type
= 0;
6904 ppd
->neighbor_fm_security
= 0;
6907 static const char * const link_down_reason_strs
[] = {
6908 [OPA_LINKDOWN_REASON_NONE
] = "None",
6909 [OPA_LINKDOWN_REASON_RCV_ERROR_0
] = "Recive error 0",
6910 [OPA_LINKDOWN_REASON_BAD_PKT_LEN
] = "Bad packet length",
6911 [OPA_LINKDOWN_REASON_PKT_TOO_LONG
] = "Packet too long",
6912 [OPA_LINKDOWN_REASON_PKT_TOO_SHORT
] = "Packet too short",
6913 [OPA_LINKDOWN_REASON_BAD_SLID
] = "Bad SLID",
6914 [OPA_LINKDOWN_REASON_BAD_DLID
] = "Bad DLID",
6915 [OPA_LINKDOWN_REASON_BAD_L2
] = "Bad L2",
6916 [OPA_LINKDOWN_REASON_BAD_SC
] = "Bad SC",
6917 [OPA_LINKDOWN_REASON_RCV_ERROR_8
] = "Receive error 8",
6918 [OPA_LINKDOWN_REASON_BAD_MID_TAIL
] = "Bad mid tail",
6919 [OPA_LINKDOWN_REASON_RCV_ERROR_10
] = "Receive error 10",
6920 [OPA_LINKDOWN_REASON_PREEMPT_ERROR
] = "Preempt error",
6921 [OPA_LINKDOWN_REASON_PREEMPT_VL15
] = "Preempt vl15",
6922 [OPA_LINKDOWN_REASON_BAD_VL_MARKER
] = "Bad VL marker",
6923 [OPA_LINKDOWN_REASON_RCV_ERROR_14
] = "Receive error 14",
6924 [OPA_LINKDOWN_REASON_RCV_ERROR_15
] = "Receive error 15",
6925 [OPA_LINKDOWN_REASON_BAD_HEAD_DIST
] = "Bad head distance",
6926 [OPA_LINKDOWN_REASON_BAD_TAIL_DIST
] = "Bad tail distance",
6927 [OPA_LINKDOWN_REASON_BAD_CTRL_DIST
] = "Bad control distance",
6928 [OPA_LINKDOWN_REASON_BAD_CREDIT_ACK
] = "Bad credit ack",
6929 [OPA_LINKDOWN_REASON_UNSUPPORTED_VL_MARKER
] = "Unsupported VL marker",
6930 [OPA_LINKDOWN_REASON_BAD_PREEMPT
] = "Bad preempt",
6931 [OPA_LINKDOWN_REASON_BAD_CONTROL_FLIT
] = "Bad control flit",
6932 [OPA_LINKDOWN_REASON_EXCEED_MULTICAST_LIMIT
] = "Exceed multicast limit",
6933 [OPA_LINKDOWN_REASON_RCV_ERROR_24
] = "Receive error 24",
6934 [OPA_LINKDOWN_REASON_RCV_ERROR_25
] = "Receive error 25",
6935 [OPA_LINKDOWN_REASON_RCV_ERROR_26
] = "Receive error 26",
6936 [OPA_LINKDOWN_REASON_RCV_ERROR_27
] = "Receive error 27",
6937 [OPA_LINKDOWN_REASON_RCV_ERROR_28
] = "Receive error 28",
6938 [OPA_LINKDOWN_REASON_RCV_ERROR_29
] = "Receive error 29",
6939 [OPA_LINKDOWN_REASON_RCV_ERROR_30
] = "Receive error 30",
6940 [OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN
] =
6941 "Excessive buffer overrun",
6942 [OPA_LINKDOWN_REASON_UNKNOWN
] = "Unknown",
6943 [OPA_LINKDOWN_REASON_REBOOT
] = "Reboot",
6944 [OPA_LINKDOWN_REASON_NEIGHBOR_UNKNOWN
] = "Neighbor unknown",
6945 [OPA_LINKDOWN_REASON_FM_BOUNCE
] = "FM bounce",
6946 [OPA_LINKDOWN_REASON_SPEED_POLICY
] = "Speed policy",
6947 [OPA_LINKDOWN_REASON_WIDTH_POLICY
] = "Width policy",
6948 [OPA_LINKDOWN_REASON_DISCONNECTED
] = "Disconnected",
6949 [OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED
] =
6950 "Local media not installed",
6951 [OPA_LINKDOWN_REASON_NOT_INSTALLED
] = "Not installed",
6952 [OPA_LINKDOWN_REASON_CHASSIS_CONFIG
] = "Chassis config",
6953 [OPA_LINKDOWN_REASON_END_TO_END_NOT_INSTALLED
] =
6954 "End to end not installed",
6955 [OPA_LINKDOWN_REASON_POWER_POLICY
] = "Power policy",
6956 [OPA_LINKDOWN_REASON_LINKSPEED_POLICY
] = "Link speed policy",
6957 [OPA_LINKDOWN_REASON_LINKWIDTH_POLICY
] = "Link width policy",
6958 [OPA_LINKDOWN_REASON_SWITCH_MGMT
] = "Switch management",
6959 [OPA_LINKDOWN_REASON_SMA_DISABLED
] = "SMA disabled",
6960 [OPA_LINKDOWN_REASON_TRANSIENT
] = "Transient"
6963 /* return the neighbor link down reason string */
6964 static const char *link_down_reason_str(u8 reason
)
6966 const char *str
= NULL
;
6968 if (reason
< ARRAY_SIZE(link_down_reason_strs
))
6969 str
= link_down_reason_strs
[reason
];
6977 * Handle a link down interrupt from the 8051.
6979 * This is a work-queue function outside of the interrupt.
6981 void handle_link_down(struct work_struct
*work
)
6983 u8 lcl_reason
, neigh_reason
= 0;
6984 u8 link_down_reason
;
6985 struct hfi1_pportdata
*ppd
= container_of(work
, struct hfi1_pportdata
,
6988 static const char ldr_str
[] = "Link down reason: ";
6990 if ((ppd
->host_link_state
&
6991 (HLS_DN_POLL
| HLS_VERIFY_CAP
| HLS_GOING_UP
)) &&
6992 ppd
->port_type
== PORT_TYPE_FIXED
)
6993 ppd
->offline_disabled_reason
=
6994 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NOT_INSTALLED
);
6996 /* Go offline first, then deal with reading/writing through 8051 */
6997 was_up
= !!(ppd
->host_link_state
& HLS_UP
);
6998 set_link_state(ppd
, HLS_DN_OFFLINE
);
7002 /* link down reason is only valid if the link was up */
7003 read_link_down_reason(ppd
->dd
, &link_down_reason
);
7004 switch (link_down_reason
) {
7005 case LDR_LINK_TRANSFER_ACTIVE_LOW
:
7006 /* the link went down, no idle message reason */
7007 dd_dev_info(ppd
->dd
, "%sUnexpected link down\n",
7010 case LDR_RECEIVED_LINKDOWN_IDLE_MSG
:
7012 * The neighbor reason is only valid if an idle message
7013 * was received for it.
7015 read_planned_down_reason_code(ppd
->dd
, &neigh_reason
);
7016 dd_dev_info(ppd
->dd
,
7017 "%sNeighbor link down message %d, %s\n",
7018 ldr_str
, neigh_reason
,
7019 link_down_reason_str(neigh_reason
));
7021 case LDR_RECEIVED_HOST_OFFLINE_REQ
:
7022 dd_dev_info(ppd
->dd
,
7023 "%sHost requested link to go offline\n",
7027 dd_dev_info(ppd
->dd
, "%sUnknown reason 0x%x\n",
7028 ldr_str
, link_down_reason
);
7033 * If no reason, assume peer-initiated but missed
7034 * LinkGoingDown idle flits.
7036 if (neigh_reason
== 0)
7037 lcl_reason
= OPA_LINKDOWN_REASON_NEIGHBOR_UNKNOWN
;
7039 /* went down while polling or going up */
7040 lcl_reason
= OPA_LINKDOWN_REASON_TRANSIENT
;
7043 set_link_down_reason(ppd
, lcl_reason
, neigh_reason
, 0);
7045 /* inform the SMA when the link transitions from up to down */
7046 if (was_up
&& ppd
->local_link_down_reason
.sma
== 0 &&
7047 ppd
->neigh_link_down_reason
.sma
== 0) {
7048 ppd
->local_link_down_reason
.sma
=
7049 ppd
->local_link_down_reason
.latest
;
7050 ppd
->neigh_link_down_reason
.sma
=
7051 ppd
->neigh_link_down_reason
.latest
;
7054 reset_neighbor_info(ppd
);
7056 /* disable the port */
7057 clear_rcvctrl(ppd
->dd
, RCV_CTRL_RCV_PORT_ENABLE_SMASK
);
7060 * If there is no cable attached, turn the DC off. Otherwise,
7061 * start the link bring up.
7063 if (ppd
->port_type
== PORT_TYPE_QSFP
&& !qsfp_mod_present(ppd
))
7064 dc_shutdown(ppd
->dd
);
7069 void handle_link_bounce(struct work_struct
*work
)
7071 struct hfi1_pportdata
*ppd
= container_of(work
, struct hfi1_pportdata
,
7075 * Only do something if the link is currently up.
7077 if (ppd
->host_link_state
& HLS_UP
) {
7078 set_link_state(ppd
, HLS_DN_OFFLINE
);
7081 dd_dev_info(ppd
->dd
, "%s: link not up (%s), nothing to do\n",
7082 __func__
, link_state_name(ppd
->host_link_state
));
7087 * Mask conversion: Capability exchange to Port LTP. The capability
7088 * exchange has an implicit 16b CRC that is mandatory.
7090 static int cap_to_port_ltp(int cap
)
7092 int port_ltp
= PORT_LTP_CRC_MODE_16
; /* this mode is mandatory */
7094 if (cap
& CAP_CRC_14B
)
7095 port_ltp
|= PORT_LTP_CRC_MODE_14
;
7096 if (cap
& CAP_CRC_48B
)
7097 port_ltp
|= PORT_LTP_CRC_MODE_48
;
7098 if (cap
& CAP_CRC_12B_16B_PER_LANE
)
7099 port_ltp
|= PORT_LTP_CRC_MODE_PER_LANE
;
7105 * Convert an OPA Port LTP mask to capability mask
7107 int port_ltp_to_cap(int port_ltp
)
7111 if (port_ltp
& PORT_LTP_CRC_MODE_14
)
7112 cap_mask
|= CAP_CRC_14B
;
7113 if (port_ltp
& PORT_LTP_CRC_MODE_48
)
7114 cap_mask
|= CAP_CRC_48B
;
7115 if (port_ltp
& PORT_LTP_CRC_MODE_PER_LANE
)
7116 cap_mask
|= CAP_CRC_12B_16B_PER_LANE
;
7122 * Convert a single DC LCB CRC mode to an OPA Port LTP mask.
7124 static int lcb_to_port_ltp(int lcb_crc
)
7128 if (lcb_crc
== LCB_CRC_12B_16B_PER_LANE
)
7129 port_ltp
= PORT_LTP_CRC_MODE_PER_LANE
;
7130 else if (lcb_crc
== LCB_CRC_48B
)
7131 port_ltp
= PORT_LTP_CRC_MODE_48
;
7132 else if (lcb_crc
== LCB_CRC_14B
)
7133 port_ltp
= PORT_LTP_CRC_MODE_14
;
7135 port_ltp
= PORT_LTP_CRC_MODE_16
;
7141 * Our neighbor has indicated that we are allowed to act as a fabric
7142 * manager, so place the full management partition key in the second
7143 * (0-based) pkey array position (see OPAv1, section 20.2.2.6.8). Note
7144 * that we should already have the limited management partition key in
7145 * array element 1, and also that the port is not yet up when
7146 * add_full_mgmt_pkey() is invoked.
7148 static void add_full_mgmt_pkey(struct hfi1_pportdata
*ppd
)
7150 struct hfi1_devdata
*dd
= ppd
->dd
;
7152 /* Sanity check - ppd->pkeys[2] should be 0, or already initialized */
7153 if (!((ppd
->pkeys
[2] == 0) || (ppd
->pkeys
[2] == FULL_MGMT_P_KEY
)))
7154 dd_dev_warn(dd
, "%s pkey[2] already set to 0x%x, resetting it to 0x%x\n",
7155 __func__
, ppd
->pkeys
[2], FULL_MGMT_P_KEY
);
7156 ppd
->pkeys
[2] = FULL_MGMT_P_KEY
;
7157 (void)hfi1_set_ib_cfg(ppd
, HFI1_IB_CFG_PKEYS
, 0);
7158 hfi1_event_pkey_change(ppd
->dd
, ppd
->port
);
7161 static void clear_full_mgmt_pkey(struct hfi1_pportdata
*ppd
)
7163 if (ppd
->pkeys
[2] != 0) {
7165 (void)hfi1_set_ib_cfg(ppd
, HFI1_IB_CFG_PKEYS
, 0);
7166 hfi1_event_pkey_change(ppd
->dd
, ppd
->port
);
7171 * Convert the given link width to the OPA link width bitmask.
7173 static u16
link_width_to_bits(struct hfi1_devdata
*dd
, u16 width
)
7178 * Simulator and quick linkup do not set the width.
7179 * Just set it to 4x without complaint.
7181 if (dd
->icode
== ICODE_FUNCTIONAL_SIMULATOR
|| quick_linkup
)
7182 return OPA_LINK_WIDTH_4X
;
7183 return 0; /* no lanes up */
7184 case 1: return OPA_LINK_WIDTH_1X
;
7185 case 2: return OPA_LINK_WIDTH_2X
;
7186 case 3: return OPA_LINK_WIDTH_3X
;
7188 dd_dev_info(dd
, "%s: invalid width %d, using 4\n",
7191 case 4: return OPA_LINK_WIDTH_4X
;
7196 * Do a population count on the bottom nibble.
7198 static const u8 bit_counts
[16] = {
7199 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4
7202 static inline u8
nibble_to_count(u8 nibble
)
7204 return bit_counts
[nibble
& 0xf];
7208 * Read the active lane information from the 8051 registers and return
7211 * Active lane information is found in these 8051 registers:
7215 static void get_link_widths(struct hfi1_devdata
*dd
, u16
*tx_width
,
7221 u8 tx_polarity_inversion
;
7222 u8 rx_polarity_inversion
;
7225 /* read the active lanes */
7226 read_tx_settings(dd
, &enable_lane_tx
, &tx_polarity_inversion
,
7227 &rx_polarity_inversion
, &max_rate
);
7228 read_local_lni(dd
, &enable_lane_rx
);
7230 /* convert to counts */
7231 tx
= nibble_to_count(enable_lane_tx
);
7232 rx
= nibble_to_count(enable_lane_rx
);
7235 * Set link_speed_active here, overriding what was set in
7236 * handle_verify_cap(). The ASIC 8051 firmware does not correctly
7237 * set the max_rate field in handle_verify_cap until v0.19.
7239 if ((dd
->icode
== ICODE_RTL_SILICON
) &&
7240 (dd
->dc8051_ver
< dc8051_ver(0, 19, 0))) {
7241 /* max_rate: 0 = 12.5G, 1 = 25G */
7244 dd
->pport
[0].link_speed_active
= OPA_LINK_SPEED_12_5G
;
7248 "%s: unexpected max rate %d, using 25Gb\n",
7249 __func__
, (int)max_rate
);
7252 dd
->pport
[0].link_speed_active
= OPA_LINK_SPEED_25G
;
7258 "Fabric active lanes (width): tx 0x%x (%d), rx 0x%x (%d)\n",
7259 enable_lane_tx
, tx
, enable_lane_rx
, rx
);
7260 *tx_width
= link_width_to_bits(dd
, tx
);
7261 *rx_width
= link_width_to_bits(dd
, rx
);
7265 * Read verify_cap_local_fm_link_width[1] to obtain the link widths.
7266 * Valid after the end of VerifyCap and during LinkUp. Does not change
7267 * after link up. I.e. look elsewhere for downgrade information.
7270 * + bits [7:4] contain the number of active transmitters
7271 * + bits [3:0] contain the number of active receivers
7272 * These are numbers 1 through 4 and can be different values if the
7273 * link is asymmetric.
7275 * verify_cap_local_fm_link_width[0] retains its original value.
7277 static void get_linkup_widths(struct hfi1_devdata
*dd
, u16
*tx_width
,
7281 u8 misc_bits
, local_flags
;
7282 u16 active_tx
, active_rx
;
7284 read_vc_local_link_width(dd
, &misc_bits
, &local_flags
, &widths
);
7286 rx
= (widths
>> 8) & 0xf;
7288 *tx_width
= link_width_to_bits(dd
, tx
);
7289 *rx_width
= link_width_to_bits(dd
, rx
);
7291 /* print the active widths */
7292 get_link_widths(dd
, &active_tx
, &active_rx
);
7296 * Set ppd->link_width_active and ppd->link_width_downgrade_active using
7297 * hardware information when the link first comes up.
7299 * The link width is not available until after VerifyCap.AllFramesReceived
7300 * (the trigger for handle_verify_cap), so this is outside that routine
7301 * and should be called when the 8051 signals linkup.
7303 void get_linkup_link_widths(struct hfi1_pportdata
*ppd
)
7305 u16 tx_width
, rx_width
;
7307 /* get end-of-LNI link widths */
7308 get_linkup_widths(ppd
->dd
, &tx_width
, &rx_width
);
7310 /* use tx_width as the link is supposed to be symmetric on link up */
7311 ppd
->link_width_active
= tx_width
;
7312 /* link width downgrade active (LWD.A) starts out matching LW.A */
7313 ppd
->link_width_downgrade_tx_active
= ppd
->link_width_active
;
7314 ppd
->link_width_downgrade_rx_active
= ppd
->link_width_active
;
7315 /* per OPA spec, on link up LWD.E resets to LWD.S */
7316 ppd
->link_width_downgrade_enabled
= ppd
->link_width_downgrade_supported
;
7317 /* cache the active egress rate (units {10^6 bits/sec]) */
7318 ppd
->current_egress_rate
= active_egress_rate(ppd
);
7322 * Handle a verify capabilities interrupt from the 8051.
7324 * This is a work-queue function outside of the interrupt.
7326 void handle_verify_cap(struct work_struct
*work
)
7328 struct hfi1_pportdata
*ppd
= container_of(work
, struct hfi1_pportdata
,
7330 struct hfi1_devdata
*dd
= ppd
->dd
;
7332 u8 power_management
;
7342 u16 active_tx
, active_rx
;
7343 u8 partner_supported_crc
;
7347 set_link_state(ppd
, HLS_VERIFY_CAP
);
7349 lcb_shutdown(dd
, 0);
7350 adjust_lcb_for_fpga_serdes(dd
);
7352 read_vc_remote_phy(dd
, &power_management
, &continious
);
7353 read_vc_remote_fabric(dd
, &vau
, &z
, &vcu
, &vl15buf
,
7354 &partner_supported_crc
);
7355 read_vc_remote_link_width(dd
, &remote_tx_rate
, &link_widths
);
7356 read_remote_device_id(dd
, &device_id
, &device_rev
);
7358 * And the 'MgmtAllowed' information, which is exchanged during
7359 * LNI, is also be available at this point.
7361 read_mgmt_allowed(dd
, &ppd
->mgmt_allowed
);
7362 /* print the active widths */
7363 get_link_widths(dd
, &active_tx
, &active_rx
);
7365 "Peer PHY: power management 0x%x, continuous updates 0x%x\n",
7366 (int)power_management
, (int)continious
);
7368 "Peer Fabric: vAU %d, Z %d, vCU %d, vl15 credits 0x%x, CRC sizes 0x%x\n",
7369 (int)vau
, (int)z
, (int)vcu
, (int)vl15buf
,
7370 (int)partner_supported_crc
);
7371 dd_dev_info(dd
, "Peer Link Width: tx rate 0x%x, widths 0x%x\n",
7372 (u32
)remote_tx_rate
, (u32
)link_widths
);
7373 dd_dev_info(dd
, "Peer Device ID: 0x%04x, Revision 0x%02x\n",
7374 (u32
)device_id
, (u32
)device_rev
);
7376 * The peer vAU value just read is the peer receiver value. HFI does
7377 * not support a transmit vAU of 0 (AU == 8). We advertised that
7378 * with Z=1 in the fabric capabilities sent to the peer. The peer
7379 * will see our Z=1, and, if it advertised a vAU of 0, will move its
7380 * receive to vAU of 1 (AU == 16). Do the same here. We do not care
7381 * about the peer Z value - our sent vAU is 3 (hardwired) and is not
7382 * subject to the Z value exception.
7386 set_up_vau(dd
, vau
);
7389 * Set VL15 credits to 0 in global credit register. Cache remote VL15
7390 * credits value and wait for link-up interrupt ot set it.
7393 dd
->vl15buf_cached
= vl15buf
;
7395 /* set up the LCB CRC mode */
7396 crc_mask
= ppd
->port_crc_mode_enabled
& partner_supported_crc
;
7398 /* order is important: use the lowest bit in common */
7399 if (crc_mask
& CAP_CRC_14B
)
7400 crc_val
= LCB_CRC_14B
;
7401 else if (crc_mask
& CAP_CRC_48B
)
7402 crc_val
= LCB_CRC_48B
;
7403 else if (crc_mask
& CAP_CRC_12B_16B_PER_LANE
)
7404 crc_val
= LCB_CRC_12B_16B_PER_LANE
;
7406 crc_val
= LCB_CRC_16B
;
7408 dd_dev_info(dd
, "Final LCB CRC mode: %d\n", (int)crc_val
);
7409 write_csr(dd
, DC_LCB_CFG_CRC_MODE
,
7410 (u64
)crc_val
<< DC_LCB_CFG_CRC_MODE_TX_VAL_SHIFT
);
7412 /* set (14b only) or clear sideband credit */
7413 reg
= read_csr(dd
, SEND_CM_CTRL
);
7414 if (crc_val
== LCB_CRC_14B
&& crc_14b_sideband
) {
7415 write_csr(dd
, SEND_CM_CTRL
,
7416 reg
| SEND_CM_CTRL_FORCE_CREDIT_MODE_SMASK
);
7418 write_csr(dd
, SEND_CM_CTRL
,
7419 reg
& ~SEND_CM_CTRL_FORCE_CREDIT_MODE_SMASK
);
7422 ppd
->link_speed_active
= 0; /* invalid value */
7423 if (dd
->dc8051_ver
< dc8051_ver(0, 20, 0)) {
7424 /* remote_tx_rate: 0 = 12.5G, 1 = 25G */
7425 switch (remote_tx_rate
) {
7427 ppd
->link_speed_active
= OPA_LINK_SPEED_12_5G
;
7430 ppd
->link_speed_active
= OPA_LINK_SPEED_25G
;
7434 /* actual rate is highest bit of the ANDed rates */
7435 u8 rate
= remote_tx_rate
& ppd
->local_tx_rate
;
7438 ppd
->link_speed_active
= OPA_LINK_SPEED_25G
;
7440 ppd
->link_speed_active
= OPA_LINK_SPEED_12_5G
;
7442 if (ppd
->link_speed_active
== 0) {
7443 dd_dev_err(dd
, "%s: unexpected remote tx rate %d, using 25Gb\n",
7444 __func__
, (int)remote_tx_rate
);
7445 ppd
->link_speed_active
= OPA_LINK_SPEED_25G
;
7449 * Cache the values of the supported, enabled, and active
7450 * LTP CRC modes to return in 'portinfo' queries. But the bit
7451 * flags that are returned in the portinfo query differ from
7452 * what's in the link_crc_mask, crc_sizes, and crc_val
7453 * variables. Convert these here.
7455 ppd
->port_ltp_crc_mode
= cap_to_port_ltp(link_crc_mask
) << 8;
7456 /* supported crc modes */
7457 ppd
->port_ltp_crc_mode
|=
7458 cap_to_port_ltp(ppd
->port_crc_mode_enabled
) << 4;
7459 /* enabled crc modes */
7460 ppd
->port_ltp_crc_mode
|= lcb_to_port_ltp(crc_val
);
7461 /* active crc mode */
7463 /* set up the remote credit return table */
7464 assign_remote_cm_au_table(dd
, vcu
);
7467 * The LCB is reset on entry to handle_verify_cap(), so this must
7468 * be applied on every link up.
7470 * Adjust LCB error kill enable to kill the link if
7471 * these RBUF errors are seen:
7472 * REPLAY_BUF_MBE_SMASK
7473 * FLIT_INPUT_BUF_MBE_SMASK
7475 if (is_ax(dd
)) { /* fixed in B0 */
7476 reg
= read_csr(dd
, DC_LCB_CFG_LINK_KILL_EN
);
7477 reg
|= DC_LCB_CFG_LINK_KILL_EN_REPLAY_BUF_MBE_SMASK
7478 | DC_LCB_CFG_LINK_KILL_EN_FLIT_INPUT_BUF_MBE_SMASK
;
7479 write_csr(dd
, DC_LCB_CFG_LINK_KILL_EN
, reg
);
7482 /* pull LCB fifos out of reset - all fifo clocks must be stable */
7483 write_csr(dd
, DC_LCB_CFG_TX_FIFOS_RESET
, 0);
7485 /* give 8051 access to the LCB CSRs */
7486 write_csr(dd
, DC_LCB_ERR_EN
, 0); /* mask LCB errors */
7487 set_8051_lcb_access(dd
);
7489 if (ppd
->mgmt_allowed
)
7490 add_full_mgmt_pkey(ppd
);
7492 /* tell the 8051 to go to LinkUp */
7493 set_link_state(ppd
, HLS_GOING_UP
);
7497 * Apply the link width downgrade enabled policy against the current active
7500 * Called when the enabled policy changes or the active link widths change.
7502 void apply_link_downgrade_policy(struct hfi1_pportdata
*ppd
, int refresh_widths
)
7509 /* use the hls lock to avoid a race with actual link up */
7512 mutex_lock(&ppd
->hls_lock
);
7513 /* only apply if the link is up */
7514 if (ppd
->host_link_state
& HLS_DOWN
) {
7515 /* still going up..wait and retry */
7516 if (ppd
->host_link_state
& HLS_GOING_UP
) {
7517 if (++tries
< 1000) {
7518 mutex_unlock(&ppd
->hls_lock
);
7519 usleep_range(100, 120); /* arbitrary */
7523 "%s: giving up waiting for link state change\n",
7529 lwde
= ppd
->link_width_downgrade_enabled
;
7531 if (refresh_widths
) {
7532 get_link_widths(ppd
->dd
, &tx
, &rx
);
7533 ppd
->link_width_downgrade_tx_active
= tx
;
7534 ppd
->link_width_downgrade_rx_active
= rx
;
7537 if (ppd
->link_width_downgrade_tx_active
== 0 ||
7538 ppd
->link_width_downgrade_rx_active
== 0) {
7539 /* the 8051 reported a dead link as a downgrade */
7540 dd_dev_err(ppd
->dd
, "Link downgrade is really a link down, ignoring\n");
7541 } else if (lwde
== 0) {
7542 /* downgrade is disabled */
7544 /* bounce if not at starting active width */
7545 if ((ppd
->link_width_active
!=
7546 ppd
->link_width_downgrade_tx_active
) ||
7547 (ppd
->link_width_active
!=
7548 ppd
->link_width_downgrade_rx_active
)) {
7550 "Link downgrade is disabled and link has downgraded, downing link\n");
7552 " original 0x%x, tx active 0x%x, rx active 0x%x\n",
7553 ppd
->link_width_active
,
7554 ppd
->link_width_downgrade_tx_active
,
7555 ppd
->link_width_downgrade_rx_active
);
7558 } else if ((lwde
& ppd
->link_width_downgrade_tx_active
) == 0 ||
7559 (lwde
& ppd
->link_width_downgrade_rx_active
) == 0) {
7560 /* Tx or Rx is outside the enabled policy */
7562 "Link is outside of downgrade allowed, downing link\n");
7564 " enabled 0x%x, tx active 0x%x, rx active 0x%x\n",
7565 lwde
, ppd
->link_width_downgrade_tx_active
,
7566 ppd
->link_width_downgrade_rx_active
);
7571 mutex_unlock(&ppd
->hls_lock
);
7574 set_link_down_reason(ppd
, OPA_LINKDOWN_REASON_WIDTH_POLICY
, 0,
7575 OPA_LINKDOWN_REASON_WIDTH_POLICY
);
7576 set_link_state(ppd
, HLS_DN_OFFLINE
);
7582 * Handle a link downgrade interrupt from the 8051.
7584 * This is a work-queue function outside of the interrupt.
7586 void handle_link_downgrade(struct work_struct
*work
)
7588 struct hfi1_pportdata
*ppd
= container_of(work
, struct hfi1_pportdata
,
7589 link_downgrade_work
);
7591 dd_dev_info(ppd
->dd
, "8051: Link width downgrade\n");
7592 apply_link_downgrade_policy(ppd
, 1);
7595 static char *dcc_err_string(char *buf
, int buf_len
, u64 flags
)
7597 return flag_string(buf
, buf_len
, flags
, dcc_err_flags
,
7598 ARRAY_SIZE(dcc_err_flags
));
7601 static char *lcb_err_string(char *buf
, int buf_len
, u64 flags
)
7603 return flag_string(buf
, buf_len
, flags
, lcb_err_flags
,
7604 ARRAY_SIZE(lcb_err_flags
));
7607 static char *dc8051_err_string(char *buf
, int buf_len
, u64 flags
)
7609 return flag_string(buf
, buf_len
, flags
, dc8051_err_flags
,
7610 ARRAY_SIZE(dc8051_err_flags
));
7613 static char *dc8051_info_err_string(char *buf
, int buf_len
, u64 flags
)
7615 return flag_string(buf
, buf_len
, flags
, dc8051_info_err_flags
,
7616 ARRAY_SIZE(dc8051_info_err_flags
));
7619 static char *dc8051_info_host_msg_string(char *buf
, int buf_len
, u64 flags
)
7621 return flag_string(buf
, buf_len
, flags
, dc8051_info_host_msg_flags
,
7622 ARRAY_SIZE(dc8051_info_host_msg_flags
));
7625 static void handle_8051_interrupt(struct hfi1_devdata
*dd
, u32 unused
, u64 reg
)
7627 struct hfi1_pportdata
*ppd
= dd
->pport
;
7628 u64 info
, err
, host_msg
;
7629 int queue_link_down
= 0;
7632 /* look at the flags */
7633 if (reg
& DC_DC8051_ERR_FLG_SET_BY_8051_SMASK
) {
7634 /* 8051 information set by firmware */
7635 /* read DC8051_DBG_ERR_INFO_SET_BY_8051 for details */
7636 info
= read_csr(dd
, DC_DC8051_DBG_ERR_INFO_SET_BY_8051
);
7637 err
= (info
>> DC_DC8051_DBG_ERR_INFO_SET_BY_8051_ERROR_SHIFT
)
7638 & DC_DC8051_DBG_ERR_INFO_SET_BY_8051_ERROR_MASK
;
7640 DC_DC8051_DBG_ERR_INFO_SET_BY_8051_HOST_MSG_SHIFT
)
7641 & DC_DC8051_DBG_ERR_INFO_SET_BY_8051_HOST_MSG_MASK
;
7644 * Handle error flags.
7646 if (err
& FAILED_LNI
) {
7648 * LNI error indications are cleared by the 8051
7649 * only when starting polling. Only pay attention
7650 * to them when in the states that occur during
7653 if (ppd
->host_link_state
7654 & (HLS_DN_POLL
| HLS_VERIFY_CAP
| HLS_GOING_UP
)) {
7655 queue_link_down
= 1;
7656 dd_dev_info(dd
, "Link error: %s\n",
7657 dc8051_info_err_string(buf
,
7662 err
&= ~(u64
)FAILED_LNI
;
7664 /* unknown frames can happen durning LNI, just count */
7665 if (err
& UNKNOWN_FRAME
) {
7666 ppd
->unknown_frame_count
++;
7667 err
&= ~(u64
)UNKNOWN_FRAME
;
7670 /* report remaining errors, but do not do anything */
7671 dd_dev_err(dd
, "8051 info error: %s\n",
7672 dc8051_info_err_string(buf
, sizeof(buf
),
7677 * Handle host message flags.
7679 if (host_msg
& HOST_REQ_DONE
) {
7681 * Presently, the driver does a busy wait for
7682 * host requests to complete. This is only an
7683 * informational message.
7684 * NOTE: The 8051 clears the host message
7685 * information *on the next 8051 command*.
7686 * Therefore, when linkup is achieved,
7687 * this flag will still be set.
7689 host_msg
&= ~(u64
)HOST_REQ_DONE
;
7691 if (host_msg
& BC_SMA_MSG
) {
7692 queue_work(ppd
->hfi1_wq
, &ppd
->sma_message_work
);
7693 host_msg
&= ~(u64
)BC_SMA_MSG
;
7695 if (host_msg
& LINKUP_ACHIEVED
) {
7696 dd_dev_info(dd
, "8051: Link up\n");
7697 queue_work(ppd
->hfi1_wq
, &ppd
->link_up_work
);
7698 host_msg
&= ~(u64
)LINKUP_ACHIEVED
;
7700 if (host_msg
& EXT_DEVICE_CFG_REQ
) {
7701 handle_8051_request(ppd
);
7702 host_msg
&= ~(u64
)EXT_DEVICE_CFG_REQ
;
7704 if (host_msg
& VERIFY_CAP_FRAME
) {
7705 queue_work(ppd
->hfi1_wq
, &ppd
->link_vc_work
);
7706 host_msg
&= ~(u64
)VERIFY_CAP_FRAME
;
7708 if (host_msg
& LINK_GOING_DOWN
) {
7709 const char *extra
= "";
7710 /* no downgrade action needed if going down */
7711 if (host_msg
& LINK_WIDTH_DOWNGRADED
) {
7712 host_msg
&= ~(u64
)LINK_WIDTH_DOWNGRADED
;
7713 extra
= " (ignoring downgrade)";
7715 dd_dev_info(dd
, "8051: Link down%s\n", extra
);
7716 queue_link_down
= 1;
7717 host_msg
&= ~(u64
)LINK_GOING_DOWN
;
7719 if (host_msg
& LINK_WIDTH_DOWNGRADED
) {
7720 queue_work(ppd
->hfi1_wq
, &ppd
->link_downgrade_work
);
7721 host_msg
&= ~(u64
)LINK_WIDTH_DOWNGRADED
;
7724 /* report remaining messages, but do not do anything */
7725 dd_dev_info(dd
, "8051 info host message: %s\n",
7726 dc8051_info_host_msg_string(buf
,
7731 reg
&= ~DC_DC8051_ERR_FLG_SET_BY_8051_SMASK
;
7733 if (reg
& DC_DC8051_ERR_FLG_LOST_8051_HEART_BEAT_SMASK
) {
7735 * Lost the 8051 heartbeat. If this happens, we
7736 * receive constant interrupts about it. Disable
7737 * the interrupt after the first.
7739 dd_dev_err(dd
, "Lost 8051 heartbeat\n");
7740 write_csr(dd
, DC_DC8051_ERR_EN
,
7741 read_csr(dd
, DC_DC8051_ERR_EN
) &
7742 ~DC_DC8051_ERR_EN_LOST_8051_HEART_BEAT_SMASK
);
7744 reg
&= ~DC_DC8051_ERR_FLG_LOST_8051_HEART_BEAT_SMASK
;
7747 /* report the error, but do not do anything */
7748 dd_dev_err(dd
, "8051 error: %s\n",
7749 dc8051_err_string(buf
, sizeof(buf
), reg
));
7752 if (queue_link_down
) {
7754 * if the link is already going down or disabled, do not
7757 if ((ppd
->host_link_state
&
7758 (HLS_GOING_OFFLINE
| HLS_LINK_COOLDOWN
)) ||
7759 ppd
->link_enabled
== 0) {
7760 dd_dev_info(dd
, "%s: not queuing link down\n",
7763 queue_work(ppd
->hfi1_wq
, &ppd
->link_down_work
);
7768 static const char * const fm_config_txt
[] = {
7770 "BadHeadDist: Distance violation between two head flits",
7772 "BadTailDist: Distance violation between two tail flits",
7774 "BadCtrlDist: Distance violation between two credit control flits",
7776 "BadCrdAck: Credits return for unsupported VL",
7778 "UnsupportedVLMarker: Received VL Marker",
7780 "BadPreempt: Exceeded the preemption nesting level",
7782 "BadControlFlit: Received unsupported control flit",
7785 "UnsupportedVLMarker: Received VL Marker for unconfigured or disabled VL",
7788 static const char * const port_rcv_txt
[] = {
7790 "BadPktLen: Illegal PktLen",
7792 "PktLenTooLong: Packet longer than PktLen",
7794 "PktLenTooShort: Packet shorter than PktLen",
7796 "BadSLID: Illegal SLID (0, using multicast as SLID, does not include security validation of SLID)",
7798 "BadDLID: Illegal DLID (0, doesn't match HFI)",
7800 "BadL2: Illegal L2 opcode",
7802 "BadSC: Unsupported SC",
7804 "BadRC: Illegal RC",
7806 "PreemptError: Preempting with same VL",
7808 "PreemptVL15: Preempting a VL15 packet",
7811 #define OPA_LDR_FMCONFIG_OFFSET 16
7812 #define OPA_LDR_PORTRCV_OFFSET 0
7813 static void handle_dcc_err(struct hfi1_devdata
*dd
, u32 unused
, u64 reg
)
7815 u64 info
, hdr0
, hdr1
;
7818 struct hfi1_pportdata
*ppd
= dd
->pport
;
7822 if (reg
& DCC_ERR_FLG_UNCORRECTABLE_ERR_SMASK
) {
7823 if (!(dd
->err_info_uncorrectable
& OPA_EI_STATUS_SMASK
)) {
7824 info
= read_csr(dd
, DCC_ERR_INFO_UNCORRECTABLE
);
7825 dd
->err_info_uncorrectable
= info
& OPA_EI_CODE_SMASK
;
7826 /* set status bit */
7827 dd
->err_info_uncorrectable
|= OPA_EI_STATUS_SMASK
;
7829 reg
&= ~DCC_ERR_FLG_UNCORRECTABLE_ERR_SMASK
;
7832 if (reg
& DCC_ERR_FLG_LINK_ERR_SMASK
) {
7833 struct hfi1_pportdata
*ppd
= dd
->pport
;
7834 /* this counter saturates at (2^32) - 1 */
7835 if (ppd
->link_downed
< (u32
)UINT_MAX
)
7837 reg
&= ~DCC_ERR_FLG_LINK_ERR_SMASK
;
7840 if (reg
& DCC_ERR_FLG_FMCONFIG_ERR_SMASK
) {
7841 u8 reason_valid
= 1;
7843 info
= read_csr(dd
, DCC_ERR_INFO_FMCONFIG
);
7844 if (!(dd
->err_info_fmconfig
& OPA_EI_STATUS_SMASK
)) {
7845 dd
->err_info_fmconfig
= info
& OPA_EI_CODE_SMASK
;
7846 /* set status bit */
7847 dd
->err_info_fmconfig
|= OPA_EI_STATUS_SMASK
;
7857 extra
= fm_config_txt
[info
];
7860 extra
= fm_config_txt
[info
];
7861 if (ppd
->port_error_action
&
7862 OPA_PI_MASK_FM_CFG_UNSUPPORTED_VL_MARKER
) {
7865 * lcl_reason cannot be derived from info
7869 OPA_LINKDOWN_REASON_UNSUPPORTED_VL_MARKER
;
7874 snprintf(buf
, sizeof(buf
), "reserved%lld", info
);
7879 if (reason_valid
&& !do_bounce
) {
7880 do_bounce
= ppd
->port_error_action
&
7881 (1 << (OPA_LDR_FMCONFIG_OFFSET
+ info
));
7882 lcl_reason
= info
+ OPA_LINKDOWN_REASON_BAD_HEAD_DIST
;
7885 /* just report this */
7886 dd_dev_info_ratelimited(dd
, "DCC Error: fmconfig error: %s\n",
7888 reg
&= ~DCC_ERR_FLG_FMCONFIG_ERR_SMASK
;
7891 if (reg
& DCC_ERR_FLG_RCVPORT_ERR_SMASK
) {
7892 u8 reason_valid
= 1;
7894 info
= read_csr(dd
, DCC_ERR_INFO_PORTRCV
);
7895 hdr0
= read_csr(dd
, DCC_ERR_INFO_PORTRCV_HDR0
);
7896 hdr1
= read_csr(dd
, DCC_ERR_INFO_PORTRCV_HDR1
);
7897 if (!(dd
->err_info_rcvport
.status_and_code
&
7898 OPA_EI_STATUS_SMASK
)) {
7899 dd
->err_info_rcvport
.status_and_code
=
7900 info
& OPA_EI_CODE_SMASK
;
7901 /* set status bit */
7902 dd
->err_info_rcvport
.status_and_code
|=
7903 OPA_EI_STATUS_SMASK
;
7905 * save first 2 flits in the packet that caused
7908 dd
->err_info_rcvport
.packet_flit1
= hdr0
;
7909 dd
->err_info_rcvport
.packet_flit2
= hdr1
;
7922 extra
= port_rcv_txt
[info
];
7926 snprintf(buf
, sizeof(buf
), "reserved%lld", info
);
7931 if (reason_valid
&& !do_bounce
) {
7932 do_bounce
= ppd
->port_error_action
&
7933 (1 << (OPA_LDR_PORTRCV_OFFSET
+ info
));
7934 lcl_reason
= info
+ OPA_LINKDOWN_REASON_RCV_ERROR_0
;
7937 /* just report this */
7938 dd_dev_info_ratelimited(dd
, "DCC Error: PortRcv error: %s\n"
7939 " hdr0 0x%llx, hdr1 0x%llx\n",
7942 reg
&= ~DCC_ERR_FLG_RCVPORT_ERR_SMASK
;
7945 if (reg
& DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_UC_SMASK
) {
7946 /* informative only */
7947 dd_dev_info_ratelimited(dd
, "8051 access to LCB blocked\n");
7948 reg
&= ~DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_UC_SMASK
;
7950 if (reg
& DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_HOST_SMASK
) {
7951 /* informative only */
7952 dd_dev_info_ratelimited(dd
, "host access to LCB blocked\n");
7953 reg
&= ~DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_HOST_SMASK
;
7956 if (unlikely(hfi1_dbg_fault_suppress_err(&dd
->verbs_dev
)))
7957 reg
&= ~DCC_ERR_FLG_LATE_EBP_ERR_SMASK
;
7959 /* report any remaining errors */
7961 dd_dev_info_ratelimited(dd
, "DCC Error: %s\n",
7962 dcc_err_string(buf
, sizeof(buf
), reg
));
7964 if (lcl_reason
== 0)
7965 lcl_reason
= OPA_LINKDOWN_REASON_UNKNOWN
;
7968 dd_dev_info_ratelimited(dd
, "%s: PortErrorAction bounce\n",
7970 set_link_down_reason(ppd
, lcl_reason
, 0, lcl_reason
);
7971 queue_work(ppd
->hfi1_wq
, &ppd
->link_bounce_work
);
7975 static void handle_lcb_err(struct hfi1_devdata
*dd
, u32 unused
, u64 reg
)
7979 dd_dev_info(dd
, "LCB Error: %s\n",
7980 lcb_err_string(buf
, sizeof(buf
), reg
));
7984 * CCE block DC interrupt. Source is < 8.
7986 static void is_dc_int(struct hfi1_devdata
*dd
, unsigned int source
)
7988 const struct err_reg_info
*eri
= &dc_errs
[source
];
7991 interrupt_clear_down(dd
, 0, eri
);
7992 } else if (source
== 3 /* dc_lbm_int */) {
7994 * This indicates that a parity error has occurred on the
7995 * address/control lines presented to the LBM. The error
7996 * is a single pulse, there is no associated error flag,
7997 * and it is non-maskable. This is because if a parity
7998 * error occurs on the request the request is dropped.
7999 * This should never occur, but it is nice to know if it
8002 dd_dev_err(dd
, "Parity error in DC LBM block\n");
8004 dd_dev_err(dd
, "Invalid DC interrupt %u\n", source
);
8009 * TX block send credit interrupt. Source is < 160.
8011 static void is_send_credit_int(struct hfi1_devdata
*dd
, unsigned int source
)
8013 sc_group_release_update(dd
, source
);
8017 * TX block SDMA interrupt. Source is < 48.
8019 * SDMA interrupts are grouped by type:
8022 * N - 2N-1 = SDmaProgress
8023 * 2N - 3N-1 = SDmaIdle
8025 static void is_sdma_eng_int(struct hfi1_devdata
*dd
, unsigned int source
)
8027 /* what interrupt */
8028 unsigned int what
= source
/ TXE_NUM_SDMA_ENGINES
;
8030 unsigned int which
= source
% TXE_NUM_SDMA_ENGINES
;
8032 #ifdef CONFIG_SDMA_VERBOSITY
8033 dd_dev_err(dd
, "CONFIG SDMA(%u) %s:%d %s()\n", which
,
8034 slashstrip(__FILE__
), __LINE__
, __func__
);
8035 sdma_dumpstate(&dd
->per_sdma
[which
]);
8038 if (likely(what
< 3 && which
< dd
->num_sdma
)) {
8039 sdma_engine_interrupt(&dd
->per_sdma
[which
], 1ull << source
);
8041 /* should not happen */
8042 dd_dev_err(dd
, "Invalid SDMA interrupt 0x%x\n", source
);
8047 * RX block receive available interrupt. Source is < 160.
8049 static void is_rcv_avail_int(struct hfi1_devdata
*dd
, unsigned int source
)
8051 struct hfi1_ctxtdata
*rcd
;
8054 if (likely(source
< dd
->num_rcv_contexts
)) {
8055 rcd
= dd
->rcd
[source
];
8057 /* Check for non-user contexts, including vnic */
8058 if ((source
< dd
->first_dyn_alloc_ctxt
) ||
8059 (rcd
->sc
&& (rcd
->sc
->type
== SC_KERNEL
)))
8060 rcd
->do_interrupt(rcd
, 0);
8062 handle_user_interrupt(rcd
);
8065 /* received an interrupt, but no rcd */
8066 err_detail
= "dataless";
8068 /* received an interrupt, but are not using that context */
8069 err_detail
= "out of range";
8071 dd_dev_err(dd
, "unexpected %s receive available context interrupt %u\n",
8072 err_detail
, source
);
8076 * RX block receive urgent interrupt. Source is < 160.
8078 static void is_rcv_urgent_int(struct hfi1_devdata
*dd
, unsigned int source
)
8080 struct hfi1_ctxtdata
*rcd
;
8083 if (likely(source
< dd
->num_rcv_contexts
)) {
8084 rcd
= dd
->rcd
[source
];
8086 /* only pay attention to user urgent interrupts */
8087 if ((source
>= dd
->first_dyn_alloc_ctxt
) &&
8088 (!rcd
->sc
|| (rcd
->sc
->type
== SC_USER
)))
8089 handle_user_interrupt(rcd
);
8092 /* received an interrupt, but no rcd */
8093 err_detail
= "dataless";
8095 /* received an interrupt, but are not using that context */
8096 err_detail
= "out of range";
8098 dd_dev_err(dd
, "unexpected %s receive urgent context interrupt %u\n",
8099 err_detail
, source
);
8103 * Reserved range interrupt. Should not be called in normal operation.
8105 static void is_reserved_int(struct hfi1_devdata
*dd
, unsigned int source
)
8109 dd_dev_err(dd
, "unexpected %s interrupt\n",
8110 is_reserved_name(name
, sizeof(name
), source
));
8113 static const struct is_table is_table
[] = {
8116 * name func interrupt func
8118 { IS_GENERAL_ERR_START
, IS_GENERAL_ERR_END
,
8119 is_misc_err_name
, is_misc_err_int
},
8120 { IS_SDMAENG_ERR_START
, IS_SDMAENG_ERR_END
,
8121 is_sdma_eng_err_name
, is_sdma_eng_err_int
},
8122 { IS_SENDCTXT_ERR_START
, IS_SENDCTXT_ERR_END
,
8123 is_sendctxt_err_name
, is_sendctxt_err_int
},
8124 { IS_SDMA_START
, IS_SDMA_END
,
8125 is_sdma_eng_name
, is_sdma_eng_int
},
8126 { IS_VARIOUS_START
, IS_VARIOUS_END
,
8127 is_various_name
, is_various_int
},
8128 { IS_DC_START
, IS_DC_END
,
8129 is_dc_name
, is_dc_int
},
8130 { IS_RCVAVAIL_START
, IS_RCVAVAIL_END
,
8131 is_rcv_avail_name
, is_rcv_avail_int
},
8132 { IS_RCVURGENT_START
, IS_RCVURGENT_END
,
8133 is_rcv_urgent_name
, is_rcv_urgent_int
},
8134 { IS_SENDCREDIT_START
, IS_SENDCREDIT_END
,
8135 is_send_credit_name
, is_send_credit_int
},
8136 { IS_RESERVED_START
, IS_RESERVED_END
,
8137 is_reserved_name
, is_reserved_int
},
8141 * Interrupt source interrupt - called when the given source has an interrupt.
8142 * Source is a bit index into an array of 64-bit integers.
8144 static void is_interrupt(struct hfi1_devdata
*dd
, unsigned int source
)
8146 const struct is_table
*entry
;
8148 /* avoids a double compare by walking the table in-order */
8149 for (entry
= &is_table
[0]; entry
->is_name
; entry
++) {
8150 if (source
< entry
->end
) {
8151 trace_hfi1_interrupt(dd
, entry
, source
);
8152 entry
->is_int(dd
, source
- entry
->start
);
8156 /* fell off the end */
8157 dd_dev_err(dd
, "invalid interrupt source %u\n", source
);
8161 * General interrupt handler. This is able to correctly handle
8162 * all interrupts in case INTx is used.
8164 static irqreturn_t
general_interrupt(int irq
, void *data
)
8166 struct hfi1_devdata
*dd
= data
;
8167 u64 regs
[CCE_NUM_INT_CSRS
];
8171 this_cpu_inc(*dd
->int_counter
);
8173 /* phase 1: scan and clear all handled interrupts */
8174 for (i
= 0; i
< CCE_NUM_INT_CSRS
; i
++) {
8175 if (dd
->gi_mask
[i
] == 0) {
8176 regs
[i
] = 0; /* used later */
8179 regs
[i
] = read_csr(dd
, CCE_INT_STATUS
+ (8 * i
)) &
8181 /* only clear if anything is set */
8183 write_csr(dd
, CCE_INT_CLEAR
+ (8 * i
), regs
[i
]);
8186 /* phase 2: call the appropriate handler */
8187 for_each_set_bit(bit
, (unsigned long *)®s
[0],
8188 CCE_NUM_INT_CSRS
* 64) {
8189 is_interrupt(dd
, bit
);
8195 static irqreturn_t
sdma_interrupt(int irq
, void *data
)
8197 struct sdma_engine
*sde
= data
;
8198 struct hfi1_devdata
*dd
= sde
->dd
;
8201 #ifdef CONFIG_SDMA_VERBOSITY
8202 dd_dev_err(dd
, "CONFIG SDMA(%u) %s:%d %s()\n", sde
->this_idx
,
8203 slashstrip(__FILE__
), __LINE__
, __func__
);
8204 sdma_dumpstate(sde
);
8207 this_cpu_inc(*dd
->int_counter
);
8209 /* This read_csr is really bad in the hot path */
8210 status
= read_csr(dd
,
8211 CCE_INT_STATUS
+ (8 * (IS_SDMA_START
/ 64)))
8213 if (likely(status
)) {
8214 /* clear the interrupt(s) */
8216 CCE_INT_CLEAR
+ (8 * (IS_SDMA_START
/ 64)),
8219 /* handle the interrupt(s) */
8220 sdma_engine_interrupt(sde
, status
);
8222 dd_dev_err(dd
, "SDMA engine %u interrupt, but no status bits set\n",
8229 * Clear the receive interrupt. Use a read of the interrupt clear CSR
8230 * to insure that the write completed. This does NOT guarantee that
8231 * queued DMA writes to memory from the chip are pushed.
8233 static inline void clear_recv_intr(struct hfi1_ctxtdata
*rcd
)
8235 struct hfi1_devdata
*dd
= rcd
->dd
;
8236 u32 addr
= CCE_INT_CLEAR
+ (8 * rcd
->ireg
);
8238 mmiowb(); /* make sure everything before is written */
8239 write_csr(dd
, addr
, rcd
->imask
);
8240 /* force the above write on the chip and get a value back */
8241 (void)read_csr(dd
, addr
);
8244 /* force the receive interrupt */
8245 void force_recv_intr(struct hfi1_ctxtdata
*rcd
)
8247 write_csr(rcd
->dd
, CCE_INT_FORCE
+ (8 * rcd
->ireg
), rcd
->imask
);
8251 * Return non-zero if a packet is present.
8253 * This routine is called when rechecking for packets after the RcvAvail
8254 * interrupt has been cleared down. First, do a quick check of memory for
8255 * a packet present. If not found, use an expensive CSR read of the context
8256 * tail to determine the actual tail. The CSR read is necessary because there
8257 * is no method to push pending DMAs to memory other than an interrupt and we
8258 * are trying to determine if we need to force an interrupt.
8260 static inline int check_packet_present(struct hfi1_ctxtdata
*rcd
)
8265 if (!HFI1_CAP_IS_KSET(DMA_RTAIL
))
8266 present
= (rcd
->seq_cnt
==
8267 rhf_rcv_seq(rhf_to_cpu(get_rhf_addr(rcd
))));
8268 else /* is RDMA rtail */
8269 present
= (rcd
->head
!= get_rcvhdrtail(rcd
));
8274 /* fall back to a CSR read, correct indpendent of DMA_RTAIL */
8275 tail
= (u32
)read_uctxt_csr(rcd
->dd
, rcd
->ctxt
, RCV_HDR_TAIL
);
8276 return rcd
->head
!= tail
;
8280 * Receive packet IRQ handler. This routine expects to be on its own IRQ.
8281 * This routine will try to handle packets immediately (latency), but if
8282 * it finds too many, it will invoke the thread handler (bandwitdh). The
8283 * chip receive interrupt is *not* cleared down until this or the thread (if
8284 * invoked) is finished. The intent is to avoid extra interrupts while we
8285 * are processing packets anyway.
8287 static irqreturn_t
receive_context_interrupt(int irq
, void *data
)
8289 struct hfi1_ctxtdata
*rcd
= data
;
8290 struct hfi1_devdata
*dd
= rcd
->dd
;
8294 trace_hfi1_receive_interrupt(dd
, rcd
->ctxt
);
8295 this_cpu_inc(*dd
->int_counter
);
8296 aspm_ctx_disable(rcd
);
8298 /* receive interrupt remains blocked while processing packets */
8299 disposition
= rcd
->do_interrupt(rcd
, 0);
8302 * Too many packets were seen while processing packets in this
8303 * IRQ handler. Invoke the handler thread. The receive interrupt
8306 if (disposition
== RCV_PKT_LIMIT
)
8307 return IRQ_WAKE_THREAD
;
8310 * The packet processor detected no more packets. Clear the receive
8311 * interrupt and recheck for a packet packet that may have arrived
8312 * after the previous check and interrupt clear. If a packet arrived,
8313 * force another interrupt.
8315 clear_recv_intr(rcd
);
8316 present
= check_packet_present(rcd
);
8318 force_recv_intr(rcd
);
8324 * Receive packet thread handler. This expects to be invoked with the
8325 * receive interrupt still blocked.
8327 static irqreturn_t
receive_context_thread(int irq
, void *data
)
8329 struct hfi1_ctxtdata
*rcd
= data
;
8332 /* receive interrupt is still blocked from the IRQ handler */
8333 (void)rcd
->do_interrupt(rcd
, 1);
8336 * The packet processor will only return if it detected no more
8337 * packets. Hold IRQs here so we can safely clear the interrupt and
8338 * recheck for a packet that may have arrived after the previous
8339 * check and the interrupt clear. If a packet arrived, force another
8342 local_irq_disable();
8343 clear_recv_intr(rcd
);
8344 present
= check_packet_present(rcd
);
8346 force_recv_intr(rcd
);
8352 /* ========================================================================= */
8354 u32
read_physical_state(struct hfi1_devdata
*dd
)
8358 reg
= read_csr(dd
, DC_DC8051_STS_CUR_STATE
);
8359 return (reg
>> DC_DC8051_STS_CUR_STATE_PORT_SHIFT
)
8360 & DC_DC8051_STS_CUR_STATE_PORT_MASK
;
8363 u32
read_logical_state(struct hfi1_devdata
*dd
)
8367 reg
= read_csr(dd
, DCC_CFG_PORT_CONFIG
);
8368 return (reg
>> DCC_CFG_PORT_CONFIG_LINK_STATE_SHIFT
)
8369 & DCC_CFG_PORT_CONFIG_LINK_STATE_MASK
;
8372 static void set_logical_state(struct hfi1_devdata
*dd
, u32 chip_lstate
)
8376 reg
= read_csr(dd
, DCC_CFG_PORT_CONFIG
);
8377 /* clear current state, set new state */
8378 reg
&= ~DCC_CFG_PORT_CONFIG_LINK_STATE_SMASK
;
8379 reg
|= (u64
)chip_lstate
<< DCC_CFG_PORT_CONFIG_LINK_STATE_SHIFT
;
8380 write_csr(dd
, DCC_CFG_PORT_CONFIG
, reg
);
8384 * Use the 8051 to read a LCB CSR.
8386 static int read_lcb_via_8051(struct hfi1_devdata
*dd
, u32 addr
, u64
*data
)
8391 if (dd
->icode
== ICODE_FUNCTIONAL_SIMULATOR
) {
8392 if (acquire_lcb_access(dd
, 0) == 0) {
8393 *data
= read_csr(dd
, addr
);
8394 release_lcb_access(dd
, 0);
8400 /* register is an index of LCB registers: (offset - base) / 8 */
8401 regno
= (addr
- DC_LCB_CFG_RUN
) >> 3;
8402 ret
= do_8051_command(dd
, HCMD_READ_LCB_CSR
, regno
, data
);
8403 if (ret
!= HCMD_SUCCESS
)
8409 * Provide a cache for some of the LCB registers in case the LCB is
8411 * (The LCB is unavailable in certain link states, for example.)
8418 static struct lcb_datum lcb_cache
[] = {
8419 { DC_LCB_ERR_INFO_RX_REPLAY_CNT
, 0},
8420 { DC_LCB_ERR_INFO_SEQ_CRC_CNT
, 0 },
8421 { DC_LCB_ERR_INFO_REINIT_FROM_PEER_CNT
, 0 },
8424 static void update_lcb_cache(struct hfi1_devdata
*dd
)
8430 for (i
= 0; i
< ARRAY_SIZE(lcb_cache
); i
++) {
8431 ret
= read_lcb_csr(dd
, lcb_cache
[i
].off
, &val
);
8433 /* Update if we get good data */
8434 if (likely(ret
!= -EBUSY
))
8435 lcb_cache
[i
].val
= val
;
8439 static int read_lcb_cache(u32 off
, u64
*val
)
8443 for (i
= 0; i
< ARRAY_SIZE(lcb_cache
); i
++) {
8444 if (lcb_cache
[i
].off
== off
) {
8445 *val
= lcb_cache
[i
].val
;
8450 pr_warn("%s bad offset 0x%x\n", __func__
, off
);
8455 * Read an LCB CSR. Access may not be in host control, so check.
8456 * Return 0 on success, -EBUSY on failure.
8458 int read_lcb_csr(struct hfi1_devdata
*dd
, u32 addr
, u64
*data
)
8460 struct hfi1_pportdata
*ppd
= dd
->pport
;
8462 /* if up, go through the 8051 for the value */
8463 if (ppd
->host_link_state
& HLS_UP
)
8464 return read_lcb_via_8051(dd
, addr
, data
);
8465 /* if going up or down, check the cache, otherwise, no access */
8466 if (ppd
->host_link_state
& (HLS_GOING_UP
| HLS_GOING_OFFLINE
)) {
8467 if (read_lcb_cache(addr
, data
))
8472 /* otherwise, host has access */
8473 *data
= read_csr(dd
, addr
);
8478 * Use the 8051 to write a LCB CSR.
8480 static int write_lcb_via_8051(struct hfi1_devdata
*dd
, u32 addr
, u64 data
)
8485 if (dd
->icode
== ICODE_FUNCTIONAL_SIMULATOR
||
8486 (dd
->dc8051_ver
< dc8051_ver(0, 20, 0))) {
8487 if (acquire_lcb_access(dd
, 0) == 0) {
8488 write_csr(dd
, addr
, data
);
8489 release_lcb_access(dd
, 0);
8495 /* register is an index of LCB registers: (offset - base) / 8 */
8496 regno
= (addr
- DC_LCB_CFG_RUN
) >> 3;
8497 ret
= do_8051_command(dd
, HCMD_WRITE_LCB_CSR
, regno
, &data
);
8498 if (ret
!= HCMD_SUCCESS
)
8504 * Write an LCB CSR. Access may not be in host control, so check.
8505 * Return 0 on success, -EBUSY on failure.
8507 int write_lcb_csr(struct hfi1_devdata
*dd
, u32 addr
, u64 data
)
8509 struct hfi1_pportdata
*ppd
= dd
->pport
;
8511 /* if up, go through the 8051 for the value */
8512 if (ppd
->host_link_state
& HLS_UP
)
8513 return write_lcb_via_8051(dd
, addr
, data
);
8514 /* if going up or down, no access */
8515 if (ppd
->host_link_state
& (HLS_GOING_UP
| HLS_GOING_OFFLINE
))
8517 /* otherwise, host has access */
8518 write_csr(dd
, addr
, data
);
8524 * < 0 = Linux error, not able to get access
8525 * > 0 = 8051 command RETURN_CODE
8527 static int do_8051_command(
8528 struct hfi1_devdata
*dd
,
8535 unsigned long timeout
;
8537 hfi1_cdbg(DC8051
, "type %d, data 0x%012llx", type
, in_data
);
8539 mutex_lock(&dd
->dc8051_lock
);
8541 /* We can't send any commands to the 8051 if it's in reset */
8542 if (dd
->dc_shutdown
) {
8543 return_code
= -ENODEV
;
8548 * If an 8051 host command timed out previously, then the 8051 is
8551 * On first timeout, attempt to reset and restart the entire DC
8552 * block (including 8051). (Is this too big of a hammer?)
8554 * If the 8051 times out a second time, the reset did not bring it
8555 * back to healthy life. In that case, fail any subsequent commands.
8557 if (dd
->dc8051_timed_out
) {
8558 if (dd
->dc8051_timed_out
> 1) {
8560 "Previous 8051 host command timed out, skipping command %u\n",
8562 return_code
= -ENXIO
;
8570 * If there is no timeout, then the 8051 command interface is
8571 * waiting for a command.
8575 * When writing a LCB CSR, out_data contains the full value to
8576 * to be written, while in_data contains the relative LCB
8577 * address in 7:0. Do the work here, rather than the caller,
8578 * of distrubting the write data to where it needs to go:
8581 * 39:00 -> in_data[47:8]
8582 * 47:40 -> DC8051_CFG_EXT_DEV_0.RETURN_CODE
8583 * 63:48 -> DC8051_CFG_EXT_DEV_0.RSP_DATA
8585 if (type
== HCMD_WRITE_LCB_CSR
) {
8586 in_data
|= ((*out_data
) & 0xffffffffffull
) << 8;
8587 /* must preserve COMPLETED - it is tied to hardware */
8588 reg
= read_csr(dd
, DC_DC8051_CFG_EXT_DEV_0
);
8589 reg
&= DC_DC8051_CFG_EXT_DEV_0_COMPLETED_SMASK
;
8590 reg
|= ((((*out_data
) >> 40) & 0xff) <<
8591 DC_DC8051_CFG_EXT_DEV_0_RETURN_CODE_SHIFT
)
8592 | ((((*out_data
) >> 48) & 0xffff) <<
8593 DC_DC8051_CFG_EXT_DEV_0_RSP_DATA_SHIFT
);
8594 write_csr(dd
, DC_DC8051_CFG_EXT_DEV_0
, reg
);
8598 * Do two writes: the first to stabilize the type and req_data, the
8599 * second to activate.
8601 reg
= ((u64
)type
& DC_DC8051_CFG_HOST_CMD_0_REQ_TYPE_MASK
)
8602 << DC_DC8051_CFG_HOST_CMD_0_REQ_TYPE_SHIFT
8603 | (in_data
& DC_DC8051_CFG_HOST_CMD_0_REQ_DATA_MASK
)
8604 << DC_DC8051_CFG_HOST_CMD_0_REQ_DATA_SHIFT
;
8605 write_csr(dd
, DC_DC8051_CFG_HOST_CMD_0
, reg
);
8606 reg
|= DC_DC8051_CFG_HOST_CMD_0_REQ_NEW_SMASK
;
8607 write_csr(dd
, DC_DC8051_CFG_HOST_CMD_0
, reg
);
8609 /* wait for completion, alternate: interrupt */
8610 timeout
= jiffies
+ msecs_to_jiffies(DC8051_COMMAND_TIMEOUT
);
8612 reg
= read_csr(dd
, DC_DC8051_CFG_HOST_CMD_1
);
8613 completed
= reg
& DC_DC8051_CFG_HOST_CMD_1_COMPLETED_SMASK
;
8616 if (time_after(jiffies
, timeout
)) {
8617 dd
->dc8051_timed_out
++;
8618 dd_dev_err(dd
, "8051 host command %u timeout\n", type
);
8621 return_code
= -ETIMEDOUT
;
8628 *out_data
= (reg
>> DC_DC8051_CFG_HOST_CMD_1_RSP_DATA_SHIFT
)
8629 & DC_DC8051_CFG_HOST_CMD_1_RSP_DATA_MASK
;
8630 if (type
== HCMD_READ_LCB_CSR
) {
8631 /* top 16 bits are in a different register */
8632 *out_data
|= (read_csr(dd
, DC_DC8051_CFG_EXT_DEV_1
)
8633 & DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SMASK
)
8635 - DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SHIFT
);
8638 return_code
= (reg
>> DC_DC8051_CFG_HOST_CMD_1_RETURN_CODE_SHIFT
)
8639 & DC_DC8051_CFG_HOST_CMD_1_RETURN_CODE_MASK
;
8640 dd
->dc8051_timed_out
= 0;
8642 * Clear command for next user.
8644 write_csr(dd
, DC_DC8051_CFG_HOST_CMD_0
, 0);
8647 mutex_unlock(&dd
->dc8051_lock
);
8651 static int set_physical_link_state(struct hfi1_devdata
*dd
, u64 state
)
8653 return do_8051_command(dd
, HCMD_CHANGE_PHY_STATE
, state
, NULL
);
8656 int load_8051_config(struct hfi1_devdata
*dd
, u8 field_id
,
8657 u8 lane_id
, u32 config_data
)
8662 data
= (u64
)field_id
<< LOAD_DATA_FIELD_ID_SHIFT
8663 | (u64
)lane_id
<< LOAD_DATA_LANE_ID_SHIFT
8664 | (u64
)config_data
<< LOAD_DATA_DATA_SHIFT
;
8665 ret
= do_8051_command(dd
, HCMD_LOAD_CONFIG_DATA
, data
, NULL
);
8666 if (ret
!= HCMD_SUCCESS
) {
8668 "load 8051 config: field id %d, lane %d, err %d\n",
8669 (int)field_id
, (int)lane_id
, ret
);
8675 * Read the 8051 firmware "registers". Use the RAM directly. Always
8676 * set the result, even on error.
8677 * Return 0 on success, -errno on failure
8679 int read_8051_config(struct hfi1_devdata
*dd
, u8 field_id
, u8 lane_id
,
8686 /* address start depends on the lane_id */
8688 addr
= (4 * NUM_GENERAL_FIELDS
)
8689 + (lane_id
* 4 * NUM_LANE_FIELDS
);
8692 addr
+= field_id
* 4;
8694 /* read is in 8-byte chunks, hardware will truncate the address down */
8695 ret
= read_8051_data(dd
, addr
, 8, &big_data
);
8698 /* extract the 4 bytes we want */
8700 *result
= (u32
)(big_data
>> 32);
8702 *result
= (u32
)big_data
;
8705 dd_dev_err(dd
, "%s: direct read failed, lane %d, field %d!\n",
8706 __func__
, lane_id
, field_id
);
8712 static int write_vc_local_phy(struct hfi1_devdata
*dd
, u8 power_management
,
8717 frame
= continuous
<< CONTINIOUS_REMOTE_UPDATE_SUPPORT_SHIFT
8718 | power_management
<< POWER_MANAGEMENT_SHIFT
;
8719 return load_8051_config(dd
, VERIFY_CAP_LOCAL_PHY
,
8720 GENERAL_CONFIG
, frame
);
8723 static int write_vc_local_fabric(struct hfi1_devdata
*dd
, u8 vau
, u8 z
, u8 vcu
,
8724 u16 vl15buf
, u8 crc_sizes
)
8728 frame
= (u32
)vau
<< VAU_SHIFT
8730 | (u32
)vcu
<< VCU_SHIFT
8731 | (u32
)vl15buf
<< VL15BUF_SHIFT
8732 | (u32
)crc_sizes
<< CRC_SIZES_SHIFT
;
8733 return load_8051_config(dd
, VERIFY_CAP_LOCAL_FABRIC
,
8734 GENERAL_CONFIG
, frame
);
8737 static void read_vc_local_link_width(struct hfi1_devdata
*dd
, u8
*misc_bits
,
8738 u8
*flag_bits
, u16
*link_widths
)
8742 read_8051_config(dd
, VERIFY_CAP_LOCAL_LINK_WIDTH
, GENERAL_CONFIG
,
8744 *misc_bits
= (frame
>> MISC_CONFIG_BITS_SHIFT
) & MISC_CONFIG_BITS_MASK
;
8745 *flag_bits
= (frame
>> LOCAL_FLAG_BITS_SHIFT
) & LOCAL_FLAG_BITS_MASK
;
8746 *link_widths
= (frame
>> LINK_WIDTH_SHIFT
) & LINK_WIDTH_MASK
;
8749 static int write_vc_local_link_width(struct hfi1_devdata
*dd
,
8756 frame
= (u32
)misc_bits
<< MISC_CONFIG_BITS_SHIFT
8757 | (u32
)flag_bits
<< LOCAL_FLAG_BITS_SHIFT
8758 | (u32
)link_widths
<< LINK_WIDTH_SHIFT
;
8759 return load_8051_config(dd
, VERIFY_CAP_LOCAL_LINK_WIDTH
, GENERAL_CONFIG
,
8763 static int write_local_device_id(struct hfi1_devdata
*dd
, u16 device_id
,
8768 frame
= ((u32
)device_id
<< LOCAL_DEVICE_ID_SHIFT
)
8769 | ((u32
)device_rev
<< LOCAL_DEVICE_REV_SHIFT
);
8770 return load_8051_config(dd
, LOCAL_DEVICE_ID
, GENERAL_CONFIG
, frame
);
8773 static void read_remote_device_id(struct hfi1_devdata
*dd
, u16
*device_id
,
8778 read_8051_config(dd
, REMOTE_DEVICE_ID
, GENERAL_CONFIG
, &frame
);
8779 *device_id
= (frame
>> REMOTE_DEVICE_ID_SHIFT
) & REMOTE_DEVICE_ID_MASK
;
8780 *device_rev
= (frame
>> REMOTE_DEVICE_REV_SHIFT
)
8781 & REMOTE_DEVICE_REV_MASK
;
8784 void read_misc_status(struct hfi1_devdata
*dd
, u8
*ver_major
, u8
*ver_minor
,
8789 read_8051_config(dd
, MISC_STATUS
, GENERAL_CONFIG
, &frame
);
8790 *ver_major
= (frame
>> STS_FM_VERSION_MAJOR_SHIFT
) &
8791 STS_FM_VERSION_MAJOR_MASK
;
8792 *ver_minor
= (frame
>> STS_FM_VERSION_MINOR_SHIFT
) &
8793 STS_FM_VERSION_MINOR_MASK
;
8795 read_8051_config(dd
, VERSION_PATCH
, GENERAL_CONFIG
, &frame
);
8796 *ver_patch
= (frame
>> STS_FM_VERSION_PATCH_SHIFT
) &
8797 STS_FM_VERSION_PATCH_MASK
;
8800 static void read_vc_remote_phy(struct hfi1_devdata
*dd
, u8
*power_management
,
8805 read_8051_config(dd
, VERIFY_CAP_REMOTE_PHY
, GENERAL_CONFIG
, &frame
);
8806 *power_management
= (frame
>> POWER_MANAGEMENT_SHIFT
)
8807 & POWER_MANAGEMENT_MASK
;
8808 *continuous
= (frame
>> CONTINIOUS_REMOTE_UPDATE_SUPPORT_SHIFT
)
8809 & CONTINIOUS_REMOTE_UPDATE_SUPPORT_MASK
;
8812 static void read_vc_remote_fabric(struct hfi1_devdata
*dd
, u8
*vau
, u8
*z
,
8813 u8
*vcu
, u16
*vl15buf
, u8
*crc_sizes
)
8817 read_8051_config(dd
, VERIFY_CAP_REMOTE_FABRIC
, GENERAL_CONFIG
, &frame
);
8818 *vau
= (frame
>> VAU_SHIFT
) & VAU_MASK
;
8819 *z
= (frame
>> Z_SHIFT
) & Z_MASK
;
8820 *vcu
= (frame
>> VCU_SHIFT
) & VCU_MASK
;
8821 *vl15buf
= (frame
>> VL15BUF_SHIFT
) & VL15BUF_MASK
;
8822 *crc_sizes
= (frame
>> CRC_SIZES_SHIFT
) & CRC_SIZES_MASK
;
8825 static void read_vc_remote_link_width(struct hfi1_devdata
*dd
,
8831 read_8051_config(dd
, VERIFY_CAP_REMOTE_LINK_WIDTH
, GENERAL_CONFIG
,
8833 *remote_tx_rate
= (frame
>> REMOTE_TX_RATE_SHIFT
)
8834 & REMOTE_TX_RATE_MASK
;
8835 *link_widths
= (frame
>> LINK_WIDTH_SHIFT
) & LINK_WIDTH_MASK
;
8838 static void read_local_lni(struct hfi1_devdata
*dd
, u8
*enable_lane_rx
)
8842 read_8051_config(dd
, LOCAL_LNI_INFO
, GENERAL_CONFIG
, &frame
);
8843 *enable_lane_rx
= (frame
>> ENABLE_LANE_RX_SHIFT
) & ENABLE_LANE_RX_MASK
;
8846 static void read_mgmt_allowed(struct hfi1_devdata
*dd
, u8
*mgmt_allowed
)
8850 read_8051_config(dd
, REMOTE_LNI_INFO
, GENERAL_CONFIG
, &frame
);
8851 *mgmt_allowed
= (frame
>> MGMT_ALLOWED_SHIFT
) & MGMT_ALLOWED_MASK
;
8854 static void read_last_local_state(struct hfi1_devdata
*dd
, u32
*lls
)
8856 read_8051_config(dd
, LAST_LOCAL_STATE_COMPLETE
, GENERAL_CONFIG
, lls
);
8859 static void read_last_remote_state(struct hfi1_devdata
*dd
, u32
*lrs
)
8861 read_8051_config(dd
, LAST_REMOTE_STATE_COMPLETE
, GENERAL_CONFIG
, lrs
);
8864 void hfi1_read_link_quality(struct hfi1_devdata
*dd
, u8
*link_quality
)
8870 if (dd
->pport
->host_link_state
& HLS_UP
) {
8871 ret
= read_8051_config(dd
, LINK_QUALITY_INFO
, GENERAL_CONFIG
,
8874 *link_quality
= (frame
>> LINK_QUALITY_SHIFT
)
8875 & LINK_QUALITY_MASK
;
8879 static void read_planned_down_reason_code(struct hfi1_devdata
*dd
, u8
*pdrrc
)
8883 read_8051_config(dd
, LINK_QUALITY_INFO
, GENERAL_CONFIG
, &frame
);
8884 *pdrrc
= (frame
>> DOWN_REMOTE_REASON_SHIFT
) & DOWN_REMOTE_REASON_MASK
;
8887 static void read_link_down_reason(struct hfi1_devdata
*dd
, u8
*ldr
)
8891 read_8051_config(dd
, LINK_DOWN_REASON
, GENERAL_CONFIG
, &frame
);
8892 *ldr
= (frame
& 0xff);
8895 static int read_tx_settings(struct hfi1_devdata
*dd
,
8897 u8
*tx_polarity_inversion
,
8898 u8
*rx_polarity_inversion
,
8904 ret
= read_8051_config(dd
, TX_SETTINGS
, GENERAL_CONFIG
, &frame
);
8905 *enable_lane_tx
= (frame
>> ENABLE_LANE_TX_SHIFT
)
8906 & ENABLE_LANE_TX_MASK
;
8907 *tx_polarity_inversion
= (frame
>> TX_POLARITY_INVERSION_SHIFT
)
8908 & TX_POLARITY_INVERSION_MASK
;
8909 *rx_polarity_inversion
= (frame
>> RX_POLARITY_INVERSION_SHIFT
)
8910 & RX_POLARITY_INVERSION_MASK
;
8911 *max_rate
= (frame
>> MAX_RATE_SHIFT
) & MAX_RATE_MASK
;
8915 static int write_tx_settings(struct hfi1_devdata
*dd
,
8917 u8 tx_polarity_inversion
,
8918 u8 rx_polarity_inversion
,
8923 /* no need to mask, all variable sizes match field widths */
8924 frame
= enable_lane_tx
<< ENABLE_LANE_TX_SHIFT
8925 | tx_polarity_inversion
<< TX_POLARITY_INVERSION_SHIFT
8926 | rx_polarity_inversion
<< RX_POLARITY_INVERSION_SHIFT
8927 | max_rate
<< MAX_RATE_SHIFT
;
8928 return load_8051_config(dd
, TX_SETTINGS
, GENERAL_CONFIG
, frame
);
8932 * Read an idle LCB message.
8934 * Returns 0 on success, -EINVAL on error
8936 static int read_idle_message(struct hfi1_devdata
*dd
, u64 type
, u64
*data_out
)
8940 ret
= do_8051_command(dd
, HCMD_READ_LCB_IDLE_MSG
, type
, data_out
);
8941 if (ret
!= HCMD_SUCCESS
) {
8942 dd_dev_err(dd
, "read idle message: type %d, err %d\n",
8946 dd_dev_info(dd
, "%s: read idle message 0x%llx\n", __func__
, *data_out
);
8947 /* return only the payload as we already know the type */
8948 *data_out
>>= IDLE_PAYLOAD_SHIFT
;
8953 * Read an idle SMA message. To be done in response to a notification from
8956 * Returns 0 on success, -EINVAL on error
8958 static int read_idle_sma(struct hfi1_devdata
*dd
, u64
*data
)
8960 return read_idle_message(dd
, (u64
)IDLE_SMA
<< IDLE_MSG_TYPE_SHIFT
,
8965 * Send an idle LCB message.
8967 * Returns 0 on success, -EINVAL on error
8969 static int send_idle_message(struct hfi1_devdata
*dd
, u64 data
)
8973 dd_dev_info(dd
, "%s: sending idle message 0x%llx\n", __func__
, data
);
8974 ret
= do_8051_command(dd
, HCMD_SEND_LCB_IDLE_MSG
, data
, NULL
);
8975 if (ret
!= HCMD_SUCCESS
) {
8976 dd_dev_err(dd
, "send idle message: data 0x%llx, err %d\n",
8984 * Send an idle SMA message.
8986 * Returns 0 on success, -EINVAL on error
8988 int send_idle_sma(struct hfi1_devdata
*dd
, u64 message
)
8992 data
= ((message
& IDLE_PAYLOAD_MASK
) << IDLE_PAYLOAD_SHIFT
) |
8993 ((u64
)IDLE_SMA
<< IDLE_MSG_TYPE_SHIFT
);
8994 return send_idle_message(dd
, data
);
8998 * Initialize the LCB then do a quick link up. This may or may not be
9001 * return 0 on success, -errno on error
9003 static int do_quick_linkup(struct hfi1_devdata
*dd
)
9007 lcb_shutdown(dd
, 0);
9010 /* LCB_CFG_LOOPBACK.VAL = 2 */
9011 /* LCB_CFG_LANE_WIDTH.VAL = 0 */
9012 write_csr(dd
, DC_LCB_CFG_LOOPBACK
,
9013 IB_PACKET_TYPE
<< DC_LCB_CFG_LOOPBACK_VAL_SHIFT
);
9014 write_csr(dd
, DC_LCB_CFG_LANE_WIDTH
, 0);
9017 /* start the LCBs */
9018 /* LCB_CFG_TX_FIFOS_RESET.VAL = 0 */
9019 write_csr(dd
, DC_LCB_CFG_TX_FIFOS_RESET
, 0);
9021 /* simulator only loopback steps */
9022 if (loopback
&& dd
->icode
== ICODE_FUNCTIONAL_SIMULATOR
) {
9023 /* LCB_CFG_RUN.EN = 1 */
9024 write_csr(dd
, DC_LCB_CFG_RUN
,
9025 1ull << DC_LCB_CFG_RUN_EN_SHIFT
);
9027 ret
= wait_link_transfer_active(dd
, 10);
9031 write_csr(dd
, DC_LCB_CFG_ALLOW_LINK_UP
,
9032 1ull << DC_LCB_CFG_ALLOW_LINK_UP_VAL_SHIFT
);
9037 * When doing quick linkup and not in loopback, both
9038 * sides must be done with LCB set-up before either
9039 * starts the quick linkup. Put a delay here so that
9040 * both sides can be started and have a chance to be
9041 * done with LCB set up before resuming.
9044 "Pausing for peer to be finished with LCB set up\n");
9046 dd_dev_err(dd
, "Continuing with quick linkup\n");
9049 write_csr(dd
, DC_LCB_ERR_EN
, 0); /* mask LCB errors */
9050 set_8051_lcb_access(dd
);
9053 * State "quick" LinkUp request sets the physical link state to
9054 * LinkUp without a verify capability sequence.
9055 * This state is in simulator v37 and later.
9057 ret
= set_physical_link_state(dd
, PLS_QUICK_LINKUP
);
9058 if (ret
!= HCMD_SUCCESS
) {
9060 "%s: set physical link state to quick LinkUp failed with return %d\n",
9063 set_host_lcb_access(dd
);
9064 write_csr(dd
, DC_LCB_ERR_EN
, ~0ull); /* watch LCB errors */
9071 return 0; /* success */
9075 * Set the SerDes to internal loopback mode.
9076 * Returns 0 on success, -errno on error.
9078 static int set_serdes_loopback_mode(struct hfi1_devdata
*dd
)
9082 ret
= set_physical_link_state(dd
, PLS_INTERNAL_SERDES_LOOPBACK
);
9083 if (ret
== HCMD_SUCCESS
)
9086 "Set physical link state to SerDes Loopback failed with return %d\n",
9094 * Do all special steps to set up loopback.
9096 static int init_loopback(struct hfi1_devdata
*dd
)
9098 dd_dev_info(dd
, "Entering loopback mode\n");
9100 /* all loopbacks should disable self GUID check */
9101 write_csr(dd
, DC_DC8051_CFG_MODE
,
9102 (read_csr(dd
, DC_DC8051_CFG_MODE
) | DISABLE_SELF_GUID_CHECK
));
9105 * The simulator has only one loopback option - LCB. Switch
9106 * to that option, which includes quick link up.
9108 * Accept all valid loopback values.
9110 if ((dd
->icode
== ICODE_FUNCTIONAL_SIMULATOR
) &&
9111 (loopback
== LOOPBACK_SERDES
|| loopback
== LOOPBACK_LCB
||
9112 loopback
== LOOPBACK_CABLE
)) {
9113 loopback
= LOOPBACK_LCB
;
9118 /* handle serdes loopback */
9119 if (loopback
== LOOPBACK_SERDES
) {
9120 /* internal serdes loopack needs quick linkup on RTL */
9121 if (dd
->icode
== ICODE_RTL_SILICON
)
9123 return set_serdes_loopback_mode(dd
);
9126 /* LCB loopback - handled at poll time */
9127 if (loopback
== LOOPBACK_LCB
) {
9128 quick_linkup
= 1; /* LCB is always quick linkup */
9130 /* not supported in emulation due to emulation RTL changes */
9131 if (dd
->icode
== ICODE_FPGA_EMULATION
) {
9133 "LCB loopback not supported in emulation\n");
9139 /* external cable loopback requires no extra steps */
9140 if (loopback
== LOOPBACK_CABLE
)
9143 dd_dev_err(dd
, "Invalid loopback mode %d\n", loopback
);
9148 * Translate from the OPA_LINK_WIDTH handed to us by the FM to bits
9149 * used in the Verify Capability link width attribute.
9151 static u16
opa_to_vc_link_widths(u16 opa_widths
)
9156 static const struct link_bits
{
9159 } opa_link_xlate
[] = {
9160 { OPA_LINK_WIDTH_1X
, 1 << (1 - 1) },
9161 { OPA_LINK_WIDTH_2X
, 1 << (2 - 1) },
9162 { OPA_LINK_WIDTH_3X
, 1 << (3 - 1) },
9163 { OPA_LINK_WIDTH_4X
, 1 << (4 - 1) },
9166 for (i
= 0; i
< ARRAY_SIZE(opa_link_xlate
); i
++) {
9167 if (opa_widths
& opa_link_xlate
[i
].from
)
9168 result
|= opa_link_xlate
[i
].to
;
9174 * Set link attributes before moving to polling.
9176 static int set_local_link_attributes(struct hfi1_pportdata
*ppd
)
9178 struct hfi1_devdata
*dd
= ppd
->dd
;
9180 u8 tx_polarity_inversion
;
9181 u8 rx_polarity_inversion
;
9184 /* reset our fabric serdes to clear any lingering problems */
9185 fabric_serdes_reset(dd
);
9187 /* set the local tx rate - need to read-modify-write */
9188 ret
= read_tx_settings(dd
, &enable_lane_tx
, &tx_polarity_inversion
,
9189 &rx_polarity_inversion
, &ppd
->local_tx_rate
);
9191 goto set_local_link_attributes_fail
;
9193 if (dd
->dc8051_ver
< dc8051_ver(0, 20, 0)) {
9194 /* set the tx rate to the fastest enabled */
9195 if (ppd
->link_speed_enabled
& OPA_LINK_SPEED_25G
)
9196 ppd
->local_tx_rate
= 1;
9198 ppd
->local_tx_rate
= 0;
9200 /* set the tx rate to all enabled */
9201 ppd
->local_tx_rate
= 0;
9202 if (ppd
->link_speed_enabled
& OPA_LINK_SPEED_25G
)
9203 ppd
->local_tx_rate
|= 2;
9204 if (ppd
->link_speed_enabled
& OPA_LINK_SPEED_12_5G
)
9205 ppd
->local_tx_rate
|= 1;
9208 enable_lane_tx
= 0xF; /* enable all four lanes */
9209 ret
= write_tx_settings(dd
, enable_lane_tx
, tx_polarity_inversion
,
9210 rx_polarity_inversion
, ppd
->local_tx_rate
);
9211 if (ret
!= HCMD_SUCCESS
)
9212 goto set_local_link_attributes_fail
;
9215 * DC supports continuous updates.
9217 ret
= write_vc_local_phy(dd
,
9218 0 /* no power management */,
9219 1 /* continuous updates */);
9220 if (ret
!= HCMD_SUCCESS
)
9221 goto set_local_link_attributes_fail
;
9223 /* z=1 in the next call: AU of 0 is not supported by the hardware */
9224 ret
= write_vc_local_fabric(dd
, dd
->vau
, 1, dd
->vcu
, dd
->vl15_init
,
9225 ppd
->port_crc_mode_enabled
);
9226 if (ret
!= HCMD_SUCCESS
)
9227 goto set_local_link_attributes_fail
;
9229 ret
= write_vc_local_link_width(dd
, 0, 0,
9230 opa_to_vc_link_widths(
9231 ppd
->link_width_enabled
));
9232 if (ret
!= HCMD_SUCCESS
)
9233 goto set_local_link_attributes_fail
;
9235 /* let peer know who we are */
9236 ret
= write_local_device_id(dd
, dd
->pcidev
->device
, dd
->minrev
);
9237 if (ret
== HCMD_SUCCESS
)
9240 set_local_link_attributes_fail
:
9242 "Failed to set local link attributes, return 0x%x\n",
9248 * Call this to start the link.
9249 * Do not do anything if the link is disabled.
9250 * Returns 0 if link is disabled, moved to polling, or the driver is not ready.
9252 int start_link(struct hfi1_pportdata
*ppd
)
9255 * Tune the SerDes to a ballpark setting for optimal signal and bit
9256 * error rate. Needs to be done before starting the link.
9260 if (!ppd
->link_enabled
) {
9261 dd_dev_info(ppd
->dd
,
9262 "%s: stopping link start because link is disabled\n",
9266 if (!ppd
->driver_link_ready
) {
9267 dd_dev_info(ppd
->dd
,
9268 "%s: stopping link start because driver is not ready\n",
9274 * FULL_MGMT_P_KEY is cleared from the pkey table, so that the
9275 * pkey table can be configured properly if the HFI unit is connected
9276 * to switch port with MgmtAllowed=NO
9278 clear_full_mgmt_pkey(ppd
);
9280 return set_link_state(ppd
, HLS_DN_POLL
);
9283 static void wait_for_qsfp_init(struct hfi1_pportdata
*ppd
)
9285 struct hfi1_devdata
*dd
= ppd
->dd
;
9287 unsigned long timeout
;
9290 * Some QSFP cables have a quirk that asserts the IntN line as a side
9291 * effect of power up on plug-in. We ignore this false positive
9292 * interrupt until the module has finished powering up by waiting for
9293 * a minimum timeout of the module inrush initialization time of
9294 * 500 ms (SFF 8679 Table 5-6) to ensure the voltage rails in the
9295 * module have stabilized.
9300 * Check for QSFP interrupt for t_init (SFF 8679 Table 8-1)
9302 timeout
= jiffies
+ msecs_to_jiffies(2000);
9304 mask
= read_csr(dd
, dd
->hfi1_id
?
9305 ASIC_QSFP2_IN
: ASIC_QSFP1_IN
);
9306 if (!(mask
& QSFP_HFI0_INT_N
))
9308 if (time_after(jiffies
, timeout
)) {
9309 dd_dev_info(dd
, "%s: No IntN detected, reset complete\n",
9317 static void set_qsfp_int_n(struct hfi1_pportdata
*ppd
, u8 enable
)
9319 struct hfi1_devdata
*dd
= ppd
->dd
;
9322 mask
= read_csr(dd
, dd
->hfi1_id
? ASIC_QSFP2_MASK
: ASIC_QSFP1_MASK
);
9325 * Clear the status register to avoid an immediate interrupt
9326 * when we re-enable the IntN pin
9328 write_csr(dd
, dd
->hfi1_id
? ASIC_QSFP2_CLEAR
: ASIC_QSFP1_CLEAR
,
9330 mask
|= (u64
)QSFP_HFI0_INT_N
;
9332 mask
&= ~(u64
)QSFP_HFI0_INT_N
;
9334 write_csr(dd
, dd
->hfi1_id
? ASIC_QSFP2_MASK
: ASIC_QSFP1_MASK
, mask
);
9337 void reset_qsfp(struct hfi1_pportdata
*ppd
)
9339 struct hfi1_devdata
*dd
= ppd
->dd
;
9340 u64 mask
, qsfp_mask
;
9342 /* Disable INT_N from triggering QSFP interrupts */
9343 set_qsfp_int_n(ppd
, 0);
9345 /* Reset the QSFP */
9346 mask
= (u64
)QSFP_HFI0_RESET_N
;
9348 qsfp_mask
= read_csr(dd
,
9349 dd
->hfi1_id
? ASIC_QSFP2_OUT
: ASIC_QSFP1_OUT
);
9352 dd
->hfi1_id
? ASIC_QSFP2_OUT
: ASIC_QSFP1_OUT
, qsfp_mask
);
9358 dd
->hfi1_id
? ASIC_QSFP2_OUT
: ASIC_QSFP1_OUT
, qsfp_mask
);
9360 wait_for_qsfp_init(ppd
);
9363 * Allow INT_N to trigger the QSFP interrupt to watch
9364 * for alarms and warnings
9366 set_qsfp_int_n(ppd
, 1);
9369 static int handle_qsfp_error_conditions(struct hfi1_pportdata
*ppd
,
9370 u8
*qsfp_interrupt_status
)
9372 struct hfi1_devdata
*dd
= ppd
->dd
;
9374 if ((qsfp_interrupt_status
[0] & QSFP_HIGH_TEMP_ALARM
) ||
9375 (qsfp_interrupt_status
[0] & QSFP_HIGH_TEMP_WARNING
))
9376 dd_dev_info(dd
, "%s: QSFP cable temperature too high\n",
9379 if ((qsfp_interrupt_status
[0] & QSFP_LOW_TEMP_ALARM
) ||
9380 (qsfp_interrupt_status
[0] & QSFP_LOW_TEMP_WARNING
))
9381 dd_dev_info(dd
, "%s: QSFP cable temperature too low\n",
9385 * The remaining alarms/warnings don't matter if the link is down.
9387 if (ppd
->host_link_state
& HLS_DOWN
)
9390 if ((qsfp_interrupt_status
[1] & QSFP_HIGH_VCC_ALARM
) ||
9391 (qsfp_interrupt_status
[1] & QSFP_HIGH_VCC_WARNING
))
9392 dd_dev_info(dd
, "%s: QSFP supply voltage too high\n",
9395 if ((qsfp_interrupt_status
[1] & QSFP_LOW_VCC_ALARM
) ||
9396 (qsfp_interrupt_status
[1] & QSFP_LOW_VCC_WARNING
))
9397 dd_dev_info(dd
, "%s: QSFP supply voltage too low\n",
9400 /* Byte 2 is vendor specific */
9402 if ((qsfp_interrupt_status
[3] & QSFP_HIGH_POWER_ALARM
) ||
9403 (qsfp_interrupt_status
[3] & QSFP_HIGH_POWER_WARNING
))
9404 dd_dev_info(dd
, "%s: Cable RX channel 1/2 power too high\n",
9407 if ((qsfp_interrupt_status
[3] & QSFP_LOW_POWER_ALARM
) ||
9408 (qsfp_interrupt_status
[3] & QSFP_LOW_POWER_WARNING
))
9409 dd_dev_info(dd
, "%s: Cable RX channel 1/2 power too low\n",
9412 if ((qsfp_interrupt_status
[4] & QSFP_HIGH_POWER_ALARM
) ||
9413 (qsfp_interrupt_status
[4] & QSFP_HIGH_POWER_WARNING
))
9414 dd_dev_info(dd
, "%s: Cable RX channel 3/4 power too high\n",
9417 if ((qsfp_interrupt_status
[4] & QSFP_LOW_POWER_ALARM
) ||
9418 (qsfp_interrupt_status
[4] & QSFP_LOW_POWER_WARNING
))
9419 dd_dev_info(dd
, "%s: Cable RX channel 3/4 power too low\n",
9422 if ((qsfp_interrupt_status
[5] & QSFP_HIGH_BIAS_ALARM
) ||
9423 (qsfp_interrupt_status
[5] & QSFP_HIGH_BIAS_WARNING
))
9424 dd_dev_info(dd
, "%s: Cable TX channel 1/2 bias too high\n",
9427 if ((qsfp_interrupt_status
[5] & QSFP_LOW_BIAS_ALARM
) ||
9428 (qsfp_interrupt_status
[5] & QSFP_LOW_BIAS_WARNING
))
9429 dd_dev_info(dd
, "%s: Cable TX channel 1/2 bias too low\n",
9432 if ((qsfp_interrupt_status
[6] & QSFP_HIGH_BIAS_ALARM
) ||
9433 (qsfp_interrupt_status
[6] & QSFP_HIGH_BIAS_WARNING
))
9434 dd_dev_info(dd
, "%s: Cable TX channel 3/4 bias too high\n",
9437 if ((qsfp_interrupt_status
[6] & QSFP_LOW_BIAS_ALARM
) ||
9438 (qsfp_interrupt_status
[6] & QSFP_LOW_BIAS_WARNING
))
9439 dd_dev_info(dd
, "%s: Cable TX channel 3/4 bias too low\n",
9442 if ((qsfp_interrupt_status
[7] & QSFP_HIGH_POWER_ALARM
) ||
9443 (qsfp_interrupt_status
[7] & QSFP_HIGH_POWER_WARNING
))
9444 dd_dev_info(dd
, "%s: Cable TX channel 1/2 power too high\n",
9447 if ((qsfp_interrupt_status
[7] & QSFP_LOW_POWER_ALARM
) ||
9448 (qsfp_interrupt_status
[7] & QSFP_LOW_POWER_WARNING
))
9449 dd_dev_info(dd
, "%s: Cable TX channel 1/2 power too low\n",
9452 if ((qsfp_interrupt_status
[8] & QSFP_HIGH_POWER_ALARM
) ||
9453 (qsfp_interrupt_status
[8] & QSFP_HIGH_POWER_WARNING
))
9454 dd_dev_info(dd
, "%s: Cable TX channel 3/4 power too high\n",
9457 if ((qsfp_interrupt_status
[8] & QSFP_LOW_POWER_ALARM
) ||
9458 (qsfp_interrupt_status
[8] & QSFP_LOW_POWER_WARNING
))
9459 dd_dev_info(dd
, "%s: Cable TX channel 3/4 power too low\n",
9462 /* Bytes 9-10 and 11-12 are reserved */
9463 /* Bytes 13-15 are vendor specific */
9468 /* This routine will only be scheduled if the QSFP module present is asserted */
9469 void qsfp_event(struct work_struct
*work
)
9471 struct qsfp_data
*qd
;
9472 struct hfi1_pportdata
*ppd
;
9473 struct hfi1_devdata
*dd
;
9475 qd
= container_of(work
, struct qsfp_data
, qsfp_work
);
9480 if (!qsfp_mod_present(ppd
))
9484 * Turn DC back on after cable has been re-inserted. Up until
9485 * now, the DC has been in reset to save power.
9489 if (qd
->cache_refresh_required
) {
9490 set_qsfp_int_n(ppd
, 0);
9492 wait_for_qsfp_init(ppd
);
9495 * Allow INT_N to trigger the QSFP interrupt to watch
9496 * for alarms and warnings
9498 set_qsfp_int_n(ppd
, 1);
9503 if (qd
->check_interrupt_flags
) {
9504 u8 qsfp_interrupt_status
[16] = {0,};
9506 if (one_qsfp_read(ppd
, dd
->hfi1_id
, 6,
9507 &qsfp_interrupt_status
[0], 16) != 16) {
9509 "%s: Failed to read status of QSFP module\n",
9512 unsigned long flags
;
9514 handle_qsfp_error_conditions(
9515 ppd
, qsfp_interrupt_status
);
9516 spin_lock_irqsave(&ppd
->qsfp_info
.qsfp_lock
, flags
);
9517 ppd
->qsfp_info
.check_interrupt_flags
= 0;
9518 spin_unlock_irqrestore(&ppd
->qsfp_info
.qsfp_lock
,
9524 static void init_qsfp_int(struct hfi1_devdata
*dd
)
9526 struct hfi1_pportdata
*ppd
= dd
->pport
;
9527 u64 qsfp_mask
, cce_int_mask
;
9528 const int qsfp1_int_smask
= QSFP1_INT
% 64;
9529 const int qsfp2_int_smask
= QSFP2_INT
% 64;
9532 * disable QSFP1 interrupts for HFI1, QSFP2 interrupts for HFI0
9533 * Qsfp1Int and Qsfp2Int are adjacent bits in the same CSR,
9534 * therefore just one of QSFP1_INT/QSFP2_INT can be used to find
9535 * the index of the appropriate CSR in the CCEIntMask CSR array
9537 cce_int_mask
= read_csr(dd
, CCE_INT_MASK
+
9538 (8 * (QSFP1_INT
/ 64)));
9540 cce_int_mask
&= ~((u64
)1 << qsfp1_int_smask
);
9541 write_csr(dd
, CCE_INT_MASK
+ (8 * (QSFP1_INT
/ 64)),
9544 cce_int_mask
&= ~((u64
)1 << qsfp2_int_smask
);
9545 write_csr(dd
, CCE_INT_MASK
+ (8 * (QSFP2_INT
/ 64)),
9549 qsfp_mask
= (u64
)(QSFP_HFI0_INT_N
| QSFP_HFI0_MODPRST_N
);
9550 /* Clear current status to avoid spurious interrupts */
9551 write_csr(dd
, dd
->hfi1_id
? ASIC_QSFP2_CLEAR
: ASIC_QSFP1_CLEAR
,
9553 write_csr(dd
, dd
->hfi1_id
? ASIC_QSFP2_MASK
: ASIC_QSFP1_MASK
,
9556 set_qsfp_int_n(ppd
, 0);
9558 /* Handle active low nature of INT_N and MODPRST_N pins */
9559 if (qsfp_mod_present(ppd
))
9560 qsfp_mask
&= ~(u64
)QSFP_HFI0_MODPRST_N
;
9562 dd
->hfi1_id
? ASIC_QSFP2_INVERT
: ASIC_QSFP1_INVERT
,
9567 * Do a one-time initialize of the LCB block.
9569 static void init_lcb(struct hfi1_devdata
*dd
)
9571 /* simulator does not correctly handle LCB cclk loopback, skip */
9572 if (dd
->icode
== ICODE_FUNCTIONAL_SIMULATOR
)
9575 /* the DC has been reset earlier in the driver load */
9577 /* set LCB for cclk loopback on the port */
9578 write_csr(dd
, DC_LCB_CFG_TX_FIFOS_RESET
, 0x01);
9579 write_csr(dd
, DC_LCB_CFG_LANE_WIDTH
, 0x00);
9580 write_csr(dd
, DC_LCB_CFG_REINIT_AS_SLAVE
, 0x00);
9581 write_csr(dd
, DC_LCB_CFG_CNT_FOR_SKIP_STALL
, 0x110);
9582 write_csr(dd
, DC_LCB_CFG_CLK_CNTR
, 0x08);
9583 write_csr(dd
, DC_LCB_CFG_LOOPBACK
, 0x02);
9584 write_csr(dd
, DC_LCB_CFG_TX_FIFOS_RESET
, 0x00);
9588 * Perform a test read on the QSFP. Return 0 on success, -ERRNO
9591 static int test_qsfp_read(struct hfi1_pportdata
*ppd
)
9597 * Report success if not a QSFP or, if it is a QSFP, but the cable is
9600 if (ppd
->port_type
!= PORT_TYPE_QSFP
|| !qsfp_mod_present(ppd
))
9603 /* read byte 2, the status byte */
9604 ret
= one_qsfp_read(ppd
, ppd
->dd
->hfi1_id
, 2, &status
, 1);
9610 return 0; /* success */
9614 * Values for QSFP retry.
9616 * Give up after 10s (20 x 500ms). The overall timeout was empirically
9617 * arrived at from experience on a large cluster.
9619 #define MAX_QSFP_RETRIES 20
9620 #define QSFP_RETRY_WAIT 500 /* msec */
9623 * Try a QSFP read. If it fails, schedule a retry for later.
9624 * Called on first link activation after driver load.
9626 static void try_start_link(struct hfi1_pportdata
*ppd
)
9628 if (test_qsfp_read(ppd
)) {
9630 if (ppd
->qsfp_retry_count
>= MAX_QSFP_RETRIES
) {
9631 dd_dev_err(ppd
->dd
, "QSFP not responding, giving up\n");
9634 dd_dev_info(ppd
->dd
,
9635 "QSFP not responding, waiting and retrying %d\n",
9636 (int)ppd
->qsfp_retry_count
);
9637 ppd
->qsfp_retry_count
++;
9638 queue_delayed_work(ppd
->hfi1_wq
, &ppd
->start_link_work
,
9639 msecs_to_jiffies(QSFP_RETRY_WAIT
));
9642 ppd
->qsfp_retry_count
= 0;
9648 * Workqueue function to start the link after a delay.
9650 void handle_start_link(struct work_struct
*work
)
9652 struct hfi1_pportdata
*ppd
= container_of(work
, struct hfi1_pportdata
,
9653 start_link_work
.work
);
9654 try_start_link(ppd
);
9657 int bringup_serdes(struct hfi1_pportdata
*ppd
)
9659 struct hfi1_devdata
*dd
= ppd
->dd
;
9663 if (HFI1_CAP_IS_KSET(EXTENDED_PSN
))
9664 add_rcvctrl(dd
, RCV_CTRL_RCV_EXTENDED_PSN_ENABLE_SMASK
);
9666 guid
= ppd
->guids
[HFI1_PORT_GUID_INDEX
];
9669 guid
= dd
->base_guid
+ ppd
->port
- 1;
9670 ppd
->guids
[HFI1_PORT_GUID_INDEX
] = guid
;
9673 /* Set linkinit_reason on power up per OPA spec */
9674 ppd
->linkinit_reason
= OPA_LINKINIT_REASON_LINKUP
;
9676 /* one-time init of the LCB */
9680 ret
= init_loopback(dd
);
9686 if (ppd
->port_type
== PORT_TYPE_QSFP
) {
9687 set_qsfp_int_n(ppd
, 0);
9688 wait_for_qsfp_init(ppd
);
9689 set_qsfp_int_n(ppd
, 1);
9692 try_start_link(ppd
);
9696 void hfi1_quiet_serdes(struct hfi1_pportdata
*ppd
)
9698 struct hfi1_devdata
*dd
= ppd
->dd
;
9701 * Shut down the link and keep it down. First turn off that the
9702 * driver wants to allow the link to be up (driver_link_ready).
9703 * Then make sure the link is not automatically restarted
9704 * (link_enabled). Cancel any pending restart. And finally
9707 ppd
->driver_link_ready
= 0;
9708 ppd
->link_enabled
= 0;
9710 ppd
->qsfp_retry_count
= MAX_QSFP_RETRIES
; /* prevent more retries */
9711 flush_delayed_work(&ppd
->start_link_work
);
9712 cancel_delayed_work_sync(&ppd
->start_link_work
);
9714 ppd
->offline_disabled_reason
=
9715 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_SMA_DISABLED
);
9716 set_link_down_reason(ppd
, OPA_LINKDOWN_REASON_SMA_DISABLED
, 0,
9717 OPA_LINKDOWN_REASON_SMA_DISABLED
);
9718 set_link_state(ppd
, HLS_DN_OFFLINE
);
9720 /* disable the port */
9721 clear_rcvctrl(dd
, RCV_CTRL_RCV_PORT_ENABLE_SMASK
);
9724 static inline int init_cpu_counters(struct hfi1_devdata
*dd
)
9726 struct hfi1_pportdata
*ppd
;
9729 ppd
= (struct hfi1_pportdata
*)(dd
+ 1);
9730 for (i
= 0; i
< dd
->num_pports
; i
++, ppd
++) {
9731 ppd
->ibport_data
.rvp
.rc_acks
= NULL
;
9732 ppd
->ibport_data
.rvp
.rc_qacks
= NULL
;
9733 ppd
->ibport_data
.rvp
.rc_acks
= alloc_percpu(u64
);
9734 ppd
->ibport_data
.rvp
.rc_qacks
= alloc_percpu(u64
);
9735 ppd
->ibport_data
.rvp
.rc_delayed_comp
= alloc_percpu(u64
);
9736 if (!ppd
->ibport_data
.rvp
.rc_acks
||
9737 !ppd
->ibport_data
.rvp
.rc_delayed_comp
||
9738 !ppd
->ibport_data
.rvp
.rc_qacks
)
9745 static const char * const pt_names
[] = {
9751 static const char *pt_name(u32 type
)
9753 return type
>= ARRAY_SIZE(pt_names
) ? "unknown" : pt_names
[type
];
9757 * index is the index into the receive array
9759 void hfi1_put_tid(struct hfi1_devdata
*dd
, u32 index
,
9760 u32 type
, unsigned long pa
, u16 order
)
9763 void __iomem
*base
= (dd
->rcvarray_wc
? dd
->rcvarray_wc
:
9764 (dd
->kregbase
+ RCV_ARRAY
));
9766 if (!(dd
->flags
& HFI1_PRESENT
))
9769 if (type
== PT_INVALID
) {
9771 } else if (type
> PT_INVALID
) {
9773 "unexpected receive array type %u for index %u, not handled\n",
9778 hfi1_cdbg(TID
, "type %s, index 0x%x, pa 0x%lx, bsize 0x%lx",
9779 pt_name(type
), index
, pa
, (unsigned long)order
);
9781 #define RT_ADDR_SHIFT 12 /* 4KB kernel address boundary */
9782 reg
= RCV_ARRAY_RT_WRITE_ENABLE_SMASK
9783 | (u64
)order
<< RCV_ARRAY_RT_BUF_SIZE_SHIFT
9784 | ((pa
>> RT_ADDR_SHIFT
) & RCV_ARRAY_RT_ADDR_MASK
)
9785 << RCV_ARRAY_RT_ADDR_SHIFT
;
9786 writeq(reg
, base
+ (index
* 8));
9788 if (type
== PT_EAGER
)
9790 * Eager entries are written one-by-one so we have to push them
9791 * after we write the entry.
9798 void hfi1_clear_tids(struct hfi1_ctxtdata
*rcd
)
9800 struct hfi1_devdata
*dd
= rcd
->dd
;
9803 /* this could be optimized */
9804 for (i
= rcd
->eager_base
; i
< rcd
->eager_base
+
9805 rcd
->egrbufs
.alloced
; i
++)
9806 hfi1_put_tid(dd
, i
, PT_INVALID
, 0, 0);
9808 for (i
= rcd
->expected_base
;
9809 i
< rcd
->expected_base
+ rcd
->expected_count
; i
++)
9810 hfi1_put_tid(dd
, i
, PT_INVALID
, 0, 0);
9813 struct ib_header
*hfi1_get_msgheader(
9814 struct hfi1_devdata
*dd
, __le32
*rhf_addr
)
9816 u32 offset
= rhf_hdrq_offset(rhf_to_cpu(rhf_addr
));
9818 return (struct ib_header
*)
9819 (rhf_addr
- dd
->rhf_offset
+ offset
);
9822 static const char * const ib_cfg_name_strings
[] = {
9823 "HFI1_IB_CFG_LIDLMC",
9824 "HFI1_IB_CFG_LWID_DG_ENB",
9825 "HFI1_IB_CFG_LWID_ENB",
9827 "HFI1_IB_CFG_SPD_ENB",
9829 "HFI1_IB_CFG_RXPOL_ENB",
9830 "HFI1_IB_CFG_LREV_ENB",
9831 "HFI1_IB_CFG_LINKLATENCY",
9832 "HFI1_IB_CFG_HRTBT",
9833 "HFI1_IB_CFG_OP_VLS",
9834 "HFI1_IB_CFG_VL_HIGH_CAP",
9835 "HFI1_IB_CFG_VL_LOW_CAP",
9836 "HFI1_IB_CFG_OVERRUN_THRESH",
9837 "HFI1_IB_CFG_PHYERR_THRESH",
9838 "HFI1_IB_CFG_LINKDEFAULT",
9839 "HFI1_IB_CFG_PKEYS",
9841 "HFI1_IB_CFG_LSTATE",
9842 "HFI1_IB_CFG_VL_HIGH_LIMIT",
9843 "HFI1_IB_CFG_PMA_TICKS",
9847 static const char *ib_cfg_name(int which
)
9849 if (which
< 0 || which
>= ARRAY_SIZE(ib_cfg_name_strings
))
9851 return ib_cfg_name_strings
[which
];
9854 int hfi1_get_ib_cfg(struct hfi1_pportdata
*ppd
, int which
)
9856 struct hfi1_devdata
*dd
= ppd
->dd
;
9860 case HFI1_IB_CFG_LWID_ENB
: /* allowed Link-width */
9861 val
= ppd
->link_width_enabled
;
9863 case HFI1_IB_CFG_LWID
: /* currently active Link-width */
9864 val
= ppd
->link_width_active
;
9866 case HFI1_IB_CFG_SPD_ENB
: /* allowed Link speeds */
9867 val
= ppd
->link_speed_enabled
;
9869 case HFI1_IB_CFG_SPD
: /* current Link speed */
9870 val
= ppd
->link_speed_active
;
9873 case HFI1_IB_CFG_RXPOL_ENB
: /* Auto-RX-polarity enable */
9874 case HFI1_IB_CFG_LREV_ENB
: /* Auto-Lane-reversal enable */
9875 case HFI1_IB_CFG_LINKLATENCY
:
9878 case HFI1_IB_CFG_OP_VLS
:
9879 val
= ppd
->vls_operational
;
9881 case HFI1_IB_CFG_VL_HIGH_CAP
: /* VL arb high priority table size */
9882 val
= VL_ARB_HIGH_PRIO_TABLE_SIZE
;
9884 case HFI1_IB_CFG_VL_LOW_CAP
: /* VL arb low priority table size */
9885 val
= VL_ARB_LOW_PRIO_TABLE_SIZE
;
9887 case HFI1_IB_CFG_OVERRUN_THRESH
: /* IB overrun threshold */
9888 val
= ppd
->overrun_threshold
;
9890 case HFI1_IB_CFG_PHYERR_THRESH
: /* IB PHY error threshold */
9891 val
= ppd
->phy_error_threshold
;
9893 case HFI1_IB_CFG_LINKDEFAULT
: /* IB link default (sleep/poll) */
9894 val
= dd
->link_default
;
9897 case HFI1_IB_CFG_HRTBT
: /* Heartbeat off/enable/auto */
9898 case HFI1_IB_CFG_PMA_TICKS
:
9901 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL
))
9904 "%s: which %s: not implemented\n",
9906 ib_cfg_name(which
));
9914 * The largest MAD packet size.
9916 #define MAX_MAD_PACKET 2048
9919 * Return the maximum header bytes that can go on the _wire_
9920 * for this device. This count includes the ICRC which is
9921 * not part of the packet held in memory but it is appended
9923 * This is dependent on the device's receive header entry size.
9924 * HFI allows this to be set per-receive context, but the
9925 * driver presently enforces a global value.
9927 u32
lrh_max_header_bytes(struct hfi1_devdata
*dd
)
9930 * The maximum non-payload (MTU) bytes in LRH.PktLen are
9931 * the Receive Header Entry Size minus the PBC (or RHF) size
9932 * plus one DW for the ICRC appended by HW.
9934 * dd->rcd[0].rcvhdrqentsize is in DW.
9935 * We use rcd[0] as all context will have the same value. Also,
9936 * the first kernel context would have been allocated by now so
9937 * we are guaranteed a valid value.
9939 return (dd
->rcd
[0]->rcvhdrqentsize
- 2/*PBC/RHF*/ + 1/*ICRC*/) << 2;
9944 * @ppd - per port data
9946 * Set the MTU by limiting how many DWs may be sent. The SendLenCheck*
9947 * registers compare against LRH.PktLen, so use the max bytes included
9950 * This routine changes all VL values except VL15, which it maintains at
9953 static void set_send_length(struct hfi1_pportdata
*ppd
)
9955 struct hfi1_devdata
*dd
= ppd
->dd
;
9956 u32 max_hb
= lrh_max_header_bytes(dd
), dcmtu
;
9957 u32 maxvlmtu
= dd
->vld
[15].mtu
;
9958 u64 len1
= 0, len2
= (((dd
->vld
[15].mtu
+ max_hb
) >> 2)
9959 & SEND_LEN_CHECK1_LEN_VL15_MASK
) <<
9960 SEND_LEN_CHECK1_LEN_VL15_SHIFT
;
9964 for (i
= 0; i
< ppd
->vls_supported
; i
++) {
9965 if (dd
->vld
[i
].mtu
> maxvlmtu
)
9966 maxvlmtu
= dd
->vld
[i
].mtu
;
9968 len1
|= (((dd
->vld
[i
].mtu
+ max_hb
) >> 2)
9969 & SEND_LEN_CHECK0_LEN_VL0_MASK
) <<
9970 ((i
% 4) * SEND_LEN_CHECK0_LEN_VL1_SHIFT
);
9972 len2
|= (((dd
->vld
[i
].mtu
+ max_hb
) >> 2)
9973 & SEND_LEN_CHECK1_LEN_VL4_MASK
) <<
9974 ((i
% 4) * SEND_LEN_CHECK1_LEN_VL5_SHIFT
);
9976 write_csr(dd
, SEND_LEN_CHECK0
, len1
);
9977 write_csr(dd
, SEND_LEN_CHECK1
, len2
);
9978 /* adjust kernel credit return thresholds based on new MTUs */
9979 /* all kernel receive contexts have the same hdrqentsize */
9980 for (i
= 0; i
< ppd
->vls_supported
; i
++) {
9981 thres
= min(sc_percent_to_threshold(dd
->vld
[i
].sc
, 50),
9982 sc_mtu_to_threshold(dd
->vld
[i
].sc
,
9984 dd
->rcd
[0]->rcvhdrqentsize
));
9985 for (j
= 0; j
< INIT_SC_PER_VL
; j
++)
9986 sc_set_cr_threshold(
9987 pio_select_send_context_vl(dd
, j
, i
),
9990 thres
= min(sc_percent_to_threshold(dd
->vld
[15].sc
, 50),
9991 sc_mtu_to_threshold(dd
->vld
[15].sc
,
9993 dd
->rcd
[0]->rcvhdrqentsize
));
9994 sc_set_cr_threshold(dd
->vld
[15].sc
, thres
);
9996 /* Adjust maximum MTU for the port in DC */
9997 dcmtu
= maxvlmtu
== 10240 ? DCC_CFG_PORT_MTU_CAP_10240
:
9998 (ilog2(maxvlmtu
>> 8) + 1);
9999 len1
= read_csr(ppd
->dd
, DCC_CFG_PORT_CONFIG
);
10000 len1
&= ~DCC_CFG_PORT_CONFIG_MTU_CAP_SMASK
;
10001 len1
|= ((u64
)dcmtu
& DCC_CFG_PORT_CONFIG_MTU_CAP_MASK
) <<
10002 DCC_CFG_PORT_CONFIG_MTU_CAP_SHIFT
;
10003 write_csr(ppd
->dd
, DCC_CFG_PORT_CONFIG
, len1
);
10006 static void set_lidlmc(struct hfi1_pportdata
*ppd
)
10010 struct hfi1_devdata
*dd
= ppd
->dd
;
10011 u32 mask
= ~((1U << ppd
->lmc
) - 1);
10012 u64 c1
= read_csr(ppd
->dd
, DCC_CFG_PORT_CONFIG1
);
10014 c1
&= ~(DCC_CFG_PORT_CONFIG1_TARGET_DLID_SMASK
10015 | DCC_CFG_PORT_CONFIG1_DLID_MASK_SMASK
);
10016 c1
|= ((ppd
->lid
& DCC_CFG_PORT_CONFIG1_TARGET_DLID_MASK
)
10017 << DCC_CFG_PORT_CONFIG1_TARGET_DLID_SHIFT
) |
10018 ((mask
& DCC_CFG_PORT_CONFIG1_DLID_MASK_MASK
)
10019 << DCC_CFG_PORT_CONFIG1_DLID_MASK_SHIFT
);
10020 write_csr(ppd
->dd
, DCC_CFG_PORT_CONFIG1
, c1
);
10023 * Iterate over all the send contexts and set their SLID check
10025 sreg
= ((mask
& SEND_CTXT_CHECK_SLID_MASK_MASK
) <<
10026 SEND_CTXT_CHECK_SLID_MASK_SHIFT
) |
10027 (((ppd
->lid
& mask
) & SEND_CTXT_CHECK_SLID_VALUE_MASK
) <<
10028 SEND_CTXT_CHECK_SLID_VALUE_SHIFT
);
10030 for (i
= 0; i
< dd
->chip_send_contexts
; i
++) {
10031 hfi1_cdbg(LINKVERB
, "SendContext[%d].SLID_CHECK = 0x%x",
10033 write_kctxt_csr(dd
, i
, SEND_CTXT_CHECK_SLID
, sreg
);
10036 /* Now we have to do the same thing for the sdma engines */
10037 sdma_update_lmc(dd
, mask
, ppd
->lid
);
10040 static int wait_phy_linkstate(struct hfi1_devdata
*dd
, u32 state
, u32 msecs
)
10042 unsigned long timeout
;
10045 timeout
= jiffies
+ msecs_to_jiffies(msecs
);
10047 curr_state
= read_physical_state(dd
);
10048 if (curr_state
== state
)
10050 if (time_after(jiffies
, timeout
)) {
10052 "timeout waiting for phy link state 0x%x, current state is 0x%x\n",
10053 state
, curr_state
);
10056 usleep_range(1950, 2050); /* sleep 2ms-ish */
10062 static const char *state_completed_string(u32 completed
)
10064 static const char * const state_completed
[] = {
10070 if (completed
< ARRAY_SIZE(state_completed
))
10071 return state_completed
[completed
];
10076 static const char all_lanes_dead_timeout_expired
[] =
10077 "All lanes were inactive – was the interconnect media removed?";
10078 static const char tx_out_of_policy
[] =
10079 "Passing lanes on local port do not meet the local link width policy";
10080 static const char no_state_complete
[] =
10081 "State timeout occurred before link partner completed the state";
10082 static const char * const state_complete_reasons
[] = {
10083 [0x00] = "Reason unknown",
10084 [0x01] = "Link was halted by driver, refer to LinkDownReason",
10085 [0x02] = "Link partner reported failure",
10086 [0x10] = "Unable to achieve frame sync on any lane",
10088 "Unable to find a common bit rate with the link partner",
10090 "Unable to achieve frame sync on sufficient lanes to meet the local link width policy",
10092 "Unable to identify preset equalization on sufficient lanes to meet the local link width policy",
10093 [0x14] = no_state_complete
,
10095 "State timeout occurred before link partner identified equalization presets",
10097 "Link partner completed the EstablishComm state, but the passing lanes do not meet the local link width policy",
10098 [0x17] = tx_out_of_policy
,
10099 [0x20] = all_lanes_dead_timeout_expired
,
10101 "Unable to achieve acceptable BER on sufficient lanes to meet the local link width policy",
10102 [0x22] = no_state_complete
,
10104 "Link partner completed the OptimizeEq state, but the passing lanes do not meet the local link width policy",
10105 [0x24] = tx_out_of_policy
,
10106 [0x30] = all_lanes_dead_timeout_expired
,
10108 "State timeout occurred waiting for host to process received frames",
10109 [0x32] = no_state_complete
,
10111 "Link partner completed the VerifyCap state, but the passing lanes do not meet the local link width policy",
10112 [0x34] = tx_out_of_policy
,
10115 static const char *state_complete_reason_code_string(struct hfi1_pportdata
*ppd
,
10118 const char *str
= NULL
;
10120 if (code
< ARRAY_SIZE(state_complete_reasons
))
10121 str
= state_complete_reasons
[code
];
10128 /* describe the given last state complete frame */
10129 static void decode_state_complete(struct hfi1_pportdata
*ppd
, u32 frame
,
10130 const char *prefix
)
10132 struct hfi1_devdata
*dd
= ppd
->dd
;
10140 * [ 0: 0] - success
10142 * [ 7: 4] - next state timeout
10143 * [15: 8] - reason code
10146 success
= frame
& 0x1;
10147 state
= (frame
>> 1) & 0x7;
10148 reason
= (frame
>> 8) & 0xff;
10149 lanes
= (frame
>> 16) & 0xffff;
10151 dd_dev_err(dd
, "Last %s LNI state complete frame 0x%08x:\n",
10153 dd_dev_err(dd
, " last reported state state: %s (0x%x)\n",
10154 state_completed_string(state
), state
);
10155 dd_dev_err(dd
, " state successfully completed: %s\n",
10156 success
? "yes" : "no");
10157 dd_dev_err(dd
, " fail reason 0x%x: %s\n",
10158 reason
, state_complete_reason_code_string(ppd
, reason
));
10159 dd_dev_err(dd
, " passing lane mask: 0x%x", lanes
);
10163 * Read the last state complete frames and explain them. This routine
10164 * expects to be called if the link went down during link negotiation
10165 * and initialization (LNI). That is, anywhere between polling and link up.
10167 static void check_lni_states(struct hfi1_pportdata
*ppd
)
10169 u32 last_local_state
;
10170 u32 last_remote_state
;
10172 read_last_local_state(ppd
->dd
, &last_local_state
);
10173 read_last_remote_state(ppd
->dd
, &last_remote_state
);
10176 * Don't report anything if there is nothing to report. A value of
10177 * 0 means the link was taken down while polling and there was no
10178 * training in-process.
10180 if (last_local_state
== 0 && last_remote_state
== 0)
10183 decode_state_complete(ppd
, last_local_state
, "transmitted");
10184 decode_state_complete(ppd
, last_remote_state
, "received");
10187 /* wait for wait_ms for LINK_TRANSFER_ACTIVE to go to 1 */
10188 static int wait_link_transfer_active(struct hfi1_devdata
*dd
, int wait_ms
)
10191 unsigned long timeout
;
10193 /* watch LCB_STS_LINK_TRANSFER_ACTIVE */
10194 timeout
= jiffies
+ msecs_to_jiffies(wait_ms
);
10196 reg
= read_csr(dd
, DC_LCB_STS_LINK_TRANSFER_ACTIVE
);
10199 if (time_after(jiffies
, timeout
)) {
10201 "timeout waiting for LINK_TRANSFER_ACTIVE\n");
10209 /* called when the logical link state is not down as it should be */
10210 static void force_logical_link_state_down(struct hfi1_pportdata
*ppd
)
10212 struct hfi1_devdata
*dd
= ppd
->dd
;
10215 * Bring link up in LCB loopback
10217 write_csr(dd
, DC_LCB_CFG_TX_FIFOS_RESET
, 1);
10218 write_csr(dd
, DC_LCB_CFG_IGNORE_LOST_RCLK
,
10219 DC_LCB_CFG_IGNORE_LOST_RCLK_EN_SMASK
);
10221 write_csr(dd
, DC_LCB_CFG_LANE_WIDTH
, 0);
10222 write_csr(dd
, DC_LCB_CFG_REINIT_AS_SLAVE
, 0);
10223 write_csr(dd
, DC_LCB_CFG_CNT_FOR_SKIP_STALL
, 0x110);
10224 write_csr(dd
, DC_LCB_CFG_LOOPBACK
, 0x2);
10226 write_csr(dd
, DC_LCB_CFG_TX_FIFOS_RESET
, 0);
10227 (void)read_csr(dd
, DC_LCB_CFG_TX_FIFOS_RESET
);
10229 write_csr(dd
, DC_LCB_CFG_ALLOW_LINK_UP
, 1);
10230 write_csr(dd
, DC_LCB_CFG_RUN
, 1ull << DC_LCB_CFG_RUN_EN_SHIFT
);
10232 wait_link_transfer_active(dd
, 100);
10235 * Bring the link down again.
10237 write_csr(dd
, DC_LCB_CFG_TX_FIFOS_RESET
, 1);
10238 write_csr(dd
, DC_LCB_CFG_ALLOW_LINK_UP
, 0);
10239 write_csr(dd
, DC_LCB_CFG_IGNORE_LOST_RCLK
, 0);
10241 /* call again to adjust ppd->statusp, if needed */
10242 get_logical_state(ppd
);
10246 * Helper for set_link_state(). Do not call except from that routine.
10247 * Expects ppd->hls_mutex to be held.
10249 * @rem_reason value to be sent to the neighbor
10251 * LinkDownReasons only set if transition succeeds.
10253 static int goto_offline(struct hfi1_pportdata
*ppd
, u8 rem_reason
)
10255 struct hfi1_devdata
*dd
= ppd
->dd
;
10256 u32 pstate
, previous_state
;
10261 update_lcb_cache(dd
);
10263 previous_state
= ppd
->host_link_state
;
10264 ppd
->host_link_state
= HLS_GOING_OFFLINE
;
10265 pstate
= read_physical_state(dd
);
10266 if (pstate
== PLS_OFFLINE
) {
10267 do_transition
= 0; /* in right state */
10268 do_wait
= 0; /* ...no need to wait */
10269 } else if ((pstate
& 0xf0) == PLS_OFFLINE
) {
10270 do_transition
= 0; /* in an offline transient state */
10271 do_wait
= 1; /* ...wait for it to settle */
10273 do_transition
= 1; /* need to move to offline */
10274 do_wait
= 1; /* ...will need to wait */
10277 if (do_transition
) {
10278 ret
= set_physical_link_state(dd
,
10279 (rem_reason
<< 8) | PLS_OFFLINE
);
10281 if (ret
!= HCMD_SUCCESS
) {
10283 "Failed to transition to Offline link state, return %d\n",
10287 if (ppd
->offline_disabled_reason
==
10288 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE
))
10289 ppd
->offline_disabled_reason
=
10290 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_TRANSIENT
);
10294 /* it can take a while for the link to go down */
10295 ret
= wait_phy_linkstate(dd
, PLS_OFFLINE
, 10000);
10301 * Now in charge of LCB - must be after the physical state is
10302 * offline.quiet and before host_link_state is changed.
10304 set_host_lcb_access(dd
);
10305 write_csr(dd
, DC_LCB_ERR_EN
, ~0ull); /* watch LCB errors */
10307 /* make sure the logical state is also down */
10308 ret
= wait_logical_linkstate(ppd
, IB_PORT_DOWN
, 1000);
10310 force_logical_link_state_down(ppd
);
10312 ppd
->host_link_state
= HLS_LINK_COOLDOWN
; /* LCB access allowed */
10314 if (ppd
->port_type
== PORT_TYPE_QSFP
&&
10315 ppd
->qsfp_info
.limiting_active
&&
10316 qsfp_mod_present(ppd
)) {
10319 ret
= acquire_chip_resource(dd
, qsfp_resource(dd
), QSFP_WAIT
);
10321 set_qsfp_tx(ppd
, 0);
10322 release_chip_resource(dd
, qsfp_resource(dd
));
10324 /* not fatal, but should warn */
10326 "Unable to acquire lock to turn off QSFP TX\n");
10331 * The LNI has a mandatory wait time after the physical state
10332 * moves to Offline.Quiet. The wait time may be different
10333 * depending on how the link went down. The 8051 firmware
10334 * will observe the needed wait time and only move to ready
10335 * when that is completed. The largest of the quiet timeouts
10336 * is 6s, so wait that long and then at least 0.5s more for
10337 * other transitions, and another 0.5s for a buffer.
10339 ret
= wait_fm_ready(dd
, 7000);
10342 "After going offline, timed out waiting for the 8051 to become ready to accept host requests\n");
10343 /* state is really offline, so make it so */
10344 ppd
->host_link_state
= HLS_DN_OFFLINE
;
10349 * The state is now offline and the 8051 is ready to accept host
10351 * - change our state
10352 * - notify others if we were previously in a linkup state
10354 ppd
->host_link_state
= HLS_DN_OFFLINE
;
10355 if (previous_state
& HLS_UP
) {
10356 /* went down while link was up */
10357 handle_linkup_change(dd
, 0);
10358 } else if (previous_state
10359 & (HLS_DN_POLL
| HLS_VERIFY_CAP
| HLS_GOING_UP
)) {
10360 /* went down while attempting link up */
10361 check_lni_states(ppd
);
10364 /* the active link width (downgrade) is 0 on link down */
10365 ppd
->link_width_active
= 0;
10366 ppd
->link_width_downgrade_tx_active
= 0;
10367 ppd
->link_width_downgrade_rx_active
= 0;
10368 ppd
->current_egress_rate
= 0;
10372 /* return the link state name */
10373 static const char *link_state_name(u32 state
)
10376 int n
= ilog2(state
);
10377 static const char * const names
[] = {
10378 [__HLS_UP_INIT_BP
] = "INIT",
10379 [__HLS_UP_ARMED_BP
] = "ARMED",
10380 [__HLS_UP_ACTIVE_BP
] = "ACTIVE",
10381 [__HLS_DN_DOWNDEF_BP
] = "DOWNDEF",
10382 [__HLS_DN_POLL_BP
] = "POLL",
10383 [__HLS_DN_DISABLE_BP
] = "DISABLE",
10384 [__HLS_DN_OFFLINE_BP
] = "OFFLINE",
10385 [__HLS_VERIFY_CAP_BP
] = "VERIFY_CAP",
10386 [__HLS_GOING_UP_BP
] = "GOING_UP",
10387 [__HLS_GOING_OFFLINE_BP
] = "GOING_OFFLINE",
10388 [__HLS_LINK_COOLDOWN_BP
] = "LINK_COOLDOWN"
10391 name
= n
< ARRAY_SIZE(names
) ? names
[n
] : NULL
;
10392 return name
? name
: "unknown";
10395 /* return the link state reason name */
10396 static const char *link_state_reason_name(struct hfi1_pportdata
*ppd
, u32 state
)
10398 if (state
== HLS_UP_INIT
) {
10399 switch (ppd
->linkinit_reason
) {
10400 case OPA_LINKINIT_REASON_LINKUP
:
10402 case OPA_LINKINIT_REASON_FLAPPING
:
10403 return "(FLAPPING)";
10404 case OPA_LINKINIT_OUTSIDE_POLICY
:
10405 return "(OUTSIDE_POLICY)";
10406 case OPA_LINKINIT_QUARANTINED
:
10407 return "(QUARANTINED)";
10408 case OPA_LINKINIT_INSUFIC_CAPABILITY
:
10409 return "(INSUFIC_CAPABILITY)";
10418 * driver_physical_state - convert the driver's notion of a port's
10419 * state (an HLS_*) into a physical state (a {IB,OPA}_PORTPHYSSTATE_*).
10420 * Return -1 (converted to a u32) to indicate error.
10422 u32
driver_physical_state(struct hfi1_pportdata
*ppd
)
10424 switch (ppd
->host_link_state
) {
10427 case HLS_UP_ACTIVE
:
10428 return IB_PORTPHYSSTATE_LINKUP
;
10430 return IB_PORTPHYSSTATE_POLLING
;
10431 case HLS_DN_DISABLE
:
10432 return IB_PORTPHYSSTATE_DISABLED
;
10433 case HLS_DN_OFFLINE
:
10434 return OPA_PORTPHYSSTATE_OFFLINE
;
10435 case HLS_VERIFY_CAP
:
10436 return IB_PORTPHYSSTATE_POLLING
;
10438 return IB_PORTPHYSSTATE_POLLING
;
10439 case HLS_GOING_OFFLINE
:
10440 return OPA_PORTPHYSSTATE_OFFLINE
;
10441 case HLS_LINK_COOLDOWN
:
10442 return OPA_PORTPHYSSTATE_OFFLINE
;
10443 case HLS_DN_DOWNDEF
:
10445 dd_dev_err(ppd
->dd
, "invalid host_link_state 0x%x\n",
10446 ppd
->host_link_state
);
10452 * driver_logical_state - convert the driver's notion of a port's
10453 * state (an HLS_*) into a logical state (a IB_PORT_*). Return -1
10454 * (converted to a u32) to indicate error.
10456 u32
driver_logical_state(struct hfi1_pportdata
*ppd
)
10458 if (ppd
->host_link_state
&& (ppd
->host_link_state
& HLS_DOWN
))
10459 return IB_PORT_DOWN
;
10461 switch (ppd
->host_link_state
& HLS_UP
) {
10463 return IB_PORT_INIT
;
10465 return IB_PORT_ARMED
;
10466 case HLS_UP_ACTIVE
:
10467 return IB_PORT_ACTIVE
;
10469 dd_dev_err(ppd
->dd
, "invalid host_link_state 0x%x\n",
10470 ppd
->host_link_state
);
10475 void set_link_down_reason(struct hfi1_pportdata
*ppd
, u8 lcl_reason
,
10476 u8 neigh_reason
, u8 rem_reason
)
10478 if (ppd
->local_link_down_reason
.latest
== 0 &&
10479 ppd
->neigh_link_down_reason
.latest
== 0) {
10480 ppd
->local_link_down_reason
.latest
= lcl_reason
;
10481 ppd
->neigh_link_down_reason
.latest
= neigh_reason
;
10482 ppd
->remote_link_down_reason
= rem_reason
;
10487 * Change the physical and/or logical link state.
10489 * Do not call this routine while inside an interrupt. It contains
10490 * calls to routines that can take multiple seconds to finish.
10492 * Returns 0 on success, -errno on failure.
10494 int set_link_state(struct hfi1_pportdata
*ppd
, u32 state
)
10496 struct hfi1_devdata
*dd
= ppd
->dd
;
10497 struct ib_event event
= {.device
= NULL
};
10499 int orig_new_state
, poll_bounce
;
10501 mutex_lock(&ppd
->hls_lock
);
10503 orig_new_state
= state
;
10504 if (state
== HLS_DN_DOWNDEF
)
10505 state
= dd
->link_default
;
10507 /* interpret poll -> poll as a link bounce */
10508 poll_bounce
= ppd
->host_link_state
== HLS_DN_POLL
&&
10509 state
== HLS_DN_POLL
;
10511 dd_dev_info(dd
, "%s: current %s, new %s %s%s\n", __func__
,
10512 link_state_name(ppd
->host_link_state
),
10513 link_state_name(orig_new_state
),
10514 poll_bounce
? "(bounce) " : "",
10515 link_state_reason_name(ppd
, state
));
10518 * If we're going to a (HLS_*) link state that implies the logical
10519 * link state is neither of (IB_PORT_ARMED, IB_PORT_ACTIVE), then
10520 * reset is_sm_config_started to 0.
10522 if (!(state
& (HLS_UP_ARMED
| HLS_UP_ACTIVE
)))
10523 ppd
->is_sm_config_started
= 0;
10526 * Do nothing if the states match. Let a poll to poll link bounce
10529 if (ppd
->host_link_state
== state
&& !poll_bounce
)
10534 if (ppd
->host_link_state
== HLS_DN_POLL
&&
10535 (quick_linkup
|| dd
->icode
== ICODE_FUNCTIONAL_SIMULATOR
)) {
10537 * Quick link up jumps from polling to here.
10539 * Whether in normal or loopback mode, the
10540 * simulator jumps from polling to link up.
10541 * Accept that here.
10544 } else if (ppd
->host_link_state
!= HLS_GOING_UP
) {
10548 ret
= wait_logical_linkstate(ppd
, IB_PORT_INIT
, 1000);
10551 "%s: logical state did not change to INIT\n",
10554 /* clear old transient LINKINIT_REASON code */
10555 if (ppd
->linkinit_reason
>= OPA_LINKINIT_REASON_CLEAR
)
10556 ppd
->linkinit_reason
=
10557 OPA_LINKINIT_REASON_LINKUP
;
10559 /* enable the port */
10560 add_rcvctrl(dd
, RCV_CTRL_RCV_PORT_ENABLE_SMASK
);
10562 handle_linkup_change(dd
, 1);
10563 ppd
->host_link_state
= HLS_UP_INIT
;
10567 if (ppd
->host_link_state
!= HLS_UP_INIT
)
10570 ppd
->host_link_state
= HLS_UP_ARMED
;
10571 set_logical_state(dd
, LSTATE_ARMED
);
10572 ret
= wait_logical_linkstate(ppd
, IB_PORT_ARMED
, 1000);
10574 /* logical state didn't change, stay at init */
10575 ppd
->host_link_state
= HLS_UP_INIT
;
10577 "%s: logical state did not change to ARMED\n",
10581 * The simulator does not currently implement SMA messages,
10582 * so neighbor_normal is not set. Set it here when we first
10585 if (dd
->icode
== ICODE_FUNCTIONAL_SIMULATOR
)
10586 ppd
->neighbor_normal
= 1;
10588 case HLS_UP_ACTIVE
:
10589 if (ppd
->host_link_state
!= HLS_UP_ARMED
)
10592 ppd
->host_link_state
= HLS_UP_ACTIVE
;
10593 set_logical_state(dd
, LSTATE_ACTIVE
);
10594 ret
= wait_logical_linkstate(ppd
, IB_PORT_ACTIVE
, 1000);
10596 /* logical state didn't change, stay at armed */
10597 ppd
->host_link_state
= HLS_UP_ARMED
;
10599 "%s: logical state did not change to ACTIVE\n",
10602 /* tell all engines to go running */
10603 sdma_all_running(dd
);
10605 /* Signal the IB layer that the port has went active */
10606 event
.device
= &dd
->verbs_dev
.rdi
.ibdev
;
10607 event
.element
.port_num
= ppd
->port
;
10608 event
.event
= IB_EVENT_PORT_ACTIVE
;
10612 if ((ppd
->host_link_state
== HLS_DN_DISABLE
||
10613 ppd
->host_link_state
== HLS_DN_OFFLINE
) &&
10616 /* Hand LED control to the DC */
10617 write_csr(dd
, DCC_CFG_LED_CNTRL
, 0);
10619 if (ppd
->host_link_state
!= HLS_DN_OFFLINE
) {
10620 u8 tmp
= ppd
->link_enabled
;
10622 ret
= goto_offline(ppd
, ppd
->remote_link_down_reason
);
10624 ppd
->link_enabled
= tmp
;
10627 ppd
->remote_link_down_reason
= 0;
10629 if (ppd
->driver_link_ready
)
10630 ppd
->link_enabled
= 1;
10633 set_all_slowpath(ppd
->dd
);
10634 ret
= set_local_link_attributes(ppd
);
10638 ppd
->port_error_action
= 0;
10639 ppd
->host_link_state
= HLS_DN_POLL
;
10641 if (quick_linkup
) {
10642 /* quick linkup does not go into polling */
10643 ret
= do_quick_linkup(dd
);
10645 ret1
= set_physical_link_state(dd
, PLS_POLLING
);
10646 if (ret1
!= HCMD_SUCCESS
) {
10648 "Failed to transition to Polling link state, return 0x%x\n",
10653 ppd
->offline_disabled_reason
=
10654 HFI1_ODR_MASK(OPA_LINKDOWN_REASON_NONE
);
10656 * If an error occurred above, go back to offline. The
10657 * caller may reschedule another attempt.
10660 goto_offline(ppd
, 0);
10662 case HLS_DN_DISABLE
:
10663 /* link is disabled */
10664 ppd
->link_enabled
= 0;
10666 /* allow any state to transition to disabled */
10668 /* must transition to offline first */
10669 if (ppd
->host_link_state
!= HLS_DN_OFFLINE
) {
10670 ret
= goto_offline(ppd
, ppd
->remote_link_down_reason
);
10673 ppd
->remote_link_down_reason
= 0;
10676 if (!dd
->dc_shutdown
) {
10677 ret1
= set_physical_link_state(dd
, PLS_DISABLED
);
10678 if (ret1
!= HCMD_SUCCESS
) {
10680 "Failed to transition to Disabled link state, return 0x%x\n",
10687 ppd
->host_link_state
= HLS_DN_DISABLE
;
10689 case HLS_DN_OFFLINE
:
10690 if (ppd
->host_link_state
== HLS_DN_DISABLE
)
10693 /* allow any state to transition to offline */
10694 ret
= goto_offline(ppd
, ppd
->remote_link_down_reason
);
10696 ppd
->remote_link_down_reason
= 0;
10698 case HLS_VERIFY_CAP
:
10699 if (ppd
->host_link_state
!= HLS_DN_POLL
)
10701 ppd
->host_link_state
= HLS_VERIFY_CAP
;
10704 if (ppd
->host_link_state
!= HLS_VERIFY_CAP
)
10707 ret1
= set_physical_link_state(dd
, PLS_LINKUP
);
10708 if (ret1
!= HCMD_SUCCESS
) {
10710 "Failed to transition to link up state, return 0x%x\n",
10715 ppd
->host_link_state
= HLS_GOING_UP
;
10718 case HLS_GOING_OFFLINE
: /* transient within goto_offline() */
10719 case HLS_LINK_COOLDOWN
: /* transient within goto_offline() */
10721 dd_dev_info(dd
, "%s: state 0x%x: not supported\n",
10730 dd_dev_err(dd
, "%s: unexpected state transition from %s to %s\n",
10731 __func__
, link_state_name(ppd
->host_link_state
),
10732 link_state_name(state
));
10736 mutex_unlock(&ppd
->hls_lock
);
10739 ib_dispatch_event(&event
);
10744 int hfi1_set_ib_cfg(struct hfi1_pportdata
*ppd
, int which
, u32 val
)
10750 case HFI1_IB_CFG_LIDLMC
:
10753 case HFI1_IB_CFG_VL_HIGH_LIMIT
:
10755 * The VL Arbitrator high limit is sent in units of 4k
10756 * bytes, while HFI stores it in units of 64 bytes.
10759 reg
= ((u64
)val
& SEND_HIGH_PRIORITY_LIMIT_LIMIT_MASK
)
10760 << SEND_HIGH_PRIORITY_LIMIT_LIMIT_SHIFT
;
10761 write_csr(ppd
->dd
, SEND_HIGH_PRIORITY_LIMIT
, reg
);
10763 case HFI1_IB_CFG_LINKDEFAULT
: /* IB link default (sleep/poll) */
10764 /* HFI only supports POLL as the default link down state */
10765 if (val
!= HLS_DN_POLL
)
10768 case HFI1_IB_CFG_OP_VLS
:
10769 if (ppd
->vls_operational
!= val
) {
10770 ppd
->vls_operational
= val
;
10776 * For link width, link width downgrade, and speed enable, always AND
10777 * the setting with what is actually supported. This has two benefits.
10778 * First, enabled can't have unsupported values, no matter what the
10779 * SM or FM might want. Second, the ALL_SUPPORTED wildcards that mean
10780 * "fill in with your supported value" have all the bits in the
10781 * field set, so simply ANDing with supported has the desired result.
10783 case HFI1_IB_CFG_LWID_ENB
: /* set allowed Link-width */
10784 ppd
->link_width_enabled
= val
& ppd
->link_width_supported
;
10786 case HFI1_IB_CFG_LWID_DG_ENB
: /* set allowed link width downgrade */
10787 ppd
->link_width_downgrade_enabled
=
10788 val
& ppd
->link_width_downgrade_supported
;
10790 case HFI1_IB_CFG_SPD_ENB
: /* allowed Link speeds */
10791 ppd
->link_speed_enabled
= val
& ppd
->link_speed_supported
;
10793 case HFI1_IB_CFG_OVERRUN_THRESH
: /* IB overrun threshold */
10795 * HFI does not follow IB specs, save this value
10796 * so we can report it, if asked.
10798 ppd
->overrun_threshold
= val
;
10800 case HFI1_IB_CFG_PHYERR_THRESH
: /* IB PHY error threshold */
10802 * HFI does not follow IB specs, save this value
10803 * so we can report it, if asked.
10805 ppd
->phy_error_threshold
= val
;
10808 case HFI1_IB_CFG_MTU
:
10809 set_send_length(ppd
);
10812 case HFI1_IB_CFG_PKEYS
:
10813 if (HFI1_CAP_IS_KSET(PKEY_CHECK
))
10814 set_partition_keys(ppd
);
10818 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL
))
10819 dd_dev_info(ppd
->dd
,
10820 "%s: which %s, val 0x%x: not implemented\n",
10821 __func__
, ib_cfg_name(which
), val
);
10827 /* begin functions related to vl arbitration table caching */
10828 static void init_vl_arb_caches(struct hfi1_pportdata
*ppd
)
10832 BUILD_BUG_ON(VL_ARB_TABLE_SIZE
!=
10833 VL_ARB_LOW_PRIO_TABLE_SIZE
);
10834 BUILD_BUG_ON(VL_ARB_TABLE_SIZE
!=
10835 VL_ARB_HIGH_PRIO_TABLE_SIZE
);
10838 * Note that we always return values directly from the
10839 * 'vl_arb_cache' (and do no CSR reads) in response to a
10840 * 'Get(VLArbTable)'. This is obviously correct after a
10841 * 'Set(VLArbTable)', since the cache will then be up to
10842 * date. But it's also correct prior to any 'Set(VLArbTable)'
10843 * since then both the cache, and the relevant h/w registers
10847 for (i
= 0; i
< MAX_PRIO_TABLE
; i
++)
10848 spin_lock_init(&ppd
->vl_arb_cache
[i
].lock
);
10852 * vl_arb_lock_cache
10854 * All other vl_arb_* functions should be called only after locking
10857 static inline struct vl_arb_cache
*
10858 vl_arb_lock_cache(struct hfi1_pportdata
*ppd
, int idx
)
10860 if (idx
!= LO_PRIO_TABLE
&& idx
!= HI_PRIO_TABLE
)
10862 spin_lock(&ppd
->vl_arb_cache
[idx
].lock
);
10863 return &ppd
->vl_arb_cache
[idx
];
10866 static inline void vl_arb_unlock_cache(struct hfi1_pportdata
*ppd
, int idx
)
10868 spin_unlock(&ppd
->vl_arb_cache
[idx
].lock
);
10871 static void vl_arb_get_cache(struct vl_arb_cache
*cache
,
10872 struct ib_vl_weight_elem
*vl
)
10874 memcpy(vl
, cache
->table
, VL_ARB_TABLE_SIZE
* sizeof(*vl
));
10877 static void vl_arb_set_cache(struct vl_arb_cache
*cache
,
10878 struct ib_vl_weight_elem
*vl
)
10880 memcpy(cache
->table
, vl
, VL_ARB_TABLE_SIZE
* sizeof(*vl
));
10883 static int vl_arb_match_cache(struct vl_arb_cache
*cache
,
10884 struct ib_vl_weight_elem
*vl
)
10886 return !memcmp(cache
->table
, vl
, VL_ARB_TABLE_SIZE
* sizeof(*vl
));
10889 /* end functions related to vl arbitration table caching */
10891 static int set_vl_weights(struct hfi1_pportdata
*ppd
, u32 target
,
10892 u32 size
, struct ib_vl_weight_elem
*vl
)
10894 struct hfi1_devdata
*dd
= ppd
->dd
;
10896 unsigned int i
, is_up
= 0;
10897 int drain
, ret
= 0;
10899 mutex_lock(&ppd
->hls_lock
);
10901 if (ppd
->host_link_state
& HLS_UP
)
10904 drain
= !is_ax(dd
) && is_up
;
10908 * Before adjusting VL arbitration weights, empty per-VL
10909 * FIFOs, otherwise a packet whose VL weight is being
10910 * set to 0 could get stuck in a FIFO with no chance to
10913 ret
= stop_drain_data_vls(dd
);
10918 "%s: cannot stop/drain VLs - refusing to change VL arbitration weights\n",
10923 for (i
= 0; i
< size
; i
++, vl
++) {
10925 * NOTE: The low priority shift and mask are used here, but
10926 * they are the same for both the low and high registers.
10928 reg
= (((u64
)vl
->vl
& SEND_LOW_PRIORITY_LIST_VL_MASK
)
10929 << SEND_LOW_PRIORITY_LIST_VL_SHIFT
)
10930 | (((u64
)vl
->weight
10931 & SEND_LOW_PRIORITY_LIST_WEIGHT_MASK
)
10932 << SEND_LOW_PRIORITY_LIST_WEIGHT_SHIFT
);
10933 write_csr(dd
, target
+ (i
* 8), reg
);
10935 pio_send_control(dd
, PSC_GLOBAL_VLARB_ENABLE
);
10938 open_fill_data_vls(dd
); /* reopen all VLs */
10941 mutex_unlock(&ppd
->hls_lock
);
10947 * Read one credit merge VL register.
10949 static void read_one_cm_vl(struct hfi1_devdata
*dd
, u32 csr
,
10950 struct vl_limit
*vll
)
10952 u64 reg
= read_csr(dd
, csr
);
10954 vll
->dedicated
= cpu_to_be16(
10955 (reg
>> SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SHIFT
)
10956 & SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_MASK
);
10957 vll
->shared
= cpu_to_be16(
10958 (reg
>> SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SHIFT
)
10959 & SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_MASK
);
10963 * Read the current credit merge limits.
10965 static int get_buffer_control(struct hfi1_devdata
*dd
,
10966 struct buffer_control
*bc
, u16
*overall_limit
)
10971 /* not all entries are filled in */
10972 memset(bc
, 0, sizeof(*bc
));
10974 /* OPA and HFI have a 1-1 mapping */
10975 for (i
= 0; i
< TXE_NUM_DATA_VL
; i
++)
10976 read_one_cm_vl(dd
, SEND_CM_CREDIT_VL
+ (8 * i
), &bc
->vl
[i
]);
10978 /* NOTE: assumes that VL* and VL15 CSRs are bit-wise identical */
10979 read_one_cm_vl(dd
, SEND_CM_CREDIT_VL15
, &bc
->vl
[15]);
10981 reg
= read_csr(dd
, SEND_CM_GLOBAL_CREDIT
);
10982 bc
->overall_shared_limit
= cpu_to_be16(
10983 (reg
>> SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SHIFT
)
10984 & SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_MASK
);
10986 *overall_limit
= (reg
10987 >> SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT
)
10988 & SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_MASK
;
10989 return sizeof(struct buffer_control
);
10992 static int get_sc2vlnt(struct hfi1_devdata
*dd
, struct sc2vlnt
*dp
)
10997 /* each register contains 16 SC->VLnt mappings, 4 bits each */
10998 reg
= read_csr(dd
, DCC_CFG_SC_VL_TABLE_15_0
);
10999 for (i
= 0; i
< sizeof(u64
); i
++) {
11000 u8 byte
= *(((u8
*)®
) + i
);
11002 dp
->vlnt
[2 * i
] = byte
& 0xf;
11003 dp
->vlnt
[(2 * i
) + 1] = (byte
& 0xf0) >> 4;
11006 reg
= read_csr(dd
, DCC_CFG_SC_VL_TABLE_31_16
);
11007 for (i
= 0; i
< sizeof(u64
); i
++) {
11008 u8 byte
= *(((u8
*)®
) + i
);
11010 dp
->vlnt
[16 + (2 * i
)] = byte
& 0xf;
11011 dp
->vlnt
[16 + (2 * i
) + 1] = (byte
& 0xf0) >> 4;
11013 return sizeof(struct sc2vlnt
);
11016 static void get_vlarb_preempt(struct hfi1_devdata
*dd
, u32 nelems
,
11017 struct ib_vl_weight_elem
*vl
)
11021 for (i
= 0; i
< nelems
; i
++, vl
++) {
11027 static void set_sc2vlnt(struct hfi1_devdata
*dd
, struct sc2vlnt
*dp
)
11029 write_csr(dd
, DCC_CFG_SC_VL_TABLE_15_0
,
11031 0, dp
->vlnt
[0] & 0xf,
11032 1, dp
->vlnt
[1] & 0xf,
11033 2, dp
->vlnt
[2] & 0xf,
11034 3, dp
->vlnt
[3] & 0xf,
11035 4, dp
->vlnt
[4] & 0xf,
11036 5, dp
->vlnt
[5] & 0xf,
11037 6, dp
->vlnt
[6] & 0xf,
11038 7, dp
->vlnt
[7] & 0xf,
11039 8, dp
->vlnt
[8] & 0xf,
11040 9, dp
->vlnt
[9] & 0xf,
11041 10, dp
->vlnt
[10] & 0xf,
11042 11, dp
->vlnt
[11] & 0xf,
11043 12, dp
->vlnt
[12] & 0xf,
11044 13, dp
->vlnt
[13] & 0xf,
11045 14, dp
->vlnt
[14] & 0xf,
11046 15, dp
->vlnt
[15] & 0xf));
11047 write_csr(dd
, DCC_CFG_SC_VL_TABLE_31_16
,
11048 DC_SC_VL_VAL(31_16
,
11049 16, dp
->vlnt
[16] & 0xf,
11050 17, dp
->vlnt
[17] & 0xf,
11051 18, dp
->vlnt
[18] & 0xf,
11052 19, dp
->vlnt
[19] & 0xf,
11053 20, dp
->vlnt
[20] & 0xf,
11054 21, dp
->vlnt
[21] & 0xf,
11055 22, dp
->vlnt
[22] & 0xf,
11056 23, dp
->vlnt
[23] & 0xf,
11057 24, dp
->vlnt
[24] & 0xf,
11058 25, dp
->vlnt
[25] & 0xf,
11059 26, dp
->vlnt
[26] & 0xf,
11060 27, dp
->vlnt
[27] & 0xf,
11061 28, dp
->vlnt
[28] & 0xf,
11062 29, dp
->vlnt
[29] & 0xf,
11063 30, dp
->vlnt
[30] & 0xf,
11064 31, dp
->vlnt
[31] & 0xf));
11067 static void nonzero_msg(struct hfi1_devdata
*dd
, int idx
, const char *what
,
11071 dd_dev_info(dd
, "Invalid %s limit %d on VL %d, ignoring\n",
11072 what
, (int)limit
, idx
);
11075 /* change only the shared limit portion of SendCmGLobalCredit */
11076 static void set_global_shared(struct hfi1_devdata
*dd
, u16 limit
)
11080 reg
= read_csr(dd
, SEND_CM_GLOBAL_CREDIT
);
11081 reg
&= ~SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SMASK
;
11082 reg
|= (u64
)limit
<< SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SHIFT
;
11083 write_csr(dd
, SEND_CM_GLOBAL_CREDIT
, reg
);
11086 /* change only the total credit limit portion of SendCmGLobalCredit */
11087 static void set_global_limit(struct hfi1_devdata
*dd
, u16 limit
)
11091 reg
= read_csr(dd
, SEND_CM_GLOBAL_CREDIT
);
11092 reg
&= ~SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SMASK
;
11093 reg
|= (u64
)limit
<< SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT
;
11094 write_csr(dd
, SEND_CM_GLOBAL_CREDIT
, reg
);
11097 /* set the given per-VL shared limit */
11098 static void set_vl_shared(struct hfi1_devdata
*dd
, int vl
, u16 limit
)
11103 if (vl
< TXE_NUM_DATA_VL
)
11104 addr
= SEND_CM_CREDIT_VL
+ (8 * vl
);
11106 addr
= SEND_CM_CREDIT_VL15
;
11108 reg
= read_csr(dd
, addr
);
11109 reg
&= ~SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SMASK
;
11110 reg
|= (u64
)limit
<< SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SHIFT
;
11111 write_csr(dd
, addr
, reg
);
11114 /* set the given per-VL dedicated limit */
11115 static void set_vl_dedicated(struct hfi1_devdata
*dd
, int vl
, u16 limit
)
11120 if (vl
< TXE_NUM_DATA_VL
)
11121 addr
= SEND_CM_CREDIT_VL
+ (8 * vl
);
11123 addr
= SEND_CM_CREDIT_VL15
;
11125 reg
= read_csr(dd
, addr
);
11126 reg
&= ~SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SMASK
;
11127 reg
|= (u64
)limit
<< SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SHIFT
;
11128 write_csr(dd
, addr
, reg
);
11131 /* spin until the given per-VL status mask bits clear */
11132 static void wait_for_vl_status_clear(struct hfi1_devdata
*dd
, u64 mask
,
11135 unsigned long timeout
;
11138 timeout
= jiffies
+ msecs_to_jiffies(VL_STATUS_CLEAR_TIMEOUT
);
11140 reg
= read_csr(dd
, SEND_CM_CREDIT_USED_STATUS
) & mask
;
11143 return; /* success */
11144 if (time_after(jiffies
, timeout
))
11145 break; /* timed out */
11150 "%s credit change status not clearing after %dms, mask 0x%llx, not clear 0x%llx\n",
11151 which
, VL_STATUS_CLEAR_TIMEOUT
, mask
, reg
);
11153 * If this occurs, it is likely there was a credit loss on the link.
11154 * The only recovery from that is a link bounce.
11157 "Continuing anyway. A credit loss may occur. Suggest a link bounce\n");
11161 * The number of credits on the VLs may be changed while everything
11162 * is "live", but the following algorithm must be followed due to
11163 * how the hardware is actually implemented. In particular,
11164 * Return_Credit_Status[] is the only correct status check.
11166 * if (reducing Global_Shared_Credit_Limit or any shared limit changing)
11167 * set Global_Shared_Credit_Limit = 0
11169 * mask0 = all VLs that are changing either dedicated or shared limits
11170 * set Shared_Limit[mask0] = 0
11171 * spin until Return_Credit_Status[use_all_vl ? all VL : mask0] == 0
11172 * if (changing any dedicated limit)
11173 * mask1 = all VLs that are lowering dedicated limits
11174 * lower Dedicated_Limit[mask1]
11175 * spin until Return_Credit_Status[mask1] == 0
11176 * raise Dedicated_Limits
11177 * raise Shared_Limits
11178 * raise Global_Shared_Credit_Limit
11180 * lower = if the new limit is lower, set the limit to the new value
11181 * raise = if the new limit is higher than the current value (may be changed
11182 * earlier in the algorithm), set the new limit to the new value
11184 int set_buffer_control(struct hfi1_pportdata
*ppd
,
11185 struct buffer_control
*new_bc
)
11187 struct hfi1_devdata
*dd
= ppd
->dd
;
11188 u64 changing_mask
, ld_mask
, stat_mask
;
11190 int i
, use_all_mask
;
11191 int this_shared_changing
;
11192 int vl_count
= 0, ret
;
11194 * A0: add the variable any_shared_limit_changing below and in the
11195 * algorithm above. If removing A0 support, it can be removed.
11197 int any_shared_limit_changing
;
11198 struct buffer_control cur_bc
;
11199 u8 changing
[OPA_MAX_VLS
];
11200 u8 lowering_dedicated
[OPA_MAX_VLS
];
11203 const u64 all_mask
=
11204 SEND_CM_CREDIT_USED_STATUS_VL0_RETURN_CREDIT_STATUS_SMASK
11205 | SEND_CM_CREDIT_USED_STATUS_VL1_RETURN_CREDIT_STATUS_SMASK
11206 | SEND_CM_CREDIT_USED_STATUS_VL2_RETURN_CREDIT_STATUS_SMASK
11207 | SEND_CM_CREDIT_USED_STATUS_VL3_RETURN_CREDIT_STATUS_SMASK
11208 | SEND_CM_CREDIT_USED_STATUS_VL4_RETURN_CREDIT_STATUS_SMASK
11209 | SEND_CM_CREDIT_USED_STATUS_VL5_RETURN_CREDIT_STATUS_SMASK
11210 | SEND_CM_CREDIT_USED_STATUS_VL6_RETURN_CREDIT_STATUS_SMASK
11211 | SEND_CM_CREDIT_USED_STATUS_VL7_RETURN_CREDIT_STATUS_SMASK
11212 | SEND_CM_CREDIT_USED_STATUS_VL15_RETURN_CREDIT_STATUS_SMASK
;
11214 #define valid_vl(idx) ((idx) < TXE_NUM_DATA_VL || (idx) == 15)
11215 #define NUM_USABLE_VLS 16 /* look at VL15 and less */
11217 /* find the new total credits, do sanity check on unused VLs */
11218 for (i
= 0; i
< OPA_MAX_VLS
; i
++) {
11220 new_total
+= be16_to_cpu(new_bc
->vl
[i
].dedicated
);
11223 nonzero_msg(dd
, i
, "dedicated",
11224 be16_to_cpu(new_bc
->vl
[i
].dedicated
));
11225 nonzero_msg(dd
, i
, "shared",
11226 be16_to_cpu(new_bc
->vl
[i
].shared
));
11227 new_bc
->vl
[i
].dedicated
= 0;
11228 new_bc
->vl
[i
].shared
= 0;
11230 new_total
+= be16_to_cpu(new_bc
->overall_shared_limit
);
11232 /* fetch the current values */
11233 get_buffer_control(dd
, &cur_bc
, &cur_total
);
11236 * Create the masks we will use.
11238 memset(changing
, 0, sizeof(changing
));
11239 memset(lowering_dedicated
, 0, sizeof(lowering_dedicated
));
11241 * NOTE: Assumes that the individual VL bits are adjacent and in
11245 SEND_CM_CREDIT_USED_STATUS_VL0_RETURN_CREDIT_STATUS_SMASK
;
11249 any_shared_limit_changing
= 0;
11250 for (i
= 0; i
< NUM_USABLE_VLS
; i
++, stat_mask
<<= 1) {
11253 this_shared_changing
= new_bc
->vl
[i
].shared
11254 != cur_bc
.vl
[i
].shared
;
11255 if (this_shared_changing
)
11256 any_shared_limit_changing
= 1;
11257 if (new_bc
->vl
[i
].dedicated
!= cur_bc
.vl
[i
].dedicated
||
11258 this_shared_changing
) {
11260 changing_mask
|= stat_mask
;
11263 if (be16_to_cpu(new_bc
->vl
[i
].dedicated
) <
11264 be16_to_cpu(cur_bc
.vl
[i
].dedicated
)) {
11265 lowering_dedicated
[i
] = 1;
11266 ld_mask
|= stat_mask
;
11270 /* bracket the credit change with a total adjustment */
11271 if (new_total
> cur_total
)
11272 set_global_limit(dd
, new_total
);
11275 * Start the credit change algorithm.
11278 if ((be16_to_cpu(new_bc
->overall_shared_limit
) <
11279 be16_to_cpu(cur_bc
.overall_shared_limit
)) ||
11280 (is_ax(dd
) && any_shared_limit_changing
)) {
11281 set_global_shared(dd
, 0);
11282 cur_bc
.overall_shared_limit
= 0;
11286 for (i
= 0; i
< NUM_USABLE_VLS
; i
++) {
11291 set_vl_shared(dd
, i
, 0);
11292 cur_bc
.vl
[i
].shared
= 0;
11296 wait_for_vl_status_clear(dd
, use_all_mask
? all_mask
: changing_mask
,
11299 if (change_count
> 0) {
11300 for (i
= 0; i
< NUM_USABLE_VLS
; i
++) {
11304 if (lowering_dedicated
[i
]) {
11305 set_vl_dedicated(dd
, i
,
11306 be16_to_cpu(new_bc
->
11308 cur_bc
.vl
[i
].dedicated
=
11309 new_bc
->vl
[i
].dedicated
;
11313 wait_for_vl_status_clear(dd
, ld_mask
, "dedicated");
11315 /* now raise all dedicated that are going up */
11316 for (i
= 0; i
< NUM_USABLE_VLS
; i
++) {
11320 if (be16_to_cpu(new_bc
->vl
[i
].dedicated
) >
11321 be16_to_cpu(cur_bc
.vl
[i
].dedicated
))
11322 set_vl_dedicated(dd
, i
,
11323 be16_to_cpu(new_bc
->
11328 /* next raise all shared that are going up */
11329 for (i
= 0; i
< NUM_USABLE_VLS
; i
++) {
11333 if (be16_to_cpu(new_bc
->vl
[i
].shared
) >
11334 be16_to_cpu(cur_bc
.vl
[i
].shared
))
11335 set_vl_shared(dd
, i
, be16_to_cpu(new_bc
->vl
[i
].shared
));
11338 /* finally raise the global shared */
11339 if (be16_to_cpu(new_bc
->overall_shared_limit
) >
11340 be16_to_cpu(cur_bc
.overall_shared_limit
))
11341 set_global_shared(dd
,
11342 be16_to_cpu(new_bc
->overall_shared_limit
));
11344 /* bracket the credit change with a total adjustment */
11345 if (new_total
< cur_total
)
11346 set_global_limit(dd
, new_total
);
11349 * Determine the actual number of operational VLS using the number of
11350 * dedicated and shared credits for each VL.
11352 if (change_count
> 0) {
11353 for (i
= 0; i
< TXE_NUM_DATA_VL
; i
++)
11354 if (be16_to_cpu(new_bc
->vl
[i
].dedicated
) > 0 ||
11355 be16_to_cpu(new_bc
->vl
[i
].shared
) > 0)
11357 ppd
->actual_vls_operational
= vl_count
;
11358 ret
= sdma_map_init(dd
, ppd
->port
- 1, vl_count
?
11359 ppd
->actual_vls_operational
:
11360 ppd
->vls_operational
,
11363 ret
= pio_map_init(dd
, ppd
->port
- 1, vl_count
?
11364 ppd
->actual_vls_operational
:
11365 ppd
->vls_operational
, NULL
);
11373 * Read the given fabric manager table. Return the size of the
11374 * table (in bytes) on success, and a negative error code on
11377 int fm_get_table(struct hfi1_pportdata
*ppd
, int which
, void *t
)
11381 struct vl_arb_cache
*vlc
;
11384 case FM_TBL_VL_HIGH_ARB
:
11387 * OPA specifies 128 elements (of 2 bytes each), though
11388 * HFI supports only 16 elements in h/w.
11390 vlc
= vl_arb_lock_cache(ppd
, HI_PRIO_TABLE
);
11391 vl_arb_get_cache(vlc
, t
);
11392 vl_arb_unlock_cache(ppd
, HI_PRIO_TABLE
);
11394 case FM_TBL_VL_LOW_ARB
:
11397 * OPA specifies 128 elements (of 2 bytes each), though
11398 * HFI supports only 16 elements in h/w.
11400 vlc
= vl_arb_lock_cache(ppd
, LO_PRIO_TABLE
);
11401 vl_arb_get_cache(vlc
, t
);
11402 vl_arb_unlock_cache(ppd
, LO_PRIO_TABLE
);
11404 case FM_TBL_BUFFER_CONTROL
:
11405 size
= get_buffer_control(ppd
->dd
, t
, NULL
);
11407 case FM_TBL_SC2VLNT
:
11408 size
= get_sc2vlnt(ppd
->dd
, t
);
11410 case FM_TBL_VL_PREEMPT_ELEMS
:
11412 /* OPA specifies 128 elements, of 2 bytes each */
11413 get_vlarb_preempt(ppd
->dd
, OPA_MAX_VLS
, t
);
11415 case FM_TBL_VL_PREEMPT_MATRIX
:
11418 * OPA specifies that this is the same size as the VL
11419 * arbitration tables (i.e., 256 bytes).
11429 * Write the given fabric manager table.
11431 int fm_set_table(struct hfi1_pportdata
*ppd
, int which
, void *t
)
11434 struct vl_arb_cache
*vlc
;
11437 case FM_TBL_VL_HIGH_ARB
:
11438 vlc
= vl_arb_lock_cache(ppd
, HI_PRIO_TABLE
);
11439 if (vl_arb_match_cache(vlc
, t
)) {
11440 vl_arb_unlock_cache(ppd
, HI_PRIO_TABLE
);
11443 vl_arb_set_cache(vlc
, t
);
11444 vl_arb_unlock_cache(ppd
, HI_PRIO_TABLE
);
11445 ret
= set_vl_weights(ppd
, SEND_HIGH_PRIORITY_LIST
,
11446 VL_ARB_HIGH_PRIO_TABLE_SIZE
, t
);
11448 case FM_TBL_VL_LOW_ARB
:
11449 vlc
= vl_arb_lock_cache(ppd
, LO_PRIO_TABLE
);
11450 if (vl_arb_match_cache(vlc
, t
)) {
11451 vl_arb_unlock_cache(ppd
, LO_PRIO_TABLE
);
11454 vl_arb_set_cache(vlc
, t
);
11455 vl_arb_unlock_cache(ppd
, LO_PRIO_TABLE
);
11456 ret
= set_vl_weights(ppd
, SEND_LOW_PRIORITY_LIST
,
11457 VL_ARB_LOW_PRIO_TABLE_SIZE
, t
);
11459 case FM_TBL_BUFFER_CONTROL
:
11460 ret
= set_buffer_control(ppd
, t
);
11462 case FM_TBL_SC2VLNT
:
11463 set_sc2vlnt(ppd
->dd
, t
);
11472 * Disable all data VLs.
11474 * Return 0 if disabled, non-zero if the VLs cannot be disabled.
11476 static int disable_data_vls(struct hfi1_devdata
*dd
)
11481 pio_send_control(dd
, PSC_DATA_VL_DISABLE
);
11487 * open_fill_data_vls() - the counterpart to stop_drain_data_vls().
11488 * Just re-enables all data VLs (the "fill" part happens
11489 * automatically - the name was chosen for symmetry with
11490 * stop_drain_data_vls()).
11492 * Return 0 if successful, non-zero if the VLs cannot be enabled.
11494 int open_fill_data_vls(struct hfi1_devdata
*dd
)
11499 pio_send_control(dd
, PSC_DATA_VL_ENABLE
);
11505 * drain_data_vls() - assumes that disable_data_vls() has been called,
11506 * wait for occupancy (of per-VL FIFOs) for all contexts, and SDMA
11507 * engines to drop to 0.
11509 static void drain_data_vls(struct hfi1_devdata
*dd
)
11513 pause_for_credit_return(dd
);
11517 * stop_drain_data_vls() - disable, then drain all per-VL fifos.
11519 * Use open_fill_data_vls() to resume using data VLs. This pair is
11520 * meant to be used like this:
11522 * stop_drain_data_vls(dd);
11523 * // do things with per-VL resources
11524 * open_fill_data_vls(dd);
11526 int stop_drain_data_vls(struct hfi1_devdata
*dd
)
11530 ret
= disable_data_vls(dd
);
11532 drain_data_vls(dd
);
11538 * Convert a nanosecond time to a cclock count. No matter how slow
11539 * the cclock, a non-zero ns will always have a non-zero result.
11541 u32
ns_to_cclock(struct hfi1_devdata
*dd
, u32 ns
)
11545 if (dd
->icode
== ICODE_FPGA_EMULATION
)
11546 cclocks
= (ns
* 1000) / FPGA_CCLOCK_PS
;
11547 else /* simulation pretends to be ASIC */
11548 cclocks
= (ns
* 1000) / ASIC_CCLOCK_PS
;
11549 if (ns
&& !cclocks
) /* if ns nonzero, must be at least 1 */
11555 * Convert a cclock count to nanoseconds. Not matter how slow
11556 * the cclock, a non-zero cclocks will always have a non-zero result.
11558 u32
cclock_to_ns(struct hfi1_devdata
*dd
, u32 cclocks
)
11562 if (dd
->icode
== ICODE_FPGA_EMULATION
)
11563 ns
= (cclocks
* FPGA_CCLOCK_PS
) / 1000;
11564 else /* simulation pretends to be ASIC */
11565 ns
= (cclocks
* ASIC_CCLOCK_PS
) / 1000;
11566 if (cclocks
&& !ns
)
11572 * Dynamically adjust the receive interrupt timeout for a context based on
11573 * incoming packet rate.
11575 * NOTE: Dynamic adjustment does not allow rcv_intr_count to be zero.
11577 static void adjust_rcv_timeout(struct hfi1_ctxtdata
*rcd
, u32 npkts
)
11579 struct hfi1_devdata
*dd
= rcd
->dd
;
11580 u32 timeout
= rcd
->rcvavail_timeout
;
11583 * This algorithm doubles or halves the timeout depending on whether
11584 * the number of packets received in this interrupt were less than or
11585 * greater equal the interrupt count.
11587 * The calculations below do not allow a steady state to be achieved.
11588 * Only at the endpoints it is possible to have an unchanging
11591 if (npkts
< rcv_intr_count
) {
11593 * Not enough packets arrived before the timeout, adjust
11594 * timeout downward.
11596 if (timeout
< 2) /* already at minimum? */
11601 * More than enough packets arrived before the timeout, adjust
11604 if (timeout
>= dd
->rcv_intr_timeout_csr
) /* already at max? */
11606 timeout
= min(timeout
<< 1, dd
->rcv_intr_timeout_csr
);
11609 rcd
->rcvavail_timeout
= timeout
;
11611 * timeout cannot be larger than rcv_intr_timeout_csr which has already
11612 * been verified to be in range
11614 write_kctxt_csr(dd
, rcd
->ctxt
, RCV_AVAIL_TIME_OUT
,
11616 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_SHIFT
);
11619 void update_usrhead(struct hfi1_ctxtdata
*rcd
, u32 hd
, u32 updegr
, u32 egrhd
,
11620 u32 intr_adjust
, u32 npkts
)
11622 struct hfi1_devdata
*dd
= rcd
->dd
;
11624 u32 ctxt
= rcd
->ctxt
;
11627 * Need to write timeout register before updating RcvHdrHead to ensure
11628 * that a new value is used when the HW decides to restart counting.
11631 adjust_rcv_timeout(rcd
, npkts
);
11633 reg
= (egrhd
& RCV_EGR_INDEX_HEAD_HEAD_MASK
)
11634 << RCV_EGR_INDEX_HEAD_HEAD_SHIFT
;
11635 write_uctxt_csr(dd
, ctxt
, RCV_EGR_INDEX_HEAD
, reg
);
11638 reg
= ((u64
)rcv_intr_count
<< RCV_HDR_HEAD_COUNTER_SHIFT
) |
11639 (((u64
)hd
& RCV_HDR_HEAD_HEAD_MASK
)
11640 << RCV_HDR_HEAD_HEAD_SHIFT
);
11641 write_uctxt_csr(dd
, ctxt
, RCV_HDR_HEAD
, reg
);
11645 u32
hdrqempty(struct hfi1_ctxtdata
*rcd
)
11649 head
= (read_uctxt_csr(rcd
->dd
, rcd
->ctxt
, RCV_HDR_HEAD
)
11650 & RCV_HDR_HEAD_HEAD_SMASK
) >> RCV_HDR_HEAD_HEAD_SHIFT
;
11652 if (rcd
->rcvhdrtail_kvaddr
)
11653 tail
= get_rcvhdrtail(rcd
);
11655 tail
= read_uctxt_csr(rcd
->dd
, rcd
->ctxt
, RCV_HDR_TAIL
);
11657 return head
== tail
;
11661 * Context Control and Receive Array encoding for buffer size:
11670 * 0x8 512 KB (Receive Array only)
11671 * 0x9 1 MB (Receive Array only)
11672 * 0xa 2 MB (Receive Array only)
11674 * 0xB-0xF - reserved (Receive Array only)
11677 * This routine assumes that the value has already been sanity checked.
11679 static u32
encoded_size(u32 size
)
11682 case 4 * 1024: return 0x1;
11683 case 8 * 1024: return 0x2;
11684 case 16 * 1024: return 0x3;
11685 case 32 * 1024: return 0x4;
11686 case 64 * 1024: return 0x5;
11687 case 128 * 1024: return 0x6;
11688 case 256 * 1024: return 0x7;
11689 case 512 * 1024: return 0x8;
11690 case 1 * 1024 * 1024: return 0x9;
11691 case 2 * 1024 * 1024: return 0xa;
11693 return 0x1; /* if invalid, go with the minimum size */
11696 void hfi1_rcvctrl(struct hfi1_devdata
*dd
, unsigned int op
, int ctxt
)
11698 struct hfi1_ctxtdata
*rcd
;
11700 int did_enable
= 0;
11702 rcd
= dd
->rcd
[ctxt
];
11706 hfi1_cdbg(RCVCTRL
, "ctxt %d op 0x%x", ctxt
, op
);
11708 rcvctrl
= read_kctxt_csr(dd
, ctxt
, RCV_CTXT_CTRL
);
11709 /* if the context already enabled, don't do the extra steps */
11710 if ((op
& HFI1_RCVCTRL_CTXT_ENB
) &&
11711 !(rcvctrl
& RCV_CTXT_CTRL_ENABLE_SMASK
)) {
11712 /* reset the tail and hdr addresses, and sequence count */
11713 write_kctxt_csr(dd
, ctxt
, RCV_HDR_ADDR
,
11715 if (HFI1_CAP_KGET_MASK(rcd
->flags
, DMA_RTAIL
))
11716 write_kctxt_csr(dd
, ctxt
, RCV_HDR_TAIL_ADDR
,
11717 rcd
->rcvhdrqtailaddr_dma
);
11720 /* reset the cached receive header queue head value */
11724 * Zero the receive header queue so we don't get false
11725 * positives when checking the sequence number. The
11726 * sequence numbers could land exactly on the same spot.
11727 * E.g. a rcd restart before the receive header wrapped.
11729 memset(rcd
->rcvhdrq
, 0, rcd
->rcvhdrq_size
);
11731 /* starting timeout */
11732 rcd
->rcvavail_timeout
= dd
->rcv_intr_timeout_csr
;
11734 /* enable the context */
11735 rcvctrl
|= RCV_CTXT_CTRL_ENABLE_SMASK
;
11737 /* clean the egr buffer size first */
11738 rcvctrl
&= ~RCV_CTXT_CTRL_EGR_BUF_SIZE_SMASK
;
11739 rcvctrl
|= ((u64
)encoded_size(rcd
->egrbufs
.rcvtid_size
)
11740 & RCV_CTXT_CTRL_EGR_BUF_SIZE_MASK
)
11741 << RCV_CTXT_CTRL_EGR_BUF_SIZE_SHIFT
;
11743 /* zero RcvHdrHead - set RcvHdrHead.Counter after enable */
11744 write_uctxt_csr(dd
, ctxt
, RCV_HDR_HEAD
, 0);
11747 /* zero RcvEgrIndexHead */
11748 write_uctxt_csr(dd
, ctxt
, RCV_EGR_INDEX_HEAD
, 0);
11750 /* set eager count and base index */
11751 reg
= (((u64
)(rcd
->egrbufs
.alloced
>> RCV_SHIFT
)
11752 & RCV_EGR_CTRL_EGR_CNT_MASK
)
11753 << RCV_EGR_CTRL_EGR_CNT_SHIFT
) |
11754 (((rcd
->eager_base
>> RCV_SHIFT
)
11755 & RCV_EGR_CTRL_EGR_BASE_INDEX_MASK
)
11756 << RCV_EGR_CTRL_EGR_BASE_INDEX_SHIFT
);
11757 write_kctxt_csr(dd
, ctxt
, RCV_EGR_CTRL
, reg
);
11760 * Set TID (expected) count and base index.
11761 * rcd->expected_count is set to individual RcvArray entries,
11762 * not pairs, and the CSR takes a pair-count in groups of
11763 * four, so divide by 8.
11765 reg
= (((rcd
->expected_count
>> RCV_SHIFT
)
11766 & RCV_TID_CTRL_TID_PAIR_CNT_MASK
)
11767 << RCV_TID_CTRL_TID_PAIR_CNT_SHIFT
) |
11768 (((rcd
->expected_base
>> RCV_SHIFT
)
11769 & RCV_TID_CTRL_TID_BASE_INDEX_MASK
)
11770 << RCV_TID_CTRL_TID_BASE_INDEX_SHIFT
);
11771 write_kctxt_csr(dd
, ctxt
, RCV_TID_CTRL
, reg
);
11772 if (ctxt
== HFI1_CTRL_CTXT
)
11773 write_csr(dd
, RCV_VL15
, HFI1_CTRL_CTXT
);
11775 if (op
& HFI1_RCVCTRL_CTXT_DIS
) {
11776 write_csr(dd
, RCV_VL15
, 0);
11778 * When receive context is being disabled turn on tail
11779 * update with a dummy tail address and then disable
11782 if (dd
->rcvhdrtail_dummy_dma
) {
11783 write_kctxt_csr(dd
, ctxt
, RCV_HDR_TAIL_ADDR
,
11784 dd
->rcvhdrtail_dummy_dma
);
11785 /* Enabling RcvCtxtCtrl.TailUpd is intentional. */
11786 rcvctrl
|= RCV_CTXT_CTRL_TAIL_UPD_SMASK
;
11789 rcvctrl
&= ~RCV_CTXT_CTRL_ENABLE_SMASK
;
11791 if (op
& HFI1_RCVCTRL_INTRAVAIL_ENB
)
11792 rcvctrl
|= RCV_CTXT_CTRL_INTR_AVAIL_SMASK
;
11793 if (op
& HFI1_RCVCTRL_INTRAVAIL_DIS
)
11794 rcvctrl
&= ~RCV_CTXT_CTRL_INTR_AVAIL_SMASK
;
11795 if (op
& HFI1_RCVCTRL_TAILUPD_ENB
&& rcd
->rcvhdrqtailaddr_dma
)
11796 rcvctrl
|= RCV_CTXT_CTRL_TAIL_UPD_SMASK
;
11797 if (op
& HFI1_RCVCTRL_TAILUPD_DIS
) {
11798 /* See comment on RcvCtxtCtrl.TailUpd above */
11799 if (!(op
& HFI1_RCVCTRL_CTXT_DIS
))
11800 rcvctrl
&= ~RCV_CTXT_CTRL_TAIL_UPD_SMASK
;
11802 if (op
& HFI1_RCVCTRL_TIDFLOW_ENB
)
11803 rcvctrl
|= RCV_CTXT_CTRL_TID_FLOW_ENABLE_SMASK
;
11804 if (op
& HFI1_RCVCTRL_TIDFLOW_DIS
)
11805 rcvctrl
&= ~RCV_CTXT_CTRL_TID_FLOW_ENABLE_SMASK
;
11806 if (op
& HFI1_RCVCTRL_ONE_PKT_EGR_ENB
) {
11808 * In one-packet-per-eager mode, the size comes from
11809 * the RcvArray entry.
11811 rcvctrl
&= ~RCV_CTXT_CTRL_EGR_BUF_SIZE_SMASK
;
11812 rcvctrl
|= RCV_CTXT_CTRL_ONE_PACKET_PER_EGR_BUFFER_SMASK
;
11814 if (op
& HFI1_RCVCTRL_ONE_PKT_EGR_DIS
)
11815 rcvctrl
&= ~RCV_CTXT_CTRL_ONE_PACKET_PER_EGR_BUFFER_SMASK
;
11816 if (op
& HFI1_RCVCTRL_NO_RHQ_DROP_ENB
)
11817 rcvctrl
|= RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK
;
11818 if (op
& HFI1_RCVCTRL_NO_RHQ_DROP_DIS
)
11819 rcvctrl
&= ~RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK
;
11820 if (op
& HFI1_RCVCTRL_NO_EGR_DROP_ENB
)
11821 rcvctrl
|= RCV_CTXT_CTRL_DONT_DROP_EGR_FULL_SMASK
;
11822 if (op
& HFI1_RCVCTRL_NO_EGR_DROP_DIS
)
11823 rcvctrl
&= ~RCV_CTXT_CTRL_DONT_DROP_EGR_FULL_SMASK
;
11824 rcd
->rcvctrl
= rcvctrl
;
11825 hfi1_cdbg(RCVCTRL
, "ctxt %d rcvctrl 0x%llx\n", ctxt
, rcvctrl
);
11826 write_kctxt_csr(dd
, ctxt
, RCV_CTXT_CTRL
, rcd
->rcvctrl
);
11828 /* work around sticky RcvCtxtStatus.BlockedRHQFull */
11830 (rcvctrl
& RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK
)) {
11831 reg
= read_kctxt_csr(dd
, ctxt
, RCV_CTXT_STATUS
);
11833 dd_dev_info(dd
, "ctxt %d status %lld (blocked)\n",
11835 read_uctxt_csr(dd
, ctxt
, RCV_HDR_HEAD
);
11836 write_uctxt_csr(dd
, ctxt
, RCV_HDR_HEAD
, 0x10);
11837 write_uctxt_csr(dd
, ctxt
, RCV_HDR_HEAD
, 0x00);
11838 read_uctxt_csr(dd
, ctxt
, RCV_HDR_HEAD
);
11839 reg
= read_kctxt_csr(dd
, ctxt
, RCV_CTXT_STATUS
);
11840 dd_dev_info(dd
, "ctxt %d status %lld (%s blocked)\n",
11841 ctxt
, reg
, reg
== 0 ? "not" : "still");
11847 * The interrupt timeout and count must be set after
11848 * the context is enabled to take effect.
11850 /* set interrupt timeout */
11851 write_kctxt_csr(dd
, ctxt
, RCV_AVAIL_TIME_OUT
,
11852 (u64
)rcd
->rcvavail_timeout
<<
11853 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_SHIFT
);
11855 /* set RcvHdrHead.Counter, zero RcvHdrHead.Head (again) */
11856 reg
= (u64
)rcv_intr_count
<< RCV_HDR_HEAD_COUNTER_SHIFT
;
11857 write_uctxt_csr(dd
, ctxt
, RCV_HDR_HEAD
, reg
);
11860 if (op
& (HFI1_RCVCTRL_TAILUPD_DIS
| HFI1_RCVCTRL_CTXT_DIS
))
11862 * If the context has been disabled and the Tail Update has
11863 * been cleared, set the RCV_HDR_TAIL_ADDR CSR to dummy address
11864 * so it doesn't contain an address that is invalid.
11866 write_kctxt_csr(dd
, ctxt
, RCV_HDR_TAIL_ADDR
,
11867 dd
->rcvhdrtail_dummy_dma
);
11870 u32
hfi1_read_cntrs(struct hfi1_devdata
*dd
, char **namep
, u64
**cntrp
)
11876 ret
= dd
->cntrnameslen
;
11877 *namep
= dd
->cntrnames
;
11879 const struct cntr_entry
*entry
;
11882 ret
= (dd
->ndevcntrs
) * sizeof(u64
);
11884 /* Get the start of the block of counters */
11885 *cntrp
= dd
->cntrs
;
11888 * Now go and fill in each counter in the block.
11890 for (i
= 0; i
< DEV_CNTR_LAST
; i
++) {
11891 entry
= &dev_cntrs
[i
];
11892 hfi1_cdbg(CNTR
, "reading %s", entry
->name
);
11893 if (entry
->flags
& CNTR_DISABLED
) {
11895 hfi1_cdbg(CNTR
, "\tDisabled\n");
11897 if (entry
->flags
& CNTR_VL
) {
11898 hfi1_cdbg(CNTR
, "\tPer VL\n");
11899 for (j
= 0; j
< C_VL_COUNT
; j
++) {
11900 val
= entry
->rw_cntr(entry
,
11906 "\t\tRead 0x%llx for %d\n",
11908 dd
->cntrs
[entry
->offset
+ j
] =
11911 } else if (entry
->flags
& CNTR_SDMA
) {
11913 "\t Per SDMA Engine\n");
11914 for (j
= 0; j
< dd
->chip_sdma_engines
;
11917 entry
->rw_cntr(entry
, dd
, j
,
11920 "\t\tRead 0x%llx for %d\n",
11922 dd
->cntrs
[entry
->offset
+ j
] =
11926 val
= entry
->rw_cntr(entry
, dd
,
11929 dd
->cntrs
[entry
->offset
] = val
;
11930 hfi1_cdbg(CNTR
, "\tRead 0x%llx", val
);
11939 * Used by sysfs to create files for hfi stats to read
11941 u32
hfi1_read_portcntrs(struct hfi1_pportdata
*ppd
, char **namep
, u64
**cntrp
)
11947 ret
= ppd
->dd
->portcntrnameslen
;
11948 *namep
= ppd
->dd
->portcntrnames
;
11950 const struct cntr_entry
*entry
;
11953 ret
= ppd
->dd
->nportcntrs
* sizeof(u64
);
11954 *cntrp
= ppd
->cntrs
;
11956 for (i
= 0; i
< PORT_CNTR_LAST
; i
++) {
11957 entry
= &port_cntrs
[i
];
11958 hfi1_cdbg(CNTR
, "reading %s", entry
->name
);
11959 if (entry
->flags
& CNTR_DISABLED
) {
11961 hfi1_cdbg(CNTR
, "\tDisabled\n");
11965 if (entry
->flags
& CNTR_VL
) {
11966 hfi1_cdbg(CNTR
, "\tPer VL");
11967 for (j
= 0; j
< C_VL_COUNT
; j
++) {
11968 val
= entry
->rw_cntr(entry
, ppd
, j
,
11973 "\t\tRead 0x%llx for %d",
11975 ppd
->cntrs
[entry
->offset
+ j
] = val
;
11978 val
= entry
->rw_cntr(entry
, ppd
,
11982 ppd
->cntrs
[entry
->offset
] = val
;
11983 hfi1_cdbg(CNTR
, "\tRead 0x%llx", val
);
11990 static void free_cntrs(struct hfi1_devdata
*dd
)
11992 struct hfi1_pportdata
*ppd
;
11995 if (dd
->synth_stats_timer
.data
)
11996 del_timer_sync(&dd
->synth_stats_timer
);
11997 dd
->synth_stats_timer
.data
= 0;
11998 ppd
= (struct hfi1_pportdata
*)(dd
+ 1);
11999 for (i
= 0; i
< dd
->num_pports
; i
++, ppd
++) {
12001 kfree(ppd
->scntrs
);
12002 free_percpu(ppd
->ibport_data
.rvp
.rc_acks
);
12003 free_percpu(ppd
->ibport_data
.rvp
.rc_qacks
);
12004 free_percpu(ppd
->ibport_data
.rvp
.rc_delayed_comp
);
12006 ppd
->scntrs
= NULL
;
12007 ppd
->ibport_data
.rvp
.rc_acks
= NULL
;
12008 ppd
->ibport_data
.rvp
.rc_qacks
= NULL
;
12009 ppd
->ibport_data
.rvp
.rc_delayed_comp
= NULL
;
12011 kfree(dd
->portcntrnames
);
12012 dd
->portcntrnames
= NULL
;
12017 kfree(dd
->cntrnames
);
12018 dd
->cntrnames
= NULL
;
12019 if (dd
->update_cntr_wq
) {
12020 destroy_workqueue(dd
->update_cntr_wq
);
12021 dd
->update_cntr_wq
= NULL
;
12025 static u64
read_dev_port_cntr(struct hfi1_devdata
*dd
, struct cntr_entry
*entry
,
12026 u64
*psval
, void *context
, int vl
)
12031 if (entry
->flags
& CNTR_DISABLED
) {
12032 dd_dev_err(dd
, "Counter %s not enabled", entry
->name
);
12036 hfi1_cdbg(CNTR
, "cntr: %s vl %d psval 0x%llx", entry
->name
, vl
, *psval
);
12038 val
= entry
->rw_cntr(entry
, context
, vl
, CNTR_MODE_R
, 0);
12040 /* If its a synthetic counter there is more work we need to do */
12041 if (entry
->flags
& CNTR_SYNTH
) {
12042 if (sval
== CNTR_MAX
) {
12043 /* No need to read already saturated */
12047 if (entry
->flags
& CNTR_32BIT
) {
12048 /* 32bit counters can wrap multiple times */
12049 u64 upper
= sval
>> 32;
12050 u64 lower
= (sval
<< 32) >> 32;
12052 if (lower
> val
) { /* hw wrapped */
12053 if (upper
== CNTR_32BIT_MAX
)
12059 if (val
!= CNTR_MAX
)
12060 val
= (upper
<< 32) | val
;
12063 /* If we rolled we are saturated */
12064 if ((val
< sval
) || (val
> CNTR_MAX
))
12071 hfi1_cdbg(CNTR
, "\tNew val=0x%llx", val
);
12076 static u64
write_dev_port_cntr(struct hfi1_devdata
*dd
,
12077 struct cntr_entry
*entry
,
12078 u64
*psval
, void *context
, int vl
, u64 data
)
12082 if (entry
->flags
& CNTR_DISABLED
) {
12083 dd_dev_err(dd
, "Counter %s not enabled", entry
->name
);
12087 hfi1_cdbg(CNTR
, "cntr: %s vl %d psval 0x%llx", entry
->name
, vl
, *psval
);
12089 if (entry
->flags
& CNTR_SYNTH
) {
12091 if (entry
->flags
& CNTR_32BIT
) {
12092 val
= entry
->rw_cntr(entry
, context
, vl
, CNTR_MODE_W
,
12093 (data
<< 32) >> 32);
12094 val
= data
; /* return the full 64bit value */
12096 val
= entry
->rw_cntr(entry
, context
, vl
, CNTR_MODE_W
,
12100 val
= entry
->rw_cntr(entry
, context
, vl
, CNTR_MODE_W
, data
);
12105 hfi1_cdbg(CNTR
, "\tNew val=0x%llx", val
);
12110 u64
read_dev_cntr(struct hfi1_devdata
*dd
, int index
, int vl
)
12112 struct cntr_entry
*entry
;
12115 entry
= &dev_cntrs
[index
];
12116 sval
= dd
->scntrs
+ entry
->offset
;
12118 if (vl
!= CNTR_INVALID_VL
)
12121 return read_dev_port_cntr(dd
, entry
, sval
, dd
, vl
);
12124 u64
write_dev_cntr(struct hfi1_devdata
*dd
, int index
, int vl
, u64 data
)
12126 struct cntr_entry
*entry
;
12129 entry
= &dev_cntrs
[index
];
12130 sval
= dd
->scntrs
+ entry
->offset
;
12132 if (vl
!= CNTR_INVALID_VL
)
12135 return write_dev_port_cntr(dd
, entry
, sval
, dd
, vl
, data
);
12138 u64
read_port_cntr(struct hfi1_pportdata
*ppd
, int index
, int vl
)
12140 struct cntr_entry
*entry
;
12143 entry
= &port_cntrs
[index
];
12144 sval
= ppd
->scntrs
+ entry
->offset
;
12146 if (vl
!= CNTR_INVALID_VL
)
12149 if ((index
>= C_RCV_HDR_OVF_FIRST
+ ppd
->dd
->num_rcv_contexts
) &&
12150 (index
<= C_RCV_HDR_OVF_LAST
)) {
12151 /* We do not want to bother for disabled contexts */
12155 return read_dev_port_cntr(ppd
->dd
, entry
, sval
, ppd
, vl
);
12158 u64
write_port_cntr(struct hfi1_pportdata
*ppd
, int index
, int vl
, u64 data
)
12160 struct cntr_entry
*entry
;
12163 entry
= &port_cntrs
[index
];
12164 sval
= ppd
->scntrs
+ entry
->offset
;
12166 if (vl
!= CNTR_INVALID_VL
)
12169 if ((index
>= C_RCV_HDR_OVF_FIRST
+ ppd
->dd
->num_rcv_contexts
) &&
12170 (index
<= C_RCV_HDR_OVF_LAST
)) {
12171 /* We do not want to bother for disabled contexts */
12175 return write_dev_port_cntr(ppd
->dd
, entry
, sval
, ppd
, vl
, data
);
12178 static void do_update_synth_timer(struct work_struct
*work
)
12185 struct hfi1_pportdata
*ppd
;
12186 struct cntr_entry
*entry
;
12187 struct hfi1_devdata
*dd
= container_of(work
, struct hfi1_devdata
,
12191 * Rather than keep beating on the CSRs pick a minimal set that we can
12192 * check to watch for potential roll over. We can do this by looking at
12193 * the number of flits sent/recv. If the total flits exceeds 32bits then
12194 * we have to iterate all the counters and update.
12196 entry
= &dev_cntrs
[C_DC_RCV_FLITS
];
12197 cur_rx
= entry
->rw_cntr(entry
, dd
, CNTR_INVALID_VL
, CNTR_MODE_R
, 0);
12199 entry
= &dev_cntrs
[C_DC_XMIT_FLITS
];
12200 cur_tx
= entry
->rw_cntr(entry
, dd
, CNTR_INVALID_VL
, CNTR_MODE_R
, 0);
12204 "[%d] curr tx=0x%llx rx=0x%llx :: last tx=0x%llx rx=0x%llx\n",
12205 dd
->unit
, cur_tx
, cur_rx
, dd
->last_tx
, dd
->last_rx
);
12207 if ((cur_tx
< dd
->last_tx
) || (cur_rx
< dd
->last_rx
)) {
12209 * May not be strictly necessary to update but it won't hurt and
12210 * simplifies the logic here.
12213 hfi1_cdbg(CNTR
, "[%d] Tripwire counter rolled, updating",
12216 total_flits
= (cur_tx
- dd
->last_tx
) + (cur_rx
- dd
->last_rx
);
12218 "[%d] total flits 0x%llx limit 0x%llx\n", dd
->unit
,
12219 total_flits
, (u64
)CNTR_32BIT_MAX
);
12220 if (total_flits
>= CNTR_32BIT_MAX
) {
12221 hfi1_cdbg(CNTR
, "[%d] 32bit limit hit, updating",
12228 hfi1_cdbg(CNTR
, "[%d] Updating dd and ppd counters", dd
->unit
);
12229 for (i
= 0; i
< DEV_CNTR_LAST
; i
++) {
12230 entry
= &dev_cntrs
[i
];
12231 if (entry
->flags
& CNTR_VL
) {
12232 for (vl
= 0; vl
< C_VL_COUNT
; vl
++)
12233 read_dev_cntr(dd
, i
, vl
);
12235 read_dev_cntr(dd
, i
, CNTR_INVALID_VL
);
12238 ppd
= (struct hfi1_pportdata
*)(dd
+ 1);
12239 for (i
= 0; i
< dd
->num_pports
; i
++, ppd
++) {
12240 for (j
= 0; j
< PORT_CNTR_LAST
; j
++) {
12241 entry
= &port_cntrs
[j
];
12242 if (entry
->flags
& CNTR_VL
) {
12243 for (vl
= 0; vl
< C_VL_COUNT
; vl
++)
12244 read_port_cntr(ppd
, j
, vl
);
12246 read_port_cntr(ppd
, j
, CNTR_INVALID_VL
);
12252 * We want the value in the register. The goal is to keep track
12253 * of the number of "ticks" not the counter value. In other
12254 * words if the register rolls we want to notice it and go ahead
12255 * and force an update.
12257 entry
= &dev_cntrs
[C_DC_XMIT_FLITS
];
12258 dd
->last_tx
= entry
->rw_cntr(entry
, dd
, CNTR_INVALID_VL
,
12261 entry
= &dev_cntrs
[C_DC_RCV_FLITS
];
12262 dd
->last_rx
= entry
->rw_cntr(entry
, dd
, CNTR_INVALID_VL
,
12265 hfi1_cdbg(CNTR
, "[%d] setting last tx/rx to 0x%llx 0x%llx",
12266 dd
->unit
, dd
->last_tx
, dd
->last_rx
);
12269 hfi1_cdbg(CNTR
, "[%d] No update necessary", dd
->unit
);
12273 static void update_synth_timer(unsigned long opaque
)
12275 struct hfi1_devdata
*dd
= (struct hfi1_devdata
*)opaque
;
12277 queue_work(dd
->update_cntr_wq
, &dd
->update_cntr_work
);
12278 mod_timer(&dd
->synth_stats_timer
, jiffies
+ HZ
* SYNTH_CNT_TIME
);
12281 #define C_MAX_NAME 16 /* 15 chars + one for /0 */
12282 static int init_cntrs(struct hfi1_devdata
*dd
)
12284 int i
, rcv_ctxts
, j
;
12287 char name
[C_MAX_NAME
];
12288 struct hfi1_pportdata
*ppd
;
12289 const char *bit_type_32
= ",32";
12290 const int bit_type_32_sz
= strlen(bit_type_32
);
12292 /* set up the stats timer; the add_timer is done at the end */
12293 setup_timer(&dd
->synth_stats_timer
, update_synth_timer
,
12294 (unsigned long)dd
);
12296 /***********************/
12297 /* per device counters */
12298 /***********************/
12300 /* size names and determine how many we have*/
12304 for (i
= 0; i
< DEV_CNTR_LAST
; i
++) {
12305 if (dev_cntrs
[i
].flags
& CNTR_DISABLED
) {
12306 hfi1_dbg_early("\tSkipping %s\n", dev_cntrs
[i
].name
);
12310 if (dev_cntrs
[i
].flags
& CNTR_VL
) {
12311 dev_cntrs
[i
].offset
= dd
->ndevcntrs
;
12312 for (j
= 0; j
< C_VL_COUNT
; j
++) {
12313 snprintf(name
, C_MAX_NAME
, "%s%d",
12314 dev_cntrs
[i
].name
, vl_from_idx(j
));
12315 sz
+= strlen(name
);
12316 /* Add ",32" for 32-bit counters */
12317 if (dev_cntrs
[i
].flags
& CNTR_32BIT
)
12318 sz
+= bit_type_32_sz
;
12322 } else if (dev_cntrs
[i
].flags
& CNTR_SDMA
) {
12323 dev_cntrs
[i
].offset
= dd
->ndevcntrs
;
12324 for (j
= 0; j
< dd
->chip_sdma_engines
; j
++) {
12325 snprintf(name
, C_MAX_NAME
, "%s%d",
12326 dev_cntrs
[i
].name
, j
);
12327 sz
+= strlen(name
);
12328 /* Add ",32" for 32-bit counters */
12329 if (dev_cntrs
[i
].flags
& CNTR_32BIT
)
12330 sz
+= bit_type_32_sz
;
12335 /* +1 for newline. */
12336 sz
+= strlen(dev_cntrs
[i
].name
) + 1;
12337 /* Add ",32" for 32-bit counters */
12338 if (dev_cntrs
[i
].flags
& CNTR_32BIT
)
12339 sz
+= bit_type_32_sz
;
12340 dev_cntrs
[i
].offset
= dd
->ndevcntrs
;
12345 /* allocate space for the counter values */
12346 dd
->cntrs
= kcalloc(dd
->ndevcntrs
, sizeof(u64
), GFP_KERNEL
);
12350 dd
->scntrs
= kcalloc(dd
->ndevcntrs
, sizeof(u64
), GFP_KERNEL
);
12354 /* allocate space for the counter names */
12355 dd
->cntrnameslen
= sz
;
12356 dd
->cntrnames
= kmalloc(sz
, GFP_KERNEL
);
12357 if (!dd
->cntrnames
)
12360 /* fill in the names */
12361 for (p
= dd
->cntrnames
, i
= 0; i
< DEV_CNTR_LAST
; i
++) {
12362 if (dev_cntrs
[i
].flags
& CNTR_DISABLED
) {
12364 } else if (dev_cntrs
[i
].flags
& CNTR_VL
) {
12365 for (j
= 0; j
< C_VL_COUNT
; j
++) {
12366 snprintf(name
, C_MAX_NAME
, "%s%d",
12369 memcpy(p
, name
, strlen(name
));
12372 /* Counter is 32 bits */
12373 if (dev_cntrs
[i
].flags
& CNTR_32BIT
) {
12374 memcpy(p
, bit_type_32
, bit_type_32_sz
);
12375 p
+= bit_type_32_sz
;
12380 } else if (dev_cntrs
[i
].flags
& CNTR_SDMA
) {
12381 for (j
= 0; j
< dd
->chip_sdma_engines
; j
++) {
12382 snprintf(name
, C_MAX_NAME
, "%s%d",
12383 dev_cntrs
[i
].name
, j
);
12384 memcpy(p
, name
, strlen(name
));
12387 /* Counter is 32 bits */
12388 if (dev_cntrs
[i
].flags
& CNTR_32BIT
) {
12389 memcpy(p
, bit_type_32
, bit_type_32_sz
);
12390 p
+= bit_type_32_sz
;
12396 memcpy(p
, dev_cntrs
[i
].name
, strlen(dev_cntrs
[i
].name
));
12397 p
+= strlen(dev_cntrs
[i
].name
);
12399 /* Counter is 32 bits */
12400 if (dev_cntrs
[i
].flags
& CNTR_32BIT
) {
12401 memcpy(p
, bit_type_32
, bit_type_32_sz
);
12402 p
+= bit_type_32_sz
;
12409 /*********************/
12410 /* per port counters */
12411 /*********************/
12414 * Go through the counters for the overflows and disable the ones we
12415 * don't need. This varies based on platform so we need to do it
12416 * dynamically here.
12418 rcv_ctxts
= dd
->num_rcv_contexts
;
12419 for (i
= C_RCV_HDR_OVF_FIRST
+ rcv_ctxts
;
12420 i
<= C_RCV_HDR_OVF_LAST
; i
++) {
12421 port_cntrs
[i
].flags
|= CNTR_DISABLED
;
12424 /* size port counter names and determine how many we have*/
12426 dd
->nportcntrs
= 0;
12427 for (i
= 0; i
< PORT_CNTR_LAST
; i
++) {
12428 if (port_cntrs
[i
].flags
& CNTR_DISABLED
) {
12429 hfi1_dbg_early("\tSkipping %s\n", port_cntrs
[i
].name
);
12433 if (port_cntrs
[i
].flags
& CNTR_VL
) {
12434 port_cntrs
[i
].offset
= dd
->nportcntrs
;
12435 for (j
= 0; j
< C_VL_COUNT
; j
++) {
12436 snprintf(name
, C_MAX_NAME
, "%s%d",
12437 port_cntrs
[i
].name
, vl_from_idx(j
));
12438 sz
+= strlen(name
);
12439 /* Add ",32" for 32-bit counters */
12440 if (port_cntrs
[i
].flags
& CNTR_32BIT
)
12441 sz
+= bit_type_32_sz
;
12446 /* +1 for newline */
12447 sz
+= strlen(port_cntrs
[i
].name
) + 1;
12448 /* Add ",32" for 32-bit counters */
12449 if (port_cntrs
[i
].flags
& CNTR_32BIT
)
12450 sz
+= bit_type_32_sz
;
12451 port_cntrs
[i
].offset
= dd
->nportcntrs
;
12456 /* allocate space for the counter names */
12457 dd
->portcntrnameslen
= sz
;
12458 dd
->portcntrnames
= kmalloc(sz
, GFP_KERNEL
);
12459 if (!dd
->portcntrnames
)
12462 /* fill in port cntr names */
12463 for (p
= dd
->portcntrnames
, i
= 0; i
< PORT_CNTR_LAST
; i
++) {
12464 if (port_cntrs
[i
].flags
& CNTR_DISABLED
)
12467 if (port_cntrs
[i
].flags
& CNTR_VL
) {
12468 for (j
= 0; j
< C_VL_COUNT
; j
++) {
12469 snprintf(name
, C_MAX_NAME
, "%s%d",
12470 port_cntrs
[i
].name
, vl_from_idx(j
));
12471 memcpy(p
, name
, strlen(name
));
12474 /* Counter is 32 bits */
12475 if (port_cntrs
[i
].flags
& CNTR_32BIT
) {
12476 memcpy(p
, bit_type_32
, bit_type_32_sz
);
12477 p
+= bit_type_32_sz
;
12483 memcpy(p
, port_cntrs
[i
].name
,
12484 strlen(port_cntrs
[i
].name
));
12485 p
+= strlen(port_cntrs
[i
].name
);
12487 /* Counter is 32 bits */
12488 if (port_cntrs
[i
].flags
& CNTR_32BIT
) {
12489 memcpy(p
, bit_type_32
, bit_type_32_sz
);
12490 p
+= bit_type_32_sz
;
12497 /* allocate per port storage for counter values */
12498 ppd
= (struct hfi1_pportdata
*)(dd
+ 1);
12499 for (i
= 0; i
< dd
->num_pports
; i
++, ppd
++) {
12500 ppd
->cntrs
= kcalloc(dd
->nportcntrs
, sizeof(u64
), GFP_KERNEL
);
12504 ppd
->scntrs
= kcalloc(dd
->nportcntrs
, sizeof(u64
), GFP_KERNEL
);
12509 /* CPU counters need to be allocated and zeroed */
12510 if (init_cpu_counters(dd
))
12513 dd
->update_cntr_wq
= alloc_ordered_workqueue("hfi1_update_cntr_%d",
12514 WQ_MEM_RECLAIM
, dd
->unit
);
12515 if (!dd
->update_cntr_wq
)
12518 INIT_WORK(&dd
->update_cntr_work
, do_update_synth_timer
);
12520 mod_timer(&dd
->synth_stats_timer
, jiffies
+ HZ
* SYNTH_CNT_TIME
);
12527 static u32
chip_to_opa_lstate(struct hfi1_devdata
*dd
, u32 chip_lstate
)
12529 switch (chip_lstate
) {
12532 "Unknown logical state 0x%x, reporting IB_PORT_DOWN\n",
12536 return IB_PORT_DOWN
;
12538 return IB_PORT_INIT
;
12540 return IB_PORT_ARMED
;
12541 case LSTATE_ACTIVE
:
12542 return IB_PORT_ACTIVE
;
12546 u32
chip_to_opa_pstate(struct hfi1_devdata
*dd
, u32 chip_pstate
)
12548 /* look at the HFI meta-states only */
12549 switch (chip_pstate
& 0xf0) {
12551 dd_dev_err(dd
, "Unexpected chip physical state of 0x%x\n",
12555 return IB_PORTPHYSSTATE_DISABLED
;
12557 return OPA_PORTPHYSSTATE_OFFLINE
;
12559 return IB_PORTPHYSSTATE_POLLING
;
12560 case PLS_CONFIGPHY
:
12561 return IB_PORTPHYSSTATE_TRAINING
;
12563 return IB_PORTPHYSSTATE_LINKUP
;
12565 return IB_PORTPHYSSTATE_PHY_TEST
;
12569 /* return the OPA port logical state name */
12570 const char *opa_lstate_name(u32 lstate
)
12572 static const char * const port_logical_names
[] = {
12578 "PORT_ACTIVE_DEFER",
12580 if (lstate
< ARRAY_SIZE(port_logical_names
))
12581 return port_logical_names
[lstate
];
12585 /* return the OPA port physical state name */
12586 const char *opa_pstate_name(u32 pstate
)
12588 static const char * const port_physical_names
[] = {
12595 "PHYS_LINK_ERR_RECOVER",
12602 if (pstate
< ARRAY_SIZE(port_physical_names
))
12603 return port_physical_names
[pstate
];
12608 * Read the hardware link state and set the driver's cached value of it.
12609 * Return the (new) current value.
12611 u32
get_logical_state(struct hfi1_pportdata
*ppd
)
12615 new_state
= chip_to_opa_lstate(ppd
->dd
, read_logical_state(ppd
->dd
));
12616 if (new_state
!= ppd
->lstate
) {
12617 dd_dev_info(ppd
->dd
, "logical state changed to %s (0x%x)\n",
12618 opa_lstate_name(new_state
), new_state
);
12619 ppd
->lstate
= new_state
;
12622 * Set port status flags in the page mapped into userspace
12623 * memory. Do it here to ensure a reliable state - this is
12624 * the only function called by all state handling code.
12625 * Always set the flags due to the fact that the cache value
12626 * might have been changed explicitly outside of this
12629 if (ppd
->statusp
) {
12630 switch (ppd
->lstate
) {
12633 *ppd
->statusp
&= ~(HFI1_STATUS_IB_CONF
|
12634 HFI1_STATUS_IB_READY
);
12636 case IB_PORT_ARMED
:
12637 *ppd
->statusp
|= HFI1_STATUS_IB_CONF
;
12639 case IB_PORT_ACTIVE
:
12640 *ppd
->statusp
|= HFI1_STATUS_IB_READY
;
12644 return ppd
->lstate
;
12648 * wait_logical_linkstate - wait for an IB link state change to occur
12649 * @ppd: port device
12650 * @state: the state to wait for
12651 * @msecs: the number of milliseconds to wait
12653 * Wait up to msecs milliseconds for IB link state change to occur.
12654 * For now, take the easy polling route.
12655 * Returns 0 if state reached, otherwise -ETIMEDOUT.
12657 static int wait_logical_linkstate(struct hfi1_pportdata
*ppd
, u32 state
,
12660 unsigned long timeout
;
12662 timeout
= jiffies
+ msecs_to_jiffies(msecs
);
12664 if (get_logical_state(ppd
) == state
)
12666 if (time_after(jiffies
, timeout
))
12670 dd_dev_err(ppd
->dd
, "timeout waiting for link state 0x%x\n", state
);
12675 u8
hfi1_ibphys_portstate(struct hfi1_pportdata
*ppd
)
12680 pstate
= read_physical_state(ppd
->dd
);
12681 ib_pstate
= chip_to_opa_pstate(ppd
->dd
, pstate
);
12682 if (ppd
->last_pstate
!= ib_pstate
) {
12683 dd_dev_info(ppd
->dd
,
12684 "%s: physical state changed to %s (0x%x), phy 0x%x\n",
12685 __func__
, opa_pstate_name(ib_pstate
), ib_pstate
,
12687 ppd
->last_pstate
= ib_pstate
;
12692 #define CLEAR_STATIC_RATE_CONTROL_SMASK(r) \
12693 (r &= ~SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK)
12695 #define SET_STATIC_RATE_CONTROL_SMASK(r) \
12696 (r |= SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK)
12698 void hfi1_init_ctxt(struct send_context
*sc
)
12701 struct hfi1_devdata
*dd
= sc
->dd
;
12703 u8 set
= (sc
->type
== SC_USER
?
12704 HFI1_CAP_IS_USET(STATIC_RATE_CTRL
) :
12705 HFI1_CAP_IS_KSET(STATIC_RATE_CTRL
));
12706 reg
= read_kctxt_csr(dd
, sc
->hw_context
,
12707 SEND_CTXT_CHECK_ENABLE
);
12709 CLEAR_STATIC_RATE_CONTROL_SMASK(reg
);
12711 SET_STATIC_RATE_CONTROL_SMASK(reg
);
12712 write_kctxt_csr(dd
, sc
->hw_context
,
12713 SEND_CTXT_CHECK_ENABLE
, reg
);
12717 int hfi1_tempsense_rd(struct hfi1_devdata
*dd
, struct hfi1_temp
*temp
)
12722 if (dd
->icode
!= ICODE_RTL_SILICON
) {
12723 if (HFI1_CAP_IS_KSET(PRINT_UNIMPL
))
12724 dd_dev_info(dd
, "%s: tempsense not supported by HW\n",
12728 reg
= read_csr(dd
, ASIC_STS_THERM
);
12729 temp
->curr
= ((reg
>> ASIC_STS_THERM_CURR_TEMP_SHIFT
) &
12730 ASIC_STS_THERM_CURR_TEMP_MASK
);
12731 temp
->lo_lim
= ((reg
>> ASIC_STS_THERM_LO_TEMP_SHIFT
) &
12732 ASIC_STS_THERM_LO_TEMP_MASK
);
12733 temp
->hi_lim
= ((reg
>> ASIC_STS_THERM_HI_TEMP_SHIFT
) &
12734 ASIC_STS_THERM_HI_TEMP_MASK
);
12735 temp
->crit_lim
= ((reg
>> ASIC_STS_THERM_CRIT_TEMP_SHIFT
) &
12736 ASIC_STS_THERM_CRIT_TEMP_MASK
);
12737 /* triggers is a 3-bit value - 1 bit per trigger. */
12738 temp
->triggers
= (u8
)((reg
>> ASIC_STS_THERM_LOW_SHIFT
) & 0x7);
12743 /* ========================================================================= */
12746 * Enable/disable chip from delivering interrupts.
12748 void set_intr_state(struct hfi1_devdata
*dd
, u32 enable
)
12753 * In HFI, the mask needs to be 1 to allow interrupts.
12756 /* enable all interrupts */
12757 for (i
= 0; i
< CCE_NUM_INT_CSRS
; i
++)
12758 write_csr(dd
, CCE_INT_MASK
+ (8 * i
), ~(u64
)0);
12762 for (i
= 0; i
< CCE_NUM_INT_CSRS
; i
++)
12763 write_csr(dd
, CCE_INT_MASK
+ (8 * i
), 0ull);
12768 * Clear all interrupt sources on the chip.
12770 static void clear_all_interrupts(struct hfi1_devdata
*dd
)
12774 for (i
= 0; i
< CCE_NUM_INT_CSRS
; i
++)
12775 write_csr(dd
, CCE_INT_CLEAR
+ (8 * i
), ~(u64
)0);
12777 write_csr(dd
, CCE_ERR_CLEAR
, ~(u64
)0);
12778 write_csr(dd
, MISC_ERR_CLEAR
, ~(u64
)0);
12779 write_csr(dd
, RCV_ERR_CLEAR
, ~(u64
)0);
12780 write_csr(dd
, SEND_ERR_CLEAR
, ~(u64
)0);
12781 write_csr(dd
, SEND_PIO_ERR_CLEAR
, ~(u64
)0);
12782 write_csr(dd
, SEND_DMA_ERR_CLEAR
, ~(u64
)0);
12783 write_csr(dd
, SEND_EGRESS_ERR_CLEAR
, ~(u64
)0);
12784 for (i
= 0; i
< dd
->chip_send_contexts
; i
++)
12785 write_kctxt_csr(dd
, i
, SEND_CTXT_ERR_CLEAR
, ~(u64
)0);
12786 for (i
= 0; i
< dd
->chip_sdma_engines
; i
++)
12787 write_kctxt_csr(dd
, i
, SEND_DMA_ENG_ERR_CLEAR
, ~(u64
)0);
12789 write_csr(dd
, DCC_ERR_FLG_CLR
, ~(u64
)0);
12790 write_csr(dd
, DC_LCB_ERR_CLR
, ~(u64
)0);
12791 write_csr(dd
, DC_DC8051_ERR_CLR
, ~(u64
)0);
12794 /* Move to pcie.c? */
12795 static void disable_intx(struct pci_dev
*pdev
)
12800 static void clean_up_interrupts(struct hfi1_devdata
*dd
)
12804 /* remove irqs - must happen before disabling/turning off */
12805 if (dd
->num_msix_entries
) {
12807 struct hfi1_msix_entry
*me
= dd
->msix_entries
;
12809 for (i
= 0; i
< dd
->num_msix_entries
; i
++, me
++) {
12810 if (!me
->arg
) /* => no irq, no affinity */
12812 hfi1_put_irq_affinity(dd
, &dd
->msix_entries
[i
]);
12813 free_irq(me
->msix
.vector
, me
->arg
);
12817 if (dd
->requested_intx_irq
) {
12818 free_irq(dd
->pcidev
->irq
, dd
);
12819 dd
->requested_intx_irq
= 0;
12823 /* turn off interrupts */
12824 if (dd
->num_msix_entries
) {
12826 pci_disable_msix(dd
->pcidev
);
12829 disable_intx(dd
->pcidev
);
12832 /* clean structures */
12833 kfree(dd
->msix_entries
);
12834 dd
->msix_entries
= NULL
;
12835 dd
->num_msix_entries
= 0;
12839 * Remap the interrupt source from the general handler to the given MSI-X
12842 static void remap_intr(struct hfi1_devdata
*dd
, int isrc
, int msix_intr
)
12847 /* clear from the handled mask of the general interrupt */
12850 dd
->gi_mask
[m
] &= ~((u64
)1 << n
);
12852 /* direct the chip source to the given MSI-X interrupt */
12855 reg
= read_csr(dd
, CCE_INT_MAP
+ (8 * m
));
12856 reg
&= ~((u64
)0xff << (8 * n
));
12857 reg
|= ((u64
)msix_intr
& 0xff) << (8 * n
);
12858 write_csr(dd
, CCE_INT_MAP
+ (8 * m
), reg
);
12861 static void remap_sdma_interrupts(struct hfi1_devdata
*dd
,
12862 int engine
, int msix_intr
)
12865 * SDMA engine interrupt sources grouped by type, rather than
12866 * engine. Per-engine interrupts are as follows:
12871 remap_intr(dd
, IS_SDMA_START
+ 0 * TXE_NUM_SDMA_ENGINES
+ engine
,
12873 remap_intr(dd
, IS_SDMA_START
+ 1 * TXE_NUM_SDMA_ENGINES
+ engine
,
12875 remap_intr(dd
, IS_SDMA_START
+ 2 * TXE_NUM_SDMA_ENGINES
+ engine
,
12879 static int request_intx_irq(struct hfi1_devdata
*dd
)
12883 snprintf(dd
->intx_name
, sizeof(dd
->intx_name
), DRIVER_NAME
"_%d",
12885 ret
= request_irq(dd
->pcidev
->irq
, general_interrupt
,
12886 IRQF_SHARED
, dd
->intx_name
, dd
);
12888 dd_dev_err(dd
, "unable to request INTx interrupt, err %d\n",
12891 dd
->requested_intx_irq
= 1;
12895 static int request_msix_irqs(struct hfi1_devdata
*dd
)
12897 int first_general
, last_general
;
12898 int first_sdma
, last_sdma
;
12899 int first_rx
, last_rx
;
12902 /* calculate the ranges we are going to use */
12904 last_general
= first_general
+ 1;
12905 first_sdma
= last_general
;
12906 last_sdma
= first_sdma
+ dd
->num_sdma
;
12907 first_rx
= last_sdma
;
12908 last_rx
= first_rx
+ dd
->n_krcv_queues
+ HFI1_NUM_VNIC_CTXT
;
12910 /* VNIC MSIx interrupts get mapped when VNIC contexts are created */
12911 dd
->first_dyn_msix_idx
= first_rx
+ dd
->n_krcv_queues
;
12914 * Sanity check - the code expects all SDMA chip source
12915 * interrupts to be in the same CSR, starting at bit 0. Verify
12916 * that this is true by checking the bit location of the start.
12918 BUILD_BUG_ON(IS_SDMA_START
% 64);
12920 for (i
= 0; i
< dd
->num_msix_entries
; i
++) {
12921 struct hfi1_msix_entry
*me
= &dd
->msix_entries
[i
];
12922 const char *err_info
;
12923 irq_handler_t handler
;
12924 irq_handler_t thread
= NULL
;
12927 struct hfi1_ctxtdata
*rcd
= NULL
;
12928 struct sdma_engine
*sde
= NULL
;
12930 /* obtain the arguments to request_irq */
12931 if (first_general
<= i
&& i
< last_general
) {
12932 idx
= i
- first_general
;
12933 handler
= general_interrupt
;
12935 snprintf(me
->name
, sizeof(me
->name
),
12936 DRIVER_NAME
"_%d", dd
->unit
);
12937 err_info
= "general";
12938 me
->type
= IRQ_GENERAL
;
12939 } else if (first_sdma
<= i
&& i
< last_sdma
) {
12940 idx
= i
- first_sdma
;
12941 sde
= &dd
->per_sdma
[idx
];
12942 handler
= sdma_interrupt
;
12944 snprintf(me
->name
, sizeof(me
->name
),
12945 DRIVER_NAME
"_%d sdma%d", dd
->unit
, idx
);
12947 remap_sdma_interrupts(dd
, idx
, i
);
12948 me
->type
= IRQ_SDMA
;
12949 } else if (first_rx
<= i
&& i
< last_rx
) {
12950 idx
= i
- first_rx
;
12951 rcd
= dd
->rcd
[idx
];
12954 * Set the interrupt register and mask for this
12955 * context's interrupt.
12957 rcd
->ireg
= (IS_RCVAVAIL_START
+ idx
) / 64;
12958 rcd
->imask
= ((u64
)1) <<
12959 ((IS_RCVAVAIL_START
+ idx
) % 64);
12960 handler
= receive_context_interrupt
;
12961 thread
= receive_context_thread
;
12963 snprintf(me
->name
, sizeof(me
->name
),
12964 DRIVER_NAME
"_%d kctxt%d",
12966 err_info
= "receive context";
12967 remap_intr(dd
, IS_RCVAVAIL_START
+ idx
, i
);
12968 me
->type
= IRQ_RCVCTXT
;
12969 rcd
->msix_intr
= i
;
12972 /* not in our expected range - complain, then
12976 "Unexpected extra MSI-X interrupt %d\n", i
);
12979 /* no argument, no interrupt */
12982 /* make sure the name is terminated */
12983 me
->name
[sizeof(me
->name
) - 1] = 0;
12985 ret
= request_threaded_irq(me
->msix
.vector
, handler
, thread
, 0,
12989 "unable to allocate %s interrupt, vector %d, index %d, err %d\n",
12990 err_info
, me
->msix
.vector
, idx
, ret
);
12994 * assign arg after request_irq call, so it will be
12999 ret
= hfi1_get_irq_affinity(dd
, me
);
13002 "unable to pin IRQ %d\n", ret
);
13008 void hfi1_vnic_synchronize_irq(struct hfi1_devdata
*dd
)
13012 if (!dd
->num_msix_entries
) {
13013 synchronize_irq(dd
->pcidev
->irq
);
13017 for (i
= 0; i
< dd
->vnic
.num_ctxt
; i
++) {
13018 struct hfi1_ctxtdata
*rcd
= dd
->vnic
.ctxt
[i
];
13019 struct hfi1_msix_entry
*me
= &dd
->msix_entries
[rcd
->msix_intr
];
13021 synchronize_irq(me
->msix
.vector
);
13025 void hfi1_reset_vnic_msix_info(struct hfi1_ctxtdata
*rcd
)
13027 struct hfi1_devdata
*dd
= rcd
->dd
;
13028 struct hfi1_msix_entry
*me
= &dd
->msix_entries
[rcd
->msix_intr
];
13030 if (!me
->arg
) /* => no irq, no affinity */
13033 hfi1_put_irq_affinity(dd
, me
);
13034 free_irq(me
->msix
.vector
, me
->arg
);
13039 void hfi1_set_vnic_msix_info(struct hfi1_ctxtdata
*rcd
)
13041 struct hfi1_devdata
*dd
= rcd
->dd
;
13042 struct hfi1_msix_entry
*me
;
13043 int idx
= rcd
->ctxt
;
13047 rcd
->msix_intr
= dd
->vnic
.msix_idx
++;
13048 me
= &dd
->msix_entries
[rcd
->msix_intr
];
13051 * Set the interrupt register and mask for this
13052 * context's interrupt.
13054 rcd
->ireg
= (IS_RCVAVAIL_START
+ idx
) / 64;
13055 rcd
->imask
= ((u64
)1) <<
13056 ((IS_RCVAVAIL_START
+ idx
) % 64);
13058 snprintf(me
->name
, sizeof(me
->name
),
13059 DRIVER_NAME
"_%d kctxt%d", dd
->unit
, idx
);
13060 me
->name
[sizeof(me
->name
) - 1] = 0;
13061 me
->type
= IRQ_RCVCTXT
;
13063 remap_intr(dd
, IS_RCVAVAIL_START
+ idx
, rcd
->msix_intr
);
13065 ret
= request_threaded_irq(me
->msix
.vector
, receive_context_interrupt
,
13066 receive_context_thread
, 0, me
->name
, arg
);
13068 dd_dev_err(dd
, "vnic irq request (vector %d, idx %d) fail %d\n",
13069 me
->msix
.vector
, idx
, ret
);
13073 * assign arg after request_irq call, so it will be
13078 ret
= hfi1_get_irq_affinity(dd
, me
);
13081 "unable to pin IRQ %d\n", ret
);
13082 free_irq(me
->msix
.vector
, me
->arg
);
13087 * Set the general handler to accept all interrupts, remap all
13088 * chip interrupts back to MSI-X 0.
13090 static void reset_interrupts(struct hfi1_devdata
*dd
)
13094 /* all interrupts handled by the general handler */
13095 for (i
= 0; i
< CCE_NUM_INT_CSRS
; i
++)
13096 dd
->gi_mask
[i
] = ~(u64
)0;
13098 /* all chip interrupts map to MSI-X 0 */
13099 for (i
= 0; i
< CCE_NUM_INT_MAP_CSRS
; i
++)
13100 write_csr(dd
, CCE_INT_MAP
+ (8 * i
), 0);
13103 static int set_up_interrupts(struct hfi1_devdata
*dd
)
13105 struct hfi1_msix_entry
*entries
;
13106 u32 total
, request
;
13108 int single_interrupt
= 0; /* we expect to have all the interrupts */
13112 * 1 general, "slow path" interrupt (includes the SDMA engines
13113 * slow source, SDMACleanupDone)
13114 * N interrupts - one per used SDMA engine
13115 * M interrupt - one per kernel receive context
13117 total
= 1 + dd
->num_sdma
+ dd
->n_krcv_queues
+ HFI1_NUM_VNIC_CTXT
;
13119 entries
= kcalloc(total
, sizeof(*entries
), GFP_KERNEL
);
13124 /* 1-1 MSI-X entry assignment */
13125 for (i
= 0; i
< total
; i
++)
13126 entries
[i
].msix
.entry
= i
;
13128 /* ask for MSI-X interrupts */
13130 request_msix(dd
, &request
, entries
);
13132 if (request
== 0) {
13134 /* dd->num_msix_entries already zero */
13136 single_interrupt
= 1;
13137 dd_dev_err(dd
, "MSI-X failed, using INTx interrupts\n");
13140 dd
->num_msix_entries
= request
;
13141 dd
->msix_entries
= entries
;
13143 if (request
!= total
) {
13144 /* using MSI-X, with reduced interrupts */
13147 "cannot handle reduced interrupt case, want %u, got %u\n",
13152 dd_dev_info(dd
, "%u MSI-X interrupts allocated\n", total
);
13155 /* mask all interrupts */
13156 set_intr_state(dd
, 0);
13157 /* clear all pending interrupts */
13158 clear_all_interrupts(dd
);
13160 /* reset general handler mask, chip MSI-X mappings */
13161 reset_interrupts(dd
);
13163 if (single_interrupt
)
13164 ret
= request_intx_irq(dd
);
13166 ret
= request_msix_irqs(dd
);
13173 clean_up_interrupts(dd
);
13178 * Set up context values in dd. Sets:
13180 * num_rcv_contexts - number of contexts being used
13181 * n_krcv_queues - number of kernel contexts
13182 * first_dyn_alloc_ctxt - first dynamically allocated context
13183 * in array of contexts
13184 * freectxts - number of free user contexts
13185 * num_send_contexts - number of PIO send contexts being used
13187 static int set_up_context_variables(struct hfi1_devdata
*dd
)
13189 unsigned long num_kernel_contexts
;
13190 int total_contexts
;
13194 int user_rmt_reduced
;
13197 * Kernel receive contexts:
13198 * - Context 0 - control context (VL15/multicast/error)
13199 * - Context 1 - first kernel context
13200 * - Context 2 - second kernel context
13205 * n_krcvqs is the sum of module parameter kernel receive
13206 * contexts, krcvqs[]. It does not include the control
13207 * context, so add that.
13209 num_kernel_contexts
= n_krcvqs
+ 1;
13211 num_kernel_contexts
= DEFAULT_KRCVQS
+ 1;
13213 * Every kernel receive context needs an ACK send context.
13214 * one send context is allocated for each VL{0-7} and VL15
13216 if (num_kernel_contexts
> (dd
->chip_send_contexts
- num_vls
- 1)) {
13218 "Reducing # kernel rcv contexts to: %d, from %lu\n",
13219 (int)(dd
->chip_send_contexts
- num_vls
- 1),
13220 num_kernel_contexts
);
13221 num_kernel_contexts
= dd
->chip_send_contexts
- num_vls
- 1;
13225 * - default to 1 user context per real (non-HT) CPU core if
13226 * num_user_contexts is negative
13228 if (num_user_contexts
< 0)
13229 num_user_contexts
=
13230 cpumask_weight(&node_affinity
.real_cpu_mask
);
13232 total_contexts
= num_kernel_contexts
+ num_user_contexts
;
13235 * Adjust the counts given a global max.
13237 if (total_contexts
> dd
->chip_rcv_contexts
) {
13239 "Reducing # user receive contexts to: %d, from %d\n",
13240 (int)(dd
->chip_rcv_contexts
- num_kernel_contexts
),
13241 (int)num_user_contexts
);
13242 num_user_contexts
= dd
->chip_rcv_contexts
- num_kernel_contexts
;
13244 total_contexts
= num_kernel_contexts
+ num_user_contexts
;
13247 /* each user context requires an entry in the RMT */
13248 qos_rmt_count
= qos_rmt_entries(dd
, NULL
, NULL
);
13249 if (qos_rmt_count
+ num_user_contexts
> NUM_MAP_ENTRIES
) {
13250 user_rmt_reduced
= NUM_MAP_ENTRIES
- qos_rmt_count
;
13252 "RMT size is reducing the number of user receive contexts from %d to %d\n",
13253 (int)num_user_contexts
,
13256 num_user_contexts
= user_rmt_reduced
;
13257 total_contexts
= num_kernel_contexts
+ num_user_contexts
;
13260 /* Accommodate VNIC contexts */
13261 if ((total_contexts
+ HFI1_NUM_VNIC_CTXT
) <= dd
->chip_rcv_contexts
)
13262 total_contexts
+= HFI1_NUM_VNIC_CTXT
;
13264 /* the first N are kernel contexts, the rest are user/vnic contexts */
13265 dd
->num_rcv_contexts
= total_contexts
;
13266 dd
->n_krcv_queues
= num_kernel_contexts
;
13267 dd
->first_dyn_alloc_ctxt
= num_kernel_contexts
;
13268 dd
->num_user_contexts
= num_user_contexts
;
13269 dd
->freectxts
= num_user_contexts
;
13271 "rcv contexts: chip %d, used %d (kernel %d, user %d)\n",
13272 (int)dd
->chip_rcv_contexts
,
13273 (int)dd
->num_rcv_contexts
,
13274 (int)dd
->n_krcv_queues
,
13275 (int)dd
->num_rcv_contexts
- dd
->n_krcv_queues
);
13278 * Receive array allocation:
13279 * All RcvArray entries are divided into groups of 8. This
13280 * is required by the hardware and will speed up writes to
13281 * consecutive entries by using write-combining of the entire
13284 * The number of groups are evenly divided among all contexts.
13285 * any left over groups will be given to the first N user
13288 dd
->rcv_entries
.group_size
= RCV_INCREMENT
;
13289 ngroups
= dd
->chip_rcv_array_count
/ dd
->rcv_entries
.group_size
;
13290 dd
->rcv_entries
.ngroups
= ngroups
/ dd
->num_rcv_contexts
;
13291 dd
->rcv_entries
.nctxt_extra
= ngroups
-
13292 (dd
->num_rcv_contexts
* dd
->rcv_entries
.ngroups
);
13293 dd_dev_info(dd
, "RcvArray groups %u, ctxts extra %u\n",
13294 dd
->rcv_entries
.ngroups
,
13295 dd
->rcv_entries
.nctxt_extra
);
13296 if (dd
->rcv_entries
.ngroups
* dd
->rcv_entries
.group_size
>
13297 MAX_EAGER_ENTRIES
* 2) {
13298 dd
->rcv_entries
.ngroups
= (MAX_EAGER_ENTRIES
* 2) /
13299 dd
->rcv_entries
.group_size
;
13301 "RcvArray group count too high, change to %u\n",
13302 dd
->rcv_entries
.ngroups
);
13303 dd
->rcv_entries
.nctxt_extra
= 0;
13306 * PIO send contexts
13308 ret
= init_sc_pools_and_sizes(dd
);
13309 if (ret
>= 0) { /* success */
13310 dd
->num_send_contexts
= ret
;
13313 "send contexts: chip %d, used %d (kernel %d, ack %d, user %d, vl15 %d)\n",
13314 dd
->chip_send_contexts
,
13315 dd
->num_send_contexts
,
13316 dd
->sc_sizes
[SC_KERNEL
].count
,
13317 dd
->sc_sizes
[SC_ACK
].count
,
13318 dd
->sc_sizes
[SC_USER
].count
,
13319 dd
->sc_sizes
[SC_VL15
].count
);
13320 ret
= 0; /* success */
13327 * Set the device/port partition key table. The MAD code
13328 * will ensure that, at least, the partial management
13329 * partition key is present in the table.
13331 static void set_partition_keys(struct hfi1_pportdata
*ppd
)
13333 struct hfi1_devdata
*dd
= ppd
->dd
;
13337 dd_dev_info(dd
, "Setting partition keys\n");
13338 for (i
= 0; i
< hfi1_get_npkeys(dd
); i
++) {
13339 reg
|= (ppd
->pkeys
[i
] &
13340 RCV_PARTITION_KEY_PARTITION_KEY_A_MASK
) <<
13342 RCV_PARTITION_KEY_PARTITION_KEY_B_SHIFT
);
13343 /* Each register holds 4 PKey values. */
13344 if ((i
% 4) == 3) {
13345 write_csr(dd
, RCV_PARTITION_KEY
+
13346 ((i
- 3) * 2), reg
);
13351 /* Always enable HW pkeys check when pkeys table is set */
13352 add_rcvctrl(dd
, RCV_CTRL_RCV_PARTITION_KEY_ENABLE_SMASK
);
13356 * These CSRs and memories are uninitialized on reset and must be
13357 * written before reading to set the ECC/parity bits.
13359 * NOTE: All user context CSRs that are not mmaped write-only
13360 * (e.g. the TID flows) must be initialized even if the driver never
13363 static void write_uninitialized_csrs_and_memories(struct hfi1_devdata
*dd
)
13368 for (i
= 0; i
< CCE_NUM_INT_MAP_CSRS
; i
++)
13369 write_csr(dd
, CCE_INT_MAP
+ (8 * i
), 0);
13371 /* SendCtxtCreditReturnAddr */
13372 for (i
= 0; i
< dd
->chip_send_contexts
; i
++)
13373 write_kctxt_csr(dd
, i
, SEND_CTXT_CREDIT_RETURN_ADDR
, 0);
13375 /* PIO Send buffers */
13376 /* SDMA Send buffers */
13378 * These are not normally read, and (presently) have no method
13379 * to be read, so are not pre-initialized
13383 /* RcvHdrTailAddr */
13384 /* RcvTidFlowTable */
13385 for (i
= 0; i
< dd
->chip_rcv_contexts
; i
++) {
13386 write_kctxt_csr(dd
, i
, RCV_HDR_ADDR
, 0);
13387 write_kctxt_csr(dd
, i
, RCV_HDR_TAIL_ADDR
, 0);
13388 for (j
= 0; j
< RXE_NUM_TID_FLOWS
; j
++)
13389 write_uctxt_csr(dd
, i
, RCV_TID_FLOW_TABLE
+ (8 * j
), 0);
13393 for (i
= 0; i
< dd
->chip_rcv_array_count
; i
++)
13394 write_csr(dd
, RCV_ARRAY
+ (8 * i
),
13395 RCV_ARRAY_RT_WRITE_ENABLE_SMASK
);
13397 /* RcvQPMapTable */
13398 for (i
= 0; i
< 32; i
++)
13399 write_csr(dd
, RCV_QP_MAP_TABLE
+ (8 * i
), 0);
13403 * Use the ctrl_bits in CceCtrl to clear the status_bits in CceStatus.
13405 static void clear_cce_status(struct hfi1_devdata
*dd
, u64 status_bits
,
13408 unsigned long timeout
;
13411 /* is the condition present? */
13412 reg
= read_csr(dd
, CCE_STATUS
);
13413 if ((reg
& status_bits
) == 0)
13416 /* clear the condition */
13417 write_csr(dd
, CCE_CTRL
, ctrl_bits
);
13419 /* wait for the condition to clear */
13420 timeout
= jiffies
+ msecs_to_jiffies(CCE_STATUS_TIMEOUT
);
13422 reg
= read_csr(dd
, CCE_STATUS
);
13423 if ((reg
& status_bits
) == 0)
13425 if (time_after(jiffies
, timeout
)) {
13427 "Timeout waiting for CceStatus to clear bits 0x%llx, remaining 0x%llx\n",
13428 status_bits
, reg
& status_bits
);
13435 /* set CCE CSRs to chip reset defaults */
13436 static void reset_cce_csrs(struct hfi1_devdata
*dd
)
13440 /* CCE_REVISION read-only */
13441 /* CCE_REVISION2 read-only */
13442 /* CCE_CTRL - bits clear automatically */
13443 /* CCE_STATUS read-only, use CceCtrl to clear */
13444 clear_cce_status(dd
, ALL_FROZE
, CCE_CTRL_SPC_UNFREEZE_SMASK
);
13445 clear_cce_status(dd
, ALL_TXE_PAUSE
, CCE_CTRL_TXE_RESUME_SMASK
);
13446 clear_cce_status(dd
, ALL_RXE_PAUSE
, CCE_CTRL_RXE_RESUME_SMASK
);
13447 for (i
= 0; i
< CCE_NUM_SCRATCH
; i
++)
13448 write_csr(dd
, CCE_SCRATCH
+ (8 * i
), 0);
13449 /* CCE_ERR_STATUS read-only */
13450 write_csr(dd
, CCE_ERR_MASK
, 0);
13451 write_csr(dd
, CCE_ERR_CLEAR
, ~0ull);
13452 /* CCE_ERR_FORCE leave alone */
13453 for (i
= 0; i
< CCE_NUM_32_BIT_COUNTERS
; i
++)
13454 write_csr(dd
, CCE_COUNTER_ARRAY32
+ (8 * i
), 0);
13455 write_csr(dd
, CCE_DC_CTRL
, CCE_DC_CTRL_RESETCSR
);
13456 /* CCE_PCIE_CTRL leave alone */
13457 for (i
= 0; i
< CCE_NUM_MSIX_VECTORS
; i
++) {
13458 write_csr(dd
, CCE_MSIX_TABLE_LOWER
+ (8 * i
), 0);
13459 write_csr(dd
, CCE_MSIX_TABLE_UPPER
+ (8 * i
),
13460 CCE_MSIX_TABLE_UPPER_RESETCSR
);
13462 for (i
= 0; i
< CCE_NUM_MSIX_PBAS
; i
++) {
13463 /* CCE_MSIX_PBA read-only */
13464 write_csr(dd
, CCE_MSIX_INT_GRANTED
, ~0ull);
13465 write_csr(dd
, CCE_MSIX_VEC_CLR_WITHOUT_INT
, ~0ull);
13467 for (i
= 0; i
< CCE_NUM_INT_MAP_CSRS
; i
++)
13468 write_csr(dd
, CCE_INT_MAP
, 0);
13469 for (i
= 0; i
< CCE_NUM_INT_CSRS
; i
++) {
13470 /* CCE_INT_STATUS read-only */
13471 write_csr(dd
, CCE_INT_MASK
+ (8 * i
), 0);
13472 write_csr(dd
, CCE_INT_CLEAR
+ (8 * i
), ~0ull);
13473 /* CCE_INT_FORCE leave alone */
13474 /* CCE_INT_BLOCKED read-only */
13476 for (i
= 0; i
< CCE_NUM_32_BIT_INT_COUNTERS
; i
++)
13477 write_csr(dd
, CCE_INT_COUNTER_ARRAY32
+ (8 * i
), 0);
13480 /* set MISC CSRs to chip reset defaults */
13481 static void reset_misc_csrs(struct hfi1_devdata
*dd
)
13485 for (i
= 0; i
< 32; i
++) {
13486 write_csr(dd
, MISC_CFG_RSA_R2
+ (8 * i
), 0);
13487 write_csr(dd
, MISC_CFG_RSA_SIGNATURE
+ (8 * i
), 0);
13488 write_csr(dd
, MISC_CFG_RSA_MODULUS
+ (8 * i
), 0);
13491 * MISC_CFG_SHA_PRELOAD leave alone - always reads 0 and can
13492 * only be written 128-byte chunks
13494 /* init RSA engine to clear lingering errors */
13495 write_csr(dd
, MISC_CFG_RSA_CMD
, 1);
13496 write_csr(dd
, MISC_CFG_RSA_MU
, 0);
13497 write_csr(dd
, MISC_CFG_FW_CTRL
, 0);
13498 /* MISC_STS_8051_DIGEST read-only */
13499 /* MISC_STS_SBM_DIGEST read-only */
13500 /* MISC_STS_PCIE_DIGEST read-only */
13501 /* MISC_STS_FAB_DIGEST read-only */
13502 /* MISC_ERR_STATUS read-only */
13503 write_csr(dd
, MISC_ERR_MASK
, 0);
13504 write_csr(dd
, MISC_ERR_CLEAR
, ~0ull);
13505 /* MISC_ERR_FORCE leave alone */
13508 /* set TXE CSRs to chip reset defaults */
13509 static void reset_txe_csrs(struct hfi1_devdata
*dd
)
13516 write_csr(dd
, SEND_CTRL
, 0);
13517 __cm_reset(dd
, 0); /* reset CM internal state */
13518 /* SEND_CONTEXTS read-only */
13519 /* SEND_DMA_ENGINES read-only */
13520 /* SEND_PIO_MEM_SIZE read-only */
13521 /* SEND_DMA_MEM_SIZE read-only */
13522 write_csr(dd
, SEND_HIGH_PRIORITY_LIMIT
, 0);
13523 pio_reset_all(dd
); /* SEND_PIO_INIT_CTXT */
13524 /* SEND_PIO_ERR_STATUS read-only */
13525 write_csr(dd
, SEND_PIO_ERR_MASK
, 0);
13526 write_csr(dd
, SEND_PIO_ERR_CLEAR
, ~0ull);
13527 /* SEND_PIO_ERR_FORCE leave alone */
13528 /* SEND_DMA_ERR_STATUS read-only */
13529 write_csr(dd
, SEND_DMA_ERR_MASK
, 0);
13530 write_csr(dd
, SEND_DMA_ERR_CLEAR
, ~0ull);
13531 /* SEND_DMA_ERR_FORCE leave alone */
13532 /* SEND_EGRESS_ERR_STATUS read-only */
13533 write_csr(dd
, SEND_EGRESS_ERR_MASK
, 0);
13534 write_csr(dd
, SEND_EGRESS_ERR_CLEAR
, ~0ull);
13535 /* SEND_EGRESS_ERR_FORCE leave alone */
13536 write_csr(dd
, SEND_BTH_QP
, 0);
13537 write_csr(dd
, SEND_STATIC_RATE_CONTROL
, 0);
13538 write_csr(dd
, SEND_SC2VLT0
, 0);
13539 write_csr(dd
, SEND_SC2VLT1
, 0);
13540 write_csr(dd
, SEND_SC2VLT2
, 0);
13541 write_csr(dd
, SEND_SC2VLT3
, 0);
13542 write_csr(dd
, SEND_LEN_CHECK0
, 0);
13543 write_csr(dd
, SEND_LEN_CHECK1
, 0);
13544 /* SEND_ERR_STATUS read-only */
13545 write_csr(dd
, SEND_ERR_MASK
, 0);
13546 write_csr(dd
, SEND_ERR_CLEAR
, ~0ull);
13547 /* SEND_ERR_FORCE read-only */
13548 for (i
= 0; i
< VL_ARB_LOW_PRIO_TABLE_SIZE
; i
++)
13549 write_csr(dd
, SEND_LOW_PRIORITY_LIST
+ (8 * i
), 0);
13550 for (i
= 0; i
< VL_ARB_HIGH_PRIO_TABLE_SIZE
; i
++)
13551 write_csr(dd
, SEND_HIGH_PRIORITY_LIST
+ (8 * i
), 0);
13552 for (i
= 0; i
< dd
->chip_send_contexts
/ NUM_CONTEXTS_PER_SET
; i
++)
13553 write_csr(dd
, SEND_CONTEXT_SET_CTRL
+ (8 * i
), 0);
13554 for (i
= 0; i
< TXE_NUM_32_BIT_COUNTER
; i
++)
13555 write_csr(dd
, SEND_COUNTER_ARRAY32
+ (8 * i
), 0);
13556 for (i
= 0; i
< TXE_NUM_64_BIT_COUNTER
; i
++)
13557 write_csr(dd
, SEND_COUNTER_ARRAY64
+ (8 * i
), 0);
13558 write_csr(dd
, SEND_CM_CTRL
, SEND_CM_CTRL_RESETCSR
);
13559 write_csr(dd
, SEND_CM_GLOBAL_CREDIT
, SEND_CM_GLOBAL_CREDIT_RESETCSR
);
13560 /* SEND_CM_CREDIT_USED_STATUS read-only */
13561 write_csr(dd
, SEND_CM_TIMER_CTRL
, 0);
13562 write_csr(dd
, SEND_CM_LOCAL_AU_TABLE0_TO3
, 0);
13563 write_csr(dd
, SEND_CM_LOCAL_AU_TABLE4_TO7
, 0);
13564 write_csr(dd
, SEND_CM_REMOTE_AU_TABLE0_TO3
, 0);
13565 write_csr(dd
, SEND_CM_REMOTE_AU_TABLE4_TO7
, 0);
13566 for (i
= 0; i
< TXE_NUM_DATA_VL
; i
++)
13567 write_csr(dd
, SEND_CM_CREDIT_VL
+ (8 * i
), 0);
13568 write_csr(dd
, SEND_CM_CREDIT_VL15
, 0);
13569 /* SEND_CM_CREDIT_USED_VL read-only */
13570 /* SEND_CM_CREDIT_USED_VL15 read-only */
13571 /* SEND_EGRESS_CTXT_STATUS read-only */
13572 /* SEND_EGRESS_SEND_DMA_STATUS read-only */
13573 write_csr(dd
, SEND_EGRESS_ERR_INFO
, ~0ull);
13574 /* SEND_EGRESS_ERR_INFO read-only */
13575 /* SEND_EGRESS_ERR_SOURCE read-only */
13578 * TXE Per-Context CSRs
13580 for (i
= 0; i
< dd
->chip_send_contexts
; i
++) {
13581 write_kctxt_csr(dd
, i
, SEND_CTXT_CTRL
, 0);
13582 write_kctxt_csr(dd
, i
, SEND_CTXT_CREDIT_CTRL
, 0);
13583 write_kctxt_csr(dd
, i
, SEND_CTXT_CREDIT_RETURN_ADDR
, 0);
13584 write_kctxt_csr(dd
, i
, SEND_CTXT_CREDIT_FORCE
, 0);
13585 write_kctxt_csr(dd
, i
, SEND_CTXT_ERR_MASK
, 0);
13586 write_kctxt_csr(dd
, i
, SEND_CTXT_ERR_CLEAR
, ~0ull);
13587 write_kctxt_csr(dd
, i
, SEND_CTXT_CHECK_ENABLE
, 0);
13588 write_kctxt_csr(dd
, i
, SEND_CTXT_CHECK_VL
, 0);
13589 write_kctxt_csr(dd
, i
, SEND_CTXT_CHECK_JOB_KEY
, 0);
13590 write_kctxt_csr(dd
, i
, SEND_CTXT_CHECK_PARTITION_KEY
, 0);
13591 write_kctxt_csr(dd
, i
, SEND_CTXT_CHECK_SLID
, 0);
13592 write_kctxt_csr(dd
, i
, SEND_CTXT_CHECK_OPCODE
, 0);
13596 * TXE Per-SDMA CSRs
13598 for (i
= 0; i
< dd
->chip_sdma_engines
; i
++) {
13599 write_kctxt_csr(dd
, i
, SEND_DMA_CTRL
, 0);
13600 /* SEND_DMA_STATUS read-only */
13601 write_kctxt_csr(dd
, i
, SEND_DMA_BASE_ADDR
, 0);
13602 write_kctxt_csr(dd
, i
, SEND_DMA_LEN_GEN
, 0);
13603 write_kctxt_csr(dd
, i
, SEND_DMA_TAIL
, 0);
13604 /* SEND_DMA_HEAD read-only */
13605 write_kctxt_csr(dd
, i
, SEND_DMA_HEAD_ADDR
, 0);
13606 write_kctxt_csr(dd
, i
, SEND_DMA_PRIORITY_THLD
, 0);
13607 /* SEND_DMA_IDLE_CNT read-only */
13608 write_kctxt_csr(dd
, i
, SEND_DMA_RELOAD_CNT
, 0);
13609 write_kctxt_csr(dd
, i
, SEND_DMA_DESC_CNT
, 0);
13610 /* SEND_DMA_DESC_FETCHED_CNT read-only */
13611 /* SEND_DMA_ENG_ERR_STATUS read-only */
13612 write_kctxt_csr(dd
, i
, SEND_DMA_ENG_ERR_MASK
, 0);
13613 write_kctxt_csr(dd
, i
, SEND_DMA_ENG_ERR_CLEAR
, ~0ull);
13614 /* SEND_DMA_ENG_ERR_FORCE leave alone */
13615 write_kctxt_csr(dd
, i
, SEND_DMA_CHECK_ENABLE
, 0);
13616 write_kctxt_csr(dd
, i
, SEND_DMA_CHECK_VL
, 0);
13617 write_kctxt_csr(dd
, i
, SEND_DMA_CHECK_JOB_KEY
, 0);
13618 write_kctxt_csr(dd
, i
, SEND_DMA_CHECK_PARTITION_KEY
, 0);
13619 write_kctxt_csr(dd
, i
, SEND_DMA_CHECK_SLID
, 0);
13620 write_kctxt_csr(dd
, i
, SEND_DMA_CHECK_OPCODE
, 0);
13621 write_kctxt_csr(dd
, i
, SEND_DMA_MEMORY
, 0);
13627 * o Packet ingress is disabled, i.e. RcvCtrl.RcvPortEnable == 0
13629 static void init_rbufs(struct hfi1_devdata
*dd
)
13635 * Wait for DMA to stop: RxRbufPktPending and RxPktInProgress are
13640 reg
= read_csr(dd
, RCV_STATUS
);
13641 if ((reg
& (RCV_STATUS_RX_RBUF_PKT_PENDING_SMASK
13642 | RCV_STATUS_RX_PKT_IN_PROGRESS_SMASK
)) == 0)
13645 * Give up after 1ms - maximum wait time.
13647 * RBuf size is 136KiB. Slowest possible is PCIe Gen1 x1 at
13648 * 250MB/s bandwidth. Lower rate to 66% for overhead to get:
13649 * 136 KB / (66% * 250MB/s) = 844us
13651 if (count
++ > 500) {
13653 "%s: in-progress DMA not clearing: RcvStatus 0x%llx, continuing\n",
13657 udelay(2); /* do not busy-wait the CSR */
13660 /* start the init - expect RcvCtrl to be 0 */
13661 write_csr(dd
, RCV_CTRL
, RCV_CTRL_RX_RBUF_INIT_SMASK
);
13664 * Read to force the write of Rcvtrl.RxRbufInit. There is a brief
13665 * period after the write before RcvStatus.RxRbufInitDone is valid.
13666 * The delay in the first run through the loop below is sufficient and
13667 * required before the first read of RcvStatus.RxRbufInintDone.
13669 read_csr(dd
, RCV_CTRL
);
13671 /* wait for the init to finish */
13674 /* delay is required first time through - see above */
13675 udelay(2); /* do not busy-wait the CSR */
13676 reg
= read_csr(dd
, RCV_STATUS
);
13677 if (reg
& (RCV_STATUS_RX_RBUF_INIT_DONE_SMASK
))
13680 /* give up after 100us - slowest possible at 33MHz is 73us */
13681 if (count
++ > 50) {
13683 "%s: RcvStatus.RxRbufInit not set, continuing\n",
13690 /* set RXE CSRs to chip reset defaults */
13691 static void reset_rxe_csrs(struct hfi1_devdata
*dd
)
13698 write_csr(dd
, RCV_CTRL
, 0);
13700 /* RCV_STATUS read-only */
13701 /* RCV_CONTEXTS read-only */
13702 /* RCV_ARRAY_CNT read-only */
13703 /* RCV_BUF_SIZE read-only */
13704 write_csr(dd
, RCV_BTH_QP
, 0);
13705 write_csr(dd
, RCV_MULTICAST
, 0);
13706 write_csr(dd
, RCV_BYPASS
, 0);
13707 write_csr(dd
, RCV_VL15
, 0);
13708 /* this is a clear-down */
13709 write_csr(dd
, RCV_ERR_INFO
,
13710 RCV_ERR_INFO_RCV_EXCESS_BUFFER_OVERRUN_SMASK
);
13711 /* RCV_ERR_STATUS read-only */
13712 write_csr(dd
, RCV_ERR_MASK
, 0);
13713 write_csr(dd
, RCV_ERR_CLEAR
, ~0ull);
13714 /* RCV_ERR_FORCE leave alone */
13715 for (i
= 0; i
< 32; i
++)
13716 write_csr(dd
, RCV_QP_MAP_TABLE
+ (8 * i
), 0);
13717 for (i
= 0; i
< 4; i
++)
13718 write_csr(dd
, RCV_PARTITION_KEY
+ (8 * i
), 0);
13719 for (i
= 0; i
< RXE_NUM_32_BIT_COUNTERS
; i
++)
13720 write_csr(dd
, RCV_COUNTER_ARRAY32
+ (8 * i
), 0);
13721 for (i
= 0; i
< RXE_NUM_64_BIT_COUNTERS
; i
++)
13722 write_csr(dd
, RCV_COUNTER_ARRAY64
+ (8 * i
), 0);
13723 for (i
= 0; i
< RXE_NUM_RSM_INSTANCES
; i
++)
13724 clear_rsm_rule(dd
, i
);
13725 for (i
= 0; i
< 32; i
++)
13726 write_csr(dd
, RCV_RSM_MAP_TABLE
+ (8 * i
), 0);
13729 * RXE Kernel and User Per-Context CSRs
13731 for (i
= 0; i
< dd
->chip_rcv_contexts
; i
++) {
13733 write_kctxt_csr(dd
, i
, RCV_CTXT_CTRL
, 0);
13734 /* RCV_CTXT_STATUS read-only */
13735 write_kctxt_csr(dd
, i
, RCV_EGR_CTRL
, 0);
13736 write_kctxt_csr(dd
, i
, RCV_TID_CTRL
, 0);
13737 write_kctxt_csr(dd
, i
, RCV_KEY_CTRL
, 0);
13738 write_kctxt_csr(dd
, i
, RCV_HDR_ADDR
, 0);
13739 write_kctxt_csr(dd
, i
, RCV_HDR_CNT
, 0);
13740 write_kctxt_csr(dd
, i
, RCV_HDR_ENT_SIZE
, 0);
13741 write_kctxt_csr(dd
, i
, RCV_HDR_SIZE
, 0);
13742 write_kctxt_csr(dd
, i
, RCV_HDR_TAIL_ADDR
, 0);
13743 write_kctxt_csr(dd
, i
, RCV_AVAIL_TIME_OUT
, 0);
13744 write_kctxt_csr(dd
, i
, RCV_HDR_OVFL_CNT
, 0);
13747 /* RCV_HDR_TAIL read-only */
13748 write_uctxt_csr(dd
, i
, RCV_HDR_HEAD
, 0);
13749 /* RCV_EGR_INDEX_TAIL read-only */
13750 write_uctxt_csr(dd
, i
, RCV_EGR_INDEX_HEAD
, 0);
13751 /* RCV_EGR_OFFSET_TAIL read-only */
13752 for (j
= 0; j
< RXE_NUM_TID_FLOWS
; j
++) {
13753 write_uctxt_csr(dd
, i
,
13754 RCV_TID_FLOW_TABLE
+ (8 * j
), 0);
13760 * Set sc2vl tables.
13762 * They power on to zeros, so to avoid send context errors
13763 * they need to be set:
13765 * SC 0-7 -> VL 0-7 (respectively)
13770 static void init_sc2vl_tables(struct hfi1_devdata
*dd
)
13773 /* init per architecture spec, constrained by hardware capability */
13775 /* HFI maps sent packets */
13776 write_csr(dd
, SEND_SC2VLT0
, SC2VL_VAL(
13782 write_csr(dd
, SEND_SC2VLT1
, SC2VL_VAL(
13788 write_csr(dd
, SEND_SC2VLT2
, SC2VL_VAL(
13794 write_csr(dd
, SEND_SC2VLT3
, SC2VL_VAL(
13801 /* DC maps received packets */
13802 write_csr(dd
, DCC_CFG_SC_VL_TABLE_15_0
, DC_SC_VL_VAL(
13804 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7,
13805 8, 0, 9, 0, 10, 0, 11, 0, 12, 0, 13, 0, 14, 0, 15, 15));
13806 write_csr(dd
, DCC_CFG_SC_VL_TABLE_31_16
, DC_SC_VL_VAL(
13808 16, 0, 17, 0, 18, 0, 19, 0, 20, 0, 21, 0, 22, 0, 23, 0,
13809 24, 0, 25, 0, 26, 0, 27, 0, 28, 0, 29, 0, 30, 0, 31, 0));
13811 /* initialize the cached sc2vl values consistently with h/w */
13812 for (i
= 0; i
< 32; i
++) {
13813 if (i
< 8 || i
== 15)
13814 *((u8
*)(dd
->sc2vl
) + i
) = (u8
)i
;
13816 *((u8
*)(dd
->sc2vl
) + i
) = 0;
13821 * Read chip sizes and then reset parts to sane, disabled, values. We cannot
13822 * depend on the chip going through a power-on reset - a driver may be loaded
13823 * and unloaded many times.
13825 * Do not write any CSR values to the chip in this routine - there may be
13826 * a reset following the (possible) FLR in this routine.
13829 static void init_chip(struct hfi1_devdata
*dd
)
13834 * Put the HFI CSRs in a known state.
13835 * Combine this with a DC reset.
13837 * Stop the device from doing anything while we do a
13838 * reset. We know there are no other active users of
13839 * the device since we are now in charge. Turn off
13840 * off all outbound and inbound traffic and make sure
13841 * the device does not generate any interrupts.
13844 /* disable send contexts and SDMA engines */
13845 write_csr(dd
, SEND_CTRL
, 0);
13846 for (i
= 0; i
< dd
->chip_send_contexts
; i
++)
13847 write_kctxt_csr(dd
, i
, SEND_CTXT_CTRL
, 0);
13848 for (i
= 0; i
< dd
->chip_sdma_engines
; i
++)
13849 write_kctxt_csr(dd
, i
, SEND_DMA_CTRL
, 0);
13850 /* disable port (turn off RXE inbound traffic) and contexts */
13851 write_csr(dd
, RCV_CTRL
, 0);
13852 for (i
= 0; i
< dd
->chip_rcv_contexts
; i
++)
13853 write_csr(dd
, RCV_CTXT_CTRL
, 0);
13854 /* mask all interrupt sources */
13855 for (i
= 0; i
< CCE_NUM_INT_CSRS
; i
++)
13856 write_csr(dd
, CCE_INT_MASK
+ (8 * i
), 0ull);
13859 * DC Reset: do a full DC reset before the register clear.
13860 * A recommended length of time to hold is one CSR read,
13861 * so reread the CceDcCtrl. Then, hold the DC in reset
13862 * across the clear.
13864 write_csr(dd
, CCE_DC_CTRL
, CCE_DC_CTRL_DC_RESET_SMASK
);
13865 (void)read_csr(dd
, CCE_DC_CTRL
);
13869 * A FLR will reset the SPC core and part of the PCIe.
13870 * The parts that need to be restored have already been
13873 dd_dev_info(dd
, "Resetting CSRs with FLR\n");
13875 /* do the FLR, the DC reset will remain */
13876 pcie_flr(dd
->pcidev
);
13878 /* restore command and BARs */
13879 restore_pci_variables(dd
);
13882 dd_dev_info(dd
, "Resetting CSRs with FLR\n");
13883 pcie_flr(dd
->pcidev
);
13884 restore_pci_variables(dd
);
13887 dd_dev_info(dd
, "Resetting CSRs with writes\n");
13888 reset_cce_csrs(dd
);
13889 reset_txe_csrs(dd
);
13890 reset_rxe_csrs(dd
);
13891 reset_misc_csrs(dd
);
13893 /* clear the DC reset */
13894 write_csr(dd
, CCE_DC_CTRL
, 0);
13896 /* Set the LED off */
13900 * Clear the QSFP reset.
13901 * An FLR enforces a 0 on all out pins. The driver does not touch
13902 * ASIC_QSFPn_OUT otherwise. This leaves RESET_N low and
13903 * anything plugged constantly in reset, if it pays attention
13905 * Prime examples of this are optical cables. Set all pins high.
13906 * I2CCLK and I2CDAT will change per direction, and INT_N and
13907 * MODPRS_N are input only and their value is ignored.
13909 write_csr(dd
, ASIC_QSFP1_OUT
, 0x1f);
13910 write_csr(dd
, ASIC_QSFP2_OUT
, 0x1f);
13911 init_chip_resources(dd
);
13914 static void init_early_variables(struct hfi1_devdata
*dd
)
13918 /* assign link credit variables */
13920 dd
->link_credits
= CM_GLOBAL_CREDITS
;
13922 dd
->link_credits
--;
13923 dd
->vcu
= cu_to_vcu(hfi1_cu
);
13924 /* enough room for 8 MAD packets plus header - 17K */
13925 dd
->vl15_init
= (8 * (2048 + 128)) / vau_to_au(dd
->vau
);
13926 if (dd
->vl15_init
> dd
->link_credits
)
13927 dd
->vl15_init
= dd
->link_credits
;
13929 write_uninitialized_csrs_and_memories(dd
);
13931 if (HFI1_CAP_IS_KSET(PKEY_CHECK
))
13932 for (i
= 0; i
< dd
->num_pports
; i
++) {
13933 struct hfi1_pportdata
*ppd
= &dd
->pport
[i
];
13935 set_partition_keys(ppd
);
13937 init_sc2vl_tables(dd
);
13940 static void init_kdeth_qp(struct hfi1_devdata
*dd
)
13942 /* user changed the KDETH_QP */
13943 if (kdeth_qp
!= 0 && kdeth_qp
>= 0xff) {
13944 /* out of range or illegal value */
13945 dd_dev_err(dd
, "Invalid KDETH queue pair prefix, ignoring");
13948 if (kdeth_qp
== 0) /* not set, or failed range check */
13949 kdeth_qp
= DEFAULT_KDETH_QP
;
13951 write_csr(dd
, SEND_BTH_QP
,
13952 (kdeth_qp
& SEND_BTH_QP_KDETH_QP_MASK
) <<
13953 SEND_BTH_QP_KDETH_QP_SHIFT
);
13955 write_csr(dd
, RCV_BTH_QP
,
13956 (kdeth_qp
& RCV_BTH_QP_KDETH_QP_MASK
) <<
13957 RCV_BTH_QP_KDETH_QP_SHIFT
);
13962 * @dd - device data
13963 * @first_ctxt - first context
13964 * @last_ctxt - first context
13966 * This return sets the qpn mapping table that
13967 * is indexed by qpn[8:1].
13969 * The routine will round robin the 256 settings
13970 * from first_ctxt to last_ctxt.
13972 * The first/last looks ahead to having specialized
13973 * receive contexts for mgmt and bypass. Normal
13974 * verbs traffic will assumed to be on a range
13975 * of receive contexts.
13977 static void init_qpmap_table(struct hfi1_devdata
*dd
,
13982 u64 regno
= RCV_QP_MAP_TABLE
;
13984 u64 ctxt
= first_ctxt
;
13986 for (i
= 0; i
< 256; i
++) {
13987 reg
|= ctxt
<< (8 * (i
% 8));
13989 if (ctxt
> last_ctxt
)
13992 write_csr(dd
, regno
, reg
);
13998 add_rcvctrl(dd
, RCV_CTRL_RCV_QP_MAP_ENABLE_SMASK
13999 | RCV_CTRL_RCV_BYPASS_ENABLE_SMASK
);
14002 struct rsm_map_table
{
14003 u64 map
[NUM_MAP_REGS
];
14007 struct rsm_rule_data
{
14023 * Return an initialized RMT map table for users to fill in. OK if it
14024 * returns NULL, indicating no table.
14026 static struct rsm_map_table
*alloc_rsm_map_table(struct hfi1_devdata
*dd
)
14028 struct rsm_map_table
*rmt
;
14029 u8 rxcontext
= is_ax(dd
) ? 0 : 0xff; /* 0 is default if a0 ver. */
14031 rmt
= kmalloc(sizeof(*rmt
), GFP_KERNEL
);
14033 memset(rmt
->map
, rxcontext
, sizeof(rmt
->map
));
14041 * Write the final RMT map table to the chip and free the table. OK if
14044 static void complete_rsm_map_table(struct hfi1_devdata
*dd
,
14045 struct rsm_map_table
*rmt
)
14050 /* write table to chip */
14051 for (i
= 0; i
< NUM_MAP_REGS
; i
++)
14052 write_csr(dd
, RCV_RSM_MAP_TABLE
+ (8 * i
), rmt
->map
[i
]);
14055 add_rcvctrl(dd
, RCV_CTRL_RCV_RSM_ENABLE_SMASK
);
14060 * Add a receive side mapping rule.
14062 static void add_rsm_rule(struct hfi1_devdata
*dd
, u8 rule_index
,
14063 struct rsm_rule_data
*rrd
)
14065 write_csr(dd
, RCV_RSM_CFG
+ (8 * rule_index
),
14066 (u64
)rrd
->offset
<< RCV_RSM_CFG_OFFSET_SHIFT
|
14067 1ull << rule_index
| /* enable bit */
14068 (u64
)rrd
->pkt_type
<< RCV_RSM_CFG_PACKET_TYPE_SHIFT
);
14069 write_csr(dd
, RCV_RSM_SELECT
+ (8 * rule_index
),
14070 (u64
)rrd
->field1_off
<< RCV_RSM_SELECT_FIELD1_OFFSET_SHIFT
|
14071 (u64
)rrd
->field2_off
<< RCV_RSM_SELECT_FIELD2_OFFSET_SHIFT
|
14072 (u64
)rrd
->index1_off
<< RCV_RSM_SELECT_INDEX1_OFFSET_SHIFT
|
14073 (u64
)rrd
->index1_width
<< RCV_RSM_SELECT_INDEX1_WIDTH_SHIFT
|
14074 (u64
)rrd
->index2_off
<< RCV_RSM_SELECT_INDEX2_OFFSET_SHIFT
|
14075 (u64
)rrd
->index2_width
<< RCV_RSM_SELECT_INDEX2_WIDTH_SHIFT
);
14076 write_csr(dd
, RCV_RSM_MATCH
+ (8 * rule_index
),
14077 (u64
)rrd
->mask1
<< RCV_RSM_MATCH_MASK1_SHIFT
|
14078 (u64
)rrd
->value1
<< RCV_RSM_MATCH_VALUE1_SHIFT
|
14079 (u64
)rrd
->mask2
<< RCV_RSM_MATCH_MASK2_SHIFT
|
14080 (u64
)rrd
->value2
<< RCV_RSM_MATCH_VALUE2_SHIFT
);
14084 * Clear a receive side mapping rule.
14086 static void clear_rsm_rule(struct hfi1_devdata
*dd
, u8 rule_index
)
14088 write_csr(dd
, RCV_RSM_CFG
+ (8 * rule_index
), 0);
14089 write_csr(dd
, RCV_RSM_SELECT
+ (8 * rule_index
), 0);
14090 write_csr(dd
, RCV_RSM_MATCH
+ (8 * rule_index
), 0);
14093 /* return the number of RSM map table entries that will be used for QOS */
14094 static int qos_rmt_entries(struct hfi1_devdata
*dd
, unsigned int *mp
,
14101 /* is QOS active at all? */
14102 if (dd
->n_krcv_queues
<= MIN_KERNEL_KCTXTS
||
14107 /* determine bits for qpn */
14108 for (i
= 0; i
< min_t(unsigned int, num_vls
, krcvqsset
); i
++)
14109 if (krcvqs
[i
] > max_by_vl
)
14110 max_by_vl
= krcvqs
[i
];
14111 if (max_by_vl
> 32)
14113 m
= ilog2(__roundup_pow_of_two(max_by_vl
));
14115 /* determine bits for vl */
14116 n
= ilog2(__roundup_pow_of_two(num_vls
));
14118 /* reject if too much is used */
14127 return 1 << (m
+ n
);
14138 * init_qos - init RX qos
14139 * @dd - device data
14140 * @rmt - RSM map table
14142 * This routine initializes Rule 0 and the RSM map table to implement
14143 * quality of service (qos).
14145 * If all of the limit tests succeed, qos is applied based on the array
14146 * interpretation of krcvqs where entry 0 is VL0.
14148 * The number of vl bits (n) and the number of qpn bits (m) are computed to
14149 * feed both the RSM map table and the single rule.
14151 static void init_qos(struct hfi1_devdata
*dd
, struct rsm_map_table
*rmt
)
14153 struct rsm_rule_data rrd
;
14154 unsigned qpns_per_vl
, ctxt
, i
, qpn
, n
= 1, m
;
14155 unsigned int rmt_entries
;
14160 rmt_entries
= qos_rmt_entries(dd
, &m
, &n
);
14161 if (rmt_entries
== 0)
14163 qpns_per_vl
= 1 << m
;
14165 /* enough room in the map table? */
14166 rmt_entries
= 1 << (m
+ n
);
14167 if (rmt
->used
+ rmt_entries
>= NUM_MAP_ENTRIES
)
14170 /* add qos entries to the the RSM map table */
14171 for (i
= 0, ctxt
= FIRST_KERNEL_KCTXT
; i
< num_vls
; i
++) {
14174 for (qpn
= 0, tctxt
= ctxt
;
14175 krcvqs
[i
] && qpn
< qpns_per_vl
; qpn
++) {
14176 unsigned idx
, regoff
, regidx
;
14178 /* generate the index the hardware will produce */
14179 idx
= rmt
->used
+ ((qpn
<< n
) ^ i
);
14180 regoff
= (idx
% 8) * 8;
14182 /* replace default with context number */
14183 reg
= rmt
->map
[regidx
];
14184 reg
&= ~(RCV_RSM_MAP_TABLE_RCV_CONTEXT_A_MASK
14186 reg
|= (u64
)(tctxt
++) << regoff
;
14187 rmt
->map
[regidx
] = reg
;
14188 if (tctxt
== ctxt
+ krcvqs
[i
])
14194 rrd
.offset
= rmt
->used
;
14196 rrd
.field1_off
= LRH_BTH_MATCH_OFFSET
;
14197 rrd
.field2_off
= LRH_SC_MATCH_OFFSET
;
14198 rrd
.index1_off
= LRH_SC_SELECT_OFFSET
;
14199 rrd
.index1_width
= n
;
14200 rrd
.index2_off
= QPN_SELECT_OFFSET
;
14201 rrd
.index2_width
= m
+ n
;
14202 rrd
.mask1
= LRH_BTH_MASK
;
14203 rrd
.value1
= LRH_BTH_VALUE
;
14204 rrd
.mask2
= LRH_SC_MASK
;
14205 rrd
.value2
= LRH_SC_VALUE
;
14208 add_rsm_rule(dd
, RSM_INS_VERBS
, &rrd
);
14210 /* mark RSM map entries as used */
14211 rmt
->used
+= rmt_entries
;
14212 /* map everything else to the mcast/err/vl15 context */
14213 init_qpmap_table(dd
, HFI1_CTRL_CTXT
, HFI1_CTRL_CTXT
);
14214 dd
->qos_shift
= n
+ 1;
14218 init_qpmap_table(dd
, FIRST_KERNEL_KCTXT
, dd
->n_krcv_queues
- 1);
14221 static void init_user_fecn_handling(struct hfi1_devdata
*dd
,
14222 struct rsm_map_table
*rmt
)
14224 struct rsm_rule_data rrd
;
14226 int i
, idx
, regoff
, regidx
;
14229 /* there needs to be enough room in the map table */
14230 if (rmt
->used
+ dd
->num_user_contexts
>= NUM_MAP_ENTRIES
) {
14231 dd_dev_err(dd
, "User FECN handling disabled - too many user contexts allocated\n");
14236 * RSM will extract the destination context as an index into the
14237 * map table. The destination contexts are a sequential block
14238 * in the range first_dyn_alloc_ctxt...num_rcv_contexts-1 (inclusive).
14239 * Map entries are accessed as offset + extracted value. Adjust
14240 * the added offset so this sequence can be placed anywhere in
14241 * the table - as long as the entries themselves do not wrap.
14242 * There are only enough bits in offset for the table size, so
14243 * start with that to allow for a "negative" offset.
14245 offset
= (u8
)(NUM_MAP_ENTRIES
+ (int)rmt
->used
-
14246 (int)dd
->first_dyn_alloc_ctxt
);
14248 for (i
= dd
->first_dyn_alloc_ctxt
, idx
= rmt
->used
;
14249 i
< dd
->num_rcv_contexts
; i
++, idx
++) {
14250 /* replace with identity mapping */
14251 regoff
= (idx
% 8) * 8;
14253 reg
= rmt
->map
[regidx
];
14254 reg
&= ~(RCV_RSM_MAP_TABLE_RCV_CONTEXT_A_MASK
<< regoff
);
14255 reg
|= (u64
)i
<< regoff
;
14256 rmt
->map
[regidx
] = reg
;
14260 * For RSM intercept of Expected FECN packets:
14261 * o packet type 0 - expected
14262 * o match on F (bit 95), using select/match 1, and
14263 * o match on SH (bit 133), using select/match 2.
14265 * Use index 1 to extract the 8-bit receive context from DestQP
14266 * (start at bit 64). Use that as the RSM map table index.
14268 rrd
.offset
= offset
;
14270 rrd
.field1_off
= 95;
14271 rrd
.field2_off
= 133;
14272 rrd
.index1_off
= 64;
14273 rrd
.index1_width
= 8;
14274 rrd
.index2_off
= 0;
14275 rrd
.index2_width
= 0;
14282 add_rsm_rule(dd
, RSM_INS_FECN
, &rrd
);
14284 rmt
->used
+= dd
->num_user_contexts
;
14287 /* Initialize RSM for VNIC */
14288 void hfi1_init_vnic_rsm(struct hfi1_devdata
*dd
)
14294 struct rsm_rule_data rrd
;
14296 if (hfi1_vnic_is_rsm_full(dd
, NUM_VNIC_MAP_ENTRIES
)) {
14297 dd_dev_err(dd
, "Vnic RSM disabled, rmt entries used = %d\n",
14298 dd
->vnic
.rmt_start
);
14302 dev_dbg(&(dd
)->pcidev
->dev
, "Vnic rsm start = %d, end %d\n",
14303 dd
->vnic
.rmt_start
,
14304 dd
->vnic
.rmt_start
+ NUM_VNIC_MAP_ENTRIES
);
14306 /* Update RSM mapping table, 32 regs, 256 entries - 1 ctx per byte */
14307 regoff
= RCV_RSM_MAP_TABLE
+ (dd
->vnic
.rmt_start
/ 8) * 8;
14308 reg
= read_csr(dd
, regoff
);
14309 for (i
= 0; i
< NUM_VNIC_MAP_ENTRIES
; i
++) {
14310 /* Update map register with vnic context */
14311 j
= (dd
->vnic
.rmt_start
+ i
) % 8;
14312 reg
&= ~(0xffllu
<< (j
* 8));
14313 reg
|= (u64
)dd
->vnic
.ctxt
[ctx_id
++]->ctxt
<< (j
* 8);
14314 /* Wrap up vnic ctx index */
14315 ctx_id
%= dd
->vnic
.num_ctxt
;
14316 /* Write back map register */
14317 if (j
== 7 || ((i
+ 1) == NUM_VNIC_MAP_ENTRIES
)) {
14318 dev_dbg(&(dd
)->pcidev
->dev
,
14319 "Vnic rsm map reg[%d] =0x%llx\n",
14320 regoff
- RCV_RSM_MAP_TABLE
, reg
);
14322 write_csr(dd
, regoff
, reg
);
14324 if (i
< (NUM_VNIC_MAP_ENTRIES
- 1))
14325 reg
= read_csr(dd
, regoff
);
14329 /* Add rule for vnic */
14330 rrd
.offset
= dd
->vnic
.rmt_start
;
14332 /* Match 16B packets */
14333 rrd
.field1_off
= L2_TYPE_MATCH_OFFSET
;
14334 rrd
.mask1
= L2_TYPE_MASK
;
14335 rrd
.value1
= L2_16B_VALUE
;
14336 /* Match ETH L4 packets */
14337 rrd
.field2_off
= L4_TYPE_MATCH_OFFSET
;
14338 rrd
.mask2
= L4_16B_TYPE_MASK
;
14339 rrd
.value2
= L4_16B_ETH_VALUE
;
14340 /* Calc context from veswid and entropy */
14341 rrd
.index1_off
= L4_16B_HDR_VESWID_OFFSET
;
14342 rrd
.index1_width
= ilog2(NUM_VNIC_MAP_ENTRIES
);
14343 rrd
.index2_off
= L2_16B_ENTROPY_OFFSET
;
14344 rrd
.index2_width
= ilog2(NUM_VNIC_MAP_ENTRIES
);
14345 add_rsm_rule(dd
, RSM_INS_VNIC
, &rrd
);
14347 /* Enable RSM if not already enabled */
14348 add_rcvctrl(dd
, RCV_CTRL_RCV_RSM_ENABLE_SMASK
);
14351 void hfi1_deinit_vnic_rsm(struct hfi1_devdata
*dd
)
14353 clear_rsm_rule(dd
, RSM_INS_VNIC
);
14355 /* Disable RSM if used only by vnic */
14356 if (dd
->vnic
.rmt_start
== 0)
14357 clear_rcvctrl(dd
, RCV_CTRL_RCV_RSM_ENABLE_SMASK
);
14360 static void init_rxe(struct hfi1_devdata
*dd
)
14362 struct rsm_map_table
*rmt
;
14364 /* enable all receive errors */
14365 write_csr(dd
, RCV_ERR_MASK
, ~0ull);
14367 rmt
= alloc_rsm_map_table(dd
);
14368 /* set up QOS, including the QPN map table */
14370 init_user_fecn_handling(dd
, rmt
);
14371 complete_rsm_map_table(dd
, rmt
);
14372 /* record number of used rsm map entries for vnic */
14373 dd
->vnic
.rmt_start
= rmt
->used
;
14377 * make sure RcvCtrl.RcvWcb <= PCIe Device Control
14378 * Register Max_Payload_Size (PCI_EXP_DEVCTL in Linux PCIe config
14379 * space, PciCfgCap2.MaxPayloadSize in HFI). There is only one
14380 * invalid configuration: RcvCtrl.RcvWcb set to its max of 256 and
14381 * Max_PayLoad_Size set to its minimum of 128.
14383 * Presently, RcvCtrl.RcvWcb is not modified from its default of 0
14384 * (64 bytes). Max_Payload_Size is possibly modified upward in
14385 * tune_pcie_caps() which is called after this routine.
14389 static void init_other(struct hfi1_devdata
*dd
)
14391 /* enable all CCE errors */
14392 write_csr(dd
, CCE_ERR_MASK
, ~0ull);
14393 /* enable *some* Misc errors */
14394 write_csr(dd
, MISC_ERR_MASK
, DRIVER_MISC_MASK
);
14395 /* enable all DC errors, except LCB */
14396 write_csr(dd
, DCC_ERR_FLG_EN
, ~0ull);
14397 write_csr(dd
, DC_DC8051_ERR_EN
, ~0ull);
14401 * Fill out the given AU table using the given CU. A CU is defined in terms
14402 * AUs. The table is a an encoding: given the index, how many AUs does that
14405 * NOTE: Assumes that the register layout is the same for the
14406 * local and remote tables.
14408 static void assign_cm_au_table(struct hfi1_devdata
*dd
, u32 cu
,
14409 u32 csr0to3
, u32 csr4to7
)
14411 write_csr(dd
, csr0to3
,
14412 0ull << SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE0_SHIFT
|
14413 1ull << SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE1_SHIFT
|
14415 SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE2_SHIFT
|
14417 SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE3_SHIFT
);
14418 write_csr(dd
, csr4to7
,
14420 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE4_SHIFT
|
14422 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE5_SHIFT
|
14424 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE6_SHIFT
|
14426 SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE7_SHIFT
);
14429 static void assign_local_cm_au_table(struct hfi1_devdata
*dd
, u8 vcu
)
14431 assign_cm_au_table(dd
, vcu_to_cu(vcu
), SEND_CM_LOCAL_AU_TABLE0_TO3
,
14432 SEND_CM_LOCAL_AU_TABLE4_TO7
);
14435 void assign_remote_cm_au_table(struct hfi1_devdata
*dd
, u8 vcu
)
14437 assign_cm_au_table(dd
, vcu_to_cu(vcu
), SEND_CM_REMOTE_AU_TABLE0_TO3
,
14438 SEND_CM_REMOTE_AU_TABLE4_TO7
);
14441 static void init_txe(struct hfi1_devdata
*dd
)
14445 /* enable all PIO, SDMA, general, and Egress errors */
14446 write_csr(dd
, SEND_PIO_ERR_MASK
, ~0ull);
14447 write_csr(dd
, SEND_DMA_ERR_MASK
, ~0ull);
14448 write_csr(dd
, SEND_ERR_MASK
, ~0ull);
14449 write_csr(dd
, SEND_EGRESS_ERR_MASK
, ~0ull);
14451 /* enable all per-context and per-SDMA engine errors */
14452 for (i
= 0; i
< dd
->chip_send_contexts
; i
++)
14453 write_kctxt_csr(dd
, i
, SEND_CTXT_ERR_MASK
, ~0ull);
14454 for (i
= 0; i
< dd
->chip_sdma_engines
; i
++)
14455 write_kctxt_csr(dd
, i
, SEND_DMA_ENG_ERR_MASK
, ~0ull);
14457 /* set the local CU to AU mapping */
14458 assign_local_cm_au_table(dd
, dd
->vcu
);
14461 * Set reasonable default for Credit Return Timer
14462 * Don't set on Simulator - causes it to choke.
14464 if (dd
->icode
!= ICODE_FUNCTIONAL_SIMULATOR
)
14465 write_csr(dd
, SEND_CM_TIMER_CTRL
, HFI1_CREDIT_RETURN_RATE
);
14468 int hfi1_set_ctxt_jkey(struct hfi1_devdata
*dd
, unsigned ctxt
, u16 jkey
)
14470 struct hfi1_ctxtdata
*rcd
= dd
->rcd
[ctxt
];
14475 if (!rcd
|| !rcd
->sc
) {
14479 sctxt
= rcd
->sc
->hw_context
;
14480 reg
= SEND_CTXT_CHECK_JOB_KEY_MASK_SMASK
| /* mask is always 1's */
14481 ((jkey
& SEND_CTXT_CHECK_JOB_KEY_VALUE_MASK
) <<
14482 SEND_CTXT_CHECK_JOB_KEY_VALUE_SHIFT
);
14483 /* JOB_KEY_ALLOW_PERMISSIVE is not allowed by default */
14484 if (HFI1_CAP_KGET_MASK(rcd
->flags
, ALLOW_PERM_JKEY
))
14485 reg
|= SEND_CTXT_CHECK_JOB_KEY_ALLOW_PERMISSIVE_SMASK
;
14486 write_kctxt_csr(dd
, sctxt
, SEND_CTXT_CHECK_JOB_KEY
, reg
);
14488 * Enable send-side J_KEY integrity check, unless this is A0 h/w
14491 reg
= read_kctxt_csr(dd
, sctxt
, SEND_CTXT_CHECK_ENABLE
);
14492 reg
|= SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK
;
14493 write_kctxt_csr(dd
, sctxt
, SEND_CTXT_CHECK_ENABLE
, reg
);
14496 /* Enable J_KEY check on receive context. */
14497 reg
= RCV_KEY_CTRL_JOB_KEY_ENABLE_SMASK
|
14498 ((jkey
& RCV_KEY_CTRL_JOB_KEY_VALUE_MASK
) <<
14499 RCV_KEY_CTRL_JOB_KEY_VALUE_SHIFT
);
14500 write_kctxt_csr(dd
, ctxt
, RCV_KEY_CTRL
, reg
);
14505 int hfi1_clear_ctxt_jkey(struct hfi1_devdata
*dd
, unsigned ctxt
)
14507 struct hfi1_ctxtdata
*rcd
= dd
->rcd
[ctxt
];
14512 if (!rcd
|| !rcd
->sc
) {
14516 sctxt
= rcd
->sc
->hw_context
;
14517 write_kctxt_csr(dd
, sctxt
, SEND_CTXT_CHECK_JOB_KEY
, 0);
14519 * Disable send-side J_KEY integrity check, unless this is A0 h/w.
14520 * This check would not have been enabled for A0 h/w, see
14524 reg
= read_kctxt_csr(dd
, sctxt
, SEND_CTXT_CHECK_ENABLE
);
14525 reg
&= ~SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK
;
14526 write_kctxt_csr(dd
, sctxt
, SEND_CTXT_CHECK_ENABLE
, reg
);
14528 /* Turn off the J_KEY on the receive side */
14529 write_kctxt_csr(dd
, ctxt
, RCV_KEY_CTRL
, 0);
14534 int hfi1_set_ctxt_pkey(struct hfi1_devdata
*dd
, unsigned ctxt
, u16 pkey
)
14536 struct hfi1_ctxtdata
*rcd
;
14541 if (ctxt
< dd
->num_rcv_contexts
) {
14542 rcd
= dd
->rcd
[ctxt
];
14547 if (!rcd
|| !rcd
->sc
) {
14551 sctxt
= rcd
->sc
->hw_context
;
14552 reg
= ((u64
)pkey
& SEND_CTXT_CHECK_PARTITION_KEY_VALUE_MASK
) <<
14553 SEND_CTXT_CHECK_PARTITION_KEY_VALUE_SHIFT
;
14554 write_kctxt_csr(dd
, sctxt
, SEND_CTXT_CHECK_PARTITION_KEY
, reg
);
14555 reg
= read_kctxt_csr(dd
, sctxt
, SEND_CTXT_CHECK_ENABLE
);
14556 reg
|= SEND_CTXT_CHECK_ENABLE_CHECK_PARTITION_KEY_SMASK
;
14557 reg
&= ~SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK
;
14558 write_kctxt_csr(dd
, sctxt
, SEND_CTXT_CHECK_ENABLE
, reg
);
14563 int hfi1_clear_ctxt_pkey(struct hfi1_devdata
*dd
, struct hfi1_ctxtdata
*ctxt
)
14568 if (!ctxt
|| !ctxt
->sc
)
14571 if (ctxt
->ctxt
>= dd
->num_rcv_contexts
)
14574 hw_ctxt
= ctxt
->sc
->hw_context
;
14575 reg
= read_kctxt_csr(dd
, hw_ctxt
, SEND_CTXT_CHECK_ENABLE
);
14576 reg
&= ~SEND_CTXT_CHECK_ENABLE_CHECK_PARTITION_KEY_SMASK
;
14577 write_kctxt_csr(dd
, hw_ctxt
, SEND_CTXT_CHECK_ENABLE
, reg
);
14578 write_kctxt_csr(dd
, hw_ctxt
, SEND_CTXT_CHECK_PARTITION_KEY
, 0);
14584 * Start doing the clean up the the chip. Our clean up happens in multiple
14585 * stages and this is just the first.
14587 void hfi1_start_cleanup(struct hfi1_devdata
*dd
)
14592 clean_up_interrupts(dd
);
14593 finish_chip_resources(dd
);
14596 #define HFI_BASE_GUID(dev) \
14597 ((dev)->base_guid & ~(1ULL << GUID_HFI_INDEX_SHIFT))
14600 * Information can be shared between the two HFIs on the same ASIC
14601 * in the same OS. This function finds the peer device and sets
14602 * up a shared structure.
14604 static int init_asic_data(struct hfi1_devdata
*dd
)
14606 unsigned long flags
;
14607 struct hfi1_devdata
*tmp
, *peer
= NULL
;
14608 struct hfi1_asic_data
*asic_data
;
14611 /* pre-allocate the asic structure in case we are the first device */
14612 asic_data
= kzalloc(sizeof(*dd
->asic_data
), GFP_KERNEL
);
14616 spin_lock_irqsave(&hfi1_devs_lock
, flags
);
14617 /* Find our peer device */
14618 list_for_each_entry(tmp
, &hfi1_dev_list
, list
) {
14619 if ((HFI_BASE_GUID(dd
) == HFI_BASE_GUID(tmp
)) &&
14620 dd
->unit
!= tmp
->unit
) {
14627 /* use already allocated structure */
14628 dd
->asic_data
= peer
->asic_data
;
14631 dd
->asic_data
= asic_data
;
14632 mutex_init(&dd
->asic_data
->asic_resource_mutex
);
14634 dd
->asic_data
->dds
[dd
->hfi1_id
] = dd
; /* self back-pointer */
14635 spin_unlock_irqrestore(&hfi1_devs_lock
, flags
);
14637 /* first one through - set up i2c devices */
14639 ret
= set_up_i2c(dd
, dd
->asic_data
);
14645 * Set dd->boardname. Use a generic name if a name is not returned from
14646 * EFI variable space.
14648 * Return 0 on success, -ENOMEM if space could not be allocated.
14650 static int obtain_boardname(struct hfi1_devdata
*dd
)
14652 /* generic board description */
14653 const char generic
[] =
14654 "Intel Omni-Path Host Fabric Interface Adapter 100 Series";
14655 unsigned long size
;
14658 ret
= read_hfi1_efi_var(dd
, "description", &size
,
14659 (void **)&dd
->boardname
);
14661 dd_dev_info(dd
, "Board description not found\n");
14662 /* use generic description */
14663 dd
->boardname
= kstrdup(generic
, GFP_KERNEL
);
14664 if (!dd
->boardname
)
14671 * Check the interrupt registers to make sure that they are mapped correctly.
14672 * It is intended to help user identify any mismapping by VMM when the driver
14673 * is running in a VM. This function should only be called before interrupt
14674 * is set up properly.
14676 * Return 0 on success, -EINVAL on failure.
14678 static int check_int_registers(struct hfi1_devdata
*dd
)
14681 u64 all_bits
= ~(u64
)0;
14684 /* Clear CceIntMask[0] to avoid raising any interrupts */
14685 mask
= read_csr(dd
, CCE_INT_MASK
);
14686 write_csr(dd
, CCE_INT_MASK
, 0ull);
14687 reg
= read_csr(dd
, CCE_INT_MASK
);
14691 /* Clear all interrupt status bits */
14692 write_csr(dd
, CCE_INT_CLEAR
, all_bits
);
14693 reg
= read_csr(dd
, CCE_INT_STATUS
);
14697 /* Set all interrupt status bits */
14698 write_csr(dd
, CCE_INT_FORCE
, all_bits
);
14699 reg
= read_csr(dd
, CCE_INT_STATUS
);
14700 if (reg
!= all_bits
)
14703 /* Restore the interrupt mask */
14704 write_csr(dd
, CCE_INT_CLEAR
, all_bits
);
14705 write_csr(dd
, CCE_INT_MASK
, mask
);
14709 write_csr(dd
, CCE_INT_MASK
, mask
);
14710 dd_dev_err(dd
, "Interrupt registers not properly mapped by VMM\n");
14715 * Allocate and initialize the device structure for the hfi.
14716 * @dev: the pci_dev for hfi1_ib device
14717 * @ent: pci_device_id struct for this dev
14719 * Also allocates, initializes, and returns the devdata struct for this
14722 * This is global, and is called directly at init to set up the
14723 * chip-specific function pointers for later use.
14725 struct hfi1_devdata
*hfi1_init_dd(struct pci_dev
*pdev
,
14726 const struct pci_device_id
*ent
)
14728 struct hfi1_devdata
*dd
;
14729 struct hfi1_pportdata
*ppd
;
14732 static const char * const inames
[] = { /* implementation names */
14734 "RTL VCS simulation",
14735 "RTL FPGA emulation",
14736 "Functional simulator"
14738 struct pci_dev
*parent
= pdev
->bus
->self
;
14740 dd
= hfi1_alloc_devdata(pdev
, NUM_IB_PORTS
*
14741 sizeof(struct hfi1_pportdata
));
14745 for (i
= 0; i
< dd
->num_pports
; i
++, ppd
++) {
14747 /* init common fields */
14748 hfi1_init_pportdata(pdev
, ppd
, dd
, 0, 1);
14749 /* DC supports 4 link widths */
14750 ppd
->link_width_supported
=
14751 OPA_LINK_WIDTH_1X
| OPA_LINK_WIDTH_2X
|
14752 OPA_LINK_WIDTH_3X
| OPA_LINK_WIDTH_4X
;
14753 ppd
->link_width_downgrade_supported
=
14754 ppd
->link_width_supported
;
14755 /* start out enabling only 4X */
14756 ppd
->link_width_enabled
= OPA_LINK_WIDTH_4X
;
14757 ppd
->link_width_downgrade_enabled
=
14758 ppd
->link_width_downgrade_supported
;
14759 /* link width active is 0 when link is down */
14760 /* link width downgrade active is 0 when link is down */
14762 if (num_vls
< HFI1_MIN_VLS_SUPPORTED
||
14763 num_vls
> HFI1_MAX_VLS_SUPPORTED
) {
14764 hfi1_early_err(&pdev
->dev
,
14765 "Invalid num_vls %u, using %u VLs\n",
14766 num_vls
, HFI1_MAX_VLS_SUPPORTED
);
14767 num_vls
= HFI1_MAX_VLS_SUPPORTED
;
14769 ppd
->vls_supported
= num_vls
;
14770 ppd
->vls_operational
= ppd
->vls_supported
;
14771 ppd
->actual_vls_operational
= ppd
->vls_supported
;
14772 /* Set the default MTU. */
14773 for (vl
= 0; vl
< num_vls
; vl
++)
14774 dd
->vld
[vl
].mtu
= hfi1_max_mtu
;
14775 dd
->vld
[15].mtu
= MAX_MAD_PACKET
;
14777 * Set the initial values to reasonable default, will be set
14778 * for real when link is up.
14780 ppd
->lstate
= IB_PORT_DOWN
;
14781 ppd
->overrun_threshold
= 0x4;
14782 ppd
->phy_error_threshold
= 0xf;
14783 ppd
->port_crc_mode_enabled
= link_crc_mask
;
14784 /* initialize supported LTP CRC mode */
14785 ppd
->port_ltp_crc_mode
= cap_to_port_ltp(link_crc_mask
) << 8;
14786 /* initialize enabled LTP CRC mode */
14787 ppd
->port_ltp_crc_mode
|= cap_to_port_ltp(link_crc_mask
) << 4;
14788 /* start in offline */
14789 ppd
->host_link_state
= HLS_DN_OFFLINE
;
14790 init_vl_arb_caches(ppd
);
14791 ppd
->last_pstate
= 0xff; /* invalid value */
14794 dd
->link_default
= HLS_DN_POLL
;
14797 * Do remaining PCIe setup and save PCIe values in dd.
14798 * Any error printing is already done by the init code.
14799 * On return, we have the chip mapped.
14801 ret
= hfi1_pcie_ddinit(dd
, pdev
);
14805 /* verify that reads actually work, save revision for reset check */
14806 dd
->revision
= read_csr(dd
, CCE_REVISION
);
14807 if (dd
->revision
== ~(u64
)0) {
14808 dd_dev_err(dd
, "cannot read chip CSRs\n");
14812 dd
->majrev
= (dd
->revision
>> CCE_REVISION_CHIP_REV_MAJOR_SHIFT
)
14813 & CCE_REVISION_CHIP_REV_MAJOR_MASK
;
14814 dd
->minrev
= (dd
->revision
>> CCE_REVISION_CHIP_REV_MINOR_SHIFT
)
14815 & CCE_REVISION_CHIP_REV_MINOR_MASK
;
14818 * Check interrupt registers mapping if the driver has no access to
14819 * the upstream component. In this case, it is likely that the driver
14820 * is running in a VM.
14823 ret
= check_int_registers(dd
);
14829 * obtain the hardware ID - NOT related to unit, which is a
14830 * software enumeration
14832 reg
= read_csr(dd
, CCE_REVISION2
);
14833 dd
->hfi1_id
= (reg
>> CCE_REVISION2_HFI_ID_SHIFT
)
14834 & CCE_REVISION2_HFI_ID_MASK
;
14835 /* the variable size will remove unwanted bits */
14836 dd
->icode
= reg
>> CCE_REVISION2_IMPL_CODE_SHIFT
;
14837 dd
->irev
= reg
>> CCE_REVISION2_IMPL_REVISION_SHIFT
;
14838 dd_dev_info(dd
, "Implementation: %s, revision 0x%x\n",
14839 dd
->icode
< ARRAY_SIZE(inames
) ?
14840 inames
[dd
->icode
] : "unknown", (int)dd
->irev
);
14842 /* speeds the hardware can support */
14843 dd
->pport
->link_speed_supported
= OPA_LINK_SPEED_25G
;
14844 /* speeds allowed to run at */
14845 dd
->pport
->link_speed_enabled
= dd
->pport
->link_speed_supported
;
14846 /* give a reasonable active value, will be set on link up */
14847 dd
->pport
->link_speed_active
= OPA_LINK_SPEED_25G
;
14849 dd
->chip_rcv_contexts
= read_csr(dd
, RCV_CONTEXTS
);
14850 dd
->chip_send_contexts
= read_csr(dd
, SEND_CONTEXTS
);
14851 dd
->chip_sdma_engines
= read_csr(dd
, SEND_DMA_ENGINES
);
14852 dd
->chip_pio_mem_size
= read_csr(dd
, SEND_PIO_MEM_SIZE
);
14853 dd
->chip_sdma_mem_size
= read_csr(dd
, SEND_DMA_MEM_SIZE
);
14854 /* fix up link widths for emulation _p */
14856 if (dd
->icode
== ICODE_FPGA_EMULATION
&& is_emulator_p(dd
)) {
14857 ppd
->link_width_supported
=
14858 ppd
->link_width_enabled
=
14859 ppd
->link_width_downgrade_supported
=
14860 ppd
->link_width_downgrade_enabled
=
14863 /* insure num_vls isn't larger than number of sdma engines */
14864 if (HFI1_CAP_IS_KSET(SDMA
) && num_vls
> dd
->chip_sdma_engines
) {
14865 dd_dev_err(dd
, "num_vls %u too large, using %u VLs\n",
14866 num_vls
, dd
->chip_sdma_engines
);
14867 num_vls
= dd
->chip_sdma_engines
;
14868 ppd
->vls_supported
= dd
->chip_sdma_engines
;
14869 ppd
->vls_operational
= ppd
->vls_supported
;
14873 * Convert the ns parameter to the 64 * cclocks used in the CSR.
14874 * Limit the max if larger than the field holds. If timeout is
14875 * non-zero, then the calculated field will be at least 1.
14877 * Must be after icode is set up - the cclock rate depends
14878 * on knowing the hardware being used.
14880 dd
->rcv_intr_timeout_csr
= ns_to_cclock(dd
, rcv_intr_timeout
) / 64;
14881 if (dd
->rcv_intr_timeout_csr
>
14882 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_MASK
)
14883 dd
->rcv_intr_timeout_csr
=
14884 RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_MASK
;
14885 else if (dd
->rcv_intr_timeout_csr
== 0 && rcv_intr_timeout
)
14886 dd
->rcv_intr_timeout_csr
= 1;
14888 /* needs to be done before we look for the peer device */
14891 /* set up shared ASIC data with peer device */
14892 ret
= init_asic_data(dd
);
14896 /* obtain chip sizes, reset chip CSRs */
14899 /* read in the PCIe link speed information */
14900 ret
= pcie_speeds(dd
);
14904 /* call before get_platform_config(), after init_chip_resources() */
14905 ret
= eprom_init(dd
);
14907 goto bail_free_rcverr
;
14909 /* Needs to be called before hfi1_firmware_init */
14910 get_platform_config(dd
);
14912 /* read in firmware */
14913 ret
= hfi1_firmware_init(dd
);
14918 * In general, the PCIe Gen3 transition must occur after the
14919 * chip has been idled (so it won't initiate any PCIe transactions
14920 * e.g. an interrupt) and before the driver changes any registers
14921 * (the transition will reset the registers).
14923 * In particular, place this call after:
14924 * - init_chip() - the chip will not initiate any PCIe transactions
14925 * - pcie_speeds() - reads the current link speed
14926 * - hfi1_firmware_init() - the needed firmware is ready to be
14929 ret
= do_pcie_gen3_transition(dd
);
14933 /* start setting dd values and adjusting CSRs */
14934 init_early_variables(dd
);
14936 parse_platform_config(dd
);
14938 ret
= obtain_boardname(dd
);
14942 snprintf(dd
->boardversion
, BOARD_VERS_MAX
,
14943 "ChipABI %u.%u, ChipRev %u.%u, SW Compat %llu\n",
14944 HFI1_CHIP_VERS_MAJ
, HFI1_CHIP_VERS_MIN
,
14947 (dd
->revision
>> CCE_REVISION_SW_SHIFT
)
14948 & CCE_REVISION_SW_MASK
);
14950 ret
= set_up_context_variables(dd
);
14954 /* set initial RXE CSRs */
14956 /* set initial TXE CSRs */
14958 /* set initial non-RXE, non-TXE CSRs */
14960 /* set up KDETH QP prefix in both RX and TX CSRs */
14963 ret
= hfi1_dev_affinity_init(dd
);
14967 /* send contexts must be set up before receive contexts */
14968 ret
= init_send_contexts(dd
);
14972 ret
= hfi1_create_ctxts(dd
);
14976 dd
->rcvhdrsize
= DEFAULT_RCVHDRSIZE
;
14978 * rcd[0] is guaranteed to be valid by this point. Also, all
14979 * context are using the same value, as per the module parameter.
14981 dd
->rhf_offset
= dd
->rcd
[0]->rcvhdrqentsize
- sizeof(u64
) / sizeof(u32
);
14983 ret
= init_pervl_scs(dd
);
14988 for (i
= 0; i
< dd
->num_pports
; ++i
) {
14989 ret
= sdma_init(dd
, i
);
14994 /* use contexts created by hfi1_create_ctxts */
14995 ret
= set_up_interrupts(dd
);
14999 /* set up LCB access - must be after set_up_interrupts() */
15000 init_lcb_access(dd
);
15003 * Serial number is created from the base guid:
15004 * [27:24] = base guid [38:35]
15005 * [23: 0] = base guid [23: 0]
15007 snprintf(dd
->serial
, SERIAL_MAX
, "0x%08llx\n",
15008 (dd
->base_guid
& 0xFFFFFF) |
15009 ((dd
->base_guid
>> 11) & 0xF000000));
15011 dd
->oui1
= dd
->base_guid
>> 56 & 0xFF;
15012 dd
->oui2
= dd
->base_guid
>> 48 & 0xFF;
15013 dd
->oui3
= dd
->base_guid
>> 40 & 0xFF;
15015 ret
= load_firmware(dd
); /* asymmetric with dispose_firmware() */
15017 goto bail_clear_intr
;
15021 ret
= init_cntrs(dd
);
15023 goto bail_clear_intr
;
15025 ret
= init_rcverr(dd
);
15027 goto bail_free_cntrs
;
15029 init_completion(&dd
->user_comp
);
15031 /* The user refcount starts with one to inidicate an active device */
15032 atomic_set(&dd
->user_refcount
, 1);
15041 clean_up_interrupts(dd
);
15043 hfi1_pcie_ddcleanup(dd
);
15045 hfi1_free_devdata(dd
);
15051 static u16
delay_cycles(struct hfi1_pportdata
*ppd
, u32 desired_egress_rate
,
15055 u32 current_egress_rate
= ppd
->current_egress_rate
;
15056 /* rates here are in units of 10^6 bits/sec */
15058 if (desired_egress_rate
== -1)
15059 return 0; /* shouldn't happen */
15061 if (desired_egress_rate
>= current_egress_rate
)
15062 return 0; /* we can't help go faster, only slower */
15064 delta_cycles
= egress_cycles(dw_len
* 4, desired_egress_rate
) -
15065 egress_cycles(dw_len
* 4, current_egress_rate
);
15067 return (u16
)delta_cycles
;
15071 * create_pbc - build a pbc for transmission
15072 * @flags: special case flags or-ed in built pbc
15073 * @srate: static rate
15075 * @dwlen: dword length (header words + data words + pbc words)
15077 * Create a PBC with the given flags, rate, VL, and length.
15079 * NOTE: The PBC created will not insert any HCRC - all callers but one are
15080 * for verbs, which does not use this PSM feature. The lone other caller
15081 * is for the diagnostic interface which calls this if the user does not
15082 * supply their own PBC.
15084 u64
create_pbc(struct hfi1_pportdata
*ppd
, u64 flags
, int srate_mbs
, u32 vl
,
15087 u64 pbc
, delay
= 0;
15089 if (unlikely(srate_mbs
))
15090 delay
= delay_cycles(ppd
, srate_mbs
, dw_len
);
15093 | (delay
<< PBC_STATIC_RATE_CONTROL_COUNT_SHIFT
)
15094 | ((u64
)PBC_IHCRC_NONE
<< PBC_INSERT_HCRC_SHIFT
)
15095 | (vl
& PBC_VL_MASK
) << PBC_VL_SHIFT
15096 | (dw_len
& PBC_LENGTH_DWS_MASK
)
15097 << PBC_LENGTH_DWS_SHIFT
;
15102 #define SBUS_THERMAL 0x4f
15103 #define SBUS_THERM_MONITOR_MODE 0x1
15105 #define THERM_FAILURE(dev, ret, reason) \
15107 "Thermal sensor initialization failed: %s (%d)\n", \
15111 * Initialize the thermal sensor.
15113 * After initialization, enable polling of thermal sensor through
15114 * SBus interface. In order for this to work, the SBus Master
15115 * firmware has to be loaded due to the fact that the HW polling
15116 * logic uses SBus interrupts, which are not supported with
15117 * default firmware. Otherwise, no data will be returned through
15118 * the ASIC_STS_THERM CSR.
15120 static int thermal_init(struct hfi1_devdata
*dd
)
15124 if (dd
->icode
!= ICODE_RTL_SILICON
||
15125 check_chip_resource(dd
, CR_THERM_INIT
, NULL
))
15128 ret
= acquire_chip_resource(dd
, CR_SBUS
, SBUS_TIMEOUT
);
15130 THERM_FAILURE(dd
, ret
, "Acquire SBus");
15134 dd_dev_info(dd
, "Initializing thermal sensor\n");
15135 /* Disable polling of thermal readings */
15136 write_csr(dd
, ASIC_CFG_THERM_POLL_EN
, 0x0);
15138 /* Thermal Sensor Initialization */
15139 /* Step 1: Reset the Thermal SBus Receiver */
15140 ret
= sbus_request_slow(dd
, SBUS_THERMAL
, 0x0,
15141 RESET_SBUS_RECEIVER
, 0);
15143 THERM_FAILURE(dd
, ret
, "Bus Reset");
15146 /* Step 2: Set Reset bit in Thermal block */
15147 ret
= sbus_request_slow(dd
, SBUS_THERMAL
, 0x0,
15148 WRITE_SBUS_RECEIVER
, 0x1);
15150 THERM_FAILURE(dd
, ret
, "Therm Block Reset");
15153 /* Step 3: Write clock divider value (100MHz -> 2MHz) */
15154 ret
= sbus_request_slow(dd
, SBUS_THERMAL
, 0x1,
15155 WRITE_SBUS_RECEIVER
, 0x32);
15157 THERM_FAILURE(dd
, ret
, "Write Clock Div");
15160 /* Step 4: Select temperature mode */
15161 ret
= sbus_request_slow(dd
, SBUS_THERMAL
, 0x3,
15162 WRITE_SBUS_RECEIVER
,
15163 SBUS_THERM_MONITOR_MODE
);
15165 THERM_FAILURE(dd
, ret
, "Write Mode Sel");
15168 /* Step 5: De-assert block reset and start conversion */
15169 ret
= sbus_request_slow(dd
, SBUS_THERMAL
, 0x0,
15170 WRITE_SBUS_RECEIVER
, 0x2);
15172 THERM_FAILURE(dd
, ret
, "Write Reset Deassert");
15175 /* Step 5.1: Wait for first conversion (21.5ms per spec) */
15178 /* Enable polling of thermal readings */
15179 write_csr(dd
, ASIC_CFG_THERM_POLL_EN
, 0x1);
15181 /* Set initialized flag */
15182 ret
= acquire_chip_resource(dd
, CR_THERM_INIT
, 0);
15184 THERM_FAILURE(dd
, ret
, "Unable to set thermal init flag");
15187 release_chip_resource(dd
, CR_SBUS
);
15191 static void handle_temp_err(struct hfi1_devdata
*dd
)
15193 struct hfi1_pportdata
*ppd
= &dd
->pport
[0];
15195 * Thermal Critical Interrupt
15196 * Put the device into forced freeze mode, take link down to
15197 * offline, and put DC into reset.
15200 "Critical temperature reached! Forcing device into freeze mode!\n");
15201 dd
->flags
|= HFI1_FORCED_FREEZE
;
15202 start_freeze_handling(ppd
, FREEZE_SELF
| FREEZE_ABORT
);
15204 * Shut DC down as much and as quickly as possible.
15206 * Step 1: Take the link down to OFFLINE. This will cause the
15207 * 8051 to put the Serdes in reset. However, we don't want to
15208 * go through the entire link state machine since we want to
15209 * shutdown ASAP. Furthermore, this is not a graceful shutdown
15210 * but rather an attempt to save the chip.
15211 * Code below is almost the same as quiet_serdes() but avoids
15212 * all the extra work and the sleeps.
15214 ppd
->driver_link_ready
= 0;
15215 ppd
->link_enabled
= 0;
15216 set_physical_link_state(dd
, (OPA_LINKDOWN_REASON_SMA_DISABLED
<< 8) |
15219 * Step 2: Shutdown LCB and 8051
15220 * After shutdown, do not restore DC_CFG_RESET value.