drivers/infiniband/hw/hfi1/common.h

   1 /*
   2  * Copyright(c) 2015, 2016 Intel Corporation.
   3  *
   4  * This file is provided under a dual BSD/GPLv2 license.  When using or
   5  * redistributing this file, you may do so under either license.
   6  *
   7  * GPL LICENSE SUMMARY
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of version 2 of the GNU General Public License as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * BSD LICENSE
  19  *
  20  * Redistribution and use in source and binary forms, with or without
  21  * modification, are permitted provided that the following conditions
  22  * are met:
  23  *
  24  *  - Redistributions of source code must retain the above copyright
  25  *    notice, this list of conditions and the following disclaimer.
  26  *  - Redistributions in binary form must reproduce the above copyright
  27  *    notice, this list of conditions and the following disclaimer in
  28  *    the documentation and/or other materials provided with the
  29  *    distribution.
  30  *  - Neither the name of Intel Corporation nor the names of its
  31  *    contributors may be used to endorse or promote products derived
  32  *    from this software without specific prior written permission.
  33  *
  34  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  35  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  36  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  37  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  38  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  39  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  40  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  41  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  42  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  43  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  44  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  45  *
  46  */
  47
  48 #ifndef _COMMON_H
  49 #define _COMMON_H
  50
  51 #include <rdma/hfi/hfi1_user.h>
  52
  53 /*
  54  * This file contains defines, structures, etc. that are used
  55  * to communicate between kernel and user code.
  56  */
  57
  58 /* version of protocol header (known to chip also). In the long run,
  59  * we should be able to generate and accept a range of version numbers;
  60  * for now we only accept one, and it's compiled in.
  61  */
  62 #define IPS_PROTO_VERSION 2
  63
  64 /*
  65  * These are compile time constants that you may want to enable or disable
  66  * if you are trying to debug problems with code or performance.
  67  * HFI1_VERBOSE_TRACING define as 1 if you want additional tracing in
  68  * fast path code
  69  * HFI1_TRACE_REGWRITES define as 1 if you want register writes to be
  70  * traced in fast path code
  71  * _HFI1_TRACING define as 0 if you want to remove all tracing in a
  72  * compilation unit
  73  */
  74
  75 /*
  76  * If a packet's QP[23:16] bits match this value, then it is
  77  * a PSM packet and the hardware will expect a KDETH header
  78  * following the BTH.
  79  */
  80 #define DEFAULT_KDETH_QP 0x80
  81
  82 /* driver/hw feature set bitmask */
  83 #define HFI1_CAP_USER_SHIFT      24
  84 #define HFI1_CAP_MASK            ((1UL << HFI1_CAP_USER_SHIFT) - 1)
  85 /* locked flag - if set, only HFI1_CAP_WRITABLE_MASK bits can be set */
  86 #define HFI1_CAP_LOCKED_SHIFT    63
  87 #define HFI1_CAP_LOCKED_MASK     0x1ULL
  88 #define HFI1_CAP_LOCKED_SMASK    (HFI1_CAP_LOCKED_MASK << HFI1_CAP_LOCKED_SHIFT)
  89 /* extra bits used between kernel and user processes */
  90 #define HFI1_CAP_MISC_SHIFT      (HFI1_CAP_USER_SHIFT * 2)
  91 #define HFI1_CAP_MISC_MASK       ((1ULL << (HFI1_CAP_LOCKED_SHIFT - \
  92                                            HFI1_CAP_MISC_SHIFT)) - 1)
  93
  94 #define HFI1_CAP_KSET(cap) ({ hfi1_cap_mask |= HFI1_CAP_##cap; hfi1_cap_mask; })
  95 #define HFI1_CAP_KCLEAR(cap)                                            \
  96         ({                                                              \
  97                 hfi1_cap_mask &= ~HFI1_CAP_##cap;                       \
  98                 hfi1_cap_mask;                                          \
  99         })
 100 #define HFI1_CAP_USET(cap)                                              \
 101         ({                                                              \
 102                 hfi1_cap_mask |= (HFI1_CAP_##cap << HFI1_CAP_USER_SHIFT); \
 103                 hfi1_cap_mask;                                          \
 104                 })
 105 #define HFI1_CAP_UCLEAR(cap)                                            \
 106         ({                                                              \
 107                 hfi1_cap_mask &= ~(HFI1_CAP_##cap << HFI1_CAP_USER_SHIFT); \
 108                 hfi1_cap_mask;                                          \
 109         })
 110 #define HFI1_CAP_SET(cap)                                               \
 111         ({                                                              \
 112                 hfi1_cap_mask |= (HFI1_CAP_##cap | (HFI1_CAP_##cap <<   \
 113                                                   HFI1_CAP_USER_SHIFT)); \
 114                 hfi1_cap_mask;                                          \
 115         })
 116 #define HFI1_CAP_CLEAR(cap)                                             \
 117         ({                                                              \
 118                 hfi1_cap_mask &= ~(HFI1_CAP_##cap |                     \
 119                                   (HFI1_CAP_##cap << HFI1_CAP_USER_SHIFT)); \
 120                 hfi1_cap_mask;                                          \
 121         })
 122 #define HFI1_CAP_LOCK()                                                 \
 123         ({ hfi1_cap_mask |= HFI1_CAP_LOCKED_SMASK; hfi1_cap_mask; })
 124 #define HFI1_CAP_LOCKED() (!!(hfi1_cap_mask & HFI1_CAP_LOCKED_SMASK))
 125 /*
 126  * The set of capability bits that can be changed after initial load
 127  * This set is the same for kernel and user contexts. However, for
 128  * user contexts, the set can be further filtered by using the
 129  * HFI1_CAP_RESERVED_MASK bits.
 130  */
 131 #define HFI1_CAP_WRITABLE_MASK   (HFI1_CAP_SDMA_AHG |                   \
 132                                   HFI1_CAP_HDRSUPP |                    \
 133                                   HFI1_CAP_MULTI_PKT_EGR |              \
 134                                   HFI1_CAP_NODROP_RHQ_FULL |            \
 135                                   HFI1_CAP_NODROP_EGR_FULL |            \
 136                                   HFI1_CAP_ALLOW_PERM_JKEY |            \
 137                                   HFI1_CAP_STATIC_RATE_CTRL |           \
 138                                   HFI1_CAP_PRINT_UNIMPL |               \
 139                                   HFI1_CAP_TID_UNMAP)
 140 /*
 141  * A set of capability bits that are "global" and are not allowed to be
 142  * set in the user bitmask.
 143  */
 144 #define HFI1_CAP_RESERVED_MASK   ((HFI1_CAP_SDMA |                      \
 145                                   HFI1_CAP_USE_SDMA_HEAD |              \
 146                                   HFI1_CAP_EXTENDED_PSN |               \
 147                                   HFI1_CAP_PRINT_UNIMPL |               \
 148                                   HFI1_CAP_NO_INTEGRITY |               \
 149                                   HFI1_CAP_PKEY_CHECK) <<               \
 150                                  HFI1_CAP_USER_SHIFT)
 151 /*
 152  * Set of capabilities that need to be enabled for kernel context in
 153  * order to be allowed for user contexts, as well.
 154  */
 155 #define HFI1_CAP_MUST_HAVE_KERN (HFI1_CAP_STATIC_RATE_CTRL)
 156 /* Default enabled capabilities (both kernel and user) */
 157 #define HFI1_CAP_MASK_DEFAULT    (HFI1_CAP_HDRSUPP |                    \
 158                                  HFI1_CAP_NODROP_RHQ_FULL |             \
 159                                  HFI1_CAP_NODROP_EGR_FULL |             \
 160                                  HFI1_CAP_SDMA |                        \
 161                                  HFI1_CAP_PRINT_UNIMPL |                \
 162                                  HFI1_CAP_STATIC_RATE_CTRL |            \
 163                                  HFI1_CAP_PKEY_CHECK |                  \
 164                                  HFI1_CAP_MULTI_PKT_EGR |               \
 165                                  HFI1_CAP_EXTENDED_PSN |                \
 166                                  ((HFI1_CAP_HDRSUPP |                   \
 167                                    HFI1_CAP_MULTI_PKT_EGR |             \
 168                                    HFI1_CAP_STATIC_RATE_CTRL |          \
 169                                    HFI1_CAP_PKEY_CHECK |                \
 170                                    HFI1_CAP_EARLY_CREDIT_RETURN) <<     \
 171                                   HFI1_CAP_USER_SHIFT))
 172 /*
 173  * A bitmask of kernel/global capabilities that should be communicated
 174  * to user level processes.
 175  */
 176 #define HFI1_CAP_K2U (HFI1_CAP_SDMA |                   \
 177                      HFI1_CAP_EXTENDED_PSN |            \
 178                      HFI1_CAP_PKEY_CHECK |              \
 179                      HFI1_CAP_NO_INTEGRITY)
 180
 181 #define HFI1_USER_SWVERSION ((HFI1_USER_SWMAJOR << HFI1_SWMAJOR_SHIFT) | \
 182                              HFI1_USER_SWMINOR)
 183
 184 #ifndef HFI1_KERN_TYPE
 185 #define HFI1_KERN_TYPE 0
 186 #endif
 187
 188 /*
 189  * Similarly, this is the kernel version going back to the user.  It's
 190  * slightly different, in that we want to tell if the driver was built as
 191  * part of a Intel release, or from the driver from openfabrics.org,
 192  * kernel.org, or a standard distribution, for support reasons.
 193  * The high bit is 0 for non-Intel and 1 for Intel-built/supplied.
 194  *
 195  * It's returned by the driver to the user code during initialization in the
 196  * spi_sw_version field of hfi1_base_info, so the user code can in turn
 197  * check for compatibility with the kernel.
 198 */
 199 #define HFI1_KERN_SWVERSION ((HFI1_KERN_TYPE << 31) | HFI1_USER_SWVERSION)
 200
 201 /*
 202  * Define the driver version number.  This is something that refers only
 203  * to the driver itself, not the software interfaces it supports.
 204  */
 205 #ifndef HFI1_DRIVER_VERSION_BASE
 206 #define HFI1_DRIVER_VERSION_BASE "0.9-294"
 207 #endif
 208
 209 /* create the final driver version string */
 210 #ifdef HFI1_IDSTR
 211 #define HFI1_DRIVER_VERSION HFI1_DRIVER_VERSION_BASE " " HFI1_IDSTR
 212 #else
 213 #define HFI1_DRIVER_VERSION HFI1_DRIVER_VERSION_BASE
 214 #endif
 215
 216 /*
 217  * Diagnostics can send a packet by writing the following
 218  * struct to the diag packet special file.
 219  *
 220  * This allows a custom PBC qword, so that special modes and deliberate
 221  * changes to CRCs can be used.
 222  */
 223 #define _DIAG_PKT_VERS 1
 224 struct diag_pkt {
 225         __u16 version;          /* structure version */
 226         __u16 unit;             /* which device */
 227         __u16 sw_index;         /* send sw index to use */
 228         __u16 len;              /* data length, in bytes */
 229         __u16 port;             /* port number */
 230         __u16 unused;
 231         __u32 flags;            /* call flags */
 232         __u64 data;             /* user data pointer */
 233         __u64 pbc;              /* PBC for the packet */
 234 };
 235
 236 /* diag_pkt flags */
 237 #define F_DIAGPKT_WAIT 0x1      /* wait until packet is sent */
 238
 239 /*
 240  * The next set of defines are for packet headers, and chip register
 241  * and memory bits that are visible to and/or used by user-mode software.
 242  */
 243
 244 /*
 245  * Receive Header Flags
 246  */
 247 #define RHF_PKT_LEN_SHIFT       0
 248 #define RHF_PKT_LEN_MASK        0xfffull
 249 #define RHF_PKT_LEN_SMASK (RHF_PKT_LEN_MASK << RHF_PKT_LEN_SHIFT)
 250
 251 #define RHF_RCV_TYPE_SHIFT      12
 252 #define RHF_RCV_TYPE_MASK       0x7ull
 253 #define RHF_RCV_TYPE_SMASK (RHF_RCV_TYPE_MASK << RHF_RCV_TYPE_SHIFT)
 254
 255 #define RHF_USE_EGR_BFR_SHIFT   15
 256 #define RHF_USE_EGR_BFR_MASK    0x1ull
 257 #define RHF_USE_EGR_BFR_SMASK (RHF_USE_EGR_BFR_MASK << RHF_USE_EGR_BFR_SHIFT)
 258
 259 #define RHF_EGR_INDEX_SHIFT     16
 260 #define RHF_EGR_INDEX_MASK      0x7ffull
 261 #define RHF_EGR_INDEX_SMASK (RHF_EGR_INDEX_MASK << RHF_EGR_INDEX_SHIFT)
 262
 263 #define RHF_DC_INFO_SHIFT       27
 264 #define RHF_DC_INFO_MASK        0x1ull
 265 #define RHF_DC_INFO_SMASK (RHF_DC_INFO_MASK << RHF_DC_INFO_SHIFT)
 266
 267 #define RHF_RCV_SEQ_SHIFT       28
 268 #define RHF_RCV_SEQ_MASK        0xfull
 269 #define RHF_RCV_SEQ_SMASK (RHF_RCV_SEQ_MASK << RHF_RCV_SEQ_SHIFT)
 270
 271 #define RHF_EGR_OFFSET_SHIFT    32
 272 #define RHF_EGR_OFFSET_MASK     0xfffull
 273 #define RHF_EGR_OFFSET_SMASK (RHF_EGR_OFFSET_MASK << RHF_EGR_OFFSET_SHIFT)
 274 #define RHF_HDRQ_OFFSET_SHIFT   44
 275 #define RHF_HDRQ_OFFSET_MASK    0x1ffull
 276 #define RHF_HDRQ_OFFSET_SMASK (RHF_HDRQ_OFFSET_MASK << RHF_HDRQ_OFFSET_SHIFT)
 277 #define RHF_K_HDR_LEN_ERR       (0x1ull << 53)
 278 #define RHF_DC_UNC_ERR          (0x1ull << 54)
 279 #define RHF_DC_ERR              (0x1ull << 55)
 280 #define RHF_RCV_TYPE_ERR_SHIFT  56
 281 #define RHF_RCV_TYPE_ERR_MASK   0x7ul
 282 #define RHF_RCV_TYPE_ERR_SMASK (RHF_RCV_TYPE_ERR_MASK << RHF_RCV_TYPE_ERR_SHIFT)
 283 #define RHF_TID_ERR             (0x1ull << 59)
 284 #define RHF_LEN_ERR             (0x1ull << 60)
 285 #define RHF_ECC_ERR             (0x1ull << 61)
 286 #define RHF_VCRC_ERR            (0x1ull << 62)
 287 #define RHF_ICRC_ERR            (0x1ull << 63)
 288
 289 #define RHF_ERROR_SMASK 0xffe0000000000000ull           /* bits 63:53 */
 290
 291 /* RHF receive types */
 292 #define RHF_RCV_TYPE_EXPECTED 0
 293 #define RHF_RCV_TYPE_EAGER    1
 294 #define RHF_RCV_TYPE_IB       2 /* normal IB, IB Raw, or IPv6 */
 295 #define RHF_RCV_TYPE_ERROR    3
 296 #define RHF_RCV_TYPE_BYPASS   4
 297 #define RHF_RCV_TYPE_INVALID5 5
 298 #define RHF_RCV_TYPE_INVALID6 6
 299 #define RHF_RCV_TYPE_INVALID7 7
 300
 301 /* RHF receive type error - expected packet errors */
 302 #define RHF_RTE_EXPECTED_FLOW_SEQ_ERR   0x2
 303 #define RHF_RTE_EXPECTED_FLOW_GEN_ERR   0x4
 304
 305 /* RHF receive type error - eager packet errors */
 306 #define RHF_RTE_EAGER_NO_ERR            0x0
 307
 308 /* RHF receive type error - IB packet errors */
 309 #define RHF_RTE_IB_NO_ERR               0x0
 310
 311 /* RHF receive type error - error packet errors */
 312 #define RHF_RTE_ERROR_NO_ERR            0x0
 313 #define RHF_RTE_ERROR_OP_CODE_ERR       0x1
 314 #define RHF_RTE_ERROR_KHDR_MIN_LEN_ERR  0x2
 315 #define RHF_RTE_ERROR_KHDR_HCRC_ERR     0x3
 316 #define RHF_RTE_ERROR_KHDR_KVER_ERR     0x4
 317 #define RHF_RTE_ERROR_CONTEXT_ERR       0x5
 318 #define RHF_RTE_ERROR_KHDR_TID_ERR      0x6
 319
 320 /* RHF receive type error - bypass packet errors */
 321 #define RHF_RTE_BYPASS_NO_ERR           0x0
 322
 323 /*
 324  * This structure contains the first field common to all protocols
 325  * that employ this chip.
 326  */
 327 struct hfi1_message_header {
 328         __be16 lrh[4];
 329 };
 330
 331 /* IB - LRH header constants */
 332 #define HFI1_LRH_GRH 0x0003      /* 1. word of IB LRH - next header: GRH */
 333 #define HFI1_LRH_BTH 0x0002      /* 1. word of IB LRH - next header: BTH */
 334
 335 /* misc. */
 336 #define SIZE_OF_CRC 1
 337
 338 #define LIM_MGMT_P_KEY       0x7FFF
 339 #define FULL_MGMT_P_KEY      0xFFFF
 340
 341 #define DEFAULT_P_KEY LIM_MGMT_P_KEY
 342 #define HFI1_AETH_CREDIT_SHIFT 24
 343 #define HFI1_AETH_CREDIT_MASK 0x1F
 344 #define HFI1_AETH_CREDIT_INVAL 0x1F
 345 #define HFI1_MSN_MASK 0xFFFFFF
 346 #define HFI1_FECN_SHIFT 31
 347 #define HFI1_FECN_MASK 1
 348 #define HFI1_FECN_SMASK BIT(HFI1_FECN_SHIFT)
 349 #define HFI1_BECN_SHIFT 30
 350 #define HFI1_BECN_MASK 1
 351 #define HFI1_BECN_SMASK BIT(HFI1_BECN_SHIFT)
 352
 353 #define HFI1_PSM_IOC_BASE_SEQ 0x0
 354
 355 static inline __u64 rhf_to_cpu(const __le32 *rbuf)
 356 {
 357         return __le64_to_cpu(*((__le64 *)rbuf));
 358 }
 359
 360 static inline u64 rhf_err_flags(u64 rhf)
 361 {
 362         return rhf & RHF_ERROR_SMASK;
 363 }
 364
 365 static inline u32 rhf_rcv_type(u64 rhf)
 366 {
 367         return (rhf >> RHF_RCV_TYPE_SHIFT) & RHF_RCV_TYPE_MASK;
 368 }
 369
 370 static inline u32 rhf_rcv_type_err(u64 rhf)
 371 {
 372         return (rhf >> RHF_RCV_TYPE_ERR_SHIFT) & RHF_RCV_TYPE_ERR_MASK;
 373 }
 374
 375 /* return size is in bytes, not DWORDs */
 376 static inline u32 rhf_pkt_len(u64 rhf)
 377 {
 378         return ((rhf & RHF_PKT_LEN_SMASK) >> RHF_PKT_LEN_SHIFT) << 2;
 379 }
 380
 381 static inline u32 rhf_egr_index(u64 rhf)
 382 {
 383         return (rhf >> RHF_EGR_INDEX_SHIFT) & RHF_EGR_INDEX_MASK;
 384 }
 385
 386 static inline u32 rhf_rcv_seq(u64 rhf)
 387 {
 388         return (rhf >> RHF_RCV_SEQ_SHIFT) & RHF_RCV_SEQ_MASK;
 389 }
 390
 391 /* returned offset is in DWORDS */
 392 static inline u32 rhf_hdrq_offset(u64 rhf)
 393 {
 394         return (rhf >> RHF_HDRQ_OFFSET_SHIFT) & RHF_HDRQ_OFFSET_MASK;
 395 }
 396
 397 static inline u64 rhf_use_egr_bfr(u64 rhf)
 398 {
 399         return rhf & RHF_USE_EGR_BFR_SMASK;
 400 }
 401
 402 static inline u64 rhf_dc_info(u64 rhf)
 403 {
 404         return rhf & RHF_DC_INFO_SMASK;
 405 }
 406
 407 static inline u32 rhf_egr_buf_offset(u64 rhf)
 408 {
 409         return (rhf >> RHF_EGR_OFFSET_SHIFT) & RHF_EGR_OFFSET_MASK;
 410 }
 411 #endif /* _COMMON_H */