2 * Copyright(c) 2015-2017 Intel Corporation.
4 * This file is provided under a dual BSD/GPLv2 license. When using or
5 * redistributing this file, you may do so under either license.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions
24 * - Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * - Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in
28 * the documentation and/or other materials provided with the
30 * - Neither the name of Intel Corporation nor the names of its
31 * contributors may be used to endorse or promote products derived
32 * from this software without specific prior written permission.
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
48 #include <linux/pci.h>
49 #include <linux/netdevice.h>
50 #include <linux/vmalloc.h>
51 #include <linux/delay.h>
52 #include <linux/idr.h>
53 #include <linux/module.h>
54 #include <linux/printk.h>
55 #include <linux/hrtimer.h>
56 #include <rdma/rdma_vt.h>
71 #define pr_fmt(fmt) DRIVER_NAME ": " fmt
73 #define HFI1_MAX_ACTIVE_WORKQUEUE_ENTRIES 5
75 * min buffers we want to have per context, after driver
77 #define HFI1_MIN_USER_CTXT_BUFCNT 7
79 #define HFI1_MIN_HDRQ_EGRBUF_CNT 2
80 #define HFI1_MAX_HDRQ_EGRBUF_CNT 16352
81 #define HFI1_MIN_EAGER_BUFFER_SIZE (4 * 1024) /* 4KB */
82 #define HFI1_MAX_EAGER_BUFFER_SIZE (256 * 1024) /* 256KB */
85 * Number of user receive contexts we are configured to use (to allow for more
86 * pio buffers per ctxt, etc.) Zero means use one user context per CPU.
88 int num_user_contexts
= -1;
89 module_param_named(num_user_contexts
, num_user_contexts
, uint
, S_IRUGO
);
91 num_user_contexts
, "Set max number of user contexts to use");
93 uint krcvqs
[RXE_NUM_DATA_VL
];
95 module_param_array(krcvqs
, uint
, &krcvqsset
, S_IRUGO
);
96 MODULE_PARM_DESC(krcvqs
, "Array of the number of non-control kernel receive queues by VL");
98 /* computed based on above array */
99 unsigned long n_krcvqs
;
101 static unsigned hfi1_rcvarr_split
= 25;
102 module_param_named(rcvarr_split
, hfi1_rcvarr_split
, uint
, S_IRUGO
);
103 MODULE_PARM_DESC(rcvarr_split
, "Percent of context's RcvArray entries used for Eager buffers");
105 static uint eager_buffer_size
= (8 << 20); /* 8MB */
106 module_param(eager_buffer_size
, uint
, S_IRUGO
);
107 MODULE_PARM_DESC(eager_buffer_size
, "Size of the eager buffers, default: 8MB");
109 static uint rcvhdrcnt
= 2048; /* 2x the max eager buffer count */
110 module_param_named(rcvhdrcnt
, rcvhdrcnt
, uint
, S_IRUGO
);
111 MODULE_PARM_DESC(rcvhdrcnt
, "Receive header queue count (default 2048)");
113 static uint hfi1_hdrq_entsize
= 32;
114 module_param_named(hdrq_entsize
, hfi1_hdrq_entsize
, uint
, S_IRUGO
);
115 MODULE_PARM_DESC(hdrq_entsize
, "Size of header queue entries: 2 - 8B, 16 - 64B (default), 32 - 128B");
117 unsigned int user_credit_return_threshold
= 33; /* default is 33% */
118 module_param(user_credit_return_threshold
, uint
, S_IRUGO
);
119 MODULE_PARM_DESC(user_credit_return_threshold
, "Credit return threshold for user send contexts, return when unreturned credits passes this many blocks (in percent of allocated blocks, 0 is off)");
121 static inline u64
encode_rcv_header_entry_size(u16 size
);
123 static struct idr hfi1_unit_table
;
124 u32 hfi1_cpulist_count
;
125 unsigned long *hfi1_cpulist
;
128 * Common code for creating the receive context array.
130 int hfi1_create_ctxts(struct hfi1_devdata
*dd
)
135 /* Control context has to be always 0 */
136 BUILD_BUG_ON(HFI1_CTRL_CTXT
!= 0);
138 dd
->rcd
= kzalloc_node(dd
->num_rcv_contexts
* sizeof(*dd
->rcd
),
139 GFP_KERNEL
, dd
->node
);
143 /* create one or more kernel contexts */
144 for (i
= 0; i
< dd
->first_dyn_alloc_ctxt
; ++i
) {
145 struct hfi1_pportdata
*ppd
;
146 struct hfi1_ctxtdata
*rcd
;
148 ppd
= dd
->pport
+ (i
% dd
->num_pports
);
150 /* dd->rcd[i] gets assigned inside the callee */
151 rcd
= hfi1_create_ctxtdata(ppd
, i
, dd
->node
);
154 "Unable to allocate kernel receive context, failing\n");
158 * Set up the kernel context flags here and now because they
159 * use default values for all receive side memories. User
160 * contexts will be handled as they are created.
162 rcd
->flags
= HFI1_CAP_KGET(MULTI_PKT_EGR
) |
163 HFI1_CAP_KGET(NODROP_RHQ_FULL
) |
164 HFI1_CAP_KGET(NODROP_EGR_FULL
) |
165 HFI1_CAP_KGET(DMA_RTAIL
);
167 /* Control context must use DMA_RTAIL */
168 if (rcd
->ctxt
== HFI1_CTRL_CTXT
)
169 rcd
->flags
|= HFI1_CAP_DMA_RTAIL
;
172 rcd
->sc
= sc_alloc(dd
, SC_ACK
, rcd
->rcvhdrqentsize
, dd
->node
);
175 "Unable to allocate kernel send context, failing\n");
179 ret
= hfi1_init_ctxt(rcd
->sc
);
182 "Failed to setup kernel receive context, failing\n");
189 * Initialize aspm, to be done after gen3 transition and setting up
190 * contexts and before enabling interrupts
199 for (i
= 0; i
< dd
->num_rcv_contexts
; ++i
)
200 hfi1_free_ctxtdata(dd
, dd
->rcd
[i
]);
208 * Common code for user and kernel context setup.
210 struct hfi1_ctxtdata
*hfi1_create_ctxtdata(struct hfi1_pportdata
*ppd
, u32 ctxt
,
213 struct hfi1_devdata
*dd
= ppd
->dd
;
214 struct hfi1_ctxtdata
*rcd
;
215 unsigned kctxt_ngroups
= 0;
218 if (dd
->rcv_entries
.nctxt_extra
>
219 dd
->num_rcv_contexts
- dd
->first_dyn_alloc_ctxt
)
220 kctxt_ngroups
= (dd
->rcv_entries
.nctxt_extra
-
221 (dd
->num_rcv_contexts
- dd
->first_dyn_alloc_ctxt
));
222 rcd
= kzalloc_node(sizeof(*rcd
), GFP_KERNEL
, numa
);
224 u32 rcvtids
, max_entries
;
226 hfi1_cdbg(PROC
, "setting up context %u\n", ctxt
);
228 INIT_LIST_HEAD(&rcd
->qp_wait_list
);
235 rcd
->rcv_array_groups
= dd
->rcv_entries
.ngroups
;
237 mutex_init(&rcd
->exp_lock
);
240 * Calculate the context's RcvArray entry starting point.
241 * We do this here because we have to take into account all
242 * the RcvArray entries that previous context would have
243 * taken and we have to account for any extra groups assigned
244 * to the static (kernel) or dynamic (vnic/user) contexts.
246 if (ctxt
< dd
->first_dyn_alloc_ctxt
) {
247 if (ctxt
< kctxt_ngroups
) {
248 base
= ctxt
* (dd
->rcv_entries
.ngroups
+ 1);
249 rcd
->rcv_array_groups
++;
251 base
= kctxt_ngroups
+
252 (ctxt
* dd
->rcv_entries
.ngroups
);
255 u16 ct
= ctxt
- dd
->first_dyn_alloc_ctxt
;
257 base
= ((dd
->n_krcv_queues
* dd
->rcv_entries
.ngroups
) +
259 if (ct
< dd
->rcv_entries
.nctxt_extra
) {
260 base
+= ct
* (dd
->rcv_entries
.ngroups
+ 1);
261 rcd
->rcv_array_groups
++;
263 base
+= dd
->rcv_entries
.nctxt_extra
+
264 (ct
* dd
->rcv_entries
.ngroups
);
267 rcd
->eager_base
= base
* dd
->rcv_entries
.group_size
;
269 rcd
->rcvhdrq_cnt
= rcvhdrcnt
;
270 rcd
->rcvhdrqentsize
= hfi1_hdrq_entsize
;
272 * Simple Eager buffer allocation: we have already pre-allocated
273 * the number of RcvArray entry groups. Each ctxtdata structure
274 * holds the number of groups for that context.
276 * To follow CSR requirements and maintain cacheline alignment,
277 * make sure all sizes and bases are multiples of group_size.
279 * The expected entry count is what is left after assigning
282 max_entries
= rcd
->rcv_array_groups
*
283 dd
->rcv_entries
.group_size
;
284 rcvtids
= ((max_entries
* hfi1_rcvarr_split
) / 100);
285 rcd
->egrbufs
.count
= round_down(rcvtids
,
286 dd
->rcv_entries
.group_size
);
287 if (rcd
->egrbufs
.count
> MAX_EAGER_ENTRIES
) {
288 dd_dev_err(dd
, "ctxt%u: requested too many RcvArray entries.\n",
290 rcd
->egrbufs
.count
= MAX_EAGER_ENTRIES
;
293 "ctxt%u: max Eager buffer RcvArray entries: %u\n",
294 rcd
->ctxt
, rcd
->egrbufs
.count
);
297 * Allocate array that will hold the eager buffer accounting
299 * This will allocate the maximum possible buffer count based
300 * on the value of the RcvArray split parameter.
301 * The resulting value will be rounded down to the closest
302 * multiple of dd->rcv_entries.group_size.
304 rcd
->egrbufs
.buffers
= kzalloc_node(
305 rcd
->egrbufs
.count
* sizeof(*rcd
->egrbufs
.buffers
),
307 if (!rcd
->egrbufs
.buffers
)
309 rcd
->egrbufs
.rcvtids
= kzalloc_node(
311 sizeof(*rcd
->egrbufs
.rcvtids
),
313 if (!rcd
->egrbufs
.rcvtids
)
315 rcd
->egrbufs
.size
= eager_buffer_size
;
317 * The size of the buffers programmed into the RcvArray
318 * entries needs to be big enough to handle the highest
321 if (rcd
->egrbufs
.size
< hfi1_max_mtu
) {
322 rcd
->egrbufs
.size
= __roundup_pow_of_two(hfi1_max_mtu
);
324 "ctxt%u: eager bufs size too small. Adjusting to %zu\n",
325 rcd
->ctxt
, rcd
->egrbufs
.size
);
327 rcd
->egrbufs
.rcvtid_size
= HFI1_MAX_EAGER_BUFFER_SIZE
;
329 /* Applicable only for statically created kernel contexts */
330 if (ctxt
< dd
->first_dyn_alloc_ctxt
) {
331 rcd
->opstats
= kzalloc_node(sizeof(*rcd
->opstats
),
339 dd
->rcd
[ctxt
] = NULL
;
340 kfree(rcd
->egrbufs
.rcvtids
);
341 kfree(rcd
->egrbufs
.buffers
);
347 * Convert a receive header entry size that to the encoding used in the CSR.
349 * Return a zero if the given size is invalid.
351 static inline u64
encode_rcv_header_entry_size(u16 size
)
353 /* there are only 3 valid receive header entry sizes */
360 return 0; /* invalid */
364 * Select the largest ccti value over all SLs to determine the intra-
365 * packet gap for the link.
367 * called with cca_timer_lock held (to protect access to cca_timer
368 * array), and rcu_read_lock() (to protect access to cc_state).
370 void set_link_ipg(struct hfi1_pportdata
*ppd
)
372 struct hfi1_devdata
*dd
= ppd
->dd
;
373 struct cc_state
*cc_state
;
375 u16 cce
, ccti_limit
, max_ccti
= 0;
378 u32 current_egress_rate
; /* Mbits /sec */
381 * max_pkt_time is the maximum packet egress time in units
382 * of the fabric clock period 1/(805 MHz).
385 cc_state
= get_cc_state(ppd
);
389 * This should _never_ happen - rcu_read_lock() is held,
390 * and set_link_ipg() should not be called if cc_state
395 for (i
= 0; i
< OPA_MAX_SLS
; i
++) {
396 u16 ccti
= ppd
->cca_timer
[i
].ccti
;
402 ccti_limit
= cc_state
->cct
.ccti_limit
;
403 if (max_ccti
> ccti_limit
)
404 max_ccti
= ccti_limit
;
406 cce
= cc_state
->cct
.entries
[max_ccti
].entry
;
407 shift
= (cce
& 0xc000) >> 14;
408 mult
= (cce
& 0x3fff);
410 current_egress_rate
= active_egress_rate(ppd
);
412 max_pkt_time
= egress_cycles(ppd
->ibmaxlen
, current_egress_rate
);
414 src
= (max_pkt_time
>> shift
) * mult
;
416 src
&= SEND_STATIC_RATE_CONTROL_CSR_SRC_RELOAD_SMASK
;
417 src
<<= SEND_STATIC_RATE_CONTROL_CSR_SRC_RELOAD_SHIFT
;
419 write_csr(dd
, SEND_STATIC_RATE_CONTROL
, src
);
422 static enum hrtimer_restart
cca_timer_fn(struct hrtimer
*t
)
424 struct cca_timer
*cca_timer
;
425 struct hfi1_pportdata
*ppd
;
427 u16 ccti_timer
, ccti_min
;
428 struct cc_state
*cc_state
;
430 enum hrtimer_restart ret
= HRTIMER_NORESTART
;
432 cca_timer
= container_of(t
, struct cca_timer
, hrtimer
);
433 ppd
= cca_timer
->ppd
;
438 cc_state
= get_cc_state(ppd
);
442 return HRTIMER_NORESTART
;
446 * 1) decrement ccti for SL
447 * 2) calculate IPG for link (set_link_ipg())
448 * 3) restart timer, unless ccti is at min value
451 ccti_min
= cc_state
->cong_setting
.entries
[sl
].ccti_min
;
452 ccti_timer
= cc_state
->cong_setting
.entries
[sl
].ccti_timer
;
454 spin_lock_irqsave(&ppd
->cca_timer_lock
, flags
);
456 if (cca_timer
->ccti
> ccti_min
) {
461 if (cca_timer
->ccti
> ccti_min
) {
462 unsigned long nsec
= 1024 * ccti_timer
;
463 /* ccti_timer is in units of 1.024 usec */
464 hrtimer_forward_now(t
, ns_to_ktime(nsec
));
465 ret
= HRTIMER_RESTART
;
468 spin_unlock_irqrestore(&ppd
->cca_timer_lock
, flags
);
474 * Common code for initializing the physical port structure.
476 void hfi1_init_pportdata(struct pci_dev
*pdev
, struct hfi1_pportdata
*ppd
,
477 struct hfi1_devdata
*dd
, u8 hw_pidx
, u8 port
)
480 uint default_pkey_idx
;
481 struct cc_state
*cc_state
;
484 ppd
->hw_pidx
= hw_pidx
;
485 ppd
->port
= port
; /* IB port number, not index */
487 default_pkey_idx
= 1;
489 ppd
->pkeys
[default_pkey_idx
] = DEFAULT_P_KEY
;
490 ppd
->part_enforce
|= HFI1_PART_ENFORCE_IN
;
491 ppd
->part_enforce
|= HFI1_PART_ENFORCE_OUT
;
494 hfi1_early_err(&pdev
->dev
,
495 "Faking data partition 0x8001 in idx %u\n",
497 ppd
->pkeys
[!default_pkey_idx
] = 0x8001;
500 INIT_WORK(&ppd
->link_vc_work
, handle_verify_cap
);
501 INIT_WORK(&ppd
->link_up_work
, handle_link_up
);
502 INIT_WORK(&ppd
->link_down_work
, handle_link_down
);
503 INIT_WORK(&ppd
->freeze_work
, handle_freeze
);
504 INIT_WORK(&ppd
->link_downgrade_work
, handle_link_downgrade
);
505 INIT_WORK(&ppd
->sma_message_work
, handle_sma_message
);
506 INIT_WORK(&ppd
->link_bounce_work
, handle_link_bounce
);
507 INIT_DELAYED_WORK(&ppd
->start_link_work
, handle_start_link
);
508 INIT_WORK(&ppd
->linkstate_active_work
, receive_interrupt_work
);
509 INIT_WORK(&ppd
->qsfp_info
.qsfp_work
, qsfp_event
);
511 mutex_init(&ppd
->hls_lock
);
512 spin_lock_init(&ppd
->qsfp_info
.qsfp_lock
);
514 ppd
->qsfp_info
.ppd
= ppd
;
515 ppd
->sm_trap_qp
= 0x0;
520 spin_lock_init(&ppd
->cca_timer_lock
);
522 for (i
= 0; i
< OPA_MAX_SLS
; i
++) {
523 hrtimer_init(&ppd
->cca_timer
[i
].hrtimer
, CLOCK_MONOTONIC
,
525 ppd
->cca_timer
[i
].ppd
= ppd
;
526 ppd
->cca_timer
[i
].sl
= i
;
527 ppd
->cca_timer
[i
].ccti
= 0;
528 ppd
->cca_timer
[i
].hrtimer
.function
= cca_timer_fn
;
531 ppd
->cc_max_table_entries
= IB_CC_TABLE_CAP_DEFAULT
;
533 spin_lock_init(&ppd
->cc_state_lock
);
534 spin_lock_init(&ppd
->cc_log_lock
);
535 cc_state
= kzalloc(sizeof(*cc_state
), GFP_KERNEL
);
536 RCU_INIT_POINTER(ppd
->cc_state
, cc_state
);
543 hfi1_early_err(&pdev
->dev
,
544 "Congestion Control Agent disabled for port %d\n", port
);
548 * Do initialization for device that is only needed on
549 * first detect, not on resets.
551 static int loadtime_init(struct hfi1_devdata
*dd
)
557 * init_after_reset - re-initialize after a reset
558 * @dd: the hfi1_ib device
560 * sanity check at least some of the values after reset, and
561 * ensure no receive or transmit (explicitly, in case reset
564 static int init_after_reset(struct hfi1_devdata
*dd
)
569 * Ensure chip does no sends or receives, tail updates, or
570 * pioavail updates while we re-initialize. This is mostly
571 * for the driver data structures, not chip registers.
573 for (i
= 0; i
< dd
->num_rcv_contexts
; i
++)
574 hfi1_rcvctrl(dd
, HFI1_RCVCTRL_CTXT_DIS
|
575 HFI1_RCVCTRL_INTRAVAIL_DIS
|
576 HFI1_RCVCTRL_TAILUPD_DIS
, i
);
577 pio_send_control(dd
, PSC_GLOBAL_DISABLE
);
578 for (i
= 0; i
< dd
->num_send_contexts
; i
++)
579 sc_disable(dd
->send_contexts
[i
].sc
);
584 static void enable_chip(struct hfi1_devdata
*dd
)
589 /* enable PIO send */
590 pio_send_control(dd
, PSC_GLOBAL_ENABLE
);
593 * Enable kernel ctxts' receive and receive interrupt.
594 * Other ctxts done as user opens and initializes them.
596 for (i
= 0; i
< dd
->first_dyn_alloc_ctxt
; ++i
) {
597 rcvmask
= HFI1_RCVCTRL_CTXT_ENB
| HFI1_RCVCTRL_INTRAVAIL_ENB
;
598 rcvmask
|= HFI1_CAP_KGET_MASK(dd
->rcd
[i
]->flags
, DMA_RTAIL
) ?
599 HFI1_RCVCTRL_TAILUPD_ENB
: HFI1_RCVCTRL_TAILUPD_DIS
;
600 if (!HFI1_CAP_KGET_MASK(dd
->rcd
[i
]->flags
, MULTI_PKT_EGR
))
601 rcvmask
|= HFI1_RCVCTRL_ONE_PKT_EGR_ENB
;
602 if (HFI1_CAP_KGET_MASK(dd
->rcd
[i
]->flags
, NODROP_RHQ_FULL
))
603 rcvmask
|= HFI1_RCVCTRL_NO_RHQ_DROP_ENB
;
604 if (HFI1_CAP_KGET_MASK(dd
->rcd
[i
]->flags
, NODROP_EGR_FULL
))
605 rcvmask
|= HFI1_RCVCTRL_NO_EGR_DROP_ENB
;
606 hfi1_rcvctrl(dd
, rcvmask
, i
);
607 sc_enable(dd
->rcd
[i
]->sc
);
612 * create_workqueues - create per port workqueues
613 * @dd: the hfi1_ib device
615 static int create_workqueues(struct hfi1_devdata
*dd
)
618 struct hfi1_pportdata
*ppd
;
620 for (pidx
= 0; pidx
< dd
->num_pports
; ++pidx
) {
621 ppd
= dd
->pport
+ pidx
;
626 WQ_SYSFS
| WQ_HIGHPRI
| WQ_CPU_INTENSIVE
,
627 HFI1_MAX_ACTIVE_WORKQUEUE_ENTRIES
,
635 pr_err("alloc_workqueue failed for port %d\n", pidx
+ 1);
636 for (pidx
= 0; pidx
< dd
->num_pports
; ++pidx
) {
637 ppd
= dd
->pport
+ pidx
;
639 destroy_workqueue(ppd
->hfi1_wq
);
647 * hfi1_init - do the actual initialization sequence on the chip
648 * @dd: the hfi1_ib device
649 * @reinit: re-initializing, so don't allocate new memory
651 * Do the actual initialization sequence on the chip. This is done
652 * both from the init routine called from the PCI infrastructure, and
653 * when we reset the chip, or detect that it was reset internally,
654 * or it's administratively re-enabled.
656 * Memory allocation here and in called routines is only done in
657 * the first case (reinit == 0). We have to be careful, because even
658 * without memory allocation, we need to re-write all the chip registers
659 * TIDs, etc. after the reset or enable has completed.
661 int hfi1_init(struct hfi1_devdata
*dd
, int reinit
)
663 int ret
= 0, pidx
, lastfail
= 0;
665 struct hfi1_ctxtdata
*rcd
;
666 struct hfi1_pportdata
*ppd
;
668 /* Set up recv low level handlers */
669 dd
->normal_rhf_rcv_functions
[RHF_RCV_TYPE_EXPECTED
] =
670 kdeth_process_expected
;
671 dd
->normal_rhf_rcv_functions
[RHF_RCV_TYPE_EAGER
] =
673 dd
->normal_rhf_rcv_functions
[RHF_RCV_TYPE_IB
] = process_receive_ib
;
674 dd
->normal_rhf_rcv_functions
[RHF_RCV_TYPE_ERROR
] =
675 process_receive_error
;
676 dd
->normal_rhf_rcv_functions
[RHF_RCV_TYPE_BYPASS
] =
677 process_receive_bypass
;
678 dd
->normal_rhf_rcv_functions
[RHF_RCV_TYPE_INVALID5
] =
679 process_receive_invalid
;
680 dd
->normal_rhf_rcv_functions
[RHF_RCV_TYPE_INVALID6
] =
681 process_receive_invalid
;
682 dd
->normal_rhf_rcv_functions
[RHF_RCV_TYPE_INVALID7
] =
683 process_receive_invalid
;
684 dd
->rhf_rcv_function_map
= dd
->normal_rhf_rcv_functions
;
686 /* Set up send low level handlers */
687 dd
->process_pio_send
= hfi1_verbs_send_pio
;
688 dd
->process_dma_send
= hfi1_verbs_send_dma
;
689 dd
->pio_inline_send
= pio_copy
;
690 dd
->process_vnic_dma_send
= hfi1_vnic_send_dma
;
693 atomic_set(&dd
->drop_packet
, DROP_PACKET_ON
);
696 atomic_set(&dd
->drop_packet
, DROP_PACKET_OFF
);
700 /* make sure the link is not "up" */
701 for (pidx
= 0; pidx
< dd
->num_pports
; ++pidx
) {
702 ppd
= dd
->pport
+ pidx
;
707 ret
= init_after_reset(dd
);
709 ret
= loadtime_init(dd
);
713 /* allocate dummy tail memory for all receive contexts */
714 dd
->rcvhdrtail_dummy_kvaddr
= dma_zalloc_coherent(
715 &dd
->pcidev
->dev
, sizeof(u64
),
716 &dd
->rcvhdrtail_dummy_dma
,
719 if (!dd
->rcvhdrtail_dummy_kvaddr
) {
720 dd_dev_err(dd
, "cannot allocate dummy tail memory\n");
725 /* dd->rcd can be NULL if early initialization failed */
726 for (i
= 0; dd
->rcd
&& i
< dd
->first_dyn_alloc_ctxt
; ++i
) {
728 * Set up the (kernel) rcvhdr queue and egr TIDs. If doing
729 * re-init, the simplest way to handle this is to free
730 * existing, and re-allocate.
731 * Need to re-create rest of ctxt 0 ctxtdata as well.
737 rcd
->do_interrupt
= &handle_receive_interrupt
;
739 lastfail
= hfi1_create_rcvhdrq(dd
, rcd
);
741 lastfail
= hfi1_setup_eagerbufs(rcd
);
744 "failed to allocate kernel ctxt's rcvhdrq and/or egr bufs\n");
749 /* Allocate enough memory for user event notification. */
750 len
= PAGE_ALIGN(dd
->chip_rcv_contexts
* HFI1_MAX_SHARED_CTXTS
*
751 sizeof(*dd
->events
));
752 dd
->events
= vmalloc_user(len
);
754 dd_dev_err(dd
, "Failed to allocate user events page\n");
756 * Allocate a page for device and port status.
757 * Page will be shared amongst all user processes.
759 dd
->status
= vmalloc_user(PAGE_SIZE
);
761 dd_dev_err(dd
, "Failed to allocate dev status page\n");
763 dd
->freezelen
= PAGE_SIZE
- (sizeof(*dd
->status
) -
764 sizeof(dd
->status
->freezemsg
));
765 for (pidx
= 0; pidx
< dd
->num_pports
; ++pidx
) {
766 ppd
= dd
->pport
+ pidx
;
768 /* Currently, we only have one port */
769 ppd
->statusp
= &dd
->status
->port
;
774 /* enable chip even if we have an error, so we can debug cause */
779 * Set status even if port serdes is not initialized
780 * so that diags will work.
783 dd
->status
->dev
|= HFI1_STATUS_CHIP_PRESENT
|
786 /* enable all interrupts from the chip */
787 set_intr_state(dd
, 1);
789 /* chip is OK for user apps; mark it as initialized */
790 for (pidx
= 0; pidx
< dd
->num_pports
; ++pidx
) {
791 ppd
= dd
->pport
+ pidx
;
794 * start the serdes - must be after interrupts are
795 * enabled so we are notified when the link goes up
797 lastfail
= bringup_serdes(ppd
);
800 "Failed to bring up port %u\n",
804 * Set status even if port serdes is not initialized
805 * so that diags will work.
808 *ppd
->statusp
|= HFI1_STATUS_CHIP_PRESENT
|
810 if (!ppd
->link_speed_enabled
)
815 /* if ret is non-zero, we probably should do some cleanup here... */
819 static inline struct hfi1_devdata
*__hfi1_lookup(int unit
)
821 return idr_find(&hfi1_unit_table
, unit
);
824 struct hfi1_devdata
*hfi1_lookup(int unit
)
826 struct hfi1_devdata
*dd
;
829 spin_lock_irqsave(&hfi1_devs_lock
, flags
);
830 dd
= __hfi1_lookup(unit
);
831 spin_unlock_irqrestore(&hfi1_devs_lock
, flags
);
837 * Stop the timers during unit shutdown, or after an error late
840 static void stop_timers(struct hfi1_devdata
*dd
)
842 struct hfi1_pportdata
*ppd
;
845 for (pidx
= 0; pidx
< dd
->num_pports
; ++pidx
) {
846 ppd
= dd
->pport
+ pidx
;
847 if (ppd
->led_override_timer
.data
) {
848 del_timer_sync(&ppd
->led_override_timer
);
849 atomic_set(&ppd
->led_override_timer_active
, 0);
855 * shutdown_device - shut down a device
856 * @dd: the hfi1_ib device
858 * This is called to make the device quiet when we are about to
859 * unload the driver, and also when the device is administratively
860 * disabled. It does not free any data structures.
861 * Everything it does has to be setup again by hfi1_init(dd, 1)
863 static void shutdown_device(struct hfi1_devdata
*dd
)
865 struct hfi1_pportdata
*ppd
;
869 for (pidx
= 0; pidx
< dd
->num_pports
; ++pidx
) {
870 ppd
= dd
->pport
+ pidx
;
874 *ppd
->statusp
&= ~(HFI1_STATUS_IB_CONF
|
875 HFI1_STATUS_IB_READY
);
877 dd
->flags
&= ~HFI1_INITTED
;
879 /* mask interrupts, but not errors */
880 set_intr_state(dd
, 0);
882 for (pidx
= 0; pidx
< dd
->num_pports
; ++pidx
) {
883 ppd
= dd
->pport
+ pidx
;
884 for (i
= 0; i
< dd
->num_rcv_contexts
; i
++)
885 hfi1_rcvctrl(dd
, HFI1_RCVCTRL_TAILUPD_DIS
|
886 HFI1_RCVCTRL_CTXT_DIS
|
887 HFI1_RCVCTRL_INTRAVAIL_DIS
|
888 HFI1_RCVCTRL_PKEY_DIS
|
889 HFI1_RCVCTRL_ONE_PKT_EGR_DIS
, i
);
891 * Gracefully stop all sends allowing any in progress to
894 for (i
= 0; i
< dd
->num_send_contexts
; i
++)
895 sc_flush(dd
->send_contexts
[i
].sc
);
899 * Enough for anything that's going to trickle out to have actually
904 for (pidx
= 0; pidx
< dd
->num_pports
; ++pidx
) {
905 ppd
= dd
->pport
+ pidx
;
907 /* disable all contexts */
908 for (i
= 0; i
< dd
->num_send_contexts
; i
++)
909 sc_disable(dd
->send_contexts
[i
].sc
);
910 /* disable the send device */
911 pio_send_control(dd
, PSC_GLOBAL_DISABLE
);
913 shutdown_led_override(ppd
);
916 * Clear SerdesEnable.
917 * We can't count on interrupts since we are stopping.
919 hfi1_quiet_serdes(ppd
);
922 destroy_workqueue(ppd
->hfi1_wq
);
930 * hfi1_free_ctxtdata - free a context's allocated data
931 * @dd: the hfi1_ib device
932 * @rcd: the ctxtdata structure
934 * free up any allocated data for a context
935 * This should not touch anything that would affect a simultaneous
936 * re-allocation of context data, because it is called after hfi1_mutex
937 * is released (and can be called from reinit as well).
938 * It should never change any chip state, or global driver state.
940 void hfi1_free_ctxtdata(struct hfi1_devdata
*dd
, struct hfi1_ctxtdata
*rcd
)
948 dma_free_coherent(&dd
->pcidev
->dev
, rcd
->rcvhdrq_size
,
949 rcd
->rcvhdrq
, rcd
->rcvhdrq_dma
);
951 if (rcd
->rcvhdrtail_kvaddr
) {
952 dma_free_coherent(&dd
->pcidev
->dev
, PAGE_SIZE
,
953 (void *)rcd
->rcvhdrtail_kvaddr
,
954 rcd
->rcvhdrqtailaddr_dma
);
955 rcd
->rcvhdrtail_kvaddr
= NULL
;
959 /* all the RcvArray entries should have been cleared by now */
960 kfree(rcd
->egrbufs
.rcvtids
);
962 for (e
= 0; e
< rcd
->egrbufs
.alloced
; e
++) {
963 if (rcd
->egrbufs
.buffers
[e
].dma
)
964 dma_free_coherent(&dd
->pcidev
->dev
,
965 rcd
->egrbufs
.buffers
[e
].len
,
966 rcd
->egrbufs
.buffers
[e
].addr
,
967 rcd
->egrbufs
.buffers
[e
].dma
);
969 kfree(rcd
->egrbufs
.buffers
);
972 vfree(rcd
->user_event_mask
);
973 vfree(rcd
->subctxt_uregbase
);
974 vfree(rcd
->subctxt_rcvegrbuf
);
975 vfree(rcd
->subctxt_rcvhdr_base
);
981 * Release our hold on the shared asic data. If we are the last one,
982 * return the structure to be finalized outside the lock. Must be
983 * holding hfi1_devs_lock.
985 static struct hfi1_asic_data
*release_asic_data(struct hfi1_devdata
*dd
)
987 struct hfi1_asic_data
*ad
;
992 dd
->asic_data
->dds
[dd
->hfi1_id
] = NULL
;
993 other
= dd
->hfi1_id
? 0 : 1;
995 dd
->asic_data
= NULL
;
996 /* return NULL if the other dd still has a link */
997 return ad
->dds
[other
] ? NULL
: ad
;
1000 static void finalize_asic_data(struct hfi1_devdata
*dd
,
1001 struct hfi1_asic_data
*ad
)
1003 clean_up_i2c(dd
, ad
);
1007 static void __hfi1_free_devdata(struct kobject
*kobj
)
1009 struct hfi1_devdata
*dd
=
1010 container_of(kobj
, struct hfi1_devdata
, kobj
);
1011 struct hfi1_asic_data
*ad
;
1012 unsigned long flags
;
1014 spin_lock_irqsave(&hfi1_devs_lock
, flags
);
1015 idr_remove(&hfi1_unit_table
, dd
->unit
);
1016 list_del(&dd
->list
);
1017 ad
= release_asic_data(dd
);
1018 spin_unlock_irqrestore(&hfi1_devs_lock
, flags
);
1020 finalize_asic_data(dd
, ad
);
1021 free_platform_config(dd
);
1022 rcu_barrier(); /* wait for rcu callbacks to complete */
1023 free_percpu(dd
->int_counter
);
1024 free_percpu(dd
->rcv_limit
);
1025 free_percpu(dd
->send_schedule
);
1026 rvt_dealloc_device(&dd
->verbs_dev
.rdi
);
1029 static struct kobj_type hfi1_devdata_type
= {
1030 .release
= __hfi1_free_devdata
,
1033 void hfi1_free_devdata(struct hfi1_devdata
*dd
)
1035 kobject_put(&dd
->kobj
);
1039 * Allocate our primary per-unit data structure. Must be done via verbs
1040 * allocator, because the verbs cleanup process both does cleanup and
1041 * free of the data structure.
1042 * "extra" is for chip-specific data.
1044 * Use the idr mechanism to get a unit number for this unit.
1046 struct hfi1_devdata
*hfi1_alloc_devdata(struct pci_dev
*pdev
, size_t extra
)
1048 unsigned long flags
;
1049 struct hfi1_devdata
*dd
;
1052 /* extra is * number of ports */
1053 nports
= extra
/ sizeof(struct hfi1_pportdata
);
1055 dd
= (struct hfi1_devdata
*)rvt_alloc_device(sizeof(*dd
) + extra
,
1058 return ERR_PTR(-ENOMEM
);
1059 dd
->num_pports
= nports
;
1060 dd
->pport
= (struct hfi1_pportdata
*)(dd
+ 1);
1062 INIT_LIST_HEAD(&dd
->list
);
1063 idr_preload(GFP_KERNEL
);
1064 spin_lock_irqsave(&hfi1_devs_lock
, flags
);
1066 ret
= idr_alloc(&hfi1_unit_table
, dd
, 0, 0, GFP_NOWAIT
);
1069 list_add(&dd
->list
, &hfi1_dev_list
);
1072 spin_unlock_irqrestore(&hfi1_devs_lock
, flags
);
1076 hfi1_early_err(&pdev
->dev
,
1077 "Could not allocate unit ID: error %d\n", -ret
);
1081 * Initialize all locks for the device. This needs to be as early as
1082 * possible so locks are usable.
1084 spin_lock_init(&dd
->sc_lock
);
1085 spin_lock_init(&dd
->sendctrl_lock
);
1086 spin_lock_init(&dd
->rcvctrl_lock
);
1087 spin_lock_init(&dd
->uctxt_lock
);
1088 spin_lock_init(&dd
->hfi1_diag_trans_lock
);
1089 spin_lock_init(&dd
->sc_init_lock
);
1090 spin_lock_init(&dd
->dc8051_memlock
);
1091 seqlock_init(&dd
->sc2vl_lock
);
1092 spin_lock_init(&dd
->sde_map_lock
);
1093 spin_lock_init(&dd
->pio_map_lock
);
1094 mutex_init(&dd
->dc8051_lock
);
1095 init_waitqueue_head(&dd
->event_queue
);
1097 dd
->int_counter
= alloc_percpu(u64
);
1098 if (!dd
->int_counter
) {
1100 hfi1_early_err(&pdev
->dev
,
1101 "Could not allocate per-cpu int_counter\n");
1105 dd
->rcv_limit
= alloc_percpu(u64
);
1106 if (!dd
->rcv_limit
) {
1108 hfi1_early_err(&pdev
->dev
,
1109 "Could not allocate per-cpu rcv_limit\n");
1113 dd
->send_schedule
= alloc_percpu(u64
);
1114 if (!dd
->send_schedule
) {
1116 hfi1_early_err(&pdev
->dev
,
1117 "Could not allocate per-cpu int_counter\n");
1121 if (!hfi1_cpulist_count
) {
1122 u32 count
= num_online_cpus();
1124 hfi1_cpulist
= kcalloc(BITS_TO_LONGS(count
), sizeof(long),
1127 hfi1_cpulist_count
= count
;
1131 "Could not alloc cpulist info, cpu affinity might be wrong\n");
1133 kobject_init(&dd
->kobj
, &hfi1_devdata_type
);
1137 if (!list_empty(&dd
->list
))
1138 list_del_init(&dd
->list
);
1139 rvt_dealloc_device(&dd
->verbs_dev
.rdi
);
1140 return ERR_PTR(ret
);
1144 * Called from freeze mode handlers, and from PCI error
1145 * reporting code. Should be paranoid about state of
1146 * system and data structures.
1148 void hfi1_disable_after_error(struct hfi1_devdata
*dd
)
1150 if (dd
->flags
& HFI1_INITTED
) {
1153 dd
->flags
&= ~HFI1_INITTED
;
1155 for (pidx
= 0; pidx
< dd
->num_pports
; ++pidx
) {
1156 struct hfi1_pportdata
*ppd
;
1158 ppd
= dd
->pport
+ pidx
;
1159 if (dd
->flags
& HFI1_PRESENT
)
1160 set_link_state(ppd
, HLS_DN_DISABLE
);
1163 *ppd
->statusp
&= ~HFI1_STATUS_IB_READY
;
1168 * Mark as having had an error for driver, and also
1169 * for /sys and status word mapped to user programs.
1170 * This marks unit as not usable, until reset.
1173 dd
->status
->dev
|= HFI1_STATUS_HWERROR
;
1176 static void remove_one(struct pci_dev
*);
1177 static int init_one(struct pci_dev
*, const struct pci_device_id
*);
1179 #define DRIVER_LOAD_MSG "Intel " DRIVER_NAME " loaded: "
1180 #define PFX DRIVER_NAME ": "
1182 const struct pci_device_id hfi1_pci_tbl
[] = {
1183 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL0
) },
1184 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL1
) },
1188 MODULE_DEVICE_TABLE(pci
, hfi1_pci_tbl
);
1190 static struct pci_driver hfi1_pci_driver
= {
1191 .name
= DRIVER_NAME
,
1193 .remove
= remove_one
,
1194 .id_table
= hfi1_pci_tbl
,
1195 .err_handler
= &hfi1_pci_err_handler
,
1198 static void __init
compute_krcvqs(void)
1202 for (i
= 0; i
< krcvqsset
; i
++)
1203 n_krcvqs
+= krcvqs
[i
];
1207 * Do all the generic driver unit- and chip-independent memory
1208 * allocation and initialization.
1210 static int __init
hfi1_mod_init(void)
1218 ret
= node_affinity_init();
1222 /* validate max MTU before any devices start */
1223 if (!valid_opa_max_mtu(hfi1_max_mtu
)) {
1224 pr_err("Invalid max_mtu 0x%x, using 0x%x instead\n",
1225 hfi1_max_mtu
, HFI1_DEFAULT_MAX_MTU
);
1226 hfi1_max_mtu
= HFI1_DEFAULT_MAX_MTU
;
1228 /* valid CUs run from 1-128 in powers of 2 */
1229 if (hfi1_cu
> 128 || !is_power_of_2(hfi1_cu
))
1231 /* valid credit return threshold is 0-100, variable is unsigned */
1232 if (user_credit_return_threshold
> 100)
1233 user_credit_return_threshold
= 100;
1237 * sanitize receive interrupt count, time must wait until after
1238 * the hardware type is known
1240 if (rcv_intr_count
> RCV_HDR_HEAD_COUNTER_MASK
)
1241 rcv_intr_count
= RCV_HDR_HEAD_COUNTER_MASK
;
1242 /* reject invalid combinations */
1243 if (rcv_intr_count
== 0 && rcv_intr_timeout
== 0) {
1244 pr_err("Invalid mode: both receive interrupt count and available timeout are zero - setting interrupt count to 1\n");
1247 if (rcv_intr_count
> 1 && rcv_intr_timeout
== 0) {
1249 * Avoid indefinite packet delivery by requiring a timeout
1252 pr_err("Invalid mode: receive interrupt count greater than 1 and available timeout is zero - setting available timeout to 1\n");
1253 rcv_intr_timeout
= 1;
1255 if (rcv_intr_dynamic
&& !(rcv_intr_count
> 1 && rcv_intr_timeout
> 0)) {
1257 * The dynamic algorithm expects a non-zero timeout
1260 pr_err("Invalid mode: dynamic receive interrupt mitigation with invalid count and timeout - turning dynamic off\n");
1261 rcv_intr_dynamic
= 0;
1264 /* sanitize link CRC options */
1265 link_crc_mask
&= SUPPORTED_CRCS
;
1268 * These must be called before the driver is registered with
1269 * the PCI subsystem.
1271 idr_init(&hfi1_unit_table
);
1274 ret
= hfi1_wss_init();
1277 ret
= pci_register_driver(&hfi1_pci_driver
);
1279 pr_err("Unable to register driver: error %d\n", -ret
);
1282 goto bail
; /* all OK */
1288 idr_destroy(&hfi1_unit_table
);
1294 module_init(hfi1_mod_init
);
1297 * Do the non-unit driver cleanup, memory free, etc. at unload.
1299 static void __exit
hfi1_mod_cleanup(void)
1301 pci_unregister_driver(&hfi1_pci_driver
);
1302 node_affinity_destroy();
1305 hfi1_cpulist_count
= 0;
1306 kfree(hfi1_cpulist
);
1308 idr_destroy(&hfi1_unit_table
);
1309 dispose_firmware(); /* asymmetric with obtain_firmware() */
1313 module_exit(hfi1_mod_cleanup
);
1315 /* this can only be called after a successful initialization */
1316 static void cleanup_device_data(struct hfi1_devdata
*dd
)
1320 struct hfi1_ctxtdata
**tmp
;
1321 unsigned long flags
;
1323 /* users can't do anything more with chip */
1324 for (pidx
= 0; pidx
< dd
->num_pports
; ++pidx
) {
1325 struct hfi1_pportdata
*ppd
= &dd
->pport
[pidx
];
1326 struct cc_state
*cc_state
;
1330 *ppd
->statusp
&= ~HFI1_STATUS_CHIP_PRESENT
;
1332 for (i
= 0; i
< OPA_MAX_SLS
; i
++)
1333 hrtimer_cancel(&ppd
->cca_timer
[i
].hrtimer
);
1335 spin_lock(&ppd
->cc_state_lock
);
1336 cc_state
= get_cc_state_protected(ppd
);
1337 RCU_INIT_POINTER(ppd
->cc_state
, NULL
);
1338 spin_unlock(&ppd
->cc_state_lock
);
1341 kfree_rcu(cc_state
, rcu
);
1344 free_credit_return(dd
);
1347 * Free any resources still in use (usually just kernel contexts)
1348 * at unload; we do for ctxtcnt, because that's what we allocate.
1349 * We acquire lock to be really paranoid that rcd isn't being
1350 * accessed from some interrupt-related code (that should not happen,
1351 * but best to be sure).
1353 spin_lock_irqsave(&dd
->uctxt_lock
, flags
);
1356 spin_unlock_irqrestore(&dd
->uctxt_lock
, flags
);
1358 if (dd
->rcvhdrtail_dummy_kvaddr
) {
1359 dma_free_coherent(&dd
->pcidev
->dev
, sizeof(u64
),
1360 (void *)dd
->rcvhdrtail_dummy_kvaddr
,
1361 dd
->rcvhdrtail_dummy_dma
);
1362 dd
->rcvhdrtail_dummy_kvaddr
= NULL
;
1365 for (ctxt
= 0; tmp
&& ctxt
< dd
->num_rcv_contexts
; ctxt
++) {
1366 struct hfi1_ctxtdata
*rcd
= tmp
[ctxt
];
1368 tmp
[ctxt
] = NULL
; /* debugging paranoia */
1370 hfi1_clear_tids(rcd
);
1371 hfi1_free_ctxtdata(dd
, rcd
);
1376 /* must follow rcv context free - need to remove rcv's hooks */
1377 for (ctxt
= 0; ctxt
< dd
->num_send_contexts
; ctxt
++)
1378 sc_free(dd
->send_contexts
[ctxt
].sc
);
1379 dd
->num_send_contexts
= 0;
1380 kfree(dd
->send_contexts
);
1381 dd
->send_contexts
= NULL
;
1382 kfree(dd
->hw_to_sw
);
1383 dd
->hw_to_sw
= NULL
;
1384 kfree(dd
->boardname
);
1390 * Clean up on unit shutdown, or error during unit load after
1391 * successful initialization.
1393 static void postinit_cleanup(struct hfi1_devdata
*dd
)
1395 hfi1_start_cleanup(dd
);
1397 hfi1_pcie_ddcleanup(dd
);
1398 hfi1_pcie_cleanup(dd
->pcidev
);
1400 cleanup_device_data(dd
);
1402 hfi1_free_devdata(dd
);
1405 static int init_validate_rcvhdrcnt(struct device
*dev
, uint thecnt
)
1407 if (thecnt
<= HFI1_MIN_HDRQ_EGRBUF_CNT
) {
1408 hfi1_early_err(dev
, "Receive header queue count too small\n");
1412 if (thecnt
> HFI1_MAX_HDRQ_EGRBUF_CNT
) {
1414 "Receive header queue count cannot be greater than %u\n",
1415 HFI1_MAX_HDRQ_EGRBUF_CNT
);
1419 if (thecnt
% HDRQ_INCREMENT
) {
1420 hfi1_early_err(dev
, "Receive header queue count %d must be divisible by %lu\n",
1421 thecnt
, HDRQ_INCREMENT
);
1428 static int init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1430 int ret
= 0, j
, pidx
, initfail
;
1431 struct hfi1_devdata
*dd
;
1432 struct hfi1_pportdata
*ppd
;
1434 /* First, lock the non-writable module parameters */
1437 /* Validate dev ids */
1438 if (!(ent
->device
== PCI_DEVICE_ID_INTEL0
||
1439 ent
->device
== PCI_DEVICE_ID_INTEL1
)) {
1440 hfi1_early_err(&pdev
->dev
,
1441 "Failing on unknown Intel deviceid 0x%x\n",
1447 /* Validate some global module parameters */
1448 ret
= init_validate_rcvhdrcnt(&pdev
->dev
, rcvhdrcnt
);
1452 /* use the encoding function as a sanitization check */
1453 if (!encode_rcv_header_entry_size(hfi1_hdrq_entsize
)) {
1454 hfi1_early_err(&pdev
->dev
, "Invalid HdrQ Entry size %u\n",
1460 /* The receive eager buffer size must be set before the receive
1461 * contexts are created.
1463 * Set the eager buffer size. Validate that it falls in a range
1464 * allowed by the hardware - all powers of 2 between the min and
1465 * max. The maximum valid MTU is within the eager buffer range
1466 * so we do not need to cap the max_mtu by an eager buffer size
1469 if (eager_buffer_size
) {
1470 if (!is_power_of_2(eager_buffer_size
))
1472 roundup_pow_of_two(eager_buffer_size
);
1474 clamp_val(eager_buffer_size
,
1475 MIN_EAGER_BUFFER
* 8,
1476 MAX_EAGER_BUFFER_TOTAL
);
1477 hfi1_early_info(&pdev
->dev
, "Eager buffer size %u\n",
1480 hfi1_early_err(&pdev
->dev
, "Invalid Eager buffer size of 0\n");
1485 /* restrict value of hfi1_rcvarr_split */
1486 hfi1_rcvarr_split
= clamp_val(hfi1_rcvarr_split
, 0, 100);
1488 ret
= hfi1_pcie_init(pdev
, ent
);
1493 * Do device-specific initialization, function table setup, dd
1496 dd
= hfi1_init_dd(pdev
, ent
);
1500 goto clean_bail
; /* error already printed */
1503 ret
= create_workqueues(dd
);
1507 /* do the generic initialization */
1508 initfail
= hfi1_init(dd
, 0);
1511 hfi1_vnic_setup(dd
);
1513 ret
= hfi1_register_ib_device(dd
);
1516 * Now ready for use. this should be cleared whenever we
1517 * detect a reset, or initiate one. If earlier failure,
1518 * we still create devices, so diags, etc. can be used
1519 * to determine cause of problem.
1521 if (!initfail
&& !ret
) {
1522 dd
->flags
|= HFI1_INITTED
;
1523 /* create debufs files after init and ib register */
1524 hfi1_dbg_ibdev_init(&dd
->verbs_dev
);
1527 j
= hfi1_device_create(dd
);
1529 dd_dev_err(dd
, "Failed to create /dev devices: %d\n", -j
);
1531 if (initfail
|| ret
) {
1533 flush_workqueue(ib_wq
);
1534 for (pidx
= 0; pidx
< dd
->num_pports
; ++pidx
) {
1535 hfi1_quiet_serdes(dd
->pport
+ pidx
);
1536 ppd
= dd
->pport
+ pidx
;
1538 destroy_workqueue(ppd
->hfi1_wq
);
1539 ppd
->hfi1_wq
= NULL
;
1543 hfi1_device_remove(dd
);
1545 hfi1_unregister_ib_device(dd
);
1546 hfi1_vnic_cleanup(dd
);
1547 postinit_cleanup(dd
);
1550 goto bail
; /* everything already cleaned */
1558 hfi1_pcie_cleanup(pdev
);
1563 static void wait_for_clients(struct hfi1_devdata
*dd
)
1566 * Remove the device init value and complete the device if there is
1567 * no clients or wait for active clients to finish.
1569 if (atomic_dec_and_test(&dd
->user_refcount
))
1570 complete(&dd
->user_comp
);
1572 wait_for_completion(&dd
->user_comp
);
1575 static void remove_one(struct pci_dev
*pdev
)
1577 struct hfi1_devdata
*dd
= pci_get_drvdata(pdev
);
1579 /* close debugfs files before ib unregister */
1580 hfi1_dbg_ibdev_exit(&dd
->verbs_dev
);
1582 /* remove the /dev hfi1 interface */
1583 hfi1_device_remove(dd
);
1585 /* wait for existing user space clients to finish */
1586 wait_for_clients(dd
);
1588 /* unregister from IB core */
1589 hfi1_unregister_ib_device(dd
);
1592 hfi1_vnic_cleanup(dd
);
1595 * Disable the IB link, disable interrupts on the device,
1596 * clear dma engines, etc.
1598 shutdown_device(dd
);
1602 /* wait until all of our (qsfp) queue_work() calls complete */
1603 flush_workqueue(ib_wq
);
1605 postinit_cleanup(dd
);
1609 * hfi1_create_rcvhdrq - create a receive header queue
1610 * @dd: the hfi1_ib device
1611 * @rcd: the context data
1613 * This must be contiguous memory (from an i/o perspective), and must be
1614 * DMA'able (which means for some systems, it will go through an IOMMU,
1615 * or be forced into a low address range).
1617 int hfi1_create_rcvhdrq(struct hfi1_devdata
*dd
, struct hfi1_ctxtdata
*rcd
)
1622 if (!rcd
->rcvhdrq
) {
1623 dma_addr_t dma_hdrqtail
;
1627 * rcvhdrqentsize is in DWs, so we have to convert to bytes
1630 amt
= PAGE_ALIGN(rcd
->rcvhdrq_cnt
* rcd
->rcvhdrqentsize
*
1633 if ((rcd
->ctxt
< dd
->first_dyn_alloc_ctxt
) ||
1634 (rcd
->sc
&& (rcd
->sc
->type
== SC_KERNEL
)))
1635 gfp_flags
= GFP_KERNEL
;
1637 gfp_flags
= GFP_USER
;
1638 rcd
->rcvhdrq
= dma_zalloc_coherent(
1639 &dd
->pcidev
->dev
, amt
, &rcd
->rcvhdrq_dma
,
1640 gfp_flags
| __GFP_COMP
);
1642 if (!rcd
->rcvhdrq
) {
1644 "attempt to allocate %d bytes for ctxt %u rcvhdrq failed\n",
1649 if (HFI1_CAP_KGET_MASK(rcd
->flags
, DMA_RTAIL
)) {
1650 rcd
->rcvhdrtail_kvaddr
= dma_zalloc_coherent(
1651 &dd
->pcidev
->dev
, PAGE_SIZE
, &dma_hdrqtail
,
1653 if (!rcd
->rcvhdrtail_kvaddr
)
1655 rcd
->rcvhdrqtailaddr_dma
= dma_hdrqtail
;
1658 rcd
->rcvhdrq_size
= amt
;
1661 * These values are per-context:
1666 reg
= ((u64
)(rcd
->rcvhdrq_cnt
>> HDRQ_SIZE_SHIFT
)
1667 & RCV_HDR_CNT_CNT_MASK
)
1668 << RCV_HDR_CNT_CNT_SHIFT
;
1669 write_kctxt_csr(dd
, rcd
->ctxt
, RCV_HDR_CNT
, reg
);
1670 reg
= (encode_rcv_header_entry_size(rcd
->rcvhdrqentsize
)
1671 & RCV_HDR_ENT_SIZE_ENT_SIZE_MASK
)
1672 << RCV_HDR_ENT_SIZE_ENT_SIZE_SHIFT
;
1673 write_kctxt_csr(dd
, rcd
->ctxt
, RCV_HDR_ENT_SIZE
, reg
);
1674 reg
= (dd
->rcvhdrsize
& RCV_HDR_SIZE_HDR_SIZE_MASK
)
1675 << RCV_HDR_SIZE_HDR_SIZE_SHIFT
;
1676 write_kctxt_csr(dd
, rcd
->ctxt
, RCV_HDR_SIZE
, reg
);
1679 * Program dummy tail address for every receive context
1680 * before enabling any receive context
1682 write_kctxt_csr(dd
, rcd
->ctxt
, RCV_HDR_TAIL_ADDR
,
1683 dd
->rcvhdrtail_dummy_dma
);
1689 "attempt to allocate 1 page for ctxt %u rcvhdrqtailaddr failed\n",
1691 vfree(rcd
->user_event_mask
);
1692 rcd
->user_event_mask
= NULL
;
1693 dma_free_coherent(&dd
->pcidev
->dev
, amt
, rcd
->rcvhdrq
,
1695 rcd
->rcvhdrq
= NULL
;
1701 * allocate eager buffers, both kernel and user contexts.
1702 * @rcd: the context we are setting up.
1704 * Allocate the eager TID buffers and program them into hip.
1705 * They are no longer completely contiguous, we do multiple allocation
1706 * calls. Otherwise we get the OOM code involved, by asking for too
1707 * much per call, with disastrous results on some kernels.
1709 int hfi1_setup_eagerbufs(struct hfi1_ctxtdata
*rcd
)
1711 struct hfi1_devdata
*dd
= rcd
->dd
;
1712 u32 max_entries
, egrtop
, alloced_bytes
= 0, idx
= 0;
1716 u16 round_mtu
= roundup_pow_of_two(hfi1_max_mtu
);
1719 * GFP_USER, but without GFP_FS, so buffer cache can be
1720 * coalesced (we hope); otherwise, even at order 4,
1721 * heavy filesystem activity makes these fail, and we can
1722 * use compound pages.
1724 gfp_flags
= __GFP_RECLAIM
| __GFP_IO
| __GFP_COMP
;
1727 * The minimum size of the eager buffers is a groups of MTU-sized
1729 * The global eager_buffer_size parameter is checked against the
1730 * theoretical lower limit of the value. Here, we check against the
1733 if (rcd
->egrbufs
.size
< (round_mtu
* dd
->rcv_entries
.group_size
))
1734 rcd
->egrbufs
.size
= round_mtu
* dd
->rcv_entries
.group_size
;
1736 * If using one-pkt-per-egr-buffer, lower the eager buffer
1737 * size to the max MTU (page-aligned).
1739 if (!HFI1_CAP_KGET_MASK(rcd
->flags
, MULTI_PKT_EGR
))
1740 rcd
->egrbufs
.rcvtid_size
= round_mtu
;
1743 * Eager buffers sizes of 1MB or less require smaller TID sizes
1744 * to satisfy the "multiple of 8 RcvArray entries" requirement.
1746 if (rcd
->egrbufs
.size
<= (1 << 20))
1747 rcd
->egrbufs
.rcvtid_size
= max((unsigned long)round_mtu
,
1748 rounddown_pow_of_two(rcd
->egrbufs
.size
/ 8));
1750 while (alloced_bytes
< rcd
->egrbufs
.size
&&
1751 rcd
->egrbufs
.alloced
< rcd
->egrbufs
.count
) {
1752 rcd
->egrbufs
.buffers
[idx
].addr
=
1753 dma_zalloc_coherent(&dd
->pcidev
->dev
,
1754 rcd
->egrbufs
.rcvtid_size
,
1755 &rcd
->egrbufs
.buffers
[idx
].dma
,
1757 if (rcd
->egrbufs
.buffers
[idx
].addr
) {
1758 rcd
->egrbufs
.buffers
[idx
].len
=
1759 rcd
->egrbufs
.rcvtid_size
;
1760 rcd
->egrbufs
.rcvtids
[rcd
->egrbufs
.alloced
].addr
=
1761 rcd
->egrbufs
.buffers
[idx
].addr
;
1762 rcd
->egrbufs
.rcvtids
[rcd
->egrbufs
.alloced
].dma
=
1763 rcd
->egrbufs
.buffers
[idx
].dma
;
1764 rcd
->egrbufs
.alloced
++;
1765 alloced_bytes
+= rcd
->egrbufs
.rcvtid_size
;
1772 * Fail the eager buffer allocation if:
1773 * - we are already using the lowest acceptable size
1774 * - we are using one-pkt-per-egr-buffer (this implies
1775 * that we are accepting only one size)
1777 if (rcd
->egrbufs
.rcvtid_size
== round_mtu
||
1778 !HFI1_CAP_KGET_MASK(rcd
->flags
, MULTI_PKT_EGR
)) {
1779 dd_dev_err(dd
, "ctxt%u: Failed to allocate eager buffers\n",
1782 goto bail_rcvegrbuf_phys
;
1785 new_size
= rcd
->egrbufs
.rcvtid_size
/ 2;
1788 * If the first attempt to allocate memory failed, don't
1789 * fail everything but continue with the next lower
1793 rcd
->egrbufs
.rcvtid_size
= new_size
;
1798 * Re-partition already allocated buffers to a smaller
1801 rcd
->egrbufs
.alloced
= 0;
1802 for (i
= 0, j
= 0, offset
= 0; j
< idx
; i
++) {
1803 if (i
>= rcd
->egrbufs
.count
)
1805 rcd
->egrbufs
.rcvtids
[i
].dma
=
1806 rcd
->egrbufs
.buffers
[j
].dma
+ offset
;
1807 rcd
->egrbufs
.rcvtids
[i
].addr
=
1808 rcd
->egrbufs
.buffers
[j
].addr
+ offset
;
1809 rcd
->egrbufs
.alloced
++;
1810 if ((rcd
->egrbufs
.buffers
[j
].dma
+ offset
+
1812 (rcd
->egrbufs
.buffers
[j
].dma
+
1813 rcd
->egrbufs
.buffers
[j
].len
)) {
1820 rcd
->egrbufs
.rcvtid_size
= new_size
;
1823 rcd
->egrbufs
.numbufs
= idx
;
1824 rcd
->egrbufs
.size
= alloced_bytes
;
1827 "ctxt%u: Alloced %u rcv tid entries @ %uKB, total %zuKB\n",
1828 rcd
->ctxt
, rcd
->egrbufs
.alloced
,
1829 rcd
->egrbufs
.rcvtid_size
/ 1024, rcd
->egrbufs
.size
/ 1024);
1832 * Set the contexts rcv array head update threshold to the closest
1833 * power of 2 (so we can use a mask instead of modulo) below half
1834 * the allocated entries.
1836 rcd
->egrbufs
.threshold
=
1837 rounddown_pow_of_two(rcd
->egrbufs
.alloced
/ 2);
1839 * Compute the expected RcvArray entry base. This is done after
1840 * allocating the eager buffers in order to maximize the
1841 * expected RcvArray entries for the context.
1843 max_entries
= rcd
->rcv_array_groups
* dd
->rcv_entries
.group_size
;
1844 egrtop
= roundup(rcd
->egrbufs
.alloced
, dd
->rcv_entries
.group_size
);
1845 rcd
->expected_count
= max_entries
- egrtop
;
1846 if (rcd
->expected_count
> MAX_TID_PAIR_ENTRIES
* 2)
1847 rcd
->expected_count
= MAX_TID_PAIR_ENTRIES
* 2;
1849 rcd
->expected_base
= rcd
->eager_base
+ egrtop
;
1850 hfi1_cdbg(PROC
, "ctxt%u: eager:%u, exp:%u, egrbase:%u, expbase:%u\n",
1851 rcd
->ctxt
, rcd
->egrbufs
.alloced
, rcd
->expected_count
,
1852 rcd
->eager_base
, rcd
->expected_base
);
1854 if (!hfi1_rcvbuf_validate(rcd
->egrbufs
.rcvtid_size
, PT_EAGER
, &order
)) {
1856 "ctxt%u: current Eager buffer size is invalid %u\n",
1857 rcd
->ctxt
, rcd
->egrbufs
.rcvtid_size
);
1862 for (idx
= 0; idx
< rcd
->egrbufs
.alloced
; idx
++) {
1863 hfi1_put_tid(dd
, rcd
->eager_base
+ idx
, PT_EAGER
,
1864 rcd
->egrbufs
.rcvtids
[idx
].dma
, order
);
1869 bail_rcvegrbuf_phys
:
1870 for (idx
= 0; idx
< rcd
->egrbufs
.alloced
&&
1871 rcd
->egrbufs
.buffers
[idx
].addr
;
1873 dma_free_coherent(&dd
->pcidev
->dev
,
1874 rcd
->egrbufs
.buffers
[idx
].len
,
1875 rcd
->egrbufs
.buffers
[idx
].addr
,
1876 rcd
->egrbufs
.buffers
[idx
].dma
);
1877 rcd
->egrbufs
.buffers
[idx
].addr
= NULL
;
1878 rcd
->egrbufs
.buffers
[idx
].dma
= 0;
1879 rcd
->egrbufs
.buffers
[idx
].len
= 0;