2 * Copyright(c) 2015, 2016 Intel Corporation.
4 * This file is provided under a dual BSD/GPLv2 license. When using or
5 * redistributing this file, you may do so under either license.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions
24 * - Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
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30 * - Neither the name of Intel Corporation nor the names of its
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32 * from this software without specific prior written permission.
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
48 #include <linux/pci.h>
50 #include <linux/delay.h>
51 #include <linux/vmalloc.h>
52 #include <linux/aer.h>
53 #include <linux/module.h>
56 #include "chip_registers.h"
59 /* link speed vector for Gen3 speed - not in Linux headers */
60 #define GEN1_SPEED_VECTOR 0x1
61 #define GEN2_SPEED_VECTOR 0x2
62 #define GEN3_SPEED_VECTOR 0x3
65 * This file contains PCIe utility routines.
69 * Code to adjust PCIe capabilities.
71 static void tune_pcie_caps(struct hfi1_devdata
*);
74 * Do all the common PCIe setup and initialization.
75 * devdata is not yet allocated, and is not allocated until after this
76 * routine returns success. Therefore dd_dev_err() can't be used for error
79 int hfi1_pcie_init(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
83 ret
= pci_enable_device(pdev
);
86 * This can happen (in theory) iff:
87 * We did a chip reset, and then failed to reprogram the
88 * BAR, or the chip reset due to an internal error. We then
89 * unloaded the driver and reloaded it.
91 * Both reset cases set the BAR back to initial state. For
92 * the latter case, the AER sticky error bit at offset 0x718
93 * should be set, but the Linux kernel doesn't yet know
94 * about that, it appears. If the original BAR was retained
95 * in the kernel data structures, this may be OK.
97 hfi1_early_err(&pdev
->dev
, "pci enable failed: error %d\n",
102 ret
= pci_request_regions(pdev
, DRIVER_NAME
);
104 hfi1_early_err(&pdev
->dev
,
105 "pci_request_regions fails: err %d\n", -ret
);
109 ret
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(64));
112 * If the 64 bit setup fails, try 32 bit. Some systems
113 * do not setup 64 bit maps on systems with 2GB or less
116 ret
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
118 hfi1_early_err(&pdev
->dev
,
119 "Unable to set DMA mask: %d\n", ret
);
122 ret
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32));
124 ret
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64));
127 hfi1_early_err(&pdev
->dev
,
128 "Unable to set DMA consistent mask: %d\n", ret
);
132 pci_set_master(pdev
);
133 (void)pci_enable_pcie_error_reporting(pdev
);
137 hfi1_pcie_cleanup(pdev
);
143 * Clean what was done in hfi1_pcie_init()
145 void hfi1_pcie_cleanup(struct pci_dev
*pdev
)
147 pci_disable_device(pdev
);
149 * Release regions should be called after the disable. OK to
150 * call if request regions has not been called or failed.
152 pci_release_regions(pdev
);
156 * Do remaining PCIe setup, once dd is allocated, and save away
157 * fields required to re-initialize after a chip reset, or for
158 * various other purposes
160 int hfi1_pcie_ddinit(struct hfi1_devdata
*dd
, struct pci_dev
*pdev
,
161 const struct pci_device_id
*ent
)
164 resource_size_t addr
;
167 pci_set_drvdata(pdev
, dd
);
169 addr
= pci_resource_start(pdev
, 0);
170 len
= pci_resource_len(pdev
, 0);
173 * The TXE PIO buffers are at the tail end of the chip space.
174 * Cut them off and map them separately.
177 /* sanity check vs expectations */
178 if (len
!= TXE_PIO_SEND
+ TXE_PIO_SIZE
) {
179 dd_dev_err(dd
, "chip PIO range does not match\n");
183 dd
->kregbase
= ioremap_nocache(addr
, TXE_PIO_SEND
);
187 dd
->piobase
= ioremap_wc(addr
+ TXE_PIO_SEND
, TXE_PIO_SIZE
);
189 iounmap(dd
->kregbase
);
193 dd
->flags
|= HFI1_PRESENT
; /* now register routines work */
195 dd
->kregend
= dd
->kregbase
+ TXE_PIO_SEND
;
196 dd
->physaddr
= addr
; /* used for io_remap, etc. */
199 * Re-map the chip's RcvArray as write-combining to allow us
200 * to write an entire cacheline worth of entries in one shot.
201 * If this re-map fails, just continue - the RcvArray programming
202 * function will handle both cases.
204 dd
->chip_rcv_array_count
= read_csr(dd
, RCV_ARRAY_CNT
);
205 dd
->rcvarray_wc
= ioremap_wc(addr
+ RCV_ARRAY
,
206 dd
->chip_rcv_array_count
* 8);
207 dd_dev_info(dd
, "WC Remapped RcvArray: %p\n", dd
->rcvarray_wc
);
209 * Save BARs and command to rewrite after device reset.
212 dd
->pcibar1
= addr
>> 32;
213 pci_read_config_dword(dd
->pcidev
, PCI_ROM_ADDRESS
, &dd
->pci_rom
);
214 pci_read_config_word(dd
->pcidev
, PCI_COMMAND
, &dd
->pci_command
);
215 pcie_capability_read_word(dd
->pcidev
, PCI_EXP_DEVCTL
, &dd
->pcie_devctl
);
216 pcie_capability_read_word(dd
->pcidev
, PCI_EXP_LNKCTL
, &dd
->pcie_lnkctl
);
217 pcie_capability_read_word(dd
->pcidev
, PCI_EXP_DEVCTL2
,
219 pci_read_config_dword(dd
->pcidev
, PCI_CFG_MSIX0
, &dd
->pci_msix0
);
220 pci_read_config_dword(dd
->pcidev
, PCIE_CFG_SPCIE1
, &dd
->pci_lnkctl3
);
221 pci_read_config_dword(dd
->pcidev
, PCIE_CFG_TPH2
, &dd
->pci_tph2
);
227 * Do PCIe cleanup related to dd, after chip-specific cleanup, etc. Just prior
228 * to releasing the dd memory.
229 * Void because all of the core pcie cleanup functions are void.
231 void hfi1_pcie_ddcleanup(struct hfi1_devdata
*dd
)
233 u64 __iomem
*base
= (void __iomem
*)dd
->kregbase
;
235 dd
->flags
&= ~HFI1_PRESENT
;
239 iounmap(dd
->rcvarray_wc
);
241 iounmap(dd
->piobase
);
245 * Do a Function Level Reset (FLR) on the device.
246 * Based on static function drivers/pci/pci.c:pcie_flr().
248 void hfi1_pcie_flr(struct hfi1_devdata
*dd
)
253 /* no need to check for the capability - we know the device has it */
255 /* wait for Transaction Pending bit to clear, at most a few ms */
256 for (i
= 0; i
< 4; i
++) {
258 msleep((1 << (i
- 1)) * 100);
260 pcie_capability_read_word(dd
->pcidev
, PCI_EXP_DEVSTA
, &status
);
261 if (!(status
& PCI_EXP_DEVSTA_TRPND
))
265 dd_dev_err(dd
, "Transaction Pending bit is not clearing, proceeding with reset anyway\n");
268 pcie_capability_set_word(dd
->pcidev
, PCI_EXP_DEVCTL
,
269 PCI_EXP_DEVCTL_BCR_FLR
);
270 /* PCIe spec requires the function to be back within 100ms */
274 static void msix_setup(struct hfi1_devdata
*dd
, int pos
, u32
*msixcnt
,
275 struct hfi1_msix_entry
*hfi1_msix_entry
)
279 struct msix_entry
*msix_entry
;
283 * We can't pass hfi1_msix_entry array to msix_setup
284 * so use a dummy msix_entry array and copy the allocated
285 * irq back to the hfi1_msix_entry array.
287 msix_entry
= kmalloc_array(nvec
, sizeof(*msix_entry
), GFP_KERNEL
);
293 for (i
= 0; i
< nvec
; i
++)
294 msix_entry
[i
] = hfi1_msix_entry
[i
].msix
;
296 ret
= pci_enable_msix_range(dd
->pcidev
, msix_entry
, 1, nvec
);
298 goto free_msix_entry
;
301 for (i
= 0; i
< nvec
; i
++)
302 hfi1_msix_entry
[i
].msix
= msix_entry
[i
];
312 dd_dev_err(dd
, "pci_enable_msix_range %d vectors failed: %d, falling back to INTx\n",
315 hfi1_enable_intx(dd
->pcidev
);
318 /* return the PCIe link speed from the given link status */
319 static u32
extract_speed(u16 linkstat
)
323 switch (linkstat
& PCI_EXP_LNKSTA_CLS
) {
324 default: /* not defined, assume Gen1 */
325 case PCI_EXP_LNKSTA_CLS_2_5GB
:
326 speed
= 2500; /* Gen 1, 2.5GHz */
328 case PCI_EXP_LNKSTA_CLS_5_0GB
:
329 speed
= 5000; /* Gen 2, 5GHz */
331 case GEN3_SPEED_VECTOR
:
332 speed
= 8000; /* Gen 3, 8GHz */
338 /* return the PCIe link speed from the given link status */
339 static u32
extract_width(u16 linkstat
)
341 return (linkstat
& PCI_EXP_LNKSTA_NLW
) >> PCI_EXP_LNKSTA_NLW_SHIFT
;
344 /* read the link status and set dd->{lbus_width,lbus_speed,lbus_info} */
345 static void update_lbus_info(struct hfi1_devdata
*dd
)
349 pcie_capability_read_word(dd
->pcidev
, PCI_EXP_LNKSTA
, &linkstat
);
350 dd
->lbus_width
= extract_width(linkstat
);
351 dd
->lbus_speed
= extract_speed(linkstat
);
352 snprintf(dd
->lbus_info
, sizeof(dd
->lbus_info
),
353 "PCIe,%uMHz,x%u", dd
->lbus_speed
, dd
->lbus_width
);
357 * Read in the current PCIe link width and speed. Find if the link is
360 int pcie_speeds(struct hfi1_devdata
*dd
)
363 struct pci_dev
*parent
= dd
->pcidev
->bus
->self
;
365 if (!pci_is_pcie(dd
->pcidev
)) {
366 dd_dev_err(dd
, "Can't find PCI Express capability!\n");
370 /* find if our max speed is Gen3 and parent supports Gen3 speeds */
371 dd
->link_gen3_capable
= 1;
373 pcie_capability_read_dword(dd
->pcidev
, PCI_EXP_LNKCAP
, &linkcap
);
374 if ((linkcap
& PCI_EXP_LNKCAP_SLS
) != GEN3_SPEED_VECTOR
) {
376 "This HFI is not Gen3 capable, max speed 0x%x, need 0x3\n",
377 linkcap
& PCI_EXP_LNKCAP_SLS
);
378 dd
->link_gen3_capable
= 0;
382 * bus->max_bus_speed is set from the bridge's linkcap Max Link Speed
384 if (parent
&& dd
->pcidev
->bus
->max_bus_speed
!= PCIE_SPEED_8_0GT
) {
385 dd_dev_info(dd
, "Parent PCIe bridge does not support Gen3\n");
386 dd
->link_gen3_capable
= 0;
389 /* obtain the link width and current speed */
390 update_lbus_info(dd
);
392 dd_dev_info(dd
, "%s\n", dd
->lbus_info
);
399 * - actual number of interrupts allocated
400 * - 0 if fell back to INTx.
402 void request_msix(struct hfi1_devdata
*dd
, u32
*nent
,
403 struct hfi1_msix_entry
*entry
)
407 pos
= dd
->pcidev
->msix_cap
;
409 msix_setup(dd
, pos
, nent
, entry
);
410 /* did it, either MSI-X or INTx */
413 hfi1_enable_intx(dd
->pcidev
);
419 void hfi1_enable_intx(struct pci_dev
*pdev
)
421 /* first, turn on INTx */
423 /* then turn off MSI-X */
424 pci_disable_msix(pdev
);
427 /* restore command and BARs after a reset has wiped them out */
428 void restore_pci_variables(struct hfi1_devdata
*dd
)
430 pci_write_config_word(dd
->pcidev
, PCI_COMMAND
, dd
->pci_command
);
431 pci_write_config_dword(dd
->pcidev
, PCI_BASE_ADDRESS_0
, dd
->pcibar0
);
432 pci_write_config_dword(dd
->pcidev
, PCI_BASE_ADDRESS_1
, dd
->pcibar1
);
433 pci_write_config_dword(dd
->pcidev
, PCI_ROM_ADDRESS
, dd
->pci_rom
);
434 pcie_capability_write_word(dd
->pcidev
, PCI_EXP_DEVCTL
, dd
->pcie_devctl
);
435 pcie_capability_write_word(dd
->pcidev
, PCI_EXP_LNKCTL
, dd
->pcie_lnkctl
);
436 pcie_capability_write_word(dd
->pcidev
, PCI_EXP_DEVCTL2
,
438 pci_write_config_dword(dd
->pcidev
, PCI_CFG_MSIX0
, dd
->pci_msix0
);
439 pci_write_config_dword(dd
->pcidev
, PCIE_CFG_SPCIE1
, dd
->pci_lnkctl3
);
440 pci_write_config_dword(dd
->pcidev
, PCIE_CFG_TPH2
, dd
->pci_tph2
);
444 * BIOS may not set PCIe bus-utilization parameters for best performance.
445 * Check and optionally adjust them to maximize our throughput.
447 static int hfi1_pcie_caps
;
448 module_param_named(pcie_caps
, hfi1_pcie_caps
, int, S_IRUGO
);
449 MODULE_PARM_DESC(pcie_caps
, "Max PCIe tuning: Payload (0..3), ReadReq (4..7)");
451 uint aspm_mode
= ASPM_MODE_DISABLED
;
452 module_param_named(aspm
, aspm_mode
, uint
, S_IRUGO
);
453 MODULE_PARM_DESC(aspm
, "PCIe ASPM: 0: disable, 1: enable, 2: dynamic");
455 static void tune_pcie_caps(struct hfi1_devdata
*dd
)
457 struct pci_dev
*parent
;
458 u16 rc_mpss
, rc_mps
, ep_mpss
, ep_mps
;
459 u16 rc_mrrs
, ep_mrrs
, max_mrrs
, ectl
;
462 * Turn on extended tags in DevCtl in case the BIOS has turned it off
463 * to improve WFR SDMA bandwidth
465 pcie_capability_read_word(dd
->pcidev
, PCI_EXP_DEVCTL
, &ectl
);
466 if (!(ectl
& PCI_EXP_DEVCTL_EXT_TAG
)) {
467 dd_dev_info(dd
, "Enabling PCIe extended tags\n");
468 ectl
|= PCI_EXP_DEVCTL_EXT_TAG
;
469 pcie_capability_write_word(dd
->pcidev
, PCI_EXP_DEVCTL
, ectl
);
471 /* Find out supported and configured values for parent (root) */
472 parent
= dd
->pcidev
->bus
->self
;
474 * The driver cannot perform the tuning if it does not have
475 * access to the upstream component.
479 if (!pci_is_root_bus(parent
->bus
)) {
480 dd_dev_info(dd
, "Parent not root\n");
484 if (!pci_is_pcie(parent
) || !pci_is_pcie(dd
->pcidev
))
486 rc_mpss
= parent
->pcie_mpss
;
487 rc_mps
= ffs(pcie_get_mps(parent
)) - 8;
488 /* Find out supported and configured values for endpoint (us) */
489 ep_mpss
= dd
->pcidev
->pcie_mpss
;
490 ep_mps
= ffs(pcie_get_mps(dd
->pcidev
)) - 8;
492 /* Find max payload supported by root, endpoint */
493 if (rc_mpss
> ep_mpss
)
496 /* If Supported greater than limit in module param, limit it */
497 if (rc_mpss
> (hfi1_pcie_caps
& 7))
498 rc_mpss
= hfi1_pcie_caps
& 7;
499 /* If less than (allowed, supported), bump root payload */
500 if (rc_mpss
> rc_mps
) {
502 pcie_set_mps(parent
, 128 << rc_mps
);
504 /* If less than (allowed, supported), bump endpoint payload */
505 if (rc_mpss
> ep_mps
) {
507 pcie_set_mps(dd
->pcidev
, 128 << ep_mps
);
511 * Now the Read Request size.
512 * No field for max supported, but PCIe spec limits it to 4096,
513 * which is code '5' (log2(4096) - 7)
516 if (max_mrrs
> ((hfi1_pcie_caps
>> 4) & 7))
517 max_mrrs
= (hfi1_pcie_caps
>> 4) & 7;
519 max_mrrs
= 128 << max_mrrs
;
520 rc_mrrs
= pcie_get_readrq(parent
);
521 ep_mrrs
= pcie_get_readrq(dd
->pcidev
);
523 if (max_mrrs
> rc_mrrs
) {
525 pcie_set_readrq(parent
, rc_mrrs
);
527 if (max_mrrs
> ep_mrrs
) {
529 pcie_set_readrq(dd
->pcidev
, ep_mrrs
);
533 /* End of PCIe capability tuning */
536 * From here through hfi1_pci_err_handler definition is invoked via
537 * PCI error infrastructure, registered via pci
539 static pci_ers_result_t
540 pci_error_detected(struct pci_dev
*pdev
, pci_channel_state_t state
)
542 struct hfi1_devdata
*dd
= pci_get_drvdata(pdev
);
543 pci_ers_result_t ret
= PCI_ERS_RESULT_RECOVERED
;
546 case pci_channel_io_normal
:
547 dd_dev_info(dd
, "State Normal, ignoring\n");
550 case pci_channel_io_frozen
:
551 dd_dev_info(dd
, "State Frozen, requesting reset\n");
552 pci_disable_device(pdev
);
553 ret
= PCI_ERS_RESULT_NEED_RESET
;
556 case pci_channel_io_perm_failure
:
558 dd_dev_info(dd
, "State Permanent Failure, disabling\n");
559 /* no more register accesses! */
560 dd
->flags
&= ~HFI1_PRESENT
;
561 hfi1_disable_after_error(dd
);
563 /* else early, or other problem */
564 ret
= PCI_ERS_RESULT_DISCONNECT
;
567 default: /* shouldn't happen */
568 dd_dev_info(dd
, "HFI1 PCI errors detected (state %d)\n",
575 static pci_ers_result_t
576 pci_mmio_enabled(struct pci_dev
*pdev
)
579 struct hfi1_devdata
*dd
= pci_get_drvdata(pdev
);
580 pci_ers_result_t ret
= PCI_ERS_RESULT_RECOVERED
;
582 if (dd
&& dd
->pport
) {
583 words
= read_port_cntr(dd
->pport
, C_RX_WORDS
, CNTR_INVALID_VL
);
585 ret
= PCI_ERS_RESULT_NEED_RESET
;
587 "HFI1 mmio_enabled function called, read wordscntr %Lx, returning %d\n",
593 static pci_ers_result_t
594 pci_slot_reset(struct pci_dev
*pdev
)
596 struct hfi1_devdata
*dd
= pci_get_drvdata(pdev
);
598 dd_dev_info(dd
, "HFI1 slot_reset function called, ignored\n");
599 return PCI_ERS_RESULT_CAN_RECOVER
;
602 static pci_ers_result_t
603 pci_link_reset(struct pci_dev
*pdev
)
605 struct hfi1_devdata
*dd
= pci_get_drvdata(pdev
);
607 dd_dev_info(dd
, "HFI1 link_reset function called, ignored\n");
608 return PCI_ERS_RESULT_CAN_RECOVER
;
612 pci_resume(struct pci_dev
*pdev
)
614 struct hfi1_devdata
*dd
= pci_get_drvdata(pdev
);
616 dd_dev_info(dd
, "HFI1 resume function called\n");
617 pci_cleanup_aer_uncorrect_error_status(pdev
);
619 * Running jobs will fail, since it's asynchronous
620 * unlike sysfs-requested reset. Better than
623 hfi1_init(dd
, 1); /* same as re-init after reset */
626 const struct pci_error_handlers hfi1_pci_err_handler
= {
627 .error_detected
= pci_error_detected
,
628 .mmio_enabled
= pci_mmio_enabled
,
629 .link_reset
= pci_link_reset
,
630 .slot_reset
= pci_slot_reset
,
631 .resume
= pci_resume
,
634 /*============================================================================*/
635 /* PCIe Gen3 support */
638 * This code is separated out because it is expected to be removed in the
639 * final shipping product. If not, then it will be revisited and items
640 * will be moved to more standard locations.
643 /* ASIC_PCI_SD_HOST_STATUS.FW_DNLD_STS field values */
644 #define DL_STATUS_HFI0 0x1 /* hfi0 firmware download complete */
645 #define DL_STATUS_HFI1 0x2 /* hfi1 firmware download complete */
646 #define DL_STATUS_BOTH 0x3 /* hfi0 and hfi1 firmware download complete */
648 /* ASIC_PCI_SD_HOST_STATUS.FW_DNLD_ERR field values */
649 #define DL_ERR_NONE 0x0 /* no error */
650 #define DL_ERR_SWAP_PARITY 0x1 /* parity error in SerDes interrupt */
651 /* or response data */
652 #define DL_ERR_DISABLED 0x2 /* hfi disabled */
653 #define DL_ERR_SECURITY 0x3 /* security check failed */
654 #define DL_ERR_SBUS 0x4 /* SBus status error */
655 #define DL_ERR_XFR_PARITY 0x5 /* parity error during ROM transfer*/
657 /* gasket block secondary bus reset delay */
658 #define SBR_DELAY_US 200000 /* 200ms */
660 /* mask for PCIe capability register lnkctl2 target link speed */
661 #define LNKCTL2_TARGET_LINK_SPEED_MASK 0xf
663 static uint pcie_target
= 3;
664 module_param(pcie_target
, uint
, S_IRUGO
);
665 MODULE_PARM_DESC(pcie_target
, "PCIe target speed (0 skip, 1-3 Gen1-3)");
667 static uint pcie_force
;
668 module_param(pcie_force
, uint
, S_IRUGO
);
669 MODULE_PARM_DESC(pcie_force
, "Force driver to do a PCIe firmware download even if already at target speed");
671 static uint pcie_retry
= 5;
672 module_param(pcie_retry
, uint
, S_IRUGO
);
673 MODULE_PARM_DESC(pcie_retry
, "Driver will try this many times to reach requested speed");
675 #define UNSET_PSET 255
676 #define DEFAULT_DISCRETE_PSET 2 /* discrete HFI */
677 #define DEFAULT_MCP_PSET 4 /* MCP HFI */
678 static uint pcie_pset
= UNSET_PSET
;
679 module_param(pcie_pset
, uint
, S_IRUGO
);
680 MODULE_PARM_DESC(pcie_pset
, "PCIe Eq Pset value to use, range is 0-10");
682 /* equalization columns */
687 /* discrete silicon preliminary equalization values */
688 static const u8 discrete_preliminary_eq
[11][3] = {
690 { 0x00, 0x00, 0x12 }, /* p0 */
691 { 0x00, 0x00, 0x0c }, /* p1 */
692 { 0x00, 0x00, 0x0f }, /* p2 */
693 { 0x00, 0x00, 0x09 }, /* p3 */
694 { 0x00, 0x00, 0x00 }, /* p4 */
695 { 0x06, 0x00, 0x00 }, /* p5 */
696 { 0x09, 0x00, 0x00 }, /* p6 */
697 { 0x06, 0x00, 0x0f }, /* p7 */
698 { 0x09, 0x00, 0x09 }, /* p8 */
699 { 0x0c, 0x00, 0x00 }, /* p9 */
700 { 0x00, 0x00, 0x18 }, /* p10 */
703 /* integrated silicon preliminary equalization values */
704 static const u8 integrated_preliminary_eq
[11][3] = {
706 { 0x00, 0x1e, 0x07 }, /* p0 */
707 { 0x00, 0x1e, 0x05 }, /* p1 */
708 { 0x00, 0x1e, 0x06 }, /* p2 */
709 { 0x00, 0x1e, 0x04 }, /* p3 */
710 { 0x00, 0x1e, 0x00 }, /* p4 */
711 { 0x03, 0x1e, 0x00 }, /* p5 */
712 { 0x04, 0x1e, 0x00 }, /* p6 */
713 { 0x03, 0x1e, 0x06 }, /* p7 */
714 { 0x03, 0x1e, 0x04 }, /* p8 */
715 { 0x05, 0x1e, 0x00 }, /* p9 */
716 { 0x00, 0x1e, 0x0a }, /* p10 */
719 /* helper to format the value to write to hardware */
720 #define eq_value(pre, curr, post) \
722 PCIE_CFG_REG_PL102_GEN3_EQ_PRE_CURSOR_PSET_SHIFT) \
723 | (((u32)(curr)) << PCIE_CFG_REG_PL102_GEN3_EQ_CURSOR_PSET_SHIFT) \
724 | (((u32)(post)) << \
725 PCIE_CFG_REG_PL102_GEN3_EQ_POST_CURSOR_PSET_SHIFT))
728 * Load the given EQ preset table into the PCIe hardware.
730 static int load_eq_table(struct hfi1_devdata
*dd
, const u8 eq
[11][3], u8 fs
,
733 struct pci_dev
*pdev
= dd
->pcidev
;
737 u8 c_minus1
, c0
, c_plus1
;
739 for (i
= 0; i
< 11; i
++) {
741 pci_write_config_dword(pdev
, PCIE_CFG_REG_PL103
, i
);
742 /* write the value */
743 c_minus1
= eq
[i
][PREC
] / div
;
744 c0
= fs
- (eq
[i
][PREC
] / div
) - (eq
[i
][POST
] / div
);
745 c_plus1
= eq
[i
][POST
] / div
;
746 pci_write_config_dword(pdev
, PCIE_CFG_REG_PL102
,
747 eq_value(c_minus1
, c0
, c_plus1
));
748 /* check if these coefficients violate EQ rules */
749 pci_read_config_dword(dd
->pcidev
, PCIE_CFG_REG_PL105
,
752 & PCIE_CFG_REG_PL105_GEN3_EQ_VIOLATE_COEF_RULES_SMASK
){
753 if (hit_error
== 0) {
755 "Gen3 EQ Table Coefficient rule violations\n");
756 dd_dev_err(dd
, " prec attn post\n");
758 dd_dev_err(dd
, " p%02d: %02x %02x %02x\n",
759 i
, (u32
)eq
[i
][0], (u32
)eq
[i
][1],
761 dd_dev_err(dd
, " %02x %02x %02x\n",
762 (u32
)c_minus1
, (u32
)c0
, (u32
)c_plus1
);
772 * Steps to be done after the PCIe firmware is downloaded and
773 * before the SBR for the Pcie Gen3.
774 * The SBus resource is already being held.
776 static void pcie_post_steps(struct hfi1_devdata
*dd
)
780 set_sbus_fast_mode(dd
);
782 * Write to the PCIe PCSes to set the G3_LOCKED_NEXT bits to 1.
783 * This avoids a spurious framing error that can otherwise be
784 * generated by the MAC layer.
786 * Use individual addresses since no broadcast is set up.
788 for (i
= 0; i
< NUM_PCIE_SERDES
; i
++) {
789 sbus_request(dd
, pcie_pcs_addrs
[dd
->hfi1_id
][i
],
790 0x03, WRITE_SBUS_RECEIVER
, 0x00022132);
793 clear_sbus_fast_mode(dd
);
797 * Trigger a secondary bus reset (SBR) on ourselves using our parent.
799 * Based on pci_parent_bus_reset() which is not exported by the
802 static int trigger_sbr(struct hfi1_devdata
*dd
)
804 struct pci_dev
*dev
= dd
->pcidev
;
805 struct pci_dev
*pdev
;
808 if (!dev
->bus
->self
) {
809 dd_dev_err(dd
, "%s: no parent device\n", __func__
);
813 /* should not be anyone else on the bus */
814 list_for_each_entry(pdev
, &dev
->bus
->devices
, bus_list
)
817 "%s: another device is on the same bus\n",
823 * A secondary bus reset (SBR) issues a hot reset to our device.
824 * The following routine does a 1s wait after the reset is dropped
825 * per PCI Trhfa (recovery time). PCIe 3.0 section 6.6.1 -
826 * Conventional Reset, paragraph 3, line 35 also says that a 1s
827 * delay after a reset is required. Per spec requirements,
828 * the link is either working or not after that point.
830 pci_reset_bridge_secondary_bus(dev
->bus
->self
);
836 * Write the given gasket interrupt register.
838 static void write_gasket_interrupt(struct hfi1_devdata
*dd
, int index
,
841 write_csr(dd
, ASIC_PCIE_SD_INTRPT_LIST
+ (index
* 8),
842 (((u64
)code
<< ASIC_PCIE_SD_INTRPT_LIST_INTRPT_CODE_SHIFT
) |
843 ((u64
)data
<< ASIC_PCIE_SD_INTRPT_LIST_INTRPT_DATA_SHIFT
)));
847 * Tell the gasket logic how to react to the reset.
849 static void arm_gasket_logic(struct hfi1_devdata
*dd
)
853 reg
= (((u64
)1 << dd
->hfi1_id
) <<
854 ASIC_PCIE_SD_HOST_CMD_INTRPT_CMD_SHIFT
) |
855 ((u64
)pcie_serdes_broadcast
[dd
->hfi1_id
] <<
856 ASIC_PCIE_SD_HOST_CMD_SBUS_RCVR_ADDR_SHIFT
|
857 ASIC_PCIE_SD_HOST_CMD_SBR_MODE_SMASK
|
858 ((u64
)SBR_DELAY_US
& ASIC_PCIE_SD_HOST_CMD_TIMER_MASK
) <<
859 ASIC_PCIE_SD_HOST_CMD_TIMER_SHIFT
);
860 write_csr(dd
, ASIC_PCIE_SD_HOST_CMD
, reg
);
861 /* read back to push the write */
862 read_csr(dd
, ASIC_PCIE_SD_HOST_CMD
);
866 * CCE_PCIE_CTRL long name helpers
867 * We redefine these shorter macros to use in the code while leaving
868 * chip_registers.h to be autogenerated from the hardware spec.
870 #define LANE_BUNDLE_MASK CCE_PCIE_CTRL_PCIE_LANE_BUNDLE_MASK
871 #define LANE_BUNDLE_SHIFT CCE_PCIE_CTRL_PCIE_LANE_BUNDLE_SHIFT
872 #define LANE_DELAY_MASK CCE_PCIE_CTRL_PCIE_LANE_DELAY_MASK
873 #define LANE_DELAY_SHIFT CCE_PCIE_CTRL_PCIE_LANE_DELAY_SHIFT
874 #define MARGIN_OVERWRITE_ENABLE_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_OVERWRITE_ENABLE_SHIFT
875 #define MARGIN_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_SHIFT
876 #define MARGIN_G1_G2_OVERWRITE_MASK CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_OVERWRITE_ENABLE_MASK
877 #define MARGIN_G1_G2_OVERWRITE_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_OVERWRITE_ENABLE_SHIFT
878 #define MARGIN_GEN1_GEN2_MASK CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_MASK
879 #define MARGIN_GEN1_GEN2_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_SHIFT
882 * Write xmt_margin for full-swing (WFR-B) or half-swing (WFR-C).
884 static void write_xmt_margin(struct hfi1_devdata
*dd
, const char *fname
)
892 pcie_ctrl
= read_csr(dd
, CCE_PCIE_CTRL
);
895 * For Discrete, use full-swing.
896 * - PCIe TX defaults to full-swing.
897 * Leave this register as default.
898 * For Integrated, use half-swing
899 * - Copy xmt_margin and xmt_margin_oe
900 * from Gen1/Gen2 to Gen3.
902 if (dd
->pcidev
->device
== PCI_DEVICE_ID_INTEL1
) { /* integrated */
903 /* extract initial fields */
904 xmt_margin
= (pcie_ctrl
>> MARGIN_GEN1_GEN2_SHIFT
)
905 & MARGIN_GEN1_GEN2_MASK
;
906 xmt_margin_oe
= (pcie_ctrl
>> MARGIN_G1_G2_OVERWRITE_SHIFT
)
907 & MARGIN_G1_G2_OVERWRITE_MASK
;
908 lane_delay
= (pcie_ctrl
>> LANE_DELAY_SHIFT
) & LANE_DELAY_MASK
;
909 lane_bundle
= (pcie_ctrl
>> LANE_BUNDLE_SHIFT
)
913 * For A0, EFUSE values are not set. Override with the
918 * xmt_margin and OverwiteEnabel should be the
919 * same for Gen1/Gen2 and Gen3
923 lane_delay
= 0xF; /* Delay 240ns. */
924 lane_bundle
= 0x0; /* Set to 1 lane. */
927 /* overwrite existing values */
928 pcie_ctrl
= (xmt_margin
<< MARGIN_GEN1_GEN2_SHIFT
)
929 | (xmt_margin_oe
<< MARGIN_G1_G2_OVERWRITE_SHIFT
)
930 | (xmt_margin
<< MARGIN_SHIFT
)
931 | (xmt_margin_oe
<< MARGIN_OVERWRITE_ENABLE_SHIFT
)
932 | (lane_delay
<< LANE_DELAY_SHIFT
)
933 | (lane_bundle
<< LANE_BUNDLE_SHIFT
);
935 write_csr(dd
, CCE_PCIE_CTRL
, pcie_ctrl
);
938 dd_dev_dbg(dd
, "%s: program XMT margin, CcePcieCtrl 0x%llx\n",
943 * Do all the steps needed to transition the PCIe link to Gen3 speed.
945 int do_pcie_gen3_transition(struct hfi1_devdata
*dd
)
947 struct pci_dev
*parent
= dd
->pcidev
->bus
->self
;
953 int do_retry
, retry_count
= 0;
955 u16 target_vector
, target_speed
;
959 int return_error
= 0;
961 /* PCIe Gen3 is for the ASIC only */
962 if (dd
->icode
!= ICODE_RTL_SILICON
)
965 if (pcie_target
== 1) { /* target Gen1 */
966 target_vector
= GEN1_SPEED_VECTOR
;
968 } else if (pcie_target
== 2) { /* target Gen2 */
969 target_vector
= GEN2_SPEED_VECTOR
;
971 } else if (pcie_target
== 3) { /* target Gen3 */
972 target_vector
= GEN3_SPEED_VECTOR
;
975 /* off or invalid target - skip */
976 dd_dev_info(dd
, "%s: Skipping PCIe transition\n", __func__
);
980 /* if already at target speed, done (unless forced) */
981 if (dd
->lbus_speed
== target_speed
) {
982 dd_dev_info(dd
, "%s: PCIe already at gen%d, %s\n", __func__
,
984 pcie_force
? "re-doing anyway" : "skipping");
990 * The driver cannot do the transition if it has no access to the
994 dd_dev_info(dd
, "%s: No upstream, Can't do gen3 transition\n",
1000 * Do the Gen3 transition. Steps are those of the PCIe Gen3
1004 /* step 1: pcie link working in gen1/gen2 */
1006 /* step 2: if either side is not capable of Gen3, done */
1007 if (pcie_target
== 3 && !dd
->link_gen3_capable
) {
1008 dd_dev_err(dd
, "The PCIe link is not Gen3 capable\n");
1013 /* hold the SBus resource across the firmware download and SBR */
1014 ret
= acquire_chip_resource(dd
, CR_SBUS
, SBUS_TIMEOUT
);
1016 dd_dev_err(dd
, "%s: unable to acquire SBus resource\n",
1021 /* make sure thermal polling is not causing interrupts */
1022 therm
= read_csr(dd
, ASIC_CFG_THERM_POLL_EN
);
1024 write_csr(dd
, ASIC_CFG_THERM_POLL_EN
, 0x0);
1026 dd_dev_info(dd
, "%s: Disabled therm polling\n",
1031 /* the SBus download will reset the spico for thermal */
1033 /* step 3: download SBus Master firmware */
1034 /* step 4: download PCIe Gen3 SerDes firmware */
1035 dd_dev_info(dd
, "%s: downloading firmware\n", __func__
);
1036 ret
= load_pcie_firmware(dd
);
1038 /* do not proceed if the firmware cannot be downloaded */
1043 /* step 5: set up device parameter settings */
1044 dd_dev_info(dd
, "%s: setting PCIe registers\n", __func__
);
1047 * PcieCfgSpcie1 - Link Control 3
1048 * Leave at reset value. No need to set PerfEq - link equalization
1049 * will be performed automatically after the SBR when the target
1053 /* clear all 16 per-lane error bits (PCIe: Lane Error Status) */
1054 pci_write_config_dword(dd
->pcidev
, PCIE_CFG_SPCIE2
, 0xffff);
1056 /* step 5a: Set Synopsys Port Logic registers */
1059 * PcieCfgRegPl2 - Port Force Link
1061 * Set the low power field to 0x10 to avoid unnecessary power
1062 * management messages. All other fields are zero.
1064 reg32
= 0x10ul
<< PCIE_CFG_REG_PL2_LOW_PWR_ENT_CNT_SHIFT
;
1065 pci_write_config_dword(dd
->pcidev
, PCIE_CFG_REG_PL2
, reg32
);
1068 * PcieCfgRegPl100 - Gen3 Control
1070 * turn off PcieCfgRegPl100.Gen3ZRxDcNonCompl
1071 * turn on PcieCfgRegPl100.EqEieosCnt
1072 * Everything else zero.
1074 reg32
= PCIE_CFG_REG_PL100_EQ_EIEOS_CNT_SMASK
;
1075 pci_write_config_dword(dd
->pcidev
, PCIE_CFG_REG_PL100
, reg32
);
1078 * PcieCfgRegPl101 - Gen3 EQ FS and LF
1079 * PcieCfgRegPl102 - Gen3 EQ Presets to Coefficients Mapping
1080 * PcieCfgRegPl103 - Gen3 EQ Preset Index
1081 * PcieCfgRegPl105 - Gen3 EQ Status
1083 * Give initial EQ settings.
1085 if (dd
->pcidev
->device
== PCI_DEVICE_ID_INTEL0
) { /* discrete */
1086 /* 1000mV, FS=24, LF = 8 */
1090 eq
= discrete_preliminary_eq
;
1091 default_pset
= DEFAULT_DISCRETE_PSET
;
1093 /* 400mV, FS=29, LF = 9 */
1097 eq
= integrated_preliminary_eq
;
1098 default_pset
= DEFAULT_MCP_PSET
;
1100 pci_write_config_dword(dd
->pcidev
, PCIE_CFG_REG_PL101
,
1102 PCIE_CFG_REG_PL101_GEN3_EQ_LOCAL_FS_SHIFT
) |
1104 PCIE_CFG_REG_PL101_GEN3_EQ_LOCAL_LF_SHIFT
));
1105 ret
= load_eq_table(dd
, eq
, fs
, div
);
1110 * PcieCfgRegPl106 - Gen3 EQ Control
1112 * Set Gen3EqPsetReqVec, leave other fields 0.
1114 if (pcie_pset
== UNSET_PSET
)
1115 pcie_pset
= default_pset
;
1116 if (pcie_pset
> 10) { /* valid range is 0-10, inclusive */
1117 dd_dev_err(dd
, "%s: Invalid Eq Pset %u, setting to %d\n",
1118 __func__
, pcie_pset
, default_pset
);
1119 pcie_pset
= default_pset
;
1121 dd_dev_info(dd
, "%s: using EQ Pset %u\n", __func__
, pcie_pset
);
1122 pci_write_config_dword(dd
->pcidev
, PCIE_CFG_REG_PL106
,
1123 ((1 << pcie_pset
) <<
1124 PCIE_CFG_REG_PL106_GEN3_EQ_PSET_REQ_VEC_SHIFT
) |
1125 PCIE_CFG_REG_PL106_GEN3_EQ_EVAL2MS_DISABLE_SMASK
|
1126 PCIE_CFG_REG_PL106_GEN3_EQ_PHASE23_EXIT_MODE_SMASK
);
1129 * step 5b: Do post firmware download steps via SBus
1131 dd_dev_info(dd
, "%s: doing pcie post steps\n", __func__
);
1132 pcie_post_steps(dd
);
1135 * step 5c: Program gasket interrupts
1137 /* set the Rx Bit Rate to REFCLK ratio */
1138 write_gasket_interrupt(dd
, 0, 0x0006, 0x0050);
1139 /* disable pCal for PCIe Gen3 RX equalization */
1140 write_gasket_interrupt(dd
, 1, 0x0026, 0x5b01);
1142 * Enable iCal for PCIe Gen3 RX equalization, and set which
1143 * evaluation of RX_EQ_EVAL will launch the iCal procedure.
1145 write_gasket_interrupt(dd
, 2, 0x0026, 0x5202);
1146 /* terminate list */
1147 write_gasket_interrupt(dd
, 3, 0x0000, 0x0000);
1150 * step 5d: program XMT margin
1152 write_xmt_margin(dd
, __func__
);
1155 * step 5e: disable active state power management (ASPM). It
1156 * will be enabled if required later
1158 dd_dev_info(dd
, "%s: clearing ASPM\n", __func__
);
1159 aspm_hw_disable_l1(dd
);
1162 * step 5f: clear DirectSpeedChange
1163 * PcieCfgRegPl67.DirectSpeedChange must be zero to prevent the
1164 * change in the speed target from starting before we are ready.
1165 * This field defaults to 0 and we are not changing it, so nothing
1169 /* step 5g: Set target link speed */
1171 * Set target link speed to be target on both device and parent.
1172 * On setting the parent: Some system BIOSs "helpfully" set the
1173 * parent target speed to Gen2 to match the ASIC's initial speed.
1174 * We can set the target Gen3 because we have already checked
1175 * that it is Gen3 capable earlier.
1177 dd_dev_info(dd
, "%s: setting parent target link speed\n", __func__
);
1178 pcie_capability_read_word(parent
, PCI_EXP_LNKCTL2
, &lnkctl2
);
1179 dd_dev_info(dd
, "%s: ..old link control2: 0x%x\n", __func__
,
1181 /* only write to parent if target is not as high as ours */
1182 if ((lnkctl2
& LNKCTL2_TARGET_LINK_SPEED_MASK
) < target_vector
) {
1183 lnkctl2
&= ~LNKCTL2_TARGET_LINK_SPEED_MASK
;
1184 lnkctl2
|= target_vector
;
1185 dd_dev_info(dd
, "%s: ..new link control2: 0x%x\n", __func__
,
1187 pcie_capability_write_word(parent
, PCI_EXP_LNKCTL2
, lnkctl2
);
1189 dd_dev_info(dd
, "%s: ..target speed is OK\n", __func__
);
1192 dd_dev_info(dd
, "%s: setting target link speed\n", __func__
);
1193 pcie_capability_read_word(dd
->pcidev
, PCI_EXP_LNKCTL2
, &lnkctl2
);
1194 dd_dev_info(dd
, "%s: ..old link control2: 0x%x\n", __func__
,
1196 lnkctl2
&= ~LNKCTL2_TARGET_LINK_SPEED_MASK
;
1197 lnkctl2
|= target_vector
;
1198 dd_dev_info(dd
, "%s: ..new link control2: 0x%x\n", __func__
,
1200 pcie_capability_write_word(dd
->pcidev
, PCI_EXP_LNKCTL2
, lnkctl2
);
1202 /* step 5h: arm gasket logic */
1203 /* hold DC in reset across the SBR */
1204 write_csr(dd
, CCE_DC_CTRL
, CCE_DC_CTRL_DC_RESET_SMASK
);
1205 (void)read_csr(dd
, CCE_DC_CTRL
); /* DC reset hold */
1206 /* save firmware control across the SBR */
1207 fw_ctrl
= read_csr(dd
, MISC_CFG_FW_CTRL
);
1209 dd_dev_info(dd
, "%s: arming gasket logic\n", __func__
);
1210 arm_gasket_logic(dd
);
1213 * step 6: quiesce PCIe link
1214 * The chip has already been reset, so there will be no traffic
1215 * from the chip. Linux has no easy way to enforce that it will
1216 * not try to access the device, so we just need to hope it doesn't
1217 * do it while we are doing the reset.
1221 * step 7: initiate the secondary bus reset (SBR)
1222 * step 8: hardware brings the links back up
1223 * step 9: wait for link speed transition to be complete
1225 dd_dev_info(dd
, "%s: calling trigger_sbr\n", __func__
);
1226 ret
= trigger_sbr(dd
);
1230 /* step 10: decide what to do next */
1232 /* check if we can read PCI space */
1233 ret
= pci_read_config_word(dd
->pcidev
, PCI_VENDOR_ID
, &vendor
);
1236 "%s: read of VendorID failed after SBR, err %d\n",
1241 if (vendor
== 0xffff) {
1242 dd_dev_info(dd
, "%s: VendorID is all 1s after SBR\n", __func__
);
1248 /* restore PCI space registers we know were reset */
1249 dd_dev_info(dd
, "%s: calling restore_pci_variables\n", __func__
);
1250 restore_pci_variables(dd
);
1251 /* restore firmware control */
1252 write_csr(dd
, MISC_CFG_FW_CTRL
, fw_ctrl
);
1255 * Check the gasket block status.
1257 * This is the first CSR read after the SBR. If the read returns
1258 * all 1s (fails), the link did not make it back.
1260 * Once we're sure we can read and write, clear the DC reset after
1261 * the SBR. Then check for any per-lane errors. Then look over
1264 reg
= read_csr(dd
, ASIC_PCIE_SD_HOST_STATUS
);
1265 dd_dev_info(dd
, "%s: gasket block status: 0x%llx\n", __func__
, reg
);
1266 if (reg
== ~0ull) { /* PCIe read failed/timeout */
1267 dd_dev_err(dd
, "SBR failed - unable to read from device\n");
1273 /* clear the DC reset */
1274 write_csr(dd
, CCE_DC_CTRL
, 0);
1276 /* Set the LED off */
1279 /* check for any per-lane errors */
1280 pci_read_config_dword(dd
->pcidev
, PCIE_CFG_SPCIE2
, ®32
);
1281 dd_dev_info(dd
, "%s: per-lane errors: 0x%x\n", __func__
, reg32
);
1283 /* extract status, look for our HFI */
1284 status
= (reg
>> ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_STS_SHIFT
)
1285 & ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_STS_MASK
;
1286 if ((status
& (1 << dd
->hfi1_id
)) == 0) {
1288 "%s: gasket status 0x%x, expecting 0x%x\n",
1289 __func__
, status
, 1 << dd
->hfi1_id
);
1295 err
= (reg
>> ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_ERR_SHIFT
)
1296 & ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_ERR_MASK
;
1298 dd_dev_err(dd
, "%s: gasket error %d\n", __func__
, err
);
1303 /* update our link information cache */
1304 update_lbus_info(dd
);
1305 dd_dev_info(dd
, "%s: new speed and width: %s\n", __func__
,
1308 if (dd
->lbus_speed
!= target_speed
) { /* not target */
1310 do_retry
= retry_count
< pcie_retry
;
1311 dd_dev_err(dd
, "PCIe link speed did not switch to Gen%d%s\n",
1312 pcie_target
, do_retry
? ", retrying" : "");
1315 msleep(100); /* allow time to settle */
1323 write_csr(dd
, ASIC_CFG_THERM_POLL_EN
, 0x1);
1325 dd_dev_info(dd
, "%s: Re-enable therm polling\n",
1328 release_chip_resource(dd
, CR_SBUS
);
1330 /* return no error if it is OK to be at current speed */
1331 if (ret
&& !return_error
) {
1332 dd_dev_err(dd
, "Proceeding at current speed PCIe speed\n");
1336 dd_dev_info(dd
, "%s: done\n", __func__
);