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Merge remote-tracking branch 'asoc/topic/pcm512x' into asoc-next
[mirror_ubuntu-focal-kernel.git] / drivers / infiniband / hw / hfi1 / pcie.c
1 /*
2 * Copyright(c) 2015 - 2017 Intel Corporation.
3 *
4 * This file is provided under a dual BSD/GPLv2 license. When using or
5 * redistributing this file, you may do so under either license.
6 *
7 * GPL LICENSE SUMMARY
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * BSD LICENSE
19 *
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions
22 * are met:
23 *
24 * - Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * - Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in
28 * the documentation and/or other materials provided with the
29 * distribution.
30 * - Neither the name of Intel Corporation nor the names of its
31 * contributors may be used to endorse or promote products derived
32 * from this software without specific prior written permission.
33 *
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 *
46 */
47
48 #include <linux/pci.h>
49 #include <linux/io.h>
50 #include <linux/delay.h>
51 #include <linux/vmalloc.h>
52 #include <linux/aer.h>
53 #include <linux/module.h>
54
55 #include "hfi.h"
56 #include "chip_registers.h"
57 #include "aspm.h"
58
59 /* link speed vector for Gen3 speed - not in Linux headers */
60 #define GEN1_SPEED_VECTOR 0x1
61 #define GEN2_SPEED_VECTOR 0x2
62 #define GEN3_SPEED_VECTOR 0x3
63
64 /*
65 * This file contains PCIe utility routines.
66 */
67
68 /*
69 * Code to adjust PCIe capabilities.
70 */
71 static void tune_pcie_caps(struct hfi1_devdata *);
72
73 /*
74 * Do all the common PCIe setup and initialization.
75 * devdata is not yet allocated, and is not allocated until after this
76 * routine returns success. Therefore dd_dev_err() can't be used for error
77 * printing.
78 */
79 int hfi1_pcie_init(struct pci_dev *pdev, const struct pci_device_id *ent)
80 {
81 int ret;
82
83 ret = pci_enable_device(pdev);
84 if (ret) {
85 /*
86 * This can happen (in theory) iff:
87 * We did a chip reset, and then failed to reprogram the
88 * BAR, or the chip reset due to an internal error. We then
89 * unloaded the driver and reloaded it.
90 *
91 * Both reset cases set the BAR back to initial state. For
92 * the latter case, the AER sticky error bit at offset 0x718
93 * should be set, but the Linux kernel doesn't yet know
94 * about that, it appears. If the original BAR was retained
95 * in the kernel data structures, this may be OK.
96 */
97 hfi1_early_err(&pdev->dev, "pci enable failed: error %d\n",
98 -ret);
99 goto done;
100 }
101
102 ret = pci_request_regions(pdev, DRIVER_NAME);
103 if (ret) {
104 hfi1_early_err(&pdev->dev,
105 "pci_request_regions fails: err %d\n", -ret);
106 goto bail;
107 }
108
109 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
110 if (ret) {
111 /*
112 * If the 64 bit setup fails, try 32 bit. Some systems
113 * do not setup 64 bit maps on systems with 2GB or less
114 * memory installed.
115 */
116 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
117 if (ret) {
118 hfi1_early_err(&pdev->dev,
119 "Unable to set DMA mask: %d\n", ret);
120 goto bail;
121 }
122 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
123 } else {
124 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
125 }
126 if (ret) {
127 hfi1_early_err(&pdev->dev,
128 "Unable to set DMA consistent mask: %d\n", ret);
129 goto bail;
130 }
131
132 pci_set_master(pdev);
133 (void)pci_enable_pcie_error_reporting(pdev);
134 goto done;
135
136 bail:
137 hfi1_pcie_cleanup(pdev);
138 done:
139 return ret;
140 }
141
142 /*
143 * Clean what was done in hfi1_pcie_init()
144 */
145 void hfi1_pcie_cleanup(struct pci_dev *pdev)
146 {
147 pci_disable_device(pdev);
148 /*
149 * Release regions should be called after the disable. OK to
150 * call if request regions has not been called or failed.
151 */
152 pci_release_regions(pdev);
153 }
154
155 /*
156 * Do remaining PCIe setup, once dd is allocated, and save away
157 * fields required to re-initialize after a chip reset, or for
158 * various other purposes
159 */
160 int hfi1_pcie_ddinit(struct hfi1_devdata *dd, struct pci_dev *pdev)
161 {
162 unsigned long len;
163 resource_size_t addr;
164 int ret = 0;
165
166 dd->pcidev = pdev;
167 pci_set_drvdata(pdev, dd);
168
169 addr = pci_resource_start(pdev, 0);
170 len = pci_resource_len(pdev, 0);
171
172 /*
173 * The TXE PIO buffers are at the tail end of the chip space.
174 * Cut them off and map them separately.
175 */
176
177 /* sanity check vs expectations */
178 if (len != TXE_PIO_SEND + TXE_PIO_SIZE) {
179 dd_dev_err(dd, "chip PIO range does not match\n");
180 return -EINVAL;
181 }
182
183 dd->kregbase1 = ioremap_nocache(addr, RCV_ARRAY);
184 if (!dd->kregbase1) {
185 dd_dev_err(dd, "UC mapping of kregbase1 failed\n");
186 return -ENOMEM;
187 }
188 dd_dev_info(dd, "UC base1: %p for %x\n", dd->kregbase1, RCV_ARRAY);
189 dd->chip_rcv_array_count = readq(dd->kregbase1 + RCV_ARRAY_CNT);
190 dd_dev_info(dd, "RcvArray count: %u\n", dd->chip_rcv_array_count);
191 dd->base2_start = RCV_ARRAY + dd->chip_rcv_array_count * 8;
192
193 dd->kregbase2 = ioremap_nocache(
194 addr + dd->base2_start,
195 TXE_PIO_SEND - dd->base2_start);
196 if (!dd->kregbase2) {
197 dd_dev_err(dd, "UC mapping of kregbase2 failed\n");
198 goto nomem;
199 }
200 dd_dev_info(dd, "UC base2: %p for %x\n", dd->kregbase2,
201 TXE_PIO_SEND - dd->base2_start);
202
203 dd->piobase = ioremap_wc(addr + TXE_PIO_SEND, TXE_PIO_SIZE);
204 if (!dd->piobase) {
205 dd_dev_err(dd, "WC mapping of send buffers failed\n");
206 goto nomem;
207 }
208 dd_dev_info(dd, "WC piobase: %p\n for %x", dd->piobase, TXE_PIO_SIZE);
209
210 dd->physaddr = addr; /* used for io_remap, etc. */
211
212 /*
213 * Map the chip's RcvArray as write-combining to allow us
214 * to write an entire cacheline worth of entries in one shot.
215 */
216 dd->rcvarray_wc = ioremap_wc(addr + RCV_ARRAY,
217 dd->chip_rcv_array_count * 8);
218 if (!dd->rcvarray_wc) {
219 dd_dev_err(dd, "WC mapping of receive array failed\n");
220 goto nomem;
221 }
222 dd_dev_info(dd, "WC RcvArray: %p for %x\n",
223 dd->rcvarray_wc, dd->chip_rcv_array_count * 8);
224
225 dd->flags |= HFI1_PRESENT; /* chip.c CSR routines now work */
226 return 0;
227 nomem:
228 ret = -ENOMEM;
229 hfi1_pcie_ddcleanup(dd);
230 return ret;
231 }
232
233 /*
234 * Do PCIe cleanup related to dd, after chip-specific cleanup, etc. Just prior
235 * to releasing the dd memory.
236 * Void because all of the core pcie cleanup functions are void.
237 */
238 void hfi1_pcie_ddcleanup(struct hfi1_devdata *dd)
239 {
240 dd->flags &= ~HFI1_PRESENT;
241 if (dd->kregbase1)
242 iounmap(dd->kregbase1);
243 dd->kregbase1 = NULL;
244 if (dd->kregbase2)
245 iounmap(dd->kregbase2);
246 dd->kregbase2 = NULL;
247 if (dd->rcvarray_wc)
248 iounmap(dd->rcvarray_wc);
249 dd->rcvarray_wc = NULL;
250 if (dd->piobase)
251 iounmap(dd->piobase);
252 dd->piobase = NULL;
253 }
254
255 /* return the PCIe link speed from the given link status */
256 static u32 extract_speed(u16 linkstat)
257 {
258 u32 speed;
259
260 switch (linkstat & PCI_EXP_LNKSTA_CLS) {
261 default: /* not defined, assume Gen1 */
262 case PCI_EXP_LNKSTA_CLS_2_5GB:
263 speed = 2500; /* Gen 1, 2.5GHz */
264 break;
265 case PCI_EXP_LNKSTA_CLS_5_0GB:
266 speed = 5000; /* Gen 2, 5GHz */
267 break;
268 case GEN3_SPEED_VECTOR:
269 speed = 8000; /* Gen 3, 8GHz */
270 break;
271 }
272 return speed;
273 }
274
275 /* return the PCIe link speed from the given link status */
276 static u32 extract_width(u16 linkstat)
277 {
278 return (linkstat & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT;
279 }
280
281 /* read the link status and set dd->{lbus_width,lbus_speed,lbus_info} */
282 static void update_lbus_info(struct hfi1_devdata *dd)
283 {
284 u16 linkstat;
285 int ret;
286
287 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKSTA, &linkstat);
288 if (ret) {
289 dd_dev_err(dd, "Unable to read from PCI config\n");
290 return;
291 }
292
293 dd->lbus_width = extract_width(linkstat);
294 dd->lbus_speed = extract_speed(linkstat);
295 snprintf(dd->lbus_info, sizeof(dd->lbus_info),
296 "PCIe,%uMHz,x%u", dd->lbus_speed, dd->lbus_width);
297 }
298
299 /*
300 * Read in the current PCIe link width and speed. Find if the link is
301 * Gen3 capable.
302 */
303 int pcie_speeds(struct hfi1_devdata *dd)
304 {
305 u32 linkcap;
306 struct pci_dev *parent = dd->pcidev->bus->self;
307 int ret;
308
309 if (!pci_is_pcie(dd->pcidev)) {
310 dd_dev_err(dd, "Can't find PCI Express capability!\n");
311 return -EINVAL;
312 }
313
314 /* find if our max speed is Gen3 and parent supports Gen3 speeds */
315 dd->link_gen3_capable = 1;
316
317 ret = pcie_capability_read_dword(dd->pcidev, PCI_EXP_LNKCAP, &linkcap);
318 if (ret) {
319 dd_dev_err(dd, "Unable to read from PCI config\n");
320 return ret;
321 }
322
323 if ((linkcap & PCI_EXP_LNKCAP_SLS) != GEN3_SPEED_VECTOR) {
324 dd_dev_info(dd,
325 "This HFI is not Gen3 capable, max speed 0x%x, need 0x3\n",
326 linkcap & PCI_EXP_LNKCAP_SLS);
327 dd->link_gen3_capable = 0;
328 }
329
330 /*
331 * bus->max_bus_speed is set from the bridge's linkcap Max Link Speed
332 */
333 if (parent && dd->pcidev->bus->max_bus_speed != PCIE_SPEED_8_0GT) {
334 dd_dev_info(dd, "Parent PCIe bridge does not support Gen3\n");
335 dd->link_gen3_capable = 0;
336 }
337
338 /* obtain the link width and current speed */
339 update_lbus_info(dd);
340
341 dd_dev_info(dd, "%s\n", dd->lbus_info);
342
343 return 0;
344 }
345
346 /*
347 * Returns:
348 * - actual number of interrupts allocated or
349 * - 0 if fell back to INTx.
350 * - error
351 */
352 int request_msix(struct hfi1_devdata *dd, u32 msireq)
353 {
354 int nvec;
355
356 nvec = pci_alloc_irq_vectors(dd->pcidev, 1, msireq,
357 PCI_IRQ_MSIX | PCI_IRQ_LEGACY);
358 if (nvec < 0) {
359 dd_dev_err(dd, "pci_alloc_irq_vectors() failed: %d\n", nvec);
360 return nvec;
361 }
362
363 tune_pcie_caps(dd);
364
365 /* check for legacy IRQ */
366 if (nvec == 1 && !dd->pcidev->msix_enabled)
367 return 0;
368
369 return nvec;
370 }
371
372 /* restore command and BARs after a reset has wiped them out */
373 int restore_pci_variables(struct hfi1_devdata *dd)
374 {
375 int ret = 0;
376
377 ret = pci_write_config_word(dd->pcidev, PCI_COMMAND, dd->pci_command);
378 if (ret)
379 goto error;
380
381 ret = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
382 dd->pcibar0);
383 if (ret)
384 goto error;
385
386 ret = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1,
387 dd->pcibar1);
388 if (ret)
389 goto error;
390
391 ret = pci_write_config_dword(dd->pcidev, PCI_ROM_ADDRESS, dd->pci_rom);
392 if (ret)
393 goto error;
394
395 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL,
396 dd->pcie_devctl);
397 if (ret)
398 goto error;
399
400 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL,
401 dd->pcie_lnkctl);
402 if (ret)
403 goto error;
404
405 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL2,
406 dd->pcie_devctl2);
407 if (ret)
408 goto error;
409
410 ret = pci_write_config_dword(dd->pcidev, PCI_CFG_MSIX0, dd->pci_msix0);
411 if (ret)
412 goto error;
413
414 if (pci_find_ext_capability(dd->pcidev, PCI_EXT_CAP_ID_TPH)) {
415 ret = pci_write_config_dword(dd->pcidev, PCIE_CFG_TPH2,
416 dd->pci_tph2);
417 if (ret)
418 goto error;
419 }
420 return 0;
421
422 error:
423 dd_dev_err(dd, "Unable to write to PCI config\n");
424 return ret;
425 }
426
427 /* Save BARs and command to rewrite after device reset */
428 int save_pci_variables(struct hfi1_devdata *dd)
429 {
430 int ret = 0;
431
432 ret = pci_read_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
433 &dd->pcibar0);
434 if (ret)
435 goto error;
436
437 ret = pci_read_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1,
438 &dd->pcibar1);
439 if (ret)
440 goto error;
441
442 ret = pci_read_config_dword(dd->pcidev, PCI_ROM_ADDRESS, &dd->pci_rom);
443 if (ret)
444 goto error;
445
446 ret = pci_read_config_word(dd->pcidev, PCI_COMMAND, &dd->pci_command);
447 if (ret)
448 goto error;
449
450 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL,
451 &dd->pcie_devctl);
452 if (ret)
453 goto error;
454
455 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL,
456 &dd->pcie_lnkctl);
457 if (ret)
458 goto error;
459
460 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL2,
461 &dd->pcie_devctl2);
462 if (ret)
463 goto error;
464
465 ret = pci_read_config_dword(dd->pcidev, PCI_CFG_MSIX0, &dd->pci_msix0);
466 if (ret)
467 goto error;
468
469 if (pci_find_ext_capability(dd->pcidev, PCI_EXT_CAP_ID_TPH)) {
470 ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_TPH2,
471 &dd->pci_tph2);
472 if (ret)
473 goto error;
474 }
475 return 0;
476
477 error:
478 dd_dev_err(dd, "Unable to read from PCI config\n");
479 return ret;
480 }
481
482 /*
483 * BIOS may not set PCIe bus-utilization parameters for best performance.
484 * Check and optionally adjust them to maximize our throughput.
485 */
486 static int hfi1_pcie_caps;
487 module_param_named(pcie_caps, hfi1_pcie_caps, int, S_IRUGO);
488 MODULE_PARM_DESC(pcie_caps, "Max PCIe tuning: Payload (0..3), ReadReq (4..7)");
489
490 uint aspm_mode = ASPM_MODE_DISABLED;
491 module_param_named(aspm, aspm_mode, uint, S_IRUGO);
492 MODULE_PARM_DESC(aspm, "PCIe ASPM: 0: disable, 1: enable, 2: dynamic");
493
494 static void tune_pcie_caps(struct hfi1_devdata *dd)
495 {
496 struct pci_dev *parent;
497 u16 rc_mpss, rc_mps, ep_mpss, ep_mps;
498 u16 rc_mrrs, ep_mrrs, max_mrrs, ectl;
499 int ret;
500
501 /*
502 * Turn on extended tags in DevCtl in case the BIOS has turned it off
503 * to improve WFR SDMA bandwidth
504 */
505 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL, &ectl);
506 if ((!ret) && !(ectl & PCI_EXP_DEVCTL_EXT_TAG)) {
507 dd_dev_info(dd, "Enabling PCIe extended tags\n");
508 ectl |= PCI_EXP_DEVCTL_EXT_TAG;
509 ret = pcie_capability_write_word(dd->pcidev,
510 PCI_EXP_DEVCTL, ectl);
511 if (ret)
512 dd_dev_info(dd, "Unable to write to PCI config\n");
513 }
514 /* Find out supported and configured values for parent (root) */
515 parent = dd->pcidev->bus->self;
516 /*
517 * The driver cannot perform the tuning if it does not have
518 * access to the upstream component.
519 */
520 if (!parent) {
521 dd_dev_info(dd, "Parent not found\n");
522 return;
523 }
524 if (!pci_is_root_bus(parent->bus)) {
525 dd_dev_info(dd, "Parent not root\n");
526 return;
527 }
528 if (!pci_is_pcie(parent)) {
529 dd_dev_info(dd, "Parent is not PCI Express capable\n");
530 return;
531 }
532 if (!pci_is_pcie(dd->pcidev)) {
533 dd_dev_info(dd, "PCI device is not PCI Express capable\n");
534 return;
535 }
536 rc_mpss = parent->pcie_mpss;
537 rc_mps = ffs(pcie_get_mps(parent)) - 8;
538 /* Find out supported and configured values for endpoint (us) */
539 ep_mpss = dd->pcidev->pcie_mpss;
540 ep_mps = ffs(pcie_get_mps(dd->pcidev)) - 8;
541
542 /* Find max payload supported by root, endpoint */
543 if (rc_mpss > ep_mpss)
544 rc_mpss = ep_mpss;
545
546 /* If Supported greater than limit in module param, limit it */
547 if (rc_mpss > (hfi1_pcie_caps & 7))
548 rc_mpss = hfi1_pcie_caps & 7;
549 /* If less than (allowed, supported), bump root payload */
550 if (rc_mpss > rc_mps) {
551 rc_mps = rc_mpss;
552 pcie_set_mps(parent, 128 << rc_mps);
553 }
554 /* If less than (allowed, supported), bump endpoint payload */
555 if (rc_mpss > ep_mps) {
556 ep_mps = rc_mpss;
557 pcie_set_mps(dd->pcidev, 128 << ep_mps);
558 }
559
560 /*
561 * Now the Read Request size.
562 * No field for max supported, but PCIe spec limits it to 4096,
563 * which is code '5' (log2(4096) - 7)
564 */
565 max_mrrs = 5;
566 if (max_mrrs > ((hfi1_pcie_caps >> 4) & 7))
567 max_mrrs = (hfi1_pcie_caps >> 4) & 7;
568
569 max_mrrs = 128 << max_mrrs;
570 rc_mrrs = pcie_get_readrq(parent);
571 ep_mrrs = pcie_get_readrq(dd->pcidev);
572
573 if (max_mrrs > rc_mrrs) {
574 rc_mrrs = max_mrrs;
575 pcie_set_readrq(parent, rc_mrrs);
576 }
577 if (max_mrrs > ep_mrrs) {
578 ep_mrrs = max_mrrs;
579 pcie_set_readrq(dd->pcidev, ep_mrrs);
580 }
581 }
582
583 /* End of PCIe capability tuning */
584
585 /*
586 * From here through hfi1_pci_err_handler definition is invoked via
587 * PCI error infrastructure, registered via pci
588 */
589 static pci_ers_result_t
590 pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
591 {
592 struct hfi1_devdata *dd = pci_get_drvdata(pdev);
593 pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED;
594
595 switch (state) {
596 case pci_channel_io_normal:
597 dd_dev_info(dd, "State Normal, ignoring\n");
598 break;
599
600 case pci_channel_io_frozen:
601 dd_dev_info(dd, "State Frozen, requesting reset\n");
602 pci_disable_device(pdev);
603 ret = PCI_ERS_RESULT_NEED_RESET;
604 break;
605
606 case pci_channel_io_perm_failure:
607 if (dd) {
608 dd_dev_info(dd, "State Permanent Failure, disabling\n");
609 /* no more register accesses! */
610 dd->flags &= ~HFI1_PRESENT;
611 hfi1_disable_after_error(dd);
612 }
613 /* else early, or other problem */
614 ret = PCI_ERS_RESULT_DISCONNECT;
615 break;
616
617 default: /* shouldn't happen */
618 dd_dev_info(dd, "HFI1 PCI errors detected (state %d)\n",
619 state);
620 break;
621 }
622 return ret;
623 }
624
625 static pci_ers_result_t
626 pci_mmio_enabled(struct pci_dev *pdev)
627 {
628 u64 words = 0U;
629 struct hfi1_devdata *dd = pci_get_drvdata(pdev);
630 pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED;
631
632 if (dd && dd->pport) {
633 words = read_port_cntr(dd->pport, C_RX_WORDS, CNTR_INVALID_VL);
634 if (words == ~0ULL)
635 ret = PCI_ERS_RESULT_NEED_RESET;
636 dd_dev_info(dd,
637 "HFI1 mmio_enabled function called, read wordscntr %llx, returning %d\n",
638 words, ret);
639 }
640 return ret;
641 }
642
643 static pci_ers_result_t
644 pci_slot_reset(struct pci_dev *pdev)
645 {
646 struct hfi1_devdata *dd = pci_get_drvdata(pdev);
647
648 dd_dev_info(dd, "HFI1 slot_reset function called, ignored\n");
649 return PCI_ERS_RESULT_CAN_RECOVER;
650 }
651
652 static void
653 pci_resume(struct pci_dev *pdev)
654 {
655 struct hfi1_devdata *dd = pci_get_drvdata(pdev);
656
657 dd_dev_info(dd, "HFI1 resume function called\n");
658 pci_cleanup_aer_uncorrect_error_status(pdev);
659 /*
660 * Running jobs will fail, since it's asynchronous
661 * unlike sysfs-requested reset. Better than
662 * doing nothing.
663 */
664 hfi1_init(dd, 1); /* same as re-init after reset */
665 }
666
667 const struct pci_error_handlers hfi1_pci_err_handler = {
668 .error_detected = pci_error_detected,
669 .mmio_enabled = pci_mmio_enabled,
670 .slot_reset = pci_slot_reset,
671 .resume = pci_resume,
672 };
673
674 /*============================================================================*/
675 /* PCIe Gen3 support */
676
677 /*
678 * This code is separated out because it is expected to be removed in the
679 * final shipping product. If not, then it will be revisited and items
680 * will be moved to more standard locations.
681 */
682
683 /* ASIC_PCI_SD_HOST_STATUS.FW_DNLD_STS field values */
684 #define DL_STATUS_HFI0 0x1 /* hfi0 firmware download complete */
685 #define DL_STATUS_HFI1 0x2 /* hfi1 firmware download complete */
686 #define DL_STATUS_BOTH 0x3 /* hfi0 and hfi1 firmware download complete */
687
688 /* ASIC_PCI_SD_HOST_STATUS.FW_DNLD_ERR field values */
689 #define DL_ERR_NONE 0x0 /* no error */
690 #define DL_ERR_SWAP_PARITY 0x1 /* parity error in SerDes interrupt */
691 /* or response data */
692 #define DL_ERR_DISABLED 0x2 /* hfi disabled */
693 #define DL_ERR_SECURITY 0x3 /* security check failed */
694 #define DL_ERR_SBUS 0x4 /* SBus status error */
695 #define DL_ERR_XFR_PARITY 0x5 /* parity error during ROM transfer*/
696
697 /* gasket block secondary bus reset delay */
698 #define SBR_DELAY_US 200000 /* 200ms */
699
700 /* mask for PCIe capability register lnkctl2 target link speed */
701 #define LNKCTL2_TARGET_LINK_SPEED_MASK 0xf
702
703 static uint pcie_target = 3;
704 module_param(pcie_target, uint, S_IRUGO);
705 MODULE_PARM_DESC(pcie_target, "PCIe target speed (0 skip, 1-3 Gen1-3)");
706
707 static uint pcie_force;
708 module_param(pcie_force, uint, S_IRUGO);
709 MODULE_PARM_DESC(pcie_force, "Force driver to do a PCIe firmware download even if already at target speed");
710
711 static uint pcie_retry = 5;
712 module_param(pcie_retry, uint, S_IRUGO);
713 MODULE_PARM_DESC(pcie_retry, "Driver will try this many times to reach requested speed");
714
715 #define UNSET_PSET 255
716 #define DEFAULT_DISCRETE_PSET 2 /* discrete HFI */
717 #define DEFAULT_MCP_PSET 6 /* MCP HFI */
718 static uint pcie_pset = UNSET_PSET;
719 module_param(pcie_pset, uint, S_IRUGO);
720 MODULE_PARM_DESC(pcie_pset, "PCIe Eq Pset value to use, range is 0-10");
721
722 static uint pcie_ctle = 3; /* discrete on, integrated on */
723 module_param(pcie_ctle, uint, S_IRUGO);
724 MODULE_PARM_DESC(pcie_ctle, "PCIe static CTLE mode, bit 0 - discrete on/off, bit 1 - integrated on/off");
725
726 /* equalization columns */
727 #define PREC 0
728 #define ATTN 1
729 #define POST 2
730
731 /* discrete silicon preliminary equalization values */
732 static const u8 discrete_preliminary_eq[11][3] = {
733 /* prec attn post */
734 { 0x00, 0x00, 0x12 }, /* p0 */
735 { 0x00, 0x00, 0x0c }, /* p1 */
736 { 0x00, 0x00, 0x0f }, /* p2 */
737 { 0x00, 0x00, 0x09 }, /* p3 */
738 { 0x00, 0x00, 0x00 }, /* p4 */
739 { 0x06, 0x00, 0x00 }, /* p5 */
740 { 0x09, 0x00, 0x00 }, /* p6 */
741 { 0x06, 0x00, 0x0f }, /* p7 */
742 { 0x09, 0x00, 0x09 }, /* p8 */
743 { 0x0c, 0x00, 0x00 }, /* p9 */
744 { 0x00, 0x00, 0x18 }, /* p10 */
745 };
746
747 /* integrated silicon preliminary equalization values */
748 static const u8 integrated_preliminary_eq[11][3] = {
749 /* prec attn post */
750 { 0x00, 0x1e, 0x07 }, /* p0 */
751 { 0x00, 0x1e, 0x05 }, /* p1 */
752 { 0x00, 0x1e, 0x06 }, /* p2 */
753 { 0x00, 0x1e, 0x04 }, /* p3 */
754 { 0x00, 0x1e, 0x00 }, /* p4 */
755 { 0x03, 0x1e, 0x00 }, /* p5 */
756 { 0x04, 0x1e, 0x00 }, /* p6 */
757 { 0x03, 0x1e, 0x06 }, /* p7 */
758 { 0x03, 0x1e, 0x04 }, /* p8 */
759 { 0x05, 0x1e, 0x00 }, /* p9 */
760 { 0x00, 0x1e, 0x0a }, /* p10 */
761 };
762
763 static const u8 discrete_ctle_tunings[11][4] = {
764 /* DC LF HF BW */
765 { 0x48, 0x0b, 0x04, 0x04 }, /* p0 */
766 { 0x60, 0x05, 0x0f, 0x0a }, /* p1 */
767 { 0x50, 0x09, 0x06, 0x06 }, /* p2 */
768 { 0x68, 0x05, 0x0f, 0x0a }, /* p3 */
769 { 0x80, 0x05, 0x0f, 0x0a }, /* p4 */
770 { 0x70, 0x05, 0x0f, 0x0a }, /* p5 */
771 { 0x68, 0x05, 0x0f, 0x0a }, /* p6 */
772 { 0x38, 0x0f, 0x00, 0x00 }, /* p7 */
773 { 0x48, 0x09, 0x06, 0x06 }, /* p8 */
774 { 0x60, 0x05, 0x0f, 0x0a }, /* p9 */
775 { 0x38, 0x0f, 0x00, 0x00 }, /* p10 */
776 };
777
778 static const u8 integrated_ctle_tunings[11][4] = {
779 /* DC LF HF BW */
780 { 0x38, 0x0f, 0x00, 0x00 }, /* p0 */
781 { 0x38, 0x0f, 0x00, 0x00 }, /* p1 */
782 { 0x38, 0x0f, 0x00, 0x00 }, /* p2 */
783 { 0x38, 0x0f, 0x00, 0x00 }, /* p3 */
784 { 0x58, 0x0a, 0x05, 0x05 }, /* p4 */
785 { 0x48, 0x0a, 0x05, 0x05 }, /* p5 */
786 { 0x40, 0x0a, 0x05, 0x05 }, /* p6 */
787 { 0x38, 0x0f, 0x00, 0x00 }, /* p7 */
788 { 0x38, 0x0f, 0x00, 0x00 }, /* p8 */
789 { 0x38, 0x09, 0x06, 0x06 }, /* p9 */
790 { 0x38, 0x0e, 0x01, 0x01 }, /* p10 */
791 };
792
793 /* helper to format the value to write to hardware */
794 #define eq_value(pre, curr, post) \
795 ((((u32)(pre)) << \
796 PCIE_CFG_REG_PL102_GEN3_EQ_PRE_CURSOR_PSET_SHIFT) \
797 | (((u32)(curr)) << PCIE_CFG_REG_PL102_GEN3_EQ_CURSOR_PSET_SHIFT) \
798 | (((u32)(post)) << \
799 PCIE_CFG_REG_PL102_GEN3_EQ_POST_CURSOR_PSET_SHIFT))
800
801 /*
802 * Load the given EQ preset table into the PCIe hardware.
803 */
804 static int load_eq_table(struct hfi1_devdata *dd, const u8 eq[11][3], u8 fs,
805 u8 div)
806 {
807 struct pci_dev *pdev = dd->pcidev;
808 u32 hit_error = 0;
809 u32 violation;
810 u32 i;
811 u8 c_minus1, c0, c_plus1;
812 int ret;
813
814 for (i = 0; i < 11; i++) {
815 /* set index */
816 pci_write_config_dword(pdev, PCIE_CFG_REG_PL103, i);
817 /* write the value */
818 c_minus1 = eq[i][PREC] / div;
819 c0 = fs - (eq[i][PREC] / div) - (eq[i][POST] / div);
820 c_plus1 = eq[i][POST] / div;
821 pci_write_config_dword(pdev, PCIE_CFG_REG_PL102,
822 eq_value(c_minus1, c0, c_plus1));
823 /* check if these coefficients violate EQ rules */
824 ret = pci_read_config_dword(dd->pcidev,
825 PCIE_CFG_REG_PL105, &violation);
826 if (ret) {
827 dd_dev_err(dd, "Unable to read from PCI config\n");
828 hit_error = 1;
829 break;
830 }
831
832 if (violation
833 & PCIE_CFG_REG_PL105_GEN3_EQ_VIOLATE_COEF_RULES_SMASK){
834 if (hit_error == 0) {
835 dd_dev_err(dd,
836 "Gen3 EQ Table Coefficient rule violations\n");
837 dd_dev_err(dd, " prec attn post\n");
838 }
839 dd_dev_err(dd, " p%02d: %02x %02x %02x\n",
840 i, (u32)eq[i][0], (u32)eq[i][1],
841 (u32)eq[i][2]);
842 dd_dev_err(dd, " %02x %02x %02x\n",
843 (u32)c_minus1, (u32)c0, (u32)c_plus1);
844 hit_error = 1;
845 }
846 }
847 if (hit_error)
848 return -EINVAL;
849 return 0;
850 }
851
852 /*
853 * Steps to be done after the PCIe firmware is downloaded and
854 * before the SBR for the Pcie Gen3.
855 * The SBus resource is already being held.
856 */
857 static void pcie_post_steps(struct hfi1_devdata *dd)
858 {
859 int i;
860
861 set_sbus_fast_mode(dd);
862 /*
863 * Write to the PCIe PCSes to set the G3_LOCKED_NEXT bits to 1.
864 * This avoids a spurious framing error that can otherwise be
865 * generated by the MAC layer.
866 *
867 * Use individual addresses since no broadcast is set up.
868 */
869 for (i = 0; i < NUM_PCIE_SERDES; i++) {
870 sbus_request(dd, pcie_pcs_addrs[dd->hfi1_id][i],
871 0x03, WRITE_SBUS_RECEIVER, 0x00022132);
872 }
873
874 clear_sbus_fast_mode(dd);
875 }
876
877 /*
878 * Trigger a secondary bus reset (SBR) on ourselves using our parent.
879 *
880 * Based on pci_parent_bus_reset() which is not exported by the
881 * kernel core.
882 */
883 static int trigger_sbr(struct hfi1_devdata *dd)
884 {
885 struct pci_dev *dev = dd->pcidev;
886 struct pci_dev *pdev;
887
888 /* need a parent */
889 if (!dev->bus->self) {
890 dd_dev_err(dd, "%s: no parent device\n", __func__);
891 return -ENOTTY;
892 }
893
894 /* should not be anyone else on the bus */
895 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
896 if (pdev != dev) {
897 dd_dev_err(dd,
898 "%s: another device is on the same bus\n",
899 __func__);
900 return -ENOTTY;
901 }
902
903 /*
904 * A secondary bus reset (SBR) issues a hot reset to our device.
905 * The following routine does a 1s wait after the reset is dropped
906 * per PCI Trhfa (recovery time). PCIe 3.0 section 6.6.1 -
907 * Conventional Reset, paragraph 3, line 35 also says that a 1s
908 * delay after a reset is required. Per spec requirements,
909 * the link is either working or not after that point.
910 */
911 pci_reset_bridge_secondary_bus(dev->bus->self);
912
913 return 0;
914 }
915
916 /*
917 * Write the given gasket interrupt register.
918 */
919 static void write_gasket_interrupt(struct hfi1_devdata *dd, int index,
920 u16 code, u16 data)
921 {
922 write_csr(dd, ASIC_PCIE_SD_INTRPT_LIST + (index * 8),
923 (((u64)code << ASIC_PCIE_SD_INTRPT_LIST_INTRPT_CODE_SHIFT) |
924 ((u64)data << ASIC_PCIE_SD_INTRPT_LIST_INTRPT_DATA_SHIFT)));
925 }
926
927 /*
928 * Tell the gasket logic how to react to the reset.
929 */
930 static void arm_gasket_logic(struct hfi1_devdata *dd)
931 {
932 u64 reg;
933
934 reg = (((u64)1 << dd->hfi1_id) <<
935 ASIC_PCIE_SD_HOST_CMD_INTRPT_CMD_SHIFT) |
936 ((u64)pcie_serdes_broadcast[dd->hfi1_id] <<
937 ASIC_PCIE_SD_HOST_CMD_SBUS_RCVR_ADDR_SHIFT |
938 ASIC_PCIE_SD_HOST_CMD_SBR_MODE_SMASK |
939 ((u64)SBR_DELAY_US & ASIC_PCIE_SD_HOST_CMD_TIMER_MASK) <<
940 ASIC_PCIE_SD_HOST_CMD_TIMER_SHIFT);
941 write_csr(dd, ASIC_PCIE_SD_HOST_CMD, reg);
942 /* read back to push the write */
943 read_csr(dd, ASIC_PCIE_SD_HOST_CMD);
944 }
945
946 /*
947 * CCE_PCIE_CTRL long name helpers
948 * We redefine these shorter macros to use in the code while leaving
949 * chip_registers.h to be autogenerated from the hardware spec.
950 */
951 #define LANE_BUNDLE_MASK CCE_PCIE_CTRL_PCIE_LANE_BUNDLE_MASK
952 #define LANE_BUNDLE_SHIFT CCE_PCIE_CTRL_PCIE_LANE_BUNDLE_SHIFT
953 #define LANE_DELAY_MASK CCE_PCIE_CTRL_PCIE_LANE_DELAY_MASK
954 #define LANE_DELAY_SHIFT CCE_PCIE_CTRL_PCIE_LANE_DELAY_SHIFT
955 #define MARGIN_OVERWRITE_ENABLE_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_OVERWRITE_ENABLE_SHIFT
956 #define MARGIN_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_SHIFT
957 #define MARGIN_G1_G2_OVERWRITE_MASK CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_OVERWRITE_ENABLE_MASK
958 #define MARGIN_G1_G2_OVERWRITE_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_OVERWRITE_ENABLE_SHIFT
959 #define MARGIN_GEN1_GEN2_MASK CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_MASK
960 #define MARGIN_GEN1_GEN2_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_SHIFT
961
962 /*
963 * Write xmt_margin for full-swing (WFR-B) or half-swing (WFR-C).
964 */
965 static void write_xmt_margin(struct hfi1_devdata *dd, const char *fname)
966 {
967 u64 pcie_ctrl;
968 u64 xmt_margin;
969 u64 xmt_margin_oe;
970 u64 lane_delay;
971 u64 lane_bundle;
972
973 pcie_ctrl = read_csr(dd, CCE_PCIE_CTRL);
974
975 /*
976 * For Discrete, use full-swing.
977 * - PCIe TX defaults to full-swing.
978 * Leave this register as default.
979 * For Integrated, use half-swing
980 * - Copy xmt_margin and xmt_margin_oe
981 * from Gen1/Gen2 to Gen3.
982 */
983 if (dd->pcidev->device == PCI_DEVICE_ID_INTEL1) { /* integrated */
984 /* extract initial fields */
985 xmt_margin = (pcie_ctrl >> MARGIN_GEN1_GEN2_SHIFT)
986 & MARGIN_GEN1_GEN2_MASK;
987 xmt_margin_oe = (pcie_ctrl >> MARGIN_G1_G2_OVERWRITE_SHIFT)
988 & MARGIN_G1_G2_OVERWRITE_MASK;
989 lane_delay = (pcie_ctrl >> LANE_DELAY_SHIFT) & LANE_DELAY_MASK;
990 lane_bundle = (pcie_ctrl >> LANE_BUNDLE_SHIFT)
991 & LANE_BUNDLE_MASK;
992
993 /*
994 * For A0, EFUSE values are not set. Override with the
995 * correct values.
996 */
997 if (is_ax(dd)) {
998 /*
999 * xmt_margin and OverwiteEnabel should be the
1000 * same for Gen1/Gen2 and Gen3
1001 */
1002 xmt_margin = 0x5;
1003 xmt_margin_oe = 0x1;
1004 lane_delay = 0xF; /* Delay 240ns. */
1005 lane_bundle = 0x0; /* Set to 1 lane. */
1006 }
1007
1008 /* overwrite existing values */
1009 pcie_ctrl = (xmt_margin << MARGIN_GEN1_GEN2_SHIFT)
1010 | (xmt_margin_oe << MARGIN_G1_G2_OVERWRITE_SHIFT)
1011 | (xmt_margin << MARGIN_SHIFT)
1012 | (xmt_margin_oe << MARGIN_OVERWRITE_ENABLE_SHIFT)
1013 | (lane_delay << LANE_DELAY_SHIFT)
1014 | (lane_bundle << LANE_BUNDLE_SHIFT);
1015
1016 write_csr(dd, CCE_PCIE_CTRL, pcie_ctrl);
1017 }
1018
1019 dd_dev_dbg(dd, "%s: program XMT margin, CcePcieCtrl 0x%llx\n",
1020 fname, pcie_ctrl);
1021 }
1022
1023 /*
1024 * Do all the steps needed to transition the PCIe link to Gen3 speed.
1025 */
1026 int do_pcie_gen3_transition(struct hfi1_devdata *dd)
1027 {
1028 struct pci_dev *parent = dd->pcidev->bus->self;
1029 u64 fw_ctrl;
1030 u64 reg, therm;
1031 u32 reg32, fs, lf;
1032 u32 status, err;
1033 int ret;
1034 int do_retry, retry_count = 0;
1035 int intnum = 0;
1036 uint default_pset;
1037 u16 target_vector, target_speed;
1038 u16 lnkctl2, vendor;
1039 u8 div;
1040 const u8 (*eq)[3];
1041 const u8 (*ctle_tunings)[4];
1042 uint static_ctle_mode;
1043 int return_error = 0;
1044
1045 /* PCIe Gen3 is for the ASIC only */
1046 if (dd->icode != ICODE_RTL_SILICON)
1047 return 0;
1048
1049 if (pcie_target == 1) { /* target Gen1 */
1050 target_vector = GEN1_SPEED_VECTOR;
1051 target_speed = 2500;
1052 } else if (pcie_target == 2) { /* target Gen2 */
1053 target_vector = GEN2_SPEED_VECTOR;
1054 target_speed = 5000;
1055 } else if (pcie_target == 3) { /* target Gen3 */
1056 target_vector = GEN3_SPEED_VECTOR;
1057 target_speed = 8000;
1058 } else {
1059 /* off or invalid target - skip */
1060 dd_dev_info(dd, "%s: Skipping PCIe transition\n", __func__);
1061 return 0;
1062 }
1063
1064 /* if already at target speed, done (unless forced) */
1065 if (dd->lbus_speed == target_speed) {
1066 dd_dev_info(dd, "%s: PCIe already at gen%d, %s\n", __func__,
1067 pcie_target,
1068 pcie_force ? "re-doing anyway" : "skipping");
1069 if (!pcie_force)
1070 return 0;
1071 }
1072
1073 /*
1074 * The driver cannot do the transition if it has no access to the
1075 * upstream component
1076 */
1077 if (!parent) {
1078 dd_dev_info(dd, "%s: No upstream, Can't do gen3 transition\n",
1079 __func__);
1080 return 0;
1081 }
1082
1083 /*
1084 * Do the Gen3 transition. Steps are those of the PCIe Gen3
1085 * recipe.
1086 */
1087
1088 /* step 1: pcie link working in gen1/gen2 */
1089
1090 /* step 2: if either side is not capable of Gen3, done */
1091 if (pcie_target == 3 && !dd->link_gen3_capable) {
1092 dd_dev_err(dd, "The PCIe link is not Gen3 capable\n");
1093 ret = -ENOSYS;
1094 goto done_no_mutex;
1095 }
1096
1097 /* hold the SBus resource across the firmware download and SBR */
1098 ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT);
1099 if (ret) {
1100 dd_dev_err(dd, "%s: unable to acquire SBus resource\n",
1101 __func__);
1102 return ret;
1103 }
1104
1105 /* make sure thermal polling is not causing interrupts */
1106 therm = read_csr(dd, ASIC_CFG_THERM_POLL_EN);
1107 if (therm) {
1108 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0);
1109 msleep(100);
1110 dd_dev_info(dd, "%s: Disabled therm polling\n",
1111 __func__);
1112 }
1113
1114 retry:
1115 /* the SBus download will reset the spico for thermal */
1116
1117 /* step 3: download SBus Master firmware */
1118 /* step 4: download PCIe Gen3 SerDes firmware */
1119 dd_dev_info(dd, "%s: downloading firmware\n", __func__);
1120 ret = load_pcie_firmware(dd);
1121 if (ret) {
1122 /* do not proceed if the firmware cannot be downloaded */
1123 return_error = 1;
1124 goto done;
1125 }
1126
1127 /* step 5: set up device parameter settings */
1128 dd_dev_info(dd, "%s: setting PCIe registers\n", __func__);
1129
1130 /*
1131 * PcieCfgSpcie1 - Link Control 3
1132 * Leave at reset value. No need to set PerfEq - link equalization
1133 * will be performed automatically after the SBR when the target
1134 * speed is 8GT/s.
1135 */
1136
1137 /* clear all 16 per-lane error bits (PCIe: Lane Error Status) */
1138 pci_write_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, 0xffff);
1139
1140 /* step 5a: Set Synopsys Port Logic registers */
1141
1142 /*
1143 * PcieCfgRegPl2 - Port Force Link
1144 *
1145 * Set the low power field to 0x10 to avoid unnecessary power
1146 * management messages. All other fields are zero.
1147 */
1148 reg32 = 0x10ul << PCIE_CFG_REG_PL2_LOW_PWR_ENT_CNT_SHIFT;
1149 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL2, reg32);
1150
1151 /*
1152 * PcieCfgRegPl100 - Gen3 Control
1153 *
1154 * turn off PcieCfgRegPl100.Gen3ZRxDcNonCompl
1155 * turn on PcieCfgRegPl100.EqEieosCnt
1156 * Everything else zero.
1157 */
1158 reg32 = PCIE_CFG_REG_PL100_EQ_EIEOS_CNT_SMASK;
1159 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL100, reg32);
1160
1161 /*
1162 * PcieCfgRegPl101 - Gen3 EQ FS and LF
1163 * PcieCfgRegPl102 - Gen3 EQ Presets to Coefficients Mapping
1164 * PcieCfgRegPl103 - Gen3 EQ Preset Index
1165 * PcieCfgRegPl105 - Gen3 EQ Status
1166 *
1167 * Give initial EQ settings.
1168 */
1169 if (dd->pcidev->device == PCI_DEVICE_ID_INTEL0) { /* discrete */
1170 /* 1000mV, FS=24, LF = 8 */
1171 fs = 24;
1172 lf = 8;
1173 div = 3;
1174 eq = discrete_preliminary_eq;
1175 default_pset = DEFAULT_DISCRETE_PSET;
1176 ctle_tunings = discrete_ctle_tunings;
1177 /* bit 0 - discrete on/off */
1178 static_ctle_mode = pcie_ctle & 0x1;
1179 } else {
1180 /* 400mV, FS=29, LF = 9 */
1181 fs = 29;
1182 lf = 9;
1183 div = 1;
1184 eq = integrated_preliminary_eq;
1185 default_pset = DEFAULT_MCP_PSET;
1186 ctle_tunings = integrated_ctle_tunings;
1187 /* bit 1 - integrated on/off */
1188 static_ctle_mode = (pcie_ctle >> 1) & 0x1;
1189 }
1190 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL101,
1191 (fs <<
1192 PCIE_CFG_REG_PL101_GEN3_EQ_LOCAL_FS_SHIFT) |
1193 (lf <<
1194 PCIE_CFG_REG_PL101_GEN3_EQ_LOCAL_LF_SHIFT));
1195 ret = load_eq_table(dd, eq, fs, div);
1196 if (ret)
1197 goto done;
1198
1199 /*
1200 * PcieCfgRegPl106 - Gen3 EQ Control
1201 *
1202 * Set Gen3EqPsetReqVec, leave other fields 0.
1203 */
1204 if (pcie_pset == UNSET_PSET)
1205 pcie_pset = default_pset;
1206 if (pcie_pset > 10) { /* valid range is 0-10, inclusive */
1207 dd_dev_err(dd, "%s: Invalid Eq Pset %u, setting to %d\n",
1208 __func__, pcie_pset, default_pset);
1209 pcie_pset = default_pset;
1210 }
1211 dd_dev_info(dd, "%s: using EQ Pset %u\n", __func__, pcie_pset);
1212 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL106,
1213 ((1 << pcie_pset) <<
1214 PCIE_CFG_REG_PL106_GEN3_EQ_PSET_REQ_VEC_SHIFT) |
1215 PCIE_CFG_REG_PL106_GEN3_EQ_EVAL2MS_DISABLE_SMASK |
1216 PCIE_CFG_REG_PL106_GEN3_EQ_PHASE23_EXIT_MODE_SMASK);
1217
1218 /*
1219 * step 5b: Do post firmware download steps via SBus
1220 */
1221 dd_dev_info(dd, "%s: doing pcie post steps\n", __func__);
1222 pcie_post_steps(dd);
1223
1224 /*
1225 * step 5c: Program gasket interrupts
1226 */
1227 /* set the Rx Bit Rate to REFCLK ratio */
1228 write_gasket_interrupt(dd, intnum++, 0x0006, 0x0050);
1229 /* disable pCal for PCIe Gen3 RX equalization */
1230 /* select adaptive or static CTLE */
1231 write_gasket_interrupt(dd, intnum++, 0x0026,
1232 0x5b01 | (static_ctle_mode << 3));
1233 /*
1234 * Enable iCal for PCIe Gen3 RX equalization, and set which
1235 * evaluation of RX_EQ_EVAL will launch the iCal procedure.
1236 */
1237 write_gasket_interrupt(dd, intnum++, 0x0026, 0x5202);
1238
1239 if (static_ctle_mode) {
1240 /* apply static CTLE tunings */
1241 u8 pcie_dc, pcie_lf, pcie_hf, pcie_bw;
1242
1243 pcie_dc = ctle_tunings[pcie_pset][0];
1244 pcie_lf = ctle_tunings[pcie_pset][1];
1245 pcie_hf = ctle_tunings[pcie_pset][2];
1246 pcie_bw = ctle_tunings[pcie_pset][3];
1247 write_gasket_interrupt(dd, intnum++, 0x0026, 0x0200 | pcie_dc);
1248 write_gasket_interrupt(dd, intnum++, 0x0026, 0x0100 | pcie_lf);
1249 write_gasket_interrupt(dd, intnum++, 0x0026, 0x0000 | pcie_hf);
1250 write_gasket_interrupt(dd, intnum++, 0x0026, 0x5500 | pcie_bw);
1251 }
1252
1253 /* terminate list */
1254 write_gasket_interrupt(dd, intnum++, 0x0000, 0x0000);
1255
1256 /*
1257 * step 5d: program XMT margin
1258 */
1259 write_xmt_margin(dd, __func__);
1260
1261 /*
1262 * step 5e: disable active state power management (ASPM). It
1263 * will be enabled if required later
1264 */
1265 dd_dev_info(dd, "%s: clearing ASPM\n", __func__);
1266 aspm_hw_disable_l1(dd);
1267
1268 /*
1269 * step 5f: clear DirectSpeedChange
1270 * PcieCfgRegPl67.DirectSpeedChange must be zero to prevent the
1271 * change in the speed target from starting before we are ready.
1272 * This field defaults to 0 and we are not changing it, so nothing
1273 * needs to be done.
1274 */
1275
1276 /* step 5g: Set target link speed */
1277 /*
1278 * Set target link speed to be target on both device and parent.
1279 * On setting the parent: Some system BIOSs "helpfully" set the
1280 * parent target speed to Gen2 to match the ASIC's initial speed.
1281 * We can set the target Gen3 because we have already checked
1282 * that it is Gen3 capable earlier.
1283 */
1284 dd_dev_info(dd, "%s: setting parent target link speed\n", __func__);
1285 ret = pcie_capability_read_word(parent, PCI_EXP_LNKCTL2, &lnkctl2);
1286 if (ret) {
1287 dd_dev_err(dd, "Unable to read from PCI config\n");
1288 return_error = 1;
1289 goto done;
1290 }
1291
1292 dd_dev_info(dd, "%s: ..old link control2: 0x%x\n", __func__,
1293 (u32)lnkctl2);
1294 /* only write to parent if target is not as high as ours */
1295 if ((lnkctl2 & LNKCTL2_TARGET_LINK_SPEED_MASK) < target_vector) {
1296 lnkctl2 &= ~LNKCTL2_TARGET_LINK_SPEED_MASK;
1297 lnkctl2 |= target_vector;
1298 dd_dev_info(dd, "%s: ..new link control2: 0x%x\n", __func__,
1299 (u32)lnkctl2);
1300 ret = pcie_capability_write_word(parent,
1301 PCI_EXP_LNKCTL2, lnkctl2);
1302 if (ret) {
1303 dd_dev_err(dd, "Unable to write to PCI config\n");
1304 return_error = 1;
1305 goto done;
1306 }
1307 } else {
1308 dd_dev_info(dd, "%s: ..target speed is OK\n", __func__);
1309 }
1310
1311 dd_dev_info(dd, "%s: setting target link speed\n", __func__);
1312 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL2, &lnkctl2);
1313 if (ret) {
1314 dd_dev_err(dd, "Unable to read from PCI config\n");
1315 return_error = 1;
1316 goto done;
1317 }
1318
1319 dd_dev_info(dd, "%s: ..old link control2: 0x%x\n", __func__,
1320 (u32)lnkctl2);
1321 lnkctl2 &= ~LNKCTL2_TARGET_LINK_SPEED_MASK;
1322 lnkctl2 |= target_vector;
1323 dd_dev_info(dd, "%s: ..new link control2: 0x%x\n", __func__,
1324 (u32)lnkctl2);
1325 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL2, lnkctl2);
1326 if (ret) {
1327 dd_dev_err(dd, "Unable to write to PCI config\n");
1328 return_error = 1;
1329 goto done;
1330 }
1331
1332 /* step 5h: arm gasket logic */
1333 /* hold DC in reset across the SBR */
1334 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK);
1335 (void)read_csr(dd, CCE_DC_CTRL); /* DC reset hold */
1336 /* save firmware control across the SBR */
1337 fw_ctrl = read_csr(dd, MISC_CFG_FW_CTRL);
1338
1339 dd_dev_info(dd, "%s: arming gasket logic\n", __func__);
1340 arm_gasket_logic(dd);
1341
1342 /*
1343 * step 6: quiesce PCIe link
1344 * The chip has already been reset, so there will be no traffic
1345 * from the chip. Linux has no easy way to enforce that it will
1346 * not try to access the device, so we just need to hope it doesn't
1347 * do it while we are doing the reset.
1348 */
1349
1350 /*
1351 * step 7: initiate the secondary bus reset (SBR)
1352 * step 8: hardware brings the links back up
1353 * step 9: wait for link speed transition to be complete
1354 */
1355 dd_dev_info(dd, "%s: calling trigger_sbr\n", __func__);
1356 ret = trigger_sbr(dd);
1357 if (ret)
1358 goto done;
1359
1360 /* step 10: decide what to do next */
1361
1362 /* check if we can read PCI space */
1363 ret = pci_read_config_word(dd->pcidev, PCI_VENDOR_ID, &vendor);
1364 if (ret) {
1365 dd_dev_info(dd,
1366 "%s: read of VendorID failed after SBR, err %d\n",
1367 __func__, ret);
1368 return_error = 1;
1369 goto done;
1370 }
1371 if (vendor == 0xffff) {
1372 dd_dev_info(dd, "%s: VendorID is all 1s after SBR\n", __func__);
1373 return_error = 1;
1374 ret = -EIO;
1375 goto done;
1376 }
1377
1378 /* restore PCI space registers we know were reset */
1379 dd_dev_info(dd, "%s: calling restore_pci_variables\n", __func__);
1380 ret = restore_pci_variables(dd);
1381 if (ret) {
1382 dd_dev_err(dd, "%s: Could not restore PCI variables\n",
1383 __func__);
1384 return_error = 1;
1385 goto done;
1386 }
1387
1388 /* restore firmware control */
1389 write_csr(dd, MISC_CFG_FW_CTRL, fw_ctrl);
1390
1391 /*
1392 * Check the gasket block status.
1393 *
1394 * This is the first CSR read after the SBR. If the read returns
1395 * all 1s (fails), the link did not make it back.
1396 *
1397 * Once we're sure we can read and write, clear the DC reset after
1398 * the SBR. Then check for any per-lane errors. Then look over
1399 * the status.
1400 */
1401 reg = read_csr(dd, ASIC_PCIE_SD_HOST_STATUS);
1402 dd_dev_info(dd, "%s: gasket block status: 0x%llx\n", __func__, reg);
1403 if (reg == ~0ull) { /* PCIe read failed/timeout */
1404 dd_dev_err(dd, "SBR failed - unable to read from device\n");
1405 return_error = 1;
1406 ret = -ENOSYS;
1407 goto done;
1408 }
1409
1410 /* clear the DC reset */
1411 write_csr(dd, CCE_DC_CTRL, 0);
1412
1413 /* Set the LED off */
1414 setextled(dd, 0);
1415
1416 /* check for any per-lane errors */
1417 ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, &reg32);
1418 if (ret) {
1419 dd_dev_err(dd, "Unable to read from PCI config\n");
1420 return_error = 1;
1421 goto done;
1422 }
1423
1424 dd_dev_info(dd, "%s: per-lane errors: 0x%x\n", __func__, reg32);
1425
1426 /* extract status, look for our HFI */
1427 status = (reg >> ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_STS_SHIFT)
1428 & ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_STS_MASK;
1429 if ((status & (1 << dd->hfi1_id)) == 0) {
1430 dd_dev_err(dd,
1431 "%s: gasket status 0x%x, expecting 0x%x\n",
1432 __func__, status, 1 << dd->hfi1_id);
1433 ret = -EIO;
1434 goto done;
1435 }
1436
1437 /* extract error */
1438 err = (reg >> ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_ERR_SHIFT)
1439 & ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_ERR_MASK;
1440 if (err) {
1441 dd_dev_err(dd, "%s: gasket error %d\n", __func__, err);
1442 ret = -EIO;
1443 goto done;
1444 }
1445
1446 /* update our link information cache */
1447 update_lbus_info(dd);
1448 dd_dev_info(dd, "%s: new speed and width: %s\n", __func__,
1449 dd->lbus_info);
1450
1451 if (dd->lbus_speed != target_speed) { /* not target */
1452 /* maybe retry */
1453 do_retry = retry_count < pcie_retry;
1454 dd_dev_err(dd, "PCIe link speed did not switch to Gen%d%s\n",
1455 pcie_target, do_retry ? ", retrying" : "");
1456 retry_count++;
1457 if (do_retry) {
1458 msleep(100); /* allow time to settle */
1459 goto retry;
1460 }
1461 ret = -EIO;
1462 }
1463
1464 done:
1465 if (therm) {
1466 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1);
1467 msleep(100);
1468 dd_dev_info(dd, "%s: Re-enable therm polling\n",
1469 __func__);
1470 }
1471 release_chip_resource(dd, CR_SBUS);
1472 done_no_mutex:
1473 /* return no error if it is OK to be at current speed */
1474 if (ret && !return_error) {
1475 dd_dev_err(dd, "Proceeding at current speed PCIe speed\n");
1476 ret = 0;
1477 }
1478
1479 dd_dev_info(dd, "%s: done\n", __func__);
1480 return ret;
1481 }
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