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IB/hfi1: Fix context recovery when PBC has an UnsupportedVL
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1 /*
2 * Copyright(c) 2015-2017 Intel Corporation.
3 *
4 * This file is provided under a dual BSD/GPLv2 license. When using or
5 * redistributing this file, you may do so under either license.
6 *
7 * GPL LICENSE SUMMARY
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * BSD LICENSE
19 *
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions
22 * are met:
23 *
24 * - Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * - Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in
28 * the documentation and/or other materials provided with the
29 * distribution.
30 * - Neither the name of Intel Corporation nor the names of its
31 * contributors may be used to endorse or promote products derived
32 * from this software without specific prior written permission.
33 *
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 *
46 */
47
48 #include <linux/delay.h>
49 #include "hfi.h"
50 #include "qp.h"
51 #include "trace.h"
52
53 #define SC(name) SEND_CTXT_##name
54 /*
55 * Send Context functions
56 */
57 static void sc_wait_for_packet_egress(struct send_context *sc, int pause);
58
59 /*
60 * Set the CM reset bit and wait for it to clear. Use the provided
61 * sendctrl register. This routine has no locking.
62 */
63 void __cm_reset(struct hfi1_devdata *dd, u64 sendctrl)
64 {
65 write_csr(dd, SEND_CTRL, sendctrl | SEND_CTRL_CM_RESET_SMASK);
66 while (1) {
67 udelay(1);
68 sendctrl = read_csr(dd, SEND_CTRL);
69 if ((sendctrl & SEND_CTRL_CM_RESET_SMASK) == 0)
70 break;
71 }
72 }
73
74 /* defined in header release 48 and higher */
75 #ifndef SEND_CTRL_UNSUPPORTED_VL_SHIFT
76 #define SEND_CTRL_UNSUPPORTED_VL_SHIFT 3
77 #define SEND_CTRL_UNSUPPORTED_VL_MASK 0xffull
78 #define SEND_CTRL_UNSUPPORTED_VL_SMASK (SEND_CTRL_UNSUPPORTED_VL_MASK \
79 << SEND_CTRL_UNSUPPORTED_VL_SHIFT)
80 #endif
81
82 /* global control of PIO send */
83 void pio_send_control(struct hfi1_devdata *dd, int op)
84 {
85 u64 reg, mask;
86 unsigned long flags;
87 int write = 1; /* write sendctrl back */
88 int flush = 0; /* re-read sendctrl to make sure it is flushed */
89 int i;
90
91 spin_lock_irqsave(&dd->sendctrl_lock, flags);
92
93 reg = read_csr(dd, SEND_CTRL);
94 switch (op) {
95 case PSC_GLOBAL_ENABLE:
96 reg |= SEND_CTRL_SEND_ENABLE_SMASK;
97 /* Fall through */
98 case PSC_DATA_VL_ENABLE:
99 mask = 0;
100 for (i = 0; i < ARRAY_SIZE(dd->vld); i++)
101 if (!dd->vld[i].mtu)
102 mask |= BIT_ULL(i);
103 /* Disallow sending on VLs not enabled */
104 mask = (mask & SEND_CTRL_UNSUPPORTED_VL_MASK) <<
105 SEND_CTRL_UNSUPPORTED_VL_SHIFT;
106 reg = (reg & ~SEND_CTRL_UNSUPPORTED_VL_SMASK) | mask;
107 break;
108 case PSC_GLOBAL_DISABLE:
109 reg &= ~SEND_CTRL_SEND_ENABLE_SMASK;
110 break;
111 case PSC_GLOBAL_VLARB_ENABLE:
112 reg |= SEND_CTRL_VL_ARBITER_ENABLE_SMASK;
113 break;
114 case PSC_GLOBAL_VLARB_DISABLE:
115 reg &= ~SEND_CTRL_VL_ARBITER_ENABLE_SMASK;
116 break;
117 case PSC_CM_RESET:
118 __cm_reset(dd, reg);
119 write = 0; /* CSR already written (and flushed) */
120 break;
121 case PSC_DATA_VL_DISABLE:
122 reg |= SEND_CTRL_UNSUPPORTED_VL_SMASK;
123 flush = 1;
124 break;
125 default:
126 dd_dev_err(dd, "%s: invalid control %d\n", __func__, op);
127 break;
128 }
129
130 if (write) {
131 write_csr(dd, SEND_CTRL, reg);
132 if (flush)
133 (void)read_csr(dd, SEND_CTRL); /* flush write */
134 }
135
136 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
137 }
138
139 /* number of send context memory pools */
140 #define NUM_SC_POOLS 2
141
142 /* Send Context Size (SCS) wildcards */
143 #define SCS_POOL_0 -1
144 #define SCS_POOL_1 -2
145
146 /* Send Context Count (SCC) wildcards */
147 #define SCC_PER_VL -1
148 #define SCC_PER_CPU -2
149 #define SCC_PER_KRCVQ -3
150
151 /* Send Context Size (SCS) constants */
152 #define SCS_ACK_CREDITS 32
153 #define SCS_VL15_CREDITS 102 /* 3 pkts of 2048B data + 128B header */
154
155 #define PIO_THRESHOLD_CEILING 4096
156
157 #define PIO_WAIT_BATCH_SIZE 5
158
159 /* default send context sizes */
160 static struct sc_config_sizes sc_config_sizes[SC_MAX] = {
161 [SC_KERNEL] = { .size = SCS_POOL_0, /* even divide, pool 0 */
162 .count = SCC_PER_VL }, /* one per NUMA */
163 [SC_ACK] = { .size = SCS_ACK_CREDITS,
164 .count = SCC_PER_KRCVQ },
165 [SC_USER] = { .size = SCS_POOL_0, /* even divide, pool 0 */
166 .count = SCC_PER_CPU }, /* one per CPU */
167 [SC_VL15] = { .size = SCS_VL15_CREDITS,
168 .count = 1 },
169
170 };
171
172 /* send context memory pool configuration */
173 struct mem_pool_config {
174 int centipercent; /* % of memory, in 100ths of 1% */
175 int absolute_blocks; /* absolute block count */
176 };
177
178 /* default memory pool configuration: 100% in pool 0 */
179 static struct mem_pool_config sc_mem_pool_config[NUM_SC_POOLS] = {
180 /* centi%, abs blocks */
181 { 10000, -1 }, /* pool 0 */
182 { 0, -1 }, /* pool 1 */
183 };
184
185 /* memory pool information, used when calculating final sizes */
186 struct mem_pool_info {
187 int centipercent; /*
188 * 100th of 1% of memory to use, -1 if blocks
189 * already set
190 */
191 int count; /* count of contexts in the pool */
192 int blocks; /* block size of the pool */
193 int size; /* context size, in blocks */
194 };
195
196 /*
197 * Convert a pool wildcard to a valid pool index. The wildcards
198 * start at -1 and increase negatively. Map them as:
199 * -1 => 0
200 * -2 => 1
201 * etc.
202 *
203 * Return -1 on non-wildcard input, otherwise convert to a pool number.
204 */
205 static int wildcard_to_pool(int wc)
206 {
207 if (wc >= 0)
208 return -1; /* non-wildcard */
209 return -wc - 1;
210 }
211
212 static const char *sc_type_names[SC_MAX] = {
213 "kernel",
214 "ack",
215 "user",
216 "vl15"
217 };
218
219 static const char *sc_type_name(int index)
220 {
221 if (index < 0 || index >= SC_MAX)
222 return "unknown";
223 return sc_type_names[index];
224 }
225
226 /*
227 * Read the send context memory pool configuration and send context
228 * size configuration. Replace any wildcards and come up with final
229 * counts and sizes for the send context types.
230 */
231 int init_sc_pools_and_sizes(struct hfi1_devdata *dd)
232 {
233 struct mem_pool_info mem_pool_info[NUM_SC_POOLS] = { { 0 } };
234 int total_blocks = (dd->chip_pio_mem_size / PIO_BLOCK_SIZE) - 1;
235 int total_contexts = 0;
236 int fixed_blocks;
237 int pool_blocks;
238 int used_blocks;
239 int cp_total; /* centipercent total */
240 int ab_total; /* absolute block total */
241 int extra;
242 int i;
243
244 /*
245 * When SDMA is enabled, kernel context pio packet size is capped by
246 * "piothreshold". Reduce pio buffer allocation for kernel context by
247 * setting it to a fixed size. The allocation allows 3-deep buffering
248 * of the largest pio packets plus up to 128 bytes header, sufficient
249 * to maintain verbs performance.
250 *
251 * When SDMA is disabled, keep the default pooling allocation.
252 */
253 if (HFI1_CAP_IS_KSET(SDMA)) {
254 u16 max_pkt_size = (piothreshold < PIO_THRESHOLD_CEILING) ?
255 piothreshold : PIO_THRESHOLD_CEILING;
256 sc_config_sizes[SC_KERNEL].size =
257 3 * (max_pkt_size + 128) / PIO_BLOCK_SIZE;
258 }
259
260 /*
261 * Step 0:
262 * - copy the centipercents/absolute sizes from the pool config
263 * - sanity check these values
264 * - add up centipercents, then later check for full value
265 * - add up absolute blocks, then later check for over-commit
266 */
267 cp_total = 0;
268 ab_total = 0;
269 for (i = 0; i < NUM_SC_POOLS; i++) {
270 int cp = sc_mem_pool_config[i].centipercent;
271 int ab = sc_mem_pool_config[i].absolute_blocks;
272
273 /*
274 * A negative value is "unused" or "invalid". Both *can*
275 * be valid, but centipercent wins, so check that first
276 */
277 if (cp >= 0) { /* centipercent valid */
278 cp_total += cp;
279 } else if (ab >= 0) { /* absolute blocks valid */
280 ab_total += ab;
281 } else { /* neither valid */
282 dd_dev_err(
283 dd,
284 "Send context memory pool %d: both the block count and centipercent are invalid\n",
285 i);
286 return -EINVAL;
287 }
288
289 mem_pool_info[i].centipercent = cp;
290 mem_pool_info[i].blocks = ab;
291 }
292
293 /* do not use both % and absolute blocks for different pools */
294 if (cp_total != 0 && ab_total != 0) {
295 dd_dev_err(
296 dd,
297 "All send context memory pools must be described as either centipercent or blocks, no mixing between pools\n");
298 return -EINVAL;
299 }
300
301 /* if any percentages are present, they must add up to 100% x 100 */
302 if (cp_total != 0 && cp_total != 10000) {
303 dd_dev_err(
304 dd,
305 "Send context memory pool centipercent is %d, expecting 10000\n",
306 cp_total);
307 return -EINVAL;
308 }
309
310 /* the absolute pool total cannot be more than the mem total */
311 if (ab_total > total_blocks) {
312 dd_dev_err(
313 dd,
314 "Send context memory pool absolute block count %d is larger than the memory size %d\n",
315 ab_total, total_blocks);
316 return -EINVAL;
317 }
318
319 /*
320 * Step 2:
321 * - copy from the context size config
322 * - replace context type wildcard counts with real values
323 * - add up non-memory pool block sizes
324 * - add up memory pool user counts
325 */
326 fixed_blocks = 0;
327 for (i = 0; i < SC_MAX; i++) {
328 int count = sc_config_sizes[i].count;
329 int size = sc_config_sizes[i].size;
330 int pool;
331
332 /*
333 * Sanity check count: Either a positive value or
334 * one of the expected wildcards is valid. The positive
335 * value is checked later when we compare against total
336 * memory available.
337 */
338 if (i == SC_ACK) {
339 count = dd->n_krcv_queues;
340 } else if (i == SC_KERNEL) {
341 count = INIT_SC_PER_VL * num_vls;
342 } else if (count == SCC_PER_CPU) {
343 count = dd->num_rcv_contexts - dd->n_krcv_queues;
344 } else if (count < 0) {
345 dd_dev_err(
346 dd,
347 "%s send context invalid count wildcard %d\n",
348 sc_type_name(i), count);
349 return -EINVAL;
350 }
351 if (total_contexts + count > dd->chip_send_contexts)
352 count = dd->chip_send_contexts - total_contexts;
353
354 total_contexts += count;
355
356 /*
357 * Sanity check pool: The conversion will return a pool
358 * number or -1 if a fixed (non-negative) value. The fixed
359 * value is checked later when we compare against
360 * total memory available.
361 */
362 pool = wildcard_to_pool(size);
363 if (pool == -1) { /* non-wildcard */
364 fixed_blocks += size * count;
365 } else if (pool < NUM_SC_POOLS) { /* valid wildcard */
366 mem_pool_info[pool].count += count;
367 } else { /* invalid wildcard */
368 dd_dev_err(
369 dd,
370 "%s send context invalid pool wildcard %d\n",
371 sc_type_name(i), size);
372 return -EINVAL;
373 }
374
375 dd->sc_sizes[i].count = count;
376 dd->sc_sizes[i].size = size;
377 }
378 if (fixed_blocks > total_blocks) {
379 dd_dev_err(
380 dd,
381 "Send context fixed block count, %u, larger than total block count %u\n",
382 fixed_blocks, total_blocks);
383 return -EINVAL;
384 }
385
386 /* step 3: calculate the blocks in the pools, and pool context sizes */
387 pool_blocks = total_blocks - fixed_blocks;
388 if (ab_total > pool_blocks) {
389 dd_dev_err(
390 dd,
391 "Send context fixed pool sizes, %u, larger than pool block count %u\n",
392 ab_total, pool_blocks);
393 return -EINVAL;
394 }
395 /* subtract off the fixed pool blocks */
396 pool_blocks -= ab_total;
397
398 for (i = 0; i < NUM_SC_POOLS; i++) {
399 struct mem_pool_info *pi = &mem_pool_info[i];
400
401 /* % beats absolute blocks */
402 if (pi->centipercent >= 0)
403 pi->blocks = (pool_blocks * pi->centipercent) / 10000;
404
405 if (pi->blocks == 0 && pi->count != 0) {
406 dd_dev_err(
407 dd,
408 "Send context memory pool %d has %u contexts, but no blocks\n",
409 i, pi->count);
410 return -EINVAL;
411 }
412 if (pi->count == 0) {
413 /* warn about wasted blocks */
414 if (pi->blocks != 0)
415 dd_dev_err(
416 dd,
417 "Send context memory pool %d has %u blocks, but zero contexts\n",
418 i, pi->blocks);
419 pi->size = 0;
420 } else {
421 pi->size = pi->blocks / pi->count;
422 }
423 }
424
425 /* step 4: fill in the context type sizes from the pool sizes */
426 used_blocks = 0;
427 for (i = 0; i < SC_MAX; i++) {
428 if (dd->sc_sizes[i].size < 0) {
429 unsigned pool = wildcard_to_pool(dd->sc_sizes[i].size);
430
431 WARN_ON_ONCE(pool >= NUM_SC_POOLS);
432 dd->sc_sizes[i].size = mem_pool_info[pool].size;
433 }
434 /* make sure we are not larger than what is allowed by the HW */
435 #define PIO_MAX_BLOCKS 1024
436 if (dd->sc_sizes[i].size > PIO_MAX_BLOCKS)
437 dd->sc_sizes[i].size = PIO_MAX_BLOCKS;
438
439 /* calculate our total usage */
440 used_blocks += dd->sc_sizes[i].size * dd->sc_sizes[i].count;
441 }
442 extra = total_blocks - used_blocks;
443 if (extra != 0)
444 dd_dev_info(dd, "unused send context blocks: %d\n", extra);
445
446 return total_contexts;
447 }
448
449 int init_send_contexts(struct hfi1_devdata *dd)
450 {
451 u16 base;
452 int ret, i, j, context;
453
454 ret = init_credit_return(dd);
455 if (ret)
456 return ret;
457
458 dd->hw_to_sw = kmalloc_array(TXE_NUM_CONTEXTS, sizeof(u8),
459 GFP_KERNEL);
460 dd->send_contexts = kcalloc(dd->num_send_contexts,
461 sizeof(struct send_context_info),
462 GFP_KERNEL);
463 if (!dd->send_contexts || !dd->hw_to_sw) {
464 kfree(dd->hw_to_sw);
465 kfree(dd->send_contexts);
466 free_credit_return(dd);
467 return -ENOMEM;
468 }
469
470 /* hardware context map starts with invalid send context indices */
471 for (i = 0; i < TXE_NUM_CONTEXTS; i++)
472 dd->hw_to_sw[i] = INVALID_SCI;
473
474 /*
475 * All send contexts have their credit sizes. Allocate credits
476 * for each context one after another from the global space.
477 */
478 context = 0;
479 base = 1;
480 for (i = 0; i < SC_MAX; i++) {
481 struct sc_config_sizes *scs = &dd->sc_sizes[i];
482
483 for (j = 0; j < scs->count; j++) {
484 struct send_context_info *sci =
485 &dd->send_contexts[context];
486 sci->type = i;
487 sci->base = base;
488 sci->credits = scs->size;
489
490 context++;
491 base += scs->size;
492 }
493 }
494
495 return 0;
496 }
497
498 /*
499 * Allocate a software index and hardware context of the given type.
500 *
501 * Must be called with dd->sc_lock held.
502 */
503 static int sc_hw_alloc(struct hfi1_devdata *dd, int type, u32 *sw_index,
504 u32 *hw_context)
505 {
506 struct send_context_info *sci;
507 u32 index;
508 u32 context;
509
510 for (index = 0, sci = &dd->send_contexts[0];
511 index < dd->num_send_contexts; index++, sci++) {
512 if (sci->type == type && sci->allocated == 0) {
513 sci->allocated = 1;
514 /* use a 1:1 mapping, but make them non-equal */
515 context = dd->chip_send_contexts - index - 1;
516 dd->hw_to_sw[context] = index;
517 *sw_index = index;
518 *hw_context = context;
519 return 0; /* success */
520 }
521 }
522 dd_dev_err(dd, "Unable to locate a free type %d send context\n", type);
523 return -ENOSPC;
524 }
525
526 /*
527 * Free the send context given by its software index.
528 *
529 * Must be called with dd->sc_lock held.
530 */
531 static void sc_hw_free(struct hfi1_devdata *dd, u32 sw_index, u32 hw_context)
532 {
533 struct send_context_info *sci;
534
535 sci = &dd->send_contexts[sw_index];
536 if (!sci->allocated) {
537 dd_dev_err(dd, "%s: sw_index %u not allocated? hw_context %u\n",
538 __func__, sw_index, hw_context);
539 }
540 sci->allocated = 0;
541 dd->hw_to_sw[hw_context] = INVALID_SCI;
542 }
543
544 /* return the base context of a context in a group */
545 static inline u32 group_context(u32 context, u32 group)
546 {
547 return (context >> group) << group;
548 }
549
550 /* return the size of a group */
551 static inline u32 group_size(u32 group)
552 {
553 return 1 << group;
554 }
555
556 /*
557 * Obtain the credit return addresses, kernel virtual and bus, for the
558 * given sc.
559 *
560 * To understand this routine:
561 * o va and dma are arrays of struct credit_return. One for each physical
562 * send context, per NUMA.
563 * o Each send context always looks in its relative location in a struct
564 * credit_return for its credit return.
565 * o Each send context in a group must have its return address CSR programmed
566 * with the same value. Use the address of the first send context in the
567 * group.
568 */
569 static void cr_group_addresses(struct send_context *sc, dma_addr_t *dma)
570 {
571 u32 gc = group_context(sc->hw_context, sc->group);
572 u32 index = sc->hw_context & 0x7;
573
574 sc->hw_free = &sc->dd->cr_base[sc->node].va[gc].cr[index];
575 *dma = (unsigned long)
576 &((struct credit_return *)sc->dd->cr_base[sc->node].dma)[gc];
577 }
578
579 /*
580 * Work queue function triggered in error interrupt routine for
581 * kernel contexts.
582 */
583 static void sc_halted(struct work_struct *work)
584 {
585 struct send_context *sc;
586
587 sc = container_of(work, struct send_context, halt_work);
588 sc_restart(sc);
589 }
590
591 /*
592 * Calculate PIO block threshold for this send context using the given MTU.
593 * Trigger a return when one MTU plus optional header of credits remain.
594 *
595 * Parameter mtu is in bytes.
596 * Parameter hdrqentsize is in DWORDs.
597 *
598 * Return value is what to write into the CSR: trigger return when
599 * unreturned credits pass this count.
600 */
601 u32 sc_mtu_to_threshold(struct send_context *sc, u32 mtu, u32 hdrqentsize)
602 {
603 u32 release_credits;
604 u32 threshold;
605
606 /* add in the header size, then divide by the PIO block size */
607 mtu += hdrqentsize << 2;
608 release_credits = DIV_ROUND_UP(mtu, PIO_BLOCK_SIZE);
609
610 /* check against this context's credits */
611 if (sc->credits <= release_credits)
612 threshold = 1;
613 else
614 threshold = sc->credits - release_credits;
615
616 return threshold;
617 }
618
619 /*
620 * Calculate credit threshold in terms of percent of the allocated credits.
621 * Trigger when unreturned credits equal or exceed the percentage of the whole.
622 *
623 * Return value is what to write into the CSR: trigger return when
624 * unreturned credits pass this count.
625 */
626 u32 sc_percent_to_threshold(struct send_context *sc, u32 percent)
627 {
628 return (sc->credits * percent) / 100;
629 }
630
631 /*
632 * Set the credit return threshold.
633 */
634 void sc_set_cr_threshold(struct send_context *sc, u32 new_threshold)
635 {
636 unsigned long flags;
637 u32 old_threshold;
638 int force_return = 0;
639
640 spin_lock_irqsave(&sc->credit_ctrl_lock, flags);
641
642 old_threshold = (sc->credit_ctrl >>
643 SC(CREDIT_CTRL_THRESHOLD_SHIFT))
644 & SC(CREDIT_CTRL_THRESHOLD_MASK);
645
646 if (new_threshold != old_threshold) {
647 sc->credit_ctrl =
648 (sc->credit_ctrl
649 & ~SC(CREDIT_CTRL_THRESHOLD_SMASK))
650 | ((new_threshold
651 & SC(CREDIT_CTRL_THRESHOLD_MASK))
652 << SC(CREDIT_CTRL_THRESHOLD_SHIFT));
653 write_kctxt_csr(sc->dd, sc->hw_context,
654 SC(CREDIT_CTRL), sc->credit_ctrl);
655
656 /* force a credit return on change to avoid a possible stall */
657 force_return = 1;
658 }
659
660 spin_unlock_irqrestore(&sc->credit_ctrl_lock, flags);
661
662 if (force_return)
663 sc_return_credits(sc);
664 }
665
666 /*
667 * set_pio_integrity
668 *
669 * Set the CHECK_ENABLE register for the send context 'sc'.
670 */
671 void set_pio_integrity(struct send_context *sc)
672 {
673 struct hfi1_devdata *dd = sc->dd;
674 u32 hw_context = sc->hw_context;
675 int type = sc->type;
676
677 write_kctxt_csr(dd, hw_context,
678 SC(CHECK_ENABLE),
679 hfi1_pkt_default_send_ctxt_mask(dd, type));
680 }
681
682 static u32 get_buffers_allocated(struct send_context *sc)
683 {
684 int cpu;
685 u32 ret = 0;
686
687 for_each_possible_cpu(cpu)
688 ret += *per_cpu_ptr(sc->buffers_allocated, cpu);
689 return ret;
690 }
691
692 static void reset_buffers_allocated(struct send_context *sc)
693 {
694 int cpu;
695
696 for_each_possible_cpu(cpu)
697 (*per_cpu_ptr(sc->buffers_allocated, cpu)) = 0;
698 }
699
700 /*
701 * Allocate a NUMA relative send context structure of the given type along
702 * with a HW context.
703 */
704 struct send_context *sc_alloc(struct hfi1_devdata *dd, int type,
705 uint hdrqentsize, int numa)
706 {
707 struct send_context_info *sci;
708 struct send_context *sc = NULL;
709 dma_addr_t dma;
710 unsigned long flags;
711 u64 reg;
712 u32 thresh;
713 u32 sw_index;
714 u32 hw_context;
715 int ret;
716 u8 opval, opmask;
717
718 /* do not allocate while frozen */
719 if (dd->flags & HFI1_FROZEN)
720 return NULL;
721
722 sc = kzalloc_node(sizeof(*sc), GFP_KERNEL, numa);
723 if (!sc)
724 return NULL;
725
726 sc->buffers_allocated = alloc_percpu(u32);
727 if (!sc->buffers_allocated) {
728 kfree(sc);
729 dd_dev_err(dd,
730 "Cannot allocate buffers_allocated per cpu counters\n"
731 );
732 return NULL;
733 }
734
735 spin_lock_irqsave(&dd->sc_lock, flags);
736 ret = sc_hw_alloc(dd, type, &sw_index, &hw_context);
737 if (ret) {
738 spin_unlock_irqrestore(&dd->sc_lock, flags);
739 free_percpu(sc->buffers_allocated);
740 kfree(sc);
741 return NULL;
742 }
743
744 sci = &dd->send_contexts[sw_index];
745 sci->sc = sc;
746
747 sc->dd = dd;
748 sc->node = numa;
749 sc->type = type;
750 spin_lock_init(&sc->alloc_lock);
751 spin_lock_init(&sc->release_lock);
752 spin_lock_init(&sc->credit_ctrl_lock);
753 INIT_LIST_HEAD(&sc->piowait);
754 INIT_WORK(&sc->halt_work, sc_halted);
755 init_waitqueue_head(&sc->halt_wait);
756
757 /* grouping is always single context for now */
758 sc->group = 0;
759
760 sc->sw_index = sw_index;
761 sc->hw_context = hw_context;
762 cr_group_addresses(sc, &dma);
763 sc->credits = sci->credits;
764 sc->size = sc->credits * PIO_BLOCK_SIZE;
765
766 /* PIO Send Memory Address details */
767 #define PIO_ADDR_CONTEXT_MASK 0xfful
768 #define PIO_ADDR_CONTEXT_SHIFT 16
769 sc->base_addr = dd->piobase + ((hw_context & PIO_ADDR_CONTEXT_MASK)
770 << PIO_ADDR_CONTEXT_SHIFT);
771
772 /* set base and credits */
773 reg = ((sci->credits & SC(CTRL_CTXT_DEPTH_MASK))
774 << SC(CTRL_CTXT_DEPTH_SHIFT))
775 | ((sci->base & SC(CTRL_CTXT_BASE_MASK))
776 << SC(CTRL_CTXT_BASE_SHIFT));
777 write_kctxt_csr(dd, hw_context, SC(CTRL), reg);
778
779 set_pio_integrity(sc);
780
781 /* unmask all errors */
782 write_kctxt_csr(dd, hw_context, SC(ERR_MASK), (u64)-1);
783
784 /* set the default partition key */
785 write_kctxt_csr(dd, hw_context, SC(CHECK_PARTITION_KEY),
786 (SC(CHECK_PARTITION_KEY_VALUE_MASK) &
787 DEFAULT_PKEY) <<
788 SC(CHECK_PARTITION_KEY_VALUE_SHIFT));
789
790 /* per context type checks */
791 if (type == SC_USER) {
792 opval = USER_OPCODE_CHECK_VAL;
793 opmask = USER_OPCODE_CHECK_MASK;
794 } else {
795 opval = OPCODE_CHECK_VAL_DISABLED;
796 opmask = OPCODE_CHECK_MASK_DISABLED;
797 }
798
799 /* set the send context check opcode mask and value */
800 write_kctxt_csr(dd, hw_context, SC(CHECK_OPCODE),
801 ((u64)opmask << SC(CHECK_OPCODE_MASK_SHIFT)) |
802 ((u64)opval << SC(CHECK_OPCODE_VALUE_SHIFT)));
803
804 /* set up credit return */
805 reg = dma & SC(CREDIT_RETURN_ADDR_ADDRESS_SMASK);
806 write_kctxt_csr(dd, hw_context, SC(CREDIT_RETURN_ADDR), reg);
807
808 /*
809 * Calculate the initial credit return threshold.
810 *
811 * For Ack contexts, set a threshold for half the credits.
812 * For User contexts use the given percentage. This has been
813 * sanitized on driver start-up.
814 * For Kernel contexts, use the default MTU plus a header
815 * or half the credits, whichever is smaller. This should
816 * work for both the 3-deep buffering allocation and the
817 * pooling allocation.
818 */
819 if (type == SC_ACK) {
820 thresh = sc_percent_to_threshold(sc, 50);
821 } else if (type == SC_USER) {
822 thresh = sc_percent_to_threshold(sc,
823 user_credit_return_threshold);
824 } else { /* kernel */
825 thresh = min(sc_percent_to_threshold(sc, 50),
826 sc_mtu_to_threshold(sc, hfi1_max_mtu,
827 hdrqentsize));
828 }
829 reg = thresh << SC(CREDIT_CTRL_THRESHOLD_SHIFT);
830 /* add in early return */
831 if (type == SC_USER && HFI1_CAP_IS_USET(EARLY_CREDIT_RETURN))
832 reg |= SC(CREDIT_CTRL_EARLY_RETURN_SMASK);
833 else if (HFI1_CAP_IS_KSET(EARLY_CREDIT_RETURN)) /* kernel, ack */
834 reg |= SC(CREDIT_CTRL_EARLY_RETURN_SMASK);
835
836 /* set up write-through credit_ctrl */
837 sc->credit_ctrl = reg;
838 write_kctxt_csr(dd, hw_context, SC(CREDIT_CTRL), reg);
839
840 /* User send contexts should not allow sending on VL15 */
841 if (type == SC_USER) {
842 reg = 1ULL << 15;
843 write_kctxt_csr(dd, hw_context, SC(CHECK_VL), reg);
844 }
845
846 spin_unlock_irqrestore(&dd->sc_lock, flags);
847
848 /*
849 * Allocate shadow ring to track outstanding PIO buffers _after_
850 * unlocking. We don't know the size until the lock is held and
851 * we can't allocate while the lock is held. No one is using
852 * the context yet, so allocate it now.
853 *
854 * User contexts do not get a shadow ring.
855 */
856 if (type != SC_USER) {
857 /*
858 * Size the shadow ring 1 larger than the number of credits
859 * so head == tail can mean empty.
860 */
861 sc->sr_size = sci->credits + 1;
862 sc->sr = kzalloc_node(sizeof(union pio_shadow_ring) *
863 sc->sr_size, GFP_KERNEL, numa);
864 if (!sc->sr) {
865 sc_free(sc);
866 return NULL;
867 }
868 }
869
870 hfi1_cdbg(PIO,
871 "Send context %u(%u) %s group %u credits %u credit_ctrl 0x%llx threshold %u\n",
872 sw_index,
873 hw_context,
874 sc_type_name(type),
875 sc->group,
876 sc->credits,
877 sc->credit_ctrl,
878 thresh);
879
880 return sc;
881 }
882
883 /* free a per-NUMA send context structure */
884 void sc_free(struct send_context *sc)
885 {
886 struct hfi1_devdata *dd;
887 unsigned long flags;
888 u32 sw_index;
889 u32 hw_context;
890
891 if (!sc)
892 return;
893
894 sc->flags |= SCF_IN_FREE; /* ensure no restarts */
895 dd = sc->dd;
896 if (!list_empty(&sc->piowait))
897 dd_dev_err(dd, "piowait list not empty!\n");
898 sw_index = sc->sw_index;
899 hw_context = sc->hw_context;
900 sc_disable(sc); /* make sure the HW is disabled */
901 flush_work(&sc->halt_work);
902
903 spin_lock_irqsave(&dd->sc_lock, flags);
904 dd->send_contexts[sw_index].sc = NULL;
905
906 /* clear/disable all registers set in sc_alloc */
907 write_kctxt_csr(dd, hw_context, SC(CTRL), 0);
908 write_kctxt_csr(dd, hw_context, SC(CHECK_ENABLE), 0);
909 write_kctxt_csr(dd, hw_context, SC(ERR_MASK), 0);
910 write_kctxt_csr(dd, hw_context, SC(CHECK_PARTITION_KEY), 0);
911 write_kctxt_csr(dd, hw_context, SC(CHECK_OPCODE), 0);
912 write_kctxt_csr(dd, hw_context, SC(CREDIT_RETURN_ADDR), 0);
913 write_kctxt_csr(dd, hw_context, SC(CREDIT_CTRL), 0);
914
915 /* release the index and context for re-use */
916 sc_hw_free(dd, sw_index, hw_context);
917 spin_unlock_irqrestore(&dd->sc_lock, flags);
918
919 kfree(sc->sr);
920 free_percpu(sc->buffers_allocated);
921 kfree(sc);
922 }
923
924 /* disable the context */
925 void sc_disable(struct send_context *sc)
926 {
927 u64 reg;
928 unsigned long flags;
929 struct pio_buf *pbuf;
930
931 if (!sc)
932 return;
933
934 /* do all steps, even if already disabled */
935 spin_lock_irqsave(&sc->alloc_lock, flags);
936 reg = read_kctxt_csr(sc->dd, sc->hw_context, SC(CTRL));
937 reg &= ~SC(CTRL_CTXT_ENABLE_SMASK);
938 sc->flags &= ~SCF_ENABLED;
939 sc_wait_for_packet_egress(sc, 1);
940 write_kctxt_csr(sc->dd, sc->hw_context, SC(CTRL), reg);
941 spin_unlock_irqrestore(&sc->alloc_lock, flags);
942
943 /*
944 * Flush any waiters. Once the context is disabled,
945 * credit return interrupts are stopped (although there
946 * could be one in-process when the context is disabled).
947 * Wait one microsecond for any lingering interrupts, then
948 * proceed with the flush.
949 */
950 udelay(1);
951 spin_lock_irqsave(&sc->release_lock, flags);
952 if (sc->sr) { /* this context has a shadow ring */
953 while (sc->sr_tail != sc->sr_head) {
954 pbuf = &sc->sr[sc->sr_tail].pbuf;
955 if (pbuf->cb)
956 (*pbuf->cb)(pbuf->arg, PRC_SC_DISABLE);
957 sc->sr_tail++;
958 if (sc->sr_tail >= sc->sr_size)
959 sc->sr_tail = 0;
960 }
961 }
962 spin_unlock_irqrestore(&sc->release_lock, flags);
963 }
964
965 /* return SendEgressCtxtStatus.PacketOccupancy */
966 static u64 packet_occupancy(u64 reg)
967 {
968 return (reg &
969 SEND_EGRESS_CTXT_STATUS_CTXT_EGRESS_PACKET_OCCUPANCY_SMASK)
970 >> SEND_EGRESS_CTXT_STATUS_CTXT_EGRESS_PACKET_OCCUPANCY_SHIFT;
971 }
972
973 /* is egress halted on the context? */
974 static bool egress_halted(u64 reg)
975 {
976 return !!(reg & SEND_EGRESS_CTXT_STATUS_CTXT_EGRESS_HALT_STATUS_SMASK);
977 }
978
979 /* is the send context halted? */
980 static bool is_sc_halted(struct hfi1_devdata *dd, u32 hw_context)
981 {
982 return !!(read_kctxt_csr(dd, hw_context, SC(STATUS)) &
983 SC(STATUS_CTXT_HALTED_SMASK));
984 }
985
986 /**
987 * sc_wait_for_packet_egress
988 * @sc: valid send context
989 * @pause: wait for credit return
990 *
991 * Wait for packet egress, optionally pause for credit return
992 *
993 * Egress halt and Context halt are not necessarily the same thing, so
994 * check for both.
995 *
996 * NOTE: The context halt bit may not be set immediately. Because of this,
997 * it is necessary to check the SW SFC_HALTED bit (set in the IRQ) and the HW
998 * context bit to determine if the context is halted.
999 */
1000 static void sc_wait_for_packet_egress(struct send_context *sc, int pause)
1001 {
1002 struct hfi1_devdata *dd = sc->dd;
1003 u64 reg = 0;
1004 u64 reg_prev;
1005 u32 loop = 0;
1006
1007 while (1) {
1008 reg_prev = reg;
1009 reg = read_csr(dd, sc->hw_context * 8 +
1010 SEND_EGRESS_CTXT_STATUS);
1011 /* done if any halt bits, SW or HW are set */
1012 if (sc->flags & SCF_HALTED ||
1013 is_sc_halted(dd, sc->hw_context) || egress_halted(reg))
1014 break;
1015 reg = packet_occupancy(reg);
1016 if (reg == 0)
1017 break;
1018 /* counter is reset if occupancy count changes */
1019 if (reg != reg_prev)
1020 loop = 0;
1021 if (loop > 50000) {
1022 /* timed out - bounce the link */
1023 dd_dev_err(dd,
1024 "%s: context %u(%u) timeout waiting for packets to egress, remaining count %u, bouncing link\n",
1025 __func__, sc->sw_index,
1026 sc->hw_context, (u32)reg);
1027 queue_work(dd->pport->link_wq,
1028 &dd->pport->link_bounce_work);
1029 break;
1030 }
1031 loop++;
1032 udelay(1);
1033 }
1034
1035 if (pause)
1036 /* Add additional delay to ensure chip returns all credits */
1037 pause_for_credit_return(dd);
1038 }
1039
1040 void sc_wait(struct hfi1_devdata *dd)
1041 {
1042 int i;
1043
1044 for (i = 0; i < dd->num_send_contexts; i++) {
1045 struct send_context *sc = dd->send_contexts[i].sc;
1046
1047 if (!sc)
1048 continue;
1049 sc_wait_for_packet_egress(sc, 0);
1050 }
1051 }
1052
1053 /*
1054 * Restart a context after it has been halted due to error.
1055 *
1056 * If the first step fails - wait for the halt to be asserted, return early.
1057 * Otherwise complain about timeouts but keep going.
1058 *
1059 * It is expected that allocations (enabled flag bit) have been shut off
1060 * already (only applies to kernel contexts).
1061 */
1062 int sc_restart(struct send_context *sc)
1063 {
1064 struct hfi1_devdata *dd = sc->dd;
1065 u64 reg;
1066 u32 loop;
1067 int count;
1068
1069 /* bounce off if not halted, or being free'd */
1070 if (!(sc->flags & SCF_HALTED) || (sc->flags & SCF_IN_FREE))
1071 return -EINVAL;
1072
1073 dd_dev_info(dd, "restarting send context %u(%u)\n", sc->sw_index,
1074 sc->hw_context);
1075
1076 /*
1077 * Step 1: Wait for the context to actually halt.
1078 *
1079 * The error interrupt is asynchronous to actually setting halt
1080 * on the context.
1081 */
1082 loop = 0;
1083 while (1) {
1084 reg = read_kctxt_csr(dd, sc->hw_context, SC(STATUS));
1085 if (reg & SC(STATUS_CTXT_HALTED_SMASK))
1086 break;
1087 if (loop > 100) {
1088 dd_dev_err(dd, "%s: context %u(%u) not halting, skipping\n",
1089 __func__, sc->sw_index, sc->hw_context);
1090 return -ETIME;
1091 }
1092 loop++;
1093 udelay(1);
1094 }
1095
1096 /*
1097 * Step 2: Ensure no users are still trying to write to PIO.
1098 *
1099 * For kernel contexts, we have already turned off buffer allocation.
1100 * Now wait for the buffer count to go to zero.
1101 *
1102 * For user contexts, the user handling code has cut off write access
1103 * to the context's PIO pages before calling this routine and will
1104 * restore write access after this routine returns.
1105 */
1106 if (sc->type != SC_USER) {
1107 /* kernel context */
1108 loop = 0;
1109 while (1) {
1110 count = get_buffers_allocated(sc);
1111 if (count == 0)
1112 break;
1113 if (loop > 100) {
1114 dd_dev_err(dd,
1115 "%s: context %u(%u) timeout waiting for PIO buffers to zero, remaining %d\n",
1116 __func__, sc->sw_index,
1117 sc->hw_context, count);
1118 }
1119 loop++;
1120 udelay(1);
1121 }
1122 }
1123
1124 /*
1125 * Step 3: Wait for all packets to egress.
1126 * This is done while disabling the send context
1127 *
1128 * Step 4: Disable the context
1129 *
1130 * This is a superset of the halt. After the disable, the
1131 * errors can be cleared.
1132 */
1133 sc_disable(sc);
1134
1135 /*
1136 * Step 5: Enable the context
1137 *
1138 * This enable will clear the halted flag and per-send context
1139 * error flags.
1140 */
1141 return sc_enable(sc);
1142 }
1143
1144 /*
1145 * PIO freeze processing. To be called after the TXE block is fully frozen.
1146 * Go through all frozen send contexts and disable them. The contexts are
1147 * already stopped by the freeze.
1148 */
1149 void pio_freeze(struct hfi1_devdata *dd)
1150 {
1151 struct send_context *sc;
1152 int i;
1153
1154 for (i = 0; i < dd->num_send_contexts; i++) {
1155 sc = dd->send_contexts[i].sc;
1156 /*
1157 * Don't disable unallocated, unfrozen, or user send contexts.
1158 * User send contexts will be disabled when the process
1159 * calls into the driver to reset its context.
1160 */
1161 if (!sc || !(sc->flags & SCF_FROZEN) || sc->type == SC_USER)
1162 continue;
1163
1164 /* only need to disable, the context is already stopped */
1165 sc_disable(sc);
1166 }
1167 }
1168
1169 /*
1170 * Unfreeze PIO for kernel send contexts. The precondition for calling this
1171 * is that all PIO send contexts have been disabled and the SPC freeze has
1172 * been cleared. Now perform the last step and re-enable each kernel context.
1173 * User (PSM) processing will occur when PSM calls into the kernel to
1174 * acknowledge the freeze.
1175 */
1176 void pio_kernel_unfreeze(struct hfi1_devdata *dd)
1177 {
1178 struct send_context *sc;
1179 int i;
1180
1181 for (i = 0; i < dd->num_send_contexts; i++) {
1182 sc = dd->send_contexts[i].sc;
1183 if (!sc || !(sc->flags & SCF_FROZEN) || sc->type == SC_USER)
1184 continue;
1185
1186 sc_enable(sc); /* will clear the sc frozen flag */
1187 }
1188 }
1189
1190 /*
1191 * Wait for the SendPioInitCtxt.PioInitInProgress bit to clear.
1192 * Returns:
1193 * -ETIMEDOUT - if we wait too long
1194 * -EIO - if there was an error
1195 */
1196 static int pio_init_wait_progress(struct hfi1_devdata *dd)
1197 {
1198 u64 reg;
1199 int max, count = 0;
1200
1201 /* max is the longest possible HW init time / delay */
1202 max = (dd->icode == ICODE_FPGA_EMULATION) ? 120 : 5;
1203 while (1) {
1204 reg = read_csr(dd, SEND_PIO_INIT_CTXT);
1205 if (!(reg & SEND_PIO_INIT_CTXT_PIO_INIT_IN_PROGRESS_SMASK))
1206 break;
1207 if (count >= max)
1208 return -ETIMEDOUT;
1209 udelay(5);
1210 count++;
1211 }
1212
1213 return reg & SEND_PIO_INIT_CTXT_PIO_INIT_ERR_SMASK ? -EIO : 0;
1214 }
1215
1216 /*
1217 * Reset all of the send contexts to their power-on state. Used
1218 * only during manual init - no lock against sc_enable needed.
1219 */
1220 void pio_reset_all(struct hfi1_devdata *dd)
1221 {
1222 int ret;
1223
1224 /* make sure the init engine is not busy */
1225 ret = pio_init_wait_progress(dd);
1226 /* ignore any timeout */
1227 if (ret == -EIO) {
1228 /* clear the error */
1229 write_csr(dd, SEND_PIO_ERR_CLEAR,
1230 SEND_PIO_ERR_CLEAR_PIO_INIT_SM_IN_ERR_SMASK);
1231 }
1232
1233 /* reset init all */
1234 write_csr(dd, SEND_PIO_INIT_CTXT,
1235 SEND_PIO_INIT_CTXT_PIO_ALL_CTXT_INIT_SMASK);
1236 udelay(2);
1237 ret = pio_init_wait_progress(dd);
1238 if (ret < 0) {
1239 dd_dev_err(dd,
1240 "PIO send context init %s while initializing all PIO blocks\n",
1241 ret == -ETIMEDOUT ? "is stuck" : "had an error");
1242 }
1243 }
1244
1245 /* enable the context */
1246 int sc_enable(struct send_context *sc)
1247 {
1248 u64 sc_ctrl, reg, pio;
1249 struct hfi1_devdata *dd;
1250 unsigned long flags;
1251 int ret = 0;
1252
1253 if (!sc)
1254 return -EINVAL;
1255 dd = sc->dd;
1256
1257 /*
1258 * Obtain the allocator lock to guard against any allocation
1259 * attempts (which should not happen prior to context being
1260 * enabled). On the release/disable side we don't need to
1261 * worry about locking since the releaser will not do anything
1262 * if the context accounting values have not changed.
1263 */
1264 spin_lock_irqsave(&sc->alloc_lock, flags);
1265 sc_ctrl = read_kctxt_csr(dd, sc->hw_context, SC(CTRL));
1266 if ((sc_ctrl & SC(CTRL_CTXT_ENABLE_SMASK)))
1267 goto unlock; /* already enabled */
1268
1269 /* IMPORTANT: only clear free and fill if transitioning 0 -> 1 */
1270
1271 *sc->hw_free = 0;
1272 sc->free = 0;
1273 sc->alloc_free = 0;
1274 sc->fill = 0;
1275 sc->fill_wrap = 0;
1276 sc->sr_head = 0;
1277 sc->sr_tail = 0;
1278 sc->flags = 0;
1279 /* the alloc lock insures no fast path allocation */
1280 reset_buffers_allocated(sc);
1281
1282 /*
1283 * Clear all per-context errors. Some of these will be set when
1284 * we are re-enabling after a context halt. Now that the context
1285 * is disabled, the halt will not clear until after the PIO init
1286 * engine runs below.
1287 */
1288 reg = read_kctxt_csr(dd, sc->hw_context, SC(ERR_STATUS));
1289 if (reg)
1290 write_kctxt_csr(dd, sc->hw_context, SC(ERR_CLEAR), reg);
1291
1292 /*
1293 * The HW PIO initialization engine can handle only one init
1294 * request at a time. Serialize access to each device's engine.
1295 */
1296 spin_lock(&dd->sc_init_lock);
1297 /*
1298 * Since access to this code block is serialized and
1299 * each access waits for the initialization to complete
1300 * before releasing the lock, the PIO initialization engine
1301 * should not be in use, so we don't have to wait for the
1302 * InProgress bit to go down.
1303 */
1304 pio = ((sc->hw_context & SEND_PIO_INIT_CTXT_PIO_CTXT_NUM_MASK) <<
1305 SEND_PIO_INIT_CTXT_PIO_CTXT_NUM_SHIFT) |
1306 SEND_PIO_INIT_CTXT_PIO_SINGLE_CTXT_INIT_SMASK;
1307 write_csr(dd, SEND_PIO_INIT_CTXT, pio);
1308 /*
1309 * Wait until the engine is done. Give the chip the required time
1310 * so, hopefully, we read the register just once.
1311 */
1312 udelay(2);
1313 ret = pio_init_wait_progress(dd);
1314 spin_unlock(&dd->sc_init_lock);
1315 if (ret) {
1316 dd_dev_err(dd,
1317 "sctxt%u(%u): Context not enabled due to init failure %d\n",
1318 sc->sw_index, sc->hw_context, ret);
1319 goto unlock;
1320 }
1321
1322 /*
1323 * All is well. Enable the context.
1324 */
1325 sc_ctrl |= SC(CTRL_CTXT_ENABLE_SMASK);
1326 write_kctxt_csr(dd, sc->hw_context, SC(CTRL), sc_ctrl);
1327 /*
1328 * Read SendCtxtCtrl to force the write out and prevent a timing
1329 * hazard where a PIO write may reach the context before the enable.
1330 */
1331 read_kctxt_csr(dd, sc->hw_context, SC(CTRL));
1332 sc->flags |= SCF_ENABLED;
1333
1334 unlock:
1335 spin_unlock_irqrestore(&sc->alloc_lock, flags);
1336
1337 return ret;
1338 }
1339
1340 /* force a credit return on the context */
1341 void sc_return_credits(struct send_context *sc)
1342 {
1343 if (!sc)
1344 return;
1345
1346 /* a 0->1 transition schedules a credit return */
1347 write_kctxt_csr(sc->dd, sc->hw_context, SC(CREDIT_FORCE),
1348 SC(CREDIT_FORCE_FORCE_RETURN_SMASK));
1349 /*
1350 * Ensure that the write is flushed and the credit return is
1351 * scheduled. We care more about the 0 -> 1 transition.
1352 */
1353 read_kctxt_csr(sc->dd, sc->hw_context, SC(CREDIT_FORCE));
1354 /* set back to 0 for next time */
1355 write_kctxt_csr(sc->dd, sc->hw_context, SC(CREDIT_FORCE), 0);
1356 }
1357
1358 /* allow all in-flight packets to drain on the context */
1359 void sc_flush(struct send_context *sc)
1360 {
1361 if (!sc)
1362 return;
1363
1364 sc_wait_for_packet_egress(sc, 1);
1365 }
1366
1367 /* drop all packets on the context, no waiting until they are sent */
1368 void sc_drop(struct send_context *sc)
1369 {
1370 if (!sc)
1371 return;
1372
1373 dd_dev_info(sc->dd, "%s: context %u(%u) - not implemented\n",
1374 __func__, sc->sw_index, sc->hw_context);
1375 }
1376
1377 /*
1378 * Start the software reaction to a context halt or SPC freeze:
1379 * - mark the context as halted or frozen
1380 * - stop buffer allocations
1381 *
1382 * Called from the error interrupt. Other work is deferred until
1383 * out of the interrupt.
1384 */
1385 void sc_stop(struct send_context *sc, int flag)
1386 {
1387 unsigned long flags;
1388
1389 /* mark the context */
1390 sc->flags |= flag;
1391
1392 /* stop buffer allocations */
1393 spin_lock_irqsave(&sc->alloc_lock, flags);
1394 sc->flags &= ~SCF_ENABLED;
1395 spin_unlock_irqrestore(&sc->alloc_lock, flags);
1396 wake_up(&sc->halt_wait);
1397 }
1398
1399 #define BLOCK_DWORDS (PIO_BLOCK_SIZE / sizeof(u32))
1400 #define dwords_to_blocks(x) DIV_ROUND_UP(x, BLOCK_DWORDS)
1401
1402 /*
1403 * The send context buffer "allocator".
1404 *
1405 * @sc: the PIO send context we are allocating from
1406 * @len: length of whole packet - including PBC - in dwords
1407 * @cb: optional callback to call when the buffer is finished sending
1408 * @arg: argument for cb
1409 *
1410 * Return a pointer to a PIO buffer if successful, NULL if not enough room.
1411 */
1412 struct pio_buf *sc_buffer_alloc(struct send_context *sc, u32 dw_len,
1413 pio_release_cb cb, void *arg)
1414 {
1415 struct pio_buf *pbuf = NULL;
1416 unsigned long flags;
1417 unsigned long avail;
1418 unsigned long blocks = dwords_to_blocks(dw_len);
1419 u32 fill_wrap;
1420 int trycount = 0;
1421 u32 head, next;
1422
1423 spin_lock_irqsave(&sc->alloc_lock, flags);
1424 if (!(sc->flags & SCF_ENABLED)) {
1425 spin_unlock_irqrestore(&sc->alloc_lock, flags);
1426 goto done;
1427 }
1428
1429 retry:
1430 avail = (unsigned long)sc->credits - (sc->fill - sc->alloc_free);
1431 if (blocks > avail) {
1432 /* not enough room */
1433 if (unlikely(trycount)) { /* already tried to get more room */
1434 spin_unlock_irqrestore(&sc->alloc_lock, flags);
1435 goto done;
1436 }
1437 /* copy from receiver cache line and recalculate */
1438 sc->alloc_free = READ_ONCE(sc->free);
1439 avail =
1440 (unsigned long)sc->credits -
1441 (sc->fill - sc->alloc_free);
1442 if (blocks > avail) {
1443 /* still no room, actively update */
1444 sc_release_update(sc);
1445 sc->alloc_free = READ_ONCE(sc->free);
1446 trycount++;
1447 goto retry;
1448 }
1449 }
1450
1451 /* there is enough room */
1452
1453 preempt_disable();
1454 this_cpu_inc(*sc->buffers_allocated);
1455
1456 /* read this once */
1457 head = sc->sr_head;
1458
1459 /* "allocate" the buffer */
1460 sc->fill += blocks;
1461 fill_wrap = sc->fill_wrap;
1462 sc->fill_wrap += blocks;
1463 if (sc->fill_wrap >= sc->credits)
1464 sc->fill_wrap = sc->fill_wrap - sc->credits;
1465
1466 /*
1467 * Fill the parts that the releaser looks at before moving the head.
1468 * The only necessary piece is the sent_at field. The credits
1469 * we have just allocated cannot have been returned yet, so the
1470 * cb and arg will not be looked at for a "while". Put them
1471 * on this side of the memory barrier anyway.
1472 */
1473 pbuf = &sc->sr[head].pbuf;
1474 pbuf->sent_at = sc->fill;
1475 pbuf->cb = cb;
1476 pbuf->arg = arg;
1477 pbuf->sc = sc; /* could be filled in at sc->sr init time */
1478 /* make sure this is in memory before updating the head */
1479
1480 /* calculate next head index, do not store */
1481 next = head + 1;
1482 if (next >= sc->sr_size)
1483 next = 0;
1484 /*
1485 * update the head - must be last! - the releaser can look at fields
1486 * in pbuf once we move the head
1487 */
1488 smp_wmb();
1489 sc->sr_head = next;
1490 spin_unlock_irqrestore(&sc->alloc_lock, flags);
1491
1492 /* finish filling in the buffer outside the lock */
1493 pbuf->start = sc->base_addr + fill_wrap * PIO_BLOCK_SIZE;
1494 pbuf->end = sc->base_addr + sc->size;
1495 pbuf->qw_written = 0;
1496 pbuf->carry_bytes = 0;
1497 pbuf->carry.val64 = 0;
1498 done:
1499 return pbuf;
1500 }
1501
1502 /*
1503 * There are at least two entities that can turn on credit return
1504 * interrupts and they can overlap. Avoid problems by implementing
1505 * a count scheme that is enforced by a lock. The lock is needed because
1506 * the count and CSR write must be paired.
1507 */
1508
1509 /*
1510 * Start credit return interrupts. This is managed by a count. If already
1511 * on, just increment the count.
1512 */
1513 void sc_add_credit_return_intr(struct send_context *sc)
1514 {
1515 unsigned long flags;
1516
1517 /* lock must surround both the count change and the CSR update */
1518 spin_lock_irqsave(&sc->credit_ctrl_lock, flags);
1519 if (sc->credit_intr_count == 0) {
1520 sc->credit_ctrl |= SC(CREDIT_CTRL_CREDIT_INTR_SMASK);
1521 write_kctxt_csr(sc->dd, sc->hw_context,
1522 SC(CREDIT_CTRL), sc->credit_ctrl);
1523 }
1524 sc->credit_intr_count++;
1525 spin_unlock_irqrestore(&sc->credit_ctrl_lock, flags);
1526 }
1527
1528 /*
1529 * Stop credit return interrupts. This is managed by a count. Decrement the
1530 * count, if the last user, then turn the credit interrupts off.
1531 */
1532 void sc_del_credit_return_intr(struct send_context *sc)
1533 {
1534 unsigned long flags;
1535
1536 WARN_ON(sc->credit_intr_count == 0);
1537
1538 /* lock must surround both the count change and the CSR update */
1539 spin_lock_irqsave(&sc->credit_ctrl_lock, flags);
1540 sc->credit_intr_count--;
1541 if (sc->credit_intr_count == 0) {
1542 sc->credit_ctrl &= ~SC(CREDIT_CTRL_CREDIT_INTR_SMASK);
1543 write_kctxt_csr(sc->dd, sc->hw_context,
1544 SC(CREDIT_CTRL), sc->credit_ctrl);
1545 }
1546 spin_unlock_irqrestore(&sc->credit_ctrl_lock, flags);
1547 }
1548
1549 /*
1550 * The caller must be careful when calling this. All needint calls
1551 * must be paired with !needint.
1552 */
1553 void hfi1_sc_wantpiobuf_intr(struct send_context *sc, u32 needint)
1554 {
1555 if (needint)
1556 sc_add_credit_return_intr(sc);
1557 else
1558 sc_del_credit_return_intr(sc);
1559 trace_hfi1_wantpiointr(sc, needint, sc->credit_ctrl);
1560 if (needint) {
1561 mmiowb();
1562 sc_return_credits(sc);
1563 }
1564 }
1565
1566 /**
1567 * sc_piobufavail - callback when a PIO buffer is available
1568 * @sc: the send context
1569 *
1570 * This is called from the interrupt handler when a PIO buffer is
1571 * available after hfi1_verbs_send() returned an error that no buffers were
1572 * available. Disable the interrupt if there are no more QPs waiting.
1573 */
1574 static void sc_piobufavail(struct send_context *sc)
1575 {
1576 struct hfi1_devdata *dd = sc->dd;
1577 struct hfi1_ibdev *dev = &dd->verbs_dev;
1578 struct list_head *list;
1579 struct rvt_qp *qps[PIO_WAIT_BATCH_SIZE];
1580 struct rvt_qp *qp;
1581 struct hfi1_qp_priv *priv;
1582 unsigned long flags;
1583 uint i, n = 0, max_idx = 0;
1584 u8 max_starved_cnt = 0;
1585
1586 if (dd->send_contexts[sc->sw_index].type != SC_KERNEL &&
1587 dd->send_contexts[sc->sw_index].type != SC_VL15)
1588 return;
1589 list = &sc->piowait;
1590 /*
1591 * Note: checking that the piowait list is empty and clearing
1592 * the buffer available interrupt needs to be atomic or we
1593 * could end up with QPs on the wait list with the interrupt
1594 * disabled.
1595 */
1596 write_seqlock_irqsave(&dev->iowait_lock, flags);
1597 while (!list_empty(list)) {
1598 struct iowait *wait;
1599
1600 if (n == ARRAY_SIZE(qps))
1601 break;
1602 wait = list_first_entry(list, struct iowait, list);
1603 qp = iowait_to_qp(wait);
1604 priv = qp->priv;
1605 list_del_init(&priv->s_iowait.list);
1606 priv->s_iowait.lock = NULL;
1607 iowait_starve_find_max(wait, &max_starved_cnt, n, &max_idx);
1608 /* refcount held until actual wake up */
1609 qps[n++] = qp;
1610 }
1611 /*
1612 * If there had been waiters and there are more
1613 * insure that we redo the force to avoid a potential hang.
1614 */
1615 if (n) {
1616 hfi1_sc_wantpiobuf_intr(sc, 0);
1617 if (!list_empty(list))
1618 hfi1_sc_wantpiobuf_intr(sc, 1);
1619 }
1620 write_sequnlock_irqrestore(&dev->iowait_lock, flags);
1621
1622 /* Wake up the most starved one first */
1623 if (n)
1624 hfi1_qp_wakeup(qps[max_idx],
1625 RVT_S_WAIT_PIO | RVT_S_WAIT_PIO_DRAIN);
1626 for (i = 0; i < n; i++)
1627 if (i != max_idx)
1628 hfi1_qp_wakeup(qps[i],
1629 RVT_S_WAIT_PIO | RVT_S_WAIT_PIO_DRAIN);
1630 }
1631
1632 /* translate a send credit update to a bit code of reasons */
1633 static inline int fill_code(u64 hw_free)
1634 {
1635 int code = 0;
1636
1637 if (hw_free & CR_STATUS_SMASK)
1638 code |= PRC_STATUS_ERR;
1639 if (hw_free & CR_CREDIT_RETURN_DUE_TO_PBC_SMASK)
1640 code |= PRC_PBC;
1641 if (hw_free & CR_CREDIT_RETURN_DUE_TO_THRESHOLD_SMASK)
1642 code |= PRC_THRESHOLD;
1643 if (hw_free & CR_CREDIT_RETURN_DUE_TO_ERR_SMASK)
1644 code |= PRC_FILL_ERR;
1645 if (hw_free & CR_CREDIT_RETURN_DUE_TO_FORCE_SMASK)
1646 code |= PRC_SC_DISABLE;
1647 return code;
1648 }
1649
1650 /* use the jiffies compare to get the wrap right */
1651 #define sent_before(a, b) time_before(a, b) /* a < b */
1652
1653 /*
1654 * The send context buffer "releaser".
1655 */
1656 void sc_release_update(struct send_context *sc)
1657 {
1658 struct pio_buf *pbuf;
1659 u64 hw_free;
1660 u32 head, tail;
1661 unsigned long old_free;
1662 unsigned long free;
1663 unsigned long extra;
1664 unsigned long flags;
1665 int code;
1666
1667 if (!sc)
1668 return;
1669
1670 spin_lock_irqsave(&sc->release_lock, flags);
1671 /* update free */
1672 hw_free = le64_to_cpu(*sc->hw_free); /* volatile read */
1673 old_free = sc->free;
1674 extra = (((hw_free & CR_COUNTER_SMASK) >> CR_COUNTER_SHIFT)
1675 - (old_free & CR_COUNTER_MASK))
1676 & CR_COUNTER_MASK;
1677 free = old_free + extra;
1678 trace_hfi1_piofree(sc, extra);
1679
1680 /* call sent buffer callbacks */
1681 code = -1; /* code not yet set */
1682 head = READ_ONCE(sc->sr_head); /* snapshot the head */
1683 tail = sc->sr_tail;
1684 while (head != tail) {
1685 pbuf = &sc->sr[tail].pbuf;
1686
1687 if (sent_before(free, pbuf->sent_at)) {
1688 /* not sent yet */
1689 break;
1690 }
1691 if (pbuf->cb) {
1692 if (code < 0) /* fill in code on first user */
1693 code = fill_code(hw_free);
1694 (*pbuf->cb)(pbuf->arg, code);
1695 }
1696
1697 tail++;
1698 if (tail >= sc->sr_size)
1699 tail = 0;
1700 }
1701 sc->sr_tail = tail;
1702 /* make sure tail is updated before free */
1703 smp_wmb();
1704 sc->free = free;
1705 spin_unlock_irqrestore(&sc->release_lock, flags);
1706 sc_piobufavail(sc);
1707 }
1708
1709 /*
1710 * Send context group releaser. Argument is the send context that caused
1711 * the interrupt. Called from the send context interrupt handler.
1712 *
1713 * Call release on all contexts in the group.
1714 *
1715 * This routine takes the sc_lock without an irqsave because it is only
1716 * called from an interrupt handler. Adjust if that changes.
1717 */
1718 void sc_group_release_update(struct hfi1_devdata *dd, u32 hw_context)
1719 {
1720 struct send_context *sc;
1721 u32 sw_index;
1722 u32 gc, gc_end;
1723
1724 spin_lock(&dd->sc_lock);
1725 sw_index = dd->hw_to_sw[hw_context];
1726 if (unlikely(sw_index >= dd->num_send_contexts)) {
1727 dd_dev_err(dd, "%s: invalid hw (%u) to sw (%u) mapping\n",
1728 __func__, hw_context, sw_index);
1729 goto done;
1730 }
1731 sc = dd->send_contexts[sw_index].sc;
1732 if (unlikely(!sc))
1733 goto done;
1734
1735 gc = group_context(hw_context, sc->group);
1736 gc_end = gc + group_size(sc->group);
1737 for (; gc < gc_end; gc++) {
1738 sw_index = dd->hw_to_sw[gc];
1739 if (unlikely(sw_index >= dd->num_send_contexts)) {
1740 dd_dev_err(dd,
1741 "%s: invalid hw (%u) to sw (%u) mapping\n",
1742 __func__, hw_context, sw_index);
1743 continue;
1744 }
1745 sc_release_update(dd->send_contexts[sw_index].sc);
1746 }
1747 done:
1748 spin_unlock(&dd->sc_lock);
1749 }
1750
1751 /*
1752 * pio_select_send_context_vl() - select send context
1753 * @dd: devdata
1754 * @selector: a spreading factor
1755 * @vl: this vl
1756 *
1757 * This function returns a send context based on the selector and a vl.
1758 * The mapping fields are protected by RCU
1759 */
1760 struct send_context *pio_select_send_context_vl(struct hfi1_devdata *dd,
1761 u32 selector, u8 vl)
1762 {
1763 struct pio_vl_map *m;
1764 struct pio_map_elem *e;
1765 struct send_context *rval;
1766
1767 /*
1768 * NOTE This should only happen if SC->VL changed after the initial
1769 * checks on the QP/AH
1770 * Default will return VL0's send context below
1771 */
1772 if (unlikely(vl >= num_vls)) {
1773 rval = NULL;
1774 goto done;
1775 }
1776
1777 rcu_read_lock();
1778 m = rcu_dereference(dd->pio_map);
1779 if (unlikely(!m)) {
1780 rcu_read_unlock();
1781 return dd->vld[0].sc;
1782 }
1783 e = m->map[vl & m->mask];
1784 rval = e->ksc[selector & e->mask];
1785 rcu_read_unlock();
1786
1787 done:
1788 rval = !rval ? dd->vld[0].sc : rval;
1789 return rval;
1790 }
1791
1792 /*
1793 * pio_select_send_context_sc() - select send context
1794 * @dd: devdata
1795 * @selector: a spreading factor
1796 * @sc5: the 5 bit sc
1797 *
1798 * This function returns an send context based on the selector and an sc
1799 */
1800 struct send_context *pio_select_send_context_sc(struct hfi1_devdata *dd,
1801 u32 selector, u8 sc5)
1802 {
1803 u8 vl = sc_to_vlt(dd, sc5);
1804
1805 return pio_select_send_context_vl(dd, selector, vl);
1806 }
1807
1808 /*
1809 * Free the indicated map struct
1810 */
1811 static void pio_map_free(struct pio_vl_map *m)
1812 {
1813 int i;
1814
1815 for (i = 0; m && i < m->actual_vls; i++)
1816 kfree(m->map[i]);
1817 kfree(m);
1818 }
1819
1820 /*
1821 * Handle RCU callback
1822 */
1823 static void pio_map_rcu_callback(struct rcu_head *list)
1824 {
1825 struct pio_vl_map *m = container_of(list, struct pio_vl_map, list);
1826
1827 pio_map_free(m);
1828 }
1829
1830 /*
1831 * Set credit return threshold for the kernel send context
1832 */
1833 static void set_threshold(struct hfi1_devdata *dd, int scontext, int i)
1834 {
1835 u32 thres;
1836
1837 thres = min(sc_percent_to_threshold(dd->kernel_send_context[scontext],
1838 50),
1839 sc_mtu_to_threshold(dd->kernel_send_context[scontext],
1840 dd->vld[i].mtu,
1841 dd->rcd[0]->rcvhdrqentsize));
1842 sc_set_cr_threshold(dd->kernel_send_context[scontext], thres);
1843 }
1844
1845 /*
1846 * pio_map_init - called when #vls change
1847 * @dd: hfi1_devdata
1848 * @port: port number
1849 * @num_vls: number of vls
1850 * @vl_scontexts: per vl send context mapping (optional)
1851 *
1852 * This routine changes the mapping based on the number of vls.
1853 *
1854 * vl_scontexts is used to specify a non-uniform vl/send context
1855 * loading. NULL implies auto computing the loading and giving each
1856 * VL an uniform distribution of send contexts per VL.
1857 *
1858 * The auto algorithm computers the sc_per_vl and the number of extra
1859 * send contexts. Any extra send contexts are added from the last VL
1860 * on down
1861 *
1862 * rcu locking is used here to control access to the mapping fields.
1863 *
1864 * If either the num_vls or num_send_contexts are non-power of 2, the
1865 * array sizes in the struct pio_vl_map and the struct pio_map_elem are
1866 * rounded up to the next highest power of 2 and the first entry is
1867 * reused in a round robin fashion.
1868 *
1869 * If an error occurs the map change is not done and the mapping is not
1870 * chaged.
1871 *
1872 */
1873 int pio_map_init(struct hfi1_devdata *dd, u8 port, u8 num_vls, u8 *vl_scontexts)
1874 {
1875 int i, j;
1876 int extra, sc_per_vl;
1877 int scontext = 1;
1878 int num_kernel_send_contexts = 0;
1879 u8 lvl_scontexts[OPA_MAX_VLS];
1880 struct pio_vl_map *oldmap, *newmap;
1881
1882 if (!vl_scontexts) {
1883 for (i = 0; i < dd->num_send_contexts; i++)
1884 if (dd->send_contexts[i].type == SC_KERNEL)
1885 num_kernel_send_contexts++;
1886 /* truncate divide */
1887 sc_per_vl = num_kernel_send_contexts / num_vls;
1888 /* extras */
1889 extra = num_kernel_send_contexts % num_vls;
1890 vl_scontexts = lvl_scontexts;
1891 /* add extras from last vl down */
1892 for (i = num_vls - 1; i >= 0; i--, extra--)
1893 vl_scontexts[i] = sc_per_vl + (extra > 0 ? 1 : 0);
1894 }
1895 /* build new map */
1896 newmap = kzalloc(sizeof(*newmap) +
1897 roundup_pow_of_two(num_vls) *
1898 sizeof(struct pio_map_elem *),
1899 GFP_KERNEL);
1900 if (!newmap)
1901 goto bail;
1902 newmap->actual_vls = num_vls;
1903 newmap->vls = roundup_pow_of_two(num_vls);
1904 newmap->mask = (1 << ilog2(newmap->vls)) - 1;
1905 for (i = 0; i < newmap->vls; i++) {
1906 /* save for wrap around */
1907 int first_scontext = scontext;
1908
1909 if (i < newmap->actual_vls) {
1910 int sz = roundup_pow_of_two(vl_scontexts[i]);
1911
1912 /* only allocate once */
1913 newmap->map[i] = kzalloc(sizeof(*newmap->map[i]) +
1914 sz * sizeof(struct
1915 send_context *),
1916 GFP_KERNEL);
1917 if (!newmap->map[i])
1918 goto bail;
1919 newmap->map[i]->mask = (1 << ilog2(sz)) - 1;
1920 /*
1921 * assign send contexts and
1922 * adjust credit return threshold
1923 */
1924 for (j = 0; j < sz; j++) {
1925 if (dd->kernel_send_context[scontext]) {
1926 newmap->map[i]->ksc[j] =
1927 dd->kernel_send_context[scontext];
1928 set_threshold(dd, scontext, i);
1929 }
1930 if (++scontext >= first_scontext +
1931 vl_scontexts[i])
1932 /* wrap back to first send context */
1933 scontext = first_scontext;
1934 }
1935 } else {
1936 /* just re-use entry without allocating */
1937 newmap->map[i] = newmap->map[i % num_vls];
1938 }
1939 scontext = first_scontext + vl_scontexts[i];
1940 }
1941 /* newmap in hand, save old map */
1942 spin_lock_irq(&dd->pio_map_lock);
1943 oldmap = rcu_dereference_protected(dd->pio_map,
1944 lockdep_is_held(&dd->pio_map_lock));
1945
1946 /* publish newmap */
1947 rcu_assign_pointer(dd->pio_map, newmap);
1948
1949 spin_unlock_irq(&dd->pio_map_lock);
1950 /* success, free any old map after grace period */
1951 if (oldmap)
1952 call_rcu(&oldmap->list, pio_map_rcu_callback);
1953 return 0;
1954 bail:
1955 /* free any partial allocation */
1956 pio_map_free(newmap);
1957 return -ENOMEM;
1958 }
1959
1960 void free_pio_map(struct hfi1_devdata *dd)
1961 {
1962 /* Free PIO map if allocated */
1963 if (rcu_access_pointer(dd->pio_map)) {
1964 spin_lock_irq(&dd->pio_map_lock);
1965 pio_map_free(rcu_access_pointer(dd->pio_map));
1966 RCU_INIT_POINTER(dd->pio_map, NULL);
1967 spin_unlock_irq(&dd->pio_map_lock);
1968 synchronize_rcu();
1969 }
1970 kfree(dd->kernel_send_context);
1971 dd->kernel_send_context = NULL;
1972 }
1973
1974 int init_pervl_scs(struct hfi1_devdata *dd)
1975 {
1976 int i;
1977 u64 mask, all_vl_mask = (u64)0x80ff; /* VLs 0-7, 15 */
1978 u64 data_vls_mask = (u64)0x00ff; /* VLs 0-7 */
1979 u32 ctxt;
1980 struct hfi1_pportdata *ppd = dd->pport;
1981
1982 dd->vld[15].sc = sc_alloc(dd, SC_VL15,
1983 dd->rcd[0]->rcvhdrqentsize, dd->node);
1984 if (!dd->vld[15].sc)
1985 return -ENOMEM;
1986
1987 hfi1_init_ctxt(dd->vld[15].sc);
1988 dd->vld[15].mtu = enum_to_mtu(OPA_MTU_2048);
1989
1990 dd->kernel_send_context = kzalloc_node(dd->num_send_contexts *
1991 sizeof(struct send_context *),
1992 GFP_KERNEL, dd->node);
1993 if (!dd->kernel_send_context)
1994 goto freesc15;
1995
1996 dd->kernel_send_context[0] = dd->vld[15].sc;
1997
1998 for (i = 0; i < num_vls; i++) {
1999 /*
2000 * Since this function does not deal with a specific
2001 * receive context but we need the RcvHdrQ entry size,
2002 * use the size from rcd[0]. It is guaranteed to be
2003 * valid at this point and will remain the same for all
2004 * receive contexts.
2005 */
2006 dd->vld[i].sc = sc_alloc(dd, SC_KERNEL,
2007 dd->rcd[0]->rcvhdrqentsize, dd->node);
2008 if (!dd->vld[i].sc)
2009 goto nomem;
2010 dd->kernel_send_context[i + 1] = dd->vld[i].sc;
2011 hfi1_init_ctxt(dd->vld[i].sc);
2012 /* non VL15 start with the max MTU */
2013 dd->vld[i].mtu = hfi1_max_mtu;
2014 }
2015 for (i = num_vls; i < INIT_SC_PER_VL * num_vls; i++) {
2016 dd->kernel_send_context[i + 1] =
2017 sc_alloc(dd, SC_KERNEL, dd->rcd[0]->rcvhdrqentsize, dd->node);
2018 if (!dd->kernel_send_context[i + 1])
2019 goto nomem;
2020 hfi1_init_ctxt(dd->kernel_send_context[i + 1]);
2021 }
2022
2023 sc_enable(dd->vld[15].sc);
2024 ctxt = dd->vld[15].sc->hw_context;
2025 mask = all_vl_mask & ~(1LL << 15);
2026 write_kctxt_csr(dd, ctxt, SC(CHECK_VL), mask);
2027 dd_dev_info(dd,
2028 "Using send context %u(%u) for VL15\n",
2029 dd->vld[15].sc->sw_index, ctxt);
2030
2031 for (i = 0; i < num_vls; i++) {
2032 sc_enable(dd->vld[i].sc);
2033 ctxt = dd->vld[i].sc->hw_context;
2034 mask = all_vl_mask & ~(data_vls_mask);
2035 write_kctxt_csr(dd, ctxt, SC(CHECK_VL), mask);
2036 }
2037 for (i = num_vls; i < INIT_SC_PER_VL * num_vls; i++) {
2038 sc_enable(dd->kernel_send_context[i + 1]);
2039 ctxt = dd->kernel_send_context[i + 1]->hw_context;
2040 mask = all_vl_mask & ~(data_vls_mask);
2041 write_kctxt_csr(dd, ctxt, SC(CHECK_VL), mask);
2042 }
2043
2044 if (pio_map_init(dd, ppd->port - 1, num_vls, NULL))
2045 goto nomem;
2046 return 0;
2047
2048 nomem:
2049 for (i = 0; i < num_vls; i++) {
2050 sc_free(dd->vld[i].sc);
2051 dd->vld[i].sc = NULL;
2052 }
2053
2054 for (i = num_vls; i < INIT_SC_PER_VL * num_vls; i++)
2055 sc_free(dd->kernel_send_context[i + 1]);
2056
2057 kfree(dd->kernel_send_context);
2058 dd->kernel_send_context = NULL;
2059
2060 freesc15:
2061 sc_free(dd->vld[15].sc);
2062 return -ENOMEM;
2063 }
2064
2065 int init_credit_return(struct hfi1_devdata *dd)
2066 {
2067 int ret;
2068 int i;
2069
2070 dd->cr_base = kcalloc(
2071 node_affinity.num_possible_nodes,
2072 sizeof(struct credit_return_base),
2073 GFP_KERNEL);
2074 if (!dd->cr_base) {
2075 ret = -ENOMEM;
2076 goto done;
2077 }
2078 for_each_node_with_cpus(i) {
2079 int bytes = TXE_NUM_CONTEXTS * sizeof(struct credit_return);
2080
2081 set_dev_node(&dd->pcidev->dev, i);
2082 dd->cr_base[i].va = dma_zalloc_coherent(
2083 &dd->pcidev->dev,
2084 bytes,
2085 &dd->cr_base[i].dma,
2086 GFP_KERNEL);
2087 if (!dd->cr_base[i].va) {
2088 set_dev_node(&dd->pcidev->dev, dd->node);
2089 dd_dev_err(dd,
2090 "Unable to allocate credit return DMA range for NUMA %d\n",
2091 i);
2092 ret = -ENOMEM;
2093 goto done;
2094 }
2095 }
2096 set_dev_node(&dd->pcidev->dev, dd->node);
2097
2098 ret = 0;
2099 done:
2100 return ret;
2101 }
2102
2103 void free_credit_return(struct hfi1_devdata *dd)
2104 {
2105 int i;
2106
2107 if (!dd->cr_base)
2108 return;
2109 for (i = 0; i < node_affinity.num_possible_nodes; i++) {
2110 if (dd->cr_base[i].va) {
2111 dma_free_coherent(&dd->pcidev->dev,
2112 TXE_NUM_CONTEXTS *
2113 sizeof(struct credit_return),
2114 dd->cr_base[i].va,
2115 dd->cr_base[i].dma);
2116 }
2117 }
2118 kfree(dd->cr_base);
2119 dd->cr_base = NULL;
2120 }