2 * Copyright(c) 2015, 2016 Intel Corporation.
4 * This file is provided under a dual BSD/GPLv2 license. When using or
5 * redistributing this file, you may do so under either license.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
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21 * modification, are permitted provided that the following conditions
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25 * notice, this list of conditions and the following disclaimer.
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44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
48 #include <linux/delay.h>
53 #define SC_CTXT_PACKET_EGRESS_TIMEOUT 350 /* in chip cycles */
55 #define SC(name) SEND_CTXT_##name
57 * Send Context functions
59 static void sc_wait_for_packet_egress(struct send_context
*sc
, int pause
);
62 * Set the CM reset bit and wait for it to clear. Use the provided
63 * sendctrl register. This routine has no locking.
65 void __cm_reset(struct hfi1_devdata
*dd
, u64 sendctrl
)
67 write_csr(dd
, SEND_CTRL
, sendctrl
| SEND_CTRL_CM_RESET_SMASK
);
70 sendctrl
= read_csr(dd
, SEND_CTRL
);
71 if ((sendctrl
& SEND_CTRL_CM_RESET_SMASK
) == 0)
76 /* defined in header release 48 and higher */
77 #ifndef SEND_CTRL_UNSUPPORTED_VL_SHIFT
78 #define SEND_CTRL_UNSUPPORTED_VL_SHIFT 3
79 #define SEND_CTRL_UNSUPPORTED_VL_MASK 0xffull
80 #define SEND_CTRL_UNSUPPORTED_VL_SMASK (SEND_CTRL_UNSUPPORTED_VL_MASK \
81 << SEND_CTRL_UNSUPPORTED_VL_SHIFT)
84 /* global control of PIO send */
85 void pio_send_control(struct hfi1_devdata
*dd
, int op
)
89 int write
= 1; /* write sendctrl back */
90 int flush
= 0; /* re-read sendctrl to make sure it is flushed */
92 spin_lock_irqsave(&dd
->sendctrl_lock
, flags
);
94 reg
= read_csr(dd
, SEND_CTRL
);
96 case PSC_GLOBAL_ENABLE
:
97 reg
|= SEND_CTRL_SEND_ENABLE_SMASK
;
99 case PSC_DATA_VL_ENABLE
:
100 /* Disallow sending on VLs not enabled */
101 mask
= (((~0ull) << num_vls
) & SEND_CTRL_UNSUPPORTED_VL_MASK
) <<
102 SEND_CTRL_UNSUPPORTED_VL_SHIFT
;
103 reg
= (reg
& ~SEND_CTRL_UNSUPPORTED_VL_SMASK
) | mask
;
105 case PSC_GLOBAL_DISABLE
:
106 reg
&= ~SEND_CTRL_SEND_ENABLE_SMASK
;
108 case PSC_GLOBAL_VLARB_ENABLE
:
109 reg
|= SEND_CTRL_VL_ARBITER_ENABLE_SMASK
;
111 case PSC_GLOBAL_VLARB_DISABLE
:
112 reg
&= ~SEND_CTRL_VL_ARBITER_ENABLE_SMASK
;
116 write
= 0; /* CSR already written (and flushed) */
118 case PSC_DATA_VL_DISABLE
:
119 reg
|= SEND_CTRL_UNSUPPORTED_VL_SMASK
;
123 dd_dev_err(dd
, "%s: invalid control %d\n", __func__
, op
);
128 write_csr(dd
, SEND_CTRL
, reg
);
130 (void)read_csr(dd
, SEND_CTRL
); /* flush write */
133 spin_unlock_irqrestore(&dd
->sendctrl_lock
, flags
);
136 /* number of send context memory pools */
137 #define NUM_SC_POOLS 2
139 /* Send Context Size (SCS) wildcards */
140 #define SCS_POOL_0 -1
141 #define SCS_POOL_1 -2
143 /* Send Context Count (SCC) wildcards */
144 #define SCC_PER_VL -1
145 #define SCC_PER_CPU -2
146 #define SCC_PER_KRCVQ -3
148 /* Send Context Size (SCS) constants */
149 #define SCS_ACK_CREDITS 32
150 #define SCS_VL15_CREDITS 102 /* 3 pkts of 2048B data + 128B header */
152 #define PIO_THRESHOLD_CEILING 4096
154 #define PIO_WAIT_BATCH_SIZE 5
156 /* default send context sizes */
157 static struct sc_config_sizes sc_config_sizes
[SC_MAX
] = {
158 [SC_KERNEL
] = { .size
= SCS_POOL_0
, /* even divide, pool 0 */
159 .count
= SCC_PER_VL
}, /* one per NUMA */
160 [SC_ACK
] = { .size
= SCS_ACK_CREDITS
,
161 .count
= SCC_PER_KRCVQ
},
162 [SC_USER
] = { .size
= SCS_POOL_0
, /* even divide, pool 0 */
163 .count
= SCC_PER_CPU
}, /* one per CPU */
164 [SC_VL15
] = { .size
= SCS_VL15_CREDITS
,
169 /* send context memory pool configuration */
170 struct mem_pool_config
{
171 int centipercent
; /* % of memory, in 100ths of 1% */
172 int absolute_blocks
; /* absolute block count */
175 /* default memory pool configuration: 100% in pool 0 */
176 static struct mem_pool_config sc_mem_pool_config
[NUM_SC_POOLS
] = {
177 /* centi%, abs blocks */
178 { 10000, -1 }, /* pool 0 */
179 { 0, -1 }, /* pool 1 */
182 /* memory pool information, used when calculating final sizes */
183 struct mem_pool_info
{
185 * 100th of 1% of memory to use, -1 if blocks
188 int count
; /* count of contexts in the pool */
189 int blocks
; /* block size of the pool */
190 int size
; /* context size, in blocks */
194 * Convert a pool wildcard to a valid pool index. The wildcards
195 * start at -1 and increase negatively. Map them as:
200 * Return -1 on non-wildcard input, otherwise convert to a pool number.
202 static int wildcard_to_pool(int wc
)
205 return -1; /* non-wildcard */
209 static const char *sc_type_names
[SC_MAX
] = {
216 static const char *sc_type_name(int index
)
218 if (index
< 0 || index
>= SC_MAX
)
220 return sc_type_names
[index
];
224 * Read the send context memory pool configuration and send context
225 * size configuration. Replace any wildcards and come up with final
226 * counts and sizes for the send context types.
228 int init_sc_pools_and_sizes(struct hfi1_devdata
*dd
)
230 struct mem_pool_info mem_pool_info
[NUM_SC_POOLS
] = { { 0 } };
231 int total_blocks
= (dd
->chip_pio_mem_size
/ PIO_BLOCK_SIZE
) - 1;
232 int total_contexts
= 0;
236 int cp_total
; /* centipercent total */
237 int ab_total
; /* absolute block total */
242 * When SDMA is enabled, kernel context pio packet size is capped by
243 * "piothreshold". Reduce pio buffer allocation for kernel context by
244 * setting it to a fixed size. The allocation allows 3-deep buffering
245 * of the largest pio packets plus up to 128 bytes header, sufficient
246 * to maintain verbs performance.
248 * When SDMA is disabled, keep the default pooling allocation.
250 if (HFI1_CAP_IS_KSET(SDMA
)) {
251 u16 max_pkt_size
= (piothreshold
< PIO_THRESHOLD_CEILING
) ?
252 piothreshold
: PIO_THRESHOLD_CEILING
;
253 sc_config_sizes
[SC_KERNEL
].size
=
254 3 * (max_pkt_size
+ 128) / PIO_BLOCK_SIZE
;
259 * - copy the centipercents/absolute sizes from the pool config
260 * - sanity check these values
261 * - add up centipercents, then later check for full value
262 * - add up absolute blocks, then later check for over-commit
266 for (i
= 0; i
< NUM_SC_POOLS
; i
++) {
267 int cp
= sc_mem_pool_config
[i
].centipercent
;
268 int ab
= sc_mem_pool_config
[i
].absolute_blocks
;
271 * A negative value is "unused" or "invalid". Both *can*
272 * be valid, but centipercent wins, so check that first
274 if (cp
>= 0) { /* centipercent valid */
276 } else if (ab
>= 0) { /* absolute blocks valid */
278 } else { /* neither valid */
281 "Send context memory pool %d: both the block count and centipercent are invalid\n",
286 mem_pool_info
[i
].centipercent
= cp
;
287 mem_pool_info
[i
].blocks
= ab
;
290 /* do not use both % and absolute blocks for different pools */
291 if (cp_total
!= 0 && ab_total
!= 0) {
294 "All send context memory pools must be described as either centipercent or blocks, no mixing between pools\n");
298 /* if any percentages are present, they must add up to 100% x 100 */
299 if (cp_total
!= 0 && cp_total
!= 10000) {
302 "Send context memory pool centipercent is %d, expecting 10000\n",
307 /* the absolute pool total cannot be more than the mem total */
308 if (ab_total
> total_blocks
) {
311 "Send context memory pool absolute block count %d is larger than the memory size %d\n",
312 ab_total
, total_blocks
);
318 * - copy from the context size config
319 * - replace context type wildcard counts with real values
320 * - add up non-memory pool block sizes
321 * - add up memory pool user counts
324 for (i
= 0; i
< SC_MAX
; i
++) {
325 int count
= sc_config_sizes
[i
].count
;
326 int size
= sc_config_sizes
[i
].size
;
330 * Sanity check count: Either a positive value or
331 * one of the expected wildcards is valid. The positive
332 * value is checked later when we compare against total
336 count
= dd
->n_krcv_queues
;
337 } else if (i
== SC_KERNEL
) {
338 count
= INIT_SC_PER_VL
* num_vls
;
339 } else if (count
== SCC_PER_CPU
) {
340 count
= dd
->num_rcv_contexts
- dd
->n_krcv_queues
;
341 } else if (count
< 0) {
344 "%s send context invalid count wildcard %d\n",
345 sc_type_name(i
), count
);
348 if (total_contexts
+ count
> dd
->chip_send_contexts
)
349 count
= dd
->chip_send_contexts
- total_contexts
;
351 total_contexts
+= count
;
354 * Sanity check pool: The conversion will return a pool
355 * number or -1 if a fixed (non-negative) value. The fixed
356 * value is checked later when we compare against
357 * total memory available.
359 pool
= wildcard_to_pool(size
);
360 if (pool
== -1) { /* non-wildcard */
361 fixed_blocks
+= size
* count
;
362 } else if (pool
< NUM_SC_POOLS
) { /* valid wildcard */
363 mem_pool_info
[pool
].count
+= count
;
364 } else { /* invalid wildcard */
367 "%s send context invalid pool wildcard %d\n",
368 sc_type_name(i
), size
);
372 dd
->sc_sizes
[i
].count
= count
;
373 dd
->sc_sizes
[i
].size
= size
;
375 if (fixed_blocks
> total_blocks
) {
378 "Send context fixed block count, %u, larger than total block count %u\n",
379 fixed_blocks
, total_blocks
);
383 /* step 3: calculate the blocks in the pools, and pool context sizes */
384 pool_blocks
= total_blocks
- fixed_blocks
;
385 if (ab_total
> pool_blocks
) {
388 "Send context fixed pool sizes, %u, larger than pool block count %u\n",
389 ab_total
, pool_blocks
);
392 /* subtract off the fixed pool blocks */
393 pool_blocks
-= ab_total
;
395 for (i
= 0; i
< NUM_SC_POOLS
; i
++) {
396 struct mem_pool_info
*pi
= &mem_pool_info
[i
];
398 /* % beats absolute blocks */
399 if (pi
->centipercent
>= 0)
400 pi
->blocks
= (pool_blocks
* pi
->centipercent
) / 10000;
402 if (pi
->blocks
== 0 && pi
->count
!= 0) {
405 "Send context memory pool %d has %u contexts, but no blocks\n",
409 if (pi
->count
== 0) {
410 /* warn about wasted blocks */
414 "Send context memory pool %d has %u blocks, but zero contexts\n",
418 pi
->size
= pi
->blocks
/ pi
->count
;
422 /* step 4: fill in the context type sizes from the pool sizes */
424 for (i
= 0; i
< SC_MAX
; i
++) {
425 if (dd
->sc_sizes
[i
].size
< 0) {
426 unsigned pool
= wildcard_to_pool(dd
->sc_sizes
[i
].size
);
428 WARN_ON_ONCE(pool
>= NUM_SC_POOLS
);
429 dd
->sc_sizes
[i
].size
= mem_pool_info
[pool
].size
;
431 /* make sure we are not larger than what is allowed by the HW */
432 #define PIO_MAX_BLOCKS 1024
433 if (dd
->sc_sizes
[i
].size
> PIO_MAX_BLOCKS
)
434 dd
->sc_sizes
[i
].size
= PIO_MAX_BLOCKS
;
436 /* calculate our total usage */
437 used_blocks
+= dd
->sc_sizes
[i
].size
* dd
->sc_sizes
[i
].count
;
439 extra
= total_blocks
- used_blocks
;
441 dd_dev_info(dd
, "unused send context blocks: %d\n", extra
);
443 return total_contexts
;
446 int init_send_contexts(struct hfi1_devdata
*dd
)
449 int ret
, i
, j
, context
;
451 ret
= init_credit_return(dd
);
455 dd
->hw_to_sw
= kmalloc_array(TXE_NUM_CONTEXTS
, sizeof(u8
),
457 dd
->send_contexts
= kcalloc(dd
->num_send_contexts
,
458 sizeof(struct send_context_info
),
460 if (!dd
->send_contexts
|| !dd
->hw_to_sw
) {
462 kfree(dd
->send_contexts
);
463 free_credit_return(dd
);
467 /* hardware context map starts with invalid send context indices */
468 for (i
= 0; i
< TXE_NUM_CONTEXTS
; i
++)
469 dd
->hw_to_sw
[i
] = INVALID_SCI
;
472 * All send contexts have their credit sizes. Allocate credits
473 * for each context one after another from the global space.
477 for (i
= 0; i
< SC_MAX
; i
++) {
478 struct sc_config_sizes
*scs
= &dd
->sc_sizes
[i
];
480 for (j
= 0; j
< scs
->count
; j
++) {
481 struct send_context_info
*sci
=
482 &dd
->send_contexts
[context
];
485 sci
->credits
= scs
->size
;
496 * Allocate a software index and hardware context of the given type.
498 * Must be called with dd->sc_lock held.
500 static int sc_hw_alloc(struct hfi1_devdata
*dd
, int type
, u32
*sw_index
,
503 struct send_context_info
*sci
;
507 for (index
= 0, sci
= &dd
->send_contexts
[0];
508 index
< dd
->num_send_contexts
; index
++, sci
++) {
509 if (sci
->type
== type
&& sci
->allocated
== 0) {
511 /* use a 1:1 mapping, but make them non-equal */
512 context
= dd
->chip_send_contexts
- index
- 1;
513 dd
->hw_to_sw
[context
] = index
;
515 *hw_context
= context
;
516 return 0; /* success */
519 dd_dev_err(dd
, "Unable to locate a free type %d send context\n", type
);
524 * Free the send context given by its software index.
526 * Must be called with dd->sc_lock held.
528 static void sc_hw_free(struct hfi1_devdata
*dd
, u32 sw_index
, u32 hw_context
)
530 struct send_context_info
*sci
;
532 sci
= &dd
->send_contexts
[sw_index
];
533 if (!sci
->allocated
) {
534 dd_dev_err(dd
, "%s: sw_index %u not allocated? hw_context %u\n",
535 __func__
, sw_index
, hw_context
);
538 dd
->hw_to_sw
[hw_context
] = INVALID_SCI
;
541 /* return the base context of a context in a group */
542 static inline u32
group_context(u32 context
, u32 group
)
544 return (context
>> group
) << group
;
547 /* return the size of a group */
548 static inline u32
group_size(u32 group
)
554 * Obtain the credit return addresses, kernel virtual and bus, for the
557 * To understand this routine:
558 * o va and dma are arrays of struct credit_return. One for each physical
559 * send context, per NUMA.
560 * o Each send context always looks in its relative location in a struct
561 * credit_return for its credit return.
562 * o Each send context in a group must have its return address CSR programmed
563 * with the same value. Use the address of the first send context in the
566 static void cr_group_addresses(struct send_context
*sc
, dma_addr_t
*dma
)
568 u32 gc
= group_context(sc
->hw_context
, sc
->group
);
569 u32 index
= sc
->hw_context
& 0x7;
571 sc
->hw_free
= &sc
->dd
->cr_base
[sc
->node
].va
[gc
].cr
[index
];
572 *dma
= (unsigned long)
573 &((struct credit_return
*)sc
->dd
->cr_base
[sc
->node
].dma
)[gc
];
577 * Work queue function triggered in error interrupt routine for
580 static void sc_halted(struct work_struct
*work
)
582 struct send_context
*sc
;
584 sc
= container_of(work
, struct send_context
, halt_work
);
589 * Calculate PIO block threshold for this send context using the given MTU.
590 * Trigger a return when one MTU plus optional header of credits remain.
592 * Parameter mtu is in bytes.
593 * Parameter hdrqentsize is in DWORDs.
595 * Return value is what to write into the CSR: trigger return when
596 * unreturned credits pass this count.
598 u32
sc_mtu_to_threshold(struct send_context
*sc
, u32 mtu
, u32 hdrqentsize
)
603 /* add in the header size, then divide by the PIO block size */
604 mtu
+= hdrqentsize
<< 2;
605 release_credits
= DIV_ROUND_UP(mtu
, PIO_BLOCK_SIZE
);
607 /* check against this context's credits */
608 if (sc
->credits
<= release_credits
)
611 threshold
= sc
->credits
- release_credits
;
617 * Calculate credit threshold in terms of percent of the allocated credits.
618 * Trigger when unreturned credits equal or exceed the percentage of the whole.
620 * Return value is what to write into the CSR: trigger return when
621 * unreturned credits pass this count.
623 u32
sc_percent_to_threshold(struct send_context
*sc
, u32 percent
)
625 return (sc
->credits
* percent
) / 100;
629 * Set the credit return threshold.
631 void sc_set_cr_threshold(struct send_context
*sc
, u32 new_threshold
)
635 int force_return
= 0;
637 spin_lock_irqsave(&sc
->credit_ctrl_lock
, flags
);
639 old_threshold
= (sc
->credit_ctrl
>>
640 SC(CREDIT_CTRL_THRESHOLD_SHIFT
))
641 & SC(CREDIT_CTRL_THRESHOLD_MASK
);
643 if (new_threshold
!= old_threshold
) {
646 & ~SC(CREDIT_CTRL_THRESHOLD_SMASK
))
648 & SC(CREDIT_CTRL_THRESHOLD_MASK
))
649 << SC(CREDIT_CTRL_THRESHOLD_SHIFT
));
650 write_kctxt_csr(sc
->dd
, sc
->hw_context
,
651 SC(CREDIT_CTRL
), sc
->credit_ctrl
);
653 /* force a credit return on change to avoid a possible stall */
657 spin_unlock_irqrestore(&sc
->credit_ctrl_lock
, flags
);
660 sc_return_credits(sc
);
666 * Set the CHECK_ENABLE register for the send context 'sc'.
668 void set_pio_integrity(struct send_context
*sc
)
670 struct hfi1_devdata
*dd
= sc
->dd
;
672 u32 hw_context
= sc
->hw_context
;
676 * No integrity checks if HFI1_CAP_NO_INTEGRITY is set, or if
679 if (likely(!HFI1_CAP_IS_KSET(NO_INTEGRITY
)) &&
680 dd
->hfi1_snoop
.mode_flag
!= HFI1_PORT_SNOOP_MODE
)
681 reg
= hfi1_pkt_default_send_ctxt_mask(dd
, type
);
683 write_kctxt_csr(dd
, hw_context
, SC(CHECK_ENABLE
), reg
);
686 static u32
get_buffers_allocated(struct send_context
*sc
)
691 for_each_possible_cpu(cpu
)
692 ret
+= *per_cpu_ptr(sc
->buffers_allocated
, cpu
);
696 static void reset_buffers_allocated(struct send_context
*sc
)
700 for_each_possible_cpu(cpu
)
701 (*per_cpu_ptr(sc
->buffers_allocated
, cpu
)) = 0;
705 * Allocate a NUMA relative send context structure of the given type along
708 struct send_context
*sc_alloc(struct hfi1_devdata
*dd
, int type
,
709 uint hdrqentsize
, int numa
)
711 struct send_context_info
*sci
;
712 struct send_context
*sc
= NULL
;
722 /* do not allocate while frozen */
723 if (dd
->flags
& HFI1_FROZEN
)
726 sc
= kzalloc_node(sizeof(*sc
), GFP_KERNEL
, numa
);
730 sc
->buffers_allocated
= alloc_percpu(u32
);
731 if (!sc
->buffers_allocated
) {
734 "Cannot allocate buffers_allocated per cpu counters\n"
739 spin_lock_irqsave(&dd
->sc_lock
, flags
);
740 ret
= sc_hw_alloc(dd
, type
, &sw_index
, &hw_context
);
742 spin_unlock_irqrestore(&dd
->sc_lock
, flags
);
743 free_percpu(sc
->buffers_allocated
);
748 sci
= &dd
->send_contexts
[sw_index
];
754 spin_lock_init(&sc
->alloc_lock
);
755 spin_lock_init(&sc
->release_lock
);
756 spin_lock_init(&sc
->credit_ctrl_lock
);
757 INIT_LIST_HEAD(&sc
->piowait
);
758 INIT_WORK(&sc
->halt_work
, sc_halted
);
759 init_waitqueue_head(&sc
->halt_wait
);
761 /* grouping is always single context for now */
764 sc
->sw_index
= sw_index
;
765 sc
->hw_context
= hw_context
;
766 cr_group_addresses(sc
, &dma
);
767 sc
->credits
= sci
->credits
;
768 sc
->size
= sc
->credits
* PIO_BLOCK_SIZE
;
770 /* PIO Send Memory Address details */
771 #define PIO_ADDR_CONTEXT_MASK 0xfful
772 #define PIO_ADDR_CONTEXT_SHIFT 16
773 sc
->base_addr
= dd
->piobase
+ ((hw_context
& PIO_ADDR_CONTEXT_MASK
)
774 << PIO_ADDR_CONTEXT_SHIFT
);
776 /* set base and credits */
777 reg
= ((sci
->credits
& SC(CTRL_CTXT_DEPTH_MASK
))
778 << SC(CTRL_CTXT_DEPTH_SHIFT
))
779 | ((sci
->base
& SC(CTRL_CTXT_BASE_MASK
))
780 << SC(CTRL_CTXT_BASE_SHIFT
));
781 write_kctxt_csr(dd
, hw_context
, SC(CTRL
), reg
);
783 set_pio_integrity(sc
);
785 /* unmask all errors */
786 write_kctxt_csr(dd
, hw_context
, SC(ERR_MASK
), (u64
)-1);
788 /* set the default partition key */
789 write_kctxt_csr(dd
, hw_context
, SC(CHECK_PARTITION_KEY
),
790 (SC(CHECK_PARTITION_KEY_VALUE_MASK
) &
792 SC(CHECK_PARTITION_KEY_VALUE_SHIFT
));
794 /* per context type checks */
795 if (type
== SC_USER
) {
796 opval
= USER_OPCODE_CHECK_VAL
;
797 opmask
= USER_OPCODE_CHECK_MASK
;
799 opval
= OPCODE_CHECK_VAL_DISABLED
;
800 opmask
= OPCODE_CHECK_MASK_DISABLED
;
803 /* set the send context check opcode mask and value */
804 write_kctxt_csr(dd
, hw_context
, SC(CHECK_OPCODE
),
805 ((u64
)opmask
<< SC(CHECK_OPCODE_MASK_SHIFT
)) |
806 ((u64
)opval
<< SC(CHECK_OPCODE_VALUE_SHIFT
)));
808 /* set up credit return */
809 reg
= dma
& SC(CREDIT_RETURN_ADDR_ADDRESS_SMASK
);
810 write_kctxt_csr(dd
, hw_context
, SC(CREDIT_RETURN_ADDR
), reg
);
813 * Calculate the initial credit return threshold.
815 * For Ack contexts, set a threshold for half the credits.
816 * For User contexts use the given percentage. This has been
817 * sanitized on driver start-up.
818 * For Kernel contexts, use the default MTU plus a header
819 * or half the credits, whichever is smaller. This should
820 * work for both the 3-deep buffering allocation and the
821 * pooling allocation.
823 if (type
== SC_ACK
) {
824 thresh
= sc_percent_to_threshold(sc
, 50);
825 } else if (type
== SC_USER
) {
826 thresh
= sc_percent_to_threshold(sc
,
827 user_credit_return_threshold
);
828 } else { /* kernel */
829 thresh
= min(sc_percent_to_threshold(sc
, 50),
830 sc_mtu_to_threshold(sc
, hfi1_max_mtu
,
833 reg
= thresh
<< SC(CREDIT_CTRL_THRESHOLD_SHIFT
);
834 /* add in early return */
835 if (type
== SC_USER
&& HFI1_CAP_IS_USET(EARLY_CREDIT_RETURN
))
836 reg
|= SC(CREDIT_CTRL_EARLY_RETURN_SMASK
);
837 else if (HFI1_CAP_IS_KSET(EARLY_CREDIT_RETURN
)) /* kernel, ack */
838 reg
|= SC(CREDIT_CTRL_EARLY_RETURN_SMASK
);
840 /* set up write-through credit_ctrl */
841 sc
->credit_ctrl
= reg
;
842 write_kctxt_csr(dd
, hw_context
, SC(CREDIT_CTRL
), reg
);
844 /* User send contexts should not allow sending on VL15 */
845 if (type
== SC_USER
) {
847 write_kctxt_csr(dd
, hw_context
, SC(CHECK_VL
), reg
);
850 spin_unlock_irqrestore(&dd
->sc_lock
, flags
);
853 * Allocate shadow ring to track outstanding PIO buffers _after_
854 * unlocking. We don't know the size until the lock is held and
855 * we can't allocate while the lock is held. No one is using
856 * the context yet, so allocate it now.
858 * User contexts do not get a shadow ring.
860 if (type
!= SC_USER
) {
862 * Size the shadow ring 1 larger than the number of credits
863 * so head == tail can mean empty.
865 sc
->sr_size
= sci
->credits
+ 1;
866 sc
->sr
= kzalloc_node(sizeof(union pio_shadow_ring
) *
867 sc
->sr_size
, GFP_KERNEL
, numa
);
875 "Send context %u(%u) %s group %u credits %u credit_ctrl 0x%llx threshold %u\n",
887 /* free a per-NUMA send context structure */
888 void sc_free(struct send_context
*sc
)
890 struct hfi1_devdata
*dd
;
898 sc
->flags
|= SCF_IN_FREE
; /* ensure no restarts */
900 if (!list_empty(&sc
->piowait
))
901 dd_dev_err(dd
, "piowait list not empty!\n");
902 sw_index
= sc
->sw_index
;
903 hw_context
= sc
->hw_context
;
904 sc_disable(sc
); /* make sure the HW is disabled */
905 flush_work(&sc
->halt_work
);
907 spin_lock_irqsave(&dd
->sc_lock
, flags
);
908 dd
->send_contexts
[sw_index
].sc
= NULL
;
910 /* clear/disable all registers set in sc_alloc */
911 write_kctxt_csr(dd
, hw_context
, SC(CTRL
), 0);
912 write_kctxt_csr(dd
, hw_context
, SC(CHECK_ENABLE
), 0);
913 write_kctxt_csr(dd
, hw_context
, SC(ERR_MASK
), 0);
914 write_kctxt_csr(dd
, hw_context
, SC(CHECK_PARTITION_KEY
), 0);
915 write_kctxt_csr(dd
, hw_context
, SC(CHECK_OPCODE
), 0);
916 write_kctxt_csr(dd
, hw_context
, SC(CREDIT_RETURN_ADDR
), 0);
917 write_kctxt_csr(dd
, hw_context
, SC(CREDIT_CTRL
), 0);
919 /* release the index and context for re-use */
920 sc_hw_free(dd
, sw_index
, hw_context
);
921 spin_unlock_irqrestore(&dd
->sc_lock
, flags
);
924 free_percpu(sc
->buffers_allocated
);
928 /* disable the context */
929 void sc_disable(struct send_context
*sc
)
933 struct pio_buf
*pbuf
;
938 /* do all steps, even if already disabled */
939 spin_lock_irqsave(&sc
->alloc_lock
, flags
);
940 reg
= read_kctxt_csr(sc
->dd
, sc
->hw_context
, SC(CTRL
));
941 reg
&= ~SC(CTRL_CTXT_ENABLE_SMASK
);
942 sc
->flags
&= ~SCF_ENABLED
;
943 sc_wait_for_packet_egress(sc
, 1);
944 write_kctxt_csr(sc
->dd
, sc
->hw_context
, SC(CTRL
), reg
);
945 spin_unlock_irqrestore(&sc
->alloc_lock
, flags
);
948 * Flush any waiters. Once the context is disabled,
949 * credit return interrupts are stopped (although there
950 * could be one in-process when the context is disabled).
951 * Wait one microsecond for any lingering interrupts, then
952 * proceed with the flush.
955 spin_lock_irqsave(&sc
->release_lock
, flags
);
956 if (sc
->sr
) { /* this context has a shadow ring */
957 while (sc
->sr_tail
!= sc
->sr_head
) {
958 pbuf
= &sc
->sr
[sc
->sr_tail
].pbuf
;
960 (*pbuf
->cb
)(pbuf
->arg
, PRC_SC_DISABLE
);
962 if (sc
->sr_tail
>= sc
->sr_size
)
966 spin_unlock_irqrestore(&sc
->release_lock
, flags
);
969 /* return SendEgressCtxtStatus.PacketOccupancy */
970 #define packet_occupancy(r) \
971 (((r) & SEND_EGRESS_CTXT_STATUS_CTXT_EGRESS_PACKET_OCCUPANCY_SMASK)\
972 >> SEND_EGRESS_CTXT_STATUS_CTXT_EGRESS_PACKET_OCCUPANCY_SHIFT)
974 /* is egress halted on the context? */
975 #define egress_halted(r) \
976 ((r) & SEND_EGRESS_CTXT_STATUS_CTXT_EGRESS_HALT_STATUS_SMASK)
978 /* wait for packet egress, optionally pause for credit return */
979 static void sc_wait_for_packet_egress(struct send_context
*sc
, int pause
)
981 struct hfi1_devdata
*dd
= sc
->dd
;
988 reg
= read_csr(dd
, sc
->hw_context
* 8 +
989 SEND_EGRESS_CTXT_STATUS
);
990 /* done if egress is stopped */
991 if (egress_halted(reg
))
993 reg
= packet_occupancy(reg
);
996 /* counter is reset if occupancy count changes */
1000 /* timed out - bounce the link */
1002 "%s: context %u(%u) timeout waiting for packets to egress, remaining count %u, bouncing link\n",
1003 __func__
, sc
->sw_index
,
1004 sc
->hw_context
, (u32
)reg
);
1005 queue_work(dd
->pport
->hfi1_wq
,
1006 &dd
->pport
->link_bounce_work
);
1014 /* Add additional delay to ensure chip returns all credits */
1015 pause_for_credit_return(dd
);
1018 void sc_wait(struct hfi1_devdata
*dd
)
1022 for (i
= 0; i
< dd
->num_send_contexts
; i
++) {
1023 struct send_context
*sc
= dd
->send_contexts
[i
].sc
;
1027 sc_wait_for_packet_egress(sc
, 0);
1032 * Restart a context after it has been halted due to error.
1034 * If the first step fails - wait for the halt to be asserted, return early.
1035 * Otherwise complain about timeouts but keep going.
1037 * It is expected that allocations (enabled flag bit) have been shut off
1038 * already (only applies to kernel contexts).
1040 int sc_restart(struct send_context
*sc
)
1042 struct hfi1_devdata
*dd
= sc
->dd
;
1047 /* bounce off if not halted, or being free'd */
1048 if (!(sc
->flags
& SCF_HALTED
) || (sc
->flags
& SCF_IN_FREE
))
1051 dd_dev_info(dd
, "restarting send context %u(%u)\n", sc
->sw_index
,
1055 * Step 1: Wait for the context to actually halt.
1057 * The error interrupt is asynchronous to actually setting halt
1062 reg
= read_kctxt_csr(dd
, sc
->hw_context
, SC(STATUS
));
1063 if (reg
& SC(STATUS_CTXT_HALTED_SMASK
))
1066 dd_dev_err(dd
, "%s: context %u(%u) not halting, skipping\n",
1067 __func__
, sc
->sw_index
, sc
->hw_context
);
1075 * Step 2: Ensure no users are still trying to write to PIO.
1077 * For kernel contexts, we have already turned off buffer allocation.
1078 * Now wait for the buffer count to go to zero.
1080 * For user contexts, the user handling code has cut off write access
1081 * to the context's PIO pages before calling this routine and will
1082 * restore write access after this routine returns.
1084 if (sc
->type
!= SC_USER
) {
1085 /* kernel context */
1088 count
= get_buffers_allocated(sc
);
1093 "%s: context %u(%u) timeout waiting for PIO buffers to zero, remaining %d\n",
1094 __func__
, sc
->sw_index
,
1095 sc
->hw_context
, count
);
1103 * Step 3: Wait for all packets to egress.
1104 * This is done while disabling the send context
1106 * Step 4: Disable the context
1108 * This is a superset of the halt. After the disable, the
1109 * errors can be cleared.
1114 * Step 5: Enable the context
1116 * This enable will clear the halted flag and per-send context
1119 return sc_enable(sc
);
1123 * PIO freeze processing. To be called after the TXE block is fully frozen.
1124 * Go through all frozen send contexts and disable them. The contexts are
1125 * already stopped by the freeze.
1127 void pio_freeze(struct hfi1_devdata
*dd
)
1129 struct send_context
*sc
;
1132 for (i
= 0; i
< dd
->num_send_contexts
; i
++) {
1133 sc
= dd
->send_contexts
[i
].sc
;
1135 * Don't disable unallocated, unfrozen, or user send contexts.
1136 * User send contexts will be disabled when the process
1137 * calls into the driver to reset its context.
1139 if (!sc
|| !(sc
->flags
& SCF_FROZEN
) || sc
->type
== SC_USER
)
1142 /* only need to disable, the context is already stopped */
1148 * Unfreeze PIO for kernel send contexts. The precondition for calling this
1149 * is that all PIO send contexts have been disabled and the SPC freeze has
1150 * been cleared. Now perform the last step and re-enable each kernel context.
1151 * User (PSM) processing will occur when PSM calls into the kernel to
1152 * acknowledge the freeze.
1154 void pio_kernel_unfreeze(struct hfi1_devdata
*dd
)
1156 struct send_context
*sc
;
1159 for (i
= 0; i
< dd
->num_send_contexts
; i
++) {
1160 sc
= dd
->send_contexts
[i
].sc
;
1161 if (!sc
|| !(sc
->flags
& SCF_FROZEN
) || sc
->type
== SC_USER
)
1164 sc_enable(sc
); /* will clear the sc frozen flag */
1169 * Wait for the SendPioInitCtxt.PioInitInProgress bit to clear.
1171 * -ETIMEDOUT - if we wait too long
1172 * -EIO - if there was an error
1174 static int pio_init_wait_progress(struct hfi1_devdata
*dd
)
1179 /* max is the longest possible HW init time / delay */
1180 max
= (dd
->icode
== ICODE_FPGA_EMULATION
) ? 120 : 5;
1182 reg
= read_csr(dd
, SEND_PIO_INIT_CTXT
);
1183 if (!(reg
& SEND_PIO_INIT_CTXT_PIO_INIT_IN_PROGRESS_SMASK
))
1191 return reg
& SEND_PIO_INIT_CTXT_PIO_INIT_ERR_SMASK
? -EIO
: 0;
1195 * Reset all of the send contexts to their power-on state. Used
1196 * only during manual init - no lock against sc_enable needed.
1198 void pio_reset_all(struct hfi1_devdata
*dd
)
1202 /* make sure the init engine is not busy */
1203 ret
= pio_init_wait_progress(dd
);
1204 /* ignore any timeout */
1206 /* clear the error */
1207 write_csr(dd
, SEND_PIO_ERR_CLEAR
,
1208 SEND_PIO_ERR_CLEAR_PIO_INIT_SM_IN_ERR_SMASK
);
1211 /* reset init all */
1212 write_csr(dd
, SEND_PIO_INIT_CTXT
,
1213 SEND_PIO_INIT_CTXT_PIO_ALL_CTXT_INIT_SMASK
);
1215 ret
= pio_init_wait_progress(dd
);
1218 "PIO send context init %s while initializing all PIO blocks\n",
1219 ret
== -ETIMEDOUT
? "is stuck" : "had an error");
1223 /* enable the context */
1224 int sc_enable(struct send_context
*sc
)
1226 u64 sc_ctrl
, reg
, pio
;
1227 struct hfi1_devdata
*dd
;
1228 unsigned long flags
;
1236 * Obtain the allocator lock to guard against any allocation
1237 * attempts (which should not happen prior to context being
1238 * enabled). On the release/disable side we don't need to
1239 * worry about locking since the releaser will not do anything
1240 * if the context accounting values have not changed.
1242 spin_lock_irqsave(&sc
->alloc_lock
, flags
);
1243 sc_ctrl
= read_kctxt_csr(dd
, sc
->hw_context
, SC(CTRL
));
1244 if ((sc_ctrl
& SC(CTRL_CTXT_ENABLE_SMASK
)))
1245 goto unlock
; /* already enabled */
1247 /* IMPORTANT: only clear free and fill if transitioning 0 -> 1 */
1257 /* the alloc lock insures no fast path allocation */
1258 reset_buffers_allocated(sc
);
1261 * Clear all per-context errors. Some of these will be set when
1262 * we are re-enabling after a context halt. Now that the context
1263 * is disabled, the halt will not clear until after the PIO init
1264 * engine runs below.
1266 reg
= read_kctxt_csr(dd
, sc
->hw_context
, SC(ERR_STATUS
));
1268 write_kctxt_csr(dd
, sc
->hw_context
, SC(ERR_CLEAR
), reg
);
1271 * The HW PIO initialization engine can handle only one init
1272 * request at a time. Serialize access to each device's engine.
1274 spin_lock(&dd
->sc_init_lock
);
1276 * Since access to this code block is serialized and
1277 * each access waits for the initialization to complete
1278 * before releasing the lock, the PIO initialization engine
1279 * should not be in use, so we don't have to wait for the
1280 * InProgress bit to go down.
1282 pio
= ((sc
->hw_context
& SEND_PIO_INIT_CTXT_PIO_CTXT_NUM_MASK
) <<
1283 SEND_PIO_INIT_CTXT_PIO_CTXT_NUM_SHIFT
) |
1284 SEND_PIO_INIT_CTXT_PIO_SINGLE_CTXT_INIT_SMASK
;
1285 write_csr(dd
, SEND_PIO_INIT_CTXT
, pio
);
1287 * Wait until the engine is done. Give the chip the required time
1288 * so, hopefully, we read the register just once.
1291 ret
= pio_init_wait_progress(dd
);
1292 spin_unlock(&dd
->sc_init_lock
);
1295 "sctxt%u(%u): Context not enabled due to init failure %d\n",
1296 sc
->sw_index
, sc
->hw_context
, ret
);
1301 * All is well. Enable the context.
1303 sc_ctrl
|= SC(CTRL_CTXT_ENABLE_SMASK
);
1304 write_kctxt_csr(dd
, sc
->hw_context
, SC(CTRL
), sc_ctrl
);
1306 * Read SendCtxtCtrl to force the write out and prevent a timing
1307 * hazard where a PIO write may reach the context before the enable.
1309 read_kctxt_csr(dd
, sc
->hw_context
, SC(CTRL
));
1310 sc
->flags
|= SCF_ENABLED
;
1313 spin_unlock_irqrestore(&sc
->alloc_lock
, flags
);
1318 /* force a credit return on the context */
1319 void sc_return_credits(struct send_context
*sc
)
1324 /* a 0->1 transition schedules a credit return */
1325 write_kctxt_csr(sc
->dd
, sc
->hw_context
, SC(CREDIT_FORCE
),
1326 SC(CREDIT_FORCE_FORCE_RETURN_SMASK
));
1328 * Ensure that the write is flushed and the credit return is
1329 * scheduled. We care more about the 0 -> 1 transition.
1331 read_kctxt_csr(sc
->dd
, sc
->hw_context
, SC(CREDIT_FORCE
));
1332 /* set back to 0 for next time */
1333 write_kctxt_csr(sc
->dd
, sc
->hw_context
, SC(CREDIT_FORCE
), 0);
1336 /* allow all in-flight packets to drain on the context */
1337 void sc_flush(struct send_context
*sc
)
1342 sc_wait_for_packet_egress(sc
, 1);
1345 /* drop all packets on the context, no waiting until they are sent */
1346 void sc_drop(struct send_context
*sc
)
1351 dd_dev_info(sc
->dd
, "%s: context %u(%u) - not implemented\n",
1352 __func__
, sc
->sw_index
, sc
->hw_context
);
1356 * Start the software reaction to a context halt or SPC freeze:
1357 * - mark the context as halted or frozen
1358 * - stop buffer allocations
1360 * Called from the error interrupt. Other work is deferred until
1361 * out of the interrupt.
1363 void sc_stop(struct send_context
*sc
, int flag
)
1365 unsigned long flags
;
1367 /* mark the context */
1370 /* stop buffer allocations */
1371 spin_lock_irqsave(&sc
->alloc_lock
, flags
);
1372 sc
->flags
&= ~SCF_ENABLED
;
1373 spin_unlock_irqrestore(&sc
->alloc_lock
, flags
);
1374 wake_up(&sc
->halt_wait
);
1377 #define BLOCK_DWORDS (PIO_BLOCK_SIZE / sizeof(u32))
1378 #define dwords_to_blocks(x) DIV_ROUND_UP(x, BLOCK_DWORDS)
1381 * The send context buffer "allocator".
1383 * @sc: the PIO send context we are allocating from
1384 * @len: length of whole packet - including PBC - in dwords
1385 * @cb: optional callback to call when the buffer is finished sending
1386 * @arg: argument for cb
1388 * Return a pointer to a PIO buffer if successful, NULL if not enough room.
1390 struct pio_buf
*sc_buffer_alloc(struct send_context
*sc
, u32 dw_len
,
1391 pio_release_cb cb
, void *arg
)
1393 struct pio_buf
*pbuf
= NULL
;
1394 unsigned long flags
;
1395 unsigned long avail
;
1396 unsigned long blocks
= dwords_to_blocks(dw_len
);
1401 spin_lock_irqsave(&sc
->alloc_lock
, flags
);
1402 if (!(sc
->flags
& SCF_ENABLED
)) {
1403 spin_unlock_irqrestore(&sc
->alloc_lock
, flags
);
1408 avail
= (unsigned long)sc
->credits
- (sc
->fill
- sc
->alloc_free
);
1409 if (blocks
> avail
) {
1410 /* not enough room */
1411 if (unlikely(trycount
)) { /* already tried to get more room */
1412 spin_unlock_irqrestore(&sc
->alloc_lock
, flags
);
1415 /* copy from receiver cache line and recalculate */
1416 sc
->alloc_free
= ACCESS_ONCE(sc
->free
);
1418 (unsigned long)sc
->credits
-
1419 (sc
->fill
- sc
->alloc_free
);
1420 if (blocks
> avail
) {
1421 /* still no room, actively update */
1422 sc_release_update(sc
);
1423 sc
->alloc_free
= ACCESS_ONCE(sc
->free
);
1429 /* there is enough room */
1432 this_cpu_inc(*sc
->buffers_allocated
);
1434 /* read this once */
1437 /* "allocate" the buffer */
1439 fill_wrap
= sc
->fill_wrap
;
1440 sc
->fill_wrap
+= blocks
;
1441 if (sc
->fill_wrap
>= sc
->credits
)
1442 sc
->fill_wrap
= sc
->fill_wrap
- sc
->credits
;
1445 * Fill the parts that the releaser looks at before moving the head.
1446 * The only necessary piece is the sent_at field. The credits
1447 * we have just allocated cannot have been returned yet, so the
1448 * cb and arg will not be looked at for a "while". Put them
1449 * on this side of the memory barrier anyway.
1451 pbuf
= &sc
->sr
[head
].pbuf
;
1452 pbuf
->sent_at
= sc
->fill
;
1455 pbuf
->sc
= sc
; /* could be filled in at sc->sr init time */
1456 /* make sure this is in memory before updating the head */
1458 /* calculate next head index, do not store */
1460 if (next
>= sc
->sr_size
)
1463 * update the head - must be last! - the releaser can look at fields
1464 * in pbuf once we move the head
1468 spin_unlock_irqrestore(&sc
->alloc_lock
, flags
);
1470 /* finish filling in the buffer outside the lock */
1471 pbuf
->start
= sc
->base_addr
+ fill_wrap
* PIO_BLOCK_SIZE
;
1472 pbuf
->end
= sc
->base_addr
+ sc
->size
;
1473 pbuf
->qw_written
= 0;
1474 pbuf
->carry_bytes
= 0;
1475 pbuf
->carry
.val64
= 0;
1481 * There are at least two entities that can turn on credit return
1482 * interrupts and they can overlap. Avoid problems by implementing
1483 * a count scheme that is enforced by a lock. The lock is needed because
1484 * the count and CSR write must be paired.
1488 * Start credit return interrupts. This is managed by a count. If already
1489 * on, just increment the count.
1491 void sc_add_credit_return_intr(struct send_context
*sc
)
1493 unsigned long flags
;
1495 /* lock must surround both the count change and the CSR update */
1496 spin_lock_irqsave(&sc
->credit_ctrl_lock
, flags
);
1497 if (sc
->credit_intr_count
== 0) {
1498 sc
->credit_ctrl
|= SC(CREDIT_CTRL_CREDIT_INTR_SMASK
);
1499 write_kctxt_csr(sc
->dd
, sc
->hw_context
,
1500 SC(CREDIT_CTRL
), sc
->credit_ctrl
);
1502 sc
->credit_intr_count
++;
1503 spin_unlock_irqrestore(&sc
->credit_ctrl_lock
, flags
);
1507 * Stop credit return interrupts. This is managed by a count. Decrement the
1508 * count, if the last user, then turn the credit interrupts off.
1510 void sc_del_credit_return_intr(struct send_context
*sc
)
1512 unsigned long flags
;
1514 WARN_ON(sc
->credit_intr_count
== 0);
1516 /* lock must surround both the count change and the CSR update */
1517 spin_lock_irqsave(&sc
->credit_ctrl_lock
, flags
);
1518 sc
->credit_intr_count
--;
1519 if (sc
->credit_intr_count
== 0) {
1520 sc
->credit_ctrl
&= ~SC(CREDIT_CTRL_CREDIT_INTR_SMASK
);
1521 write_kctxt_csr(sc
->dd
, sc
->hw_context
,
1522 SC(CREDIT_CTRL
), sc
->credit_ctrl
);
1524 spin_unlock_irqrestore(&sc
->credit_ctrl_lock
, flags
);
1528 * The caller must be careful when calling this. All needint calls
1529 * must be paired with !needint.
1531 void hfi1_sc_wantpiobuf_intr(struct send_context
*sc
, u32 needint
)
1534 sc_add_credit_return_intr(sc
);
1536 sc_del_credit_return_intr(sc
);
1537 trace_hfi1_wantpiointr(sc
, needint
, sc
->credit_ctrl
);
1540 sc_return_credits(sc
);
1545 * sc_piobufavail - callback when a PIO buffer is available
1546 * @sc: the send context
1548 * This is called from the interrupt handler when a PIO buffer is
1549 * available after hfi1_verbs_send() returned an error that no buffers were
1550 * available. Disable the interrupt if there are no more QPs waiting.
1552 static void sc_piobufavail(struct send_context
*sc
)
1554 struct hfi1_devdata
*dd
= sc
->dd
;
1555 struct hfi1_ibdev
*dev
= &dd
->verbs_dev
;
1556 struct list_head
*list
;
1557 struct rvt_qp
*qps
[PIO_WAIT_BATCH_SIZE
];
1559 struct hfi1_qp_priv
*priv
;
1560 unsigned long flags
;
1563 if (dd
->send_contexts
[sc
->sw_index
].type
!= SC_KERNEL
&&
1564 dd
->send_contexts
[sc
->sw_index
].type
!= SC_VL15
)
1566 list
= &sc
->piowait
;
1568 * Note: checking that the piowait list is empty and clearing
1569 * the buffer available interrupt needs to be atomic or we
1570 * could end up with QPs on the wait list with the interrupt
1573 write_seqlock_irqsave(&dev
->iowait_lock
, flags
);
1574 while (!list_empty(list
)) {
1575 struct iowait
*wait
;
1577 if (n
== ARRAY_SIZE(qps
))
1579 wait
= list_first_entry(list
, struct iowait
, list
);
1580 qp
= iowait_to_qp(wait
);
1582 list_del_init(&priv
->s_iowait
.list
);
1583 priv
->s_iowait
.lock
= NULL
;
1584 /* refcount held until actual wake up */
1588 * If there had been waiters and there are more
1589 * insure that we redo the force to avoid a potential hang.
1592 hfi1_sc_wantpiobuf_intr(sc
, 0);
1593 if (!list_empty(list
))
1594 hfi1_sc_wantpiobuf_intr(sc
, 1);
1596 write_sequnlock_irqrestore(&dev
->iowait_lock
, flags
);
1598 for (i
= 0; i
< n
; i
++)
1599 hfi1_qp_wakeup(qps
[i
],
1600 RVT_S_WAIT_PIO
| RVT_S_WAIT_PIO_DRAIN
);
1603 /* translate a send credit update to a bit code of reasons */
1604 static inline int fill_code(u64 hw_free
)
1608 if (hw_free
& CR_STATUS_SMASK
)
1609 code
|= PRC_STATUS_ERR
;
1610 if (hw_free
& CR_CREDIT_RETURN_DUE_TO_PBC_SMASK
)
1612 if (hw_free
& CR_CREDIT_RETURN_DUE_TO_THRESHOLD_SMASK
)
1613 code
|= PRC_THRESHOLD
;
1614 if (hw_free
& CR_CREDIT_RETURN_DUE_TO_ERR_SMASK
)
1615 code
|= PRC_FILL_ERR
;
1616 if (hw_free
& CR_CREDIT_RETURN_DUE_TO_FORCE_SMASK
)
1617 code
|= PRC_SC_DISABLE
;
1621 /* use the jiffies compare to get the wrap right */
1622 #define sent_before(a, b) time_before(a, b) /* a < b */
1625 * The send context buffer "releaser".
1627 void sc_release_update(struct send_context
*sc
)
1629 struct pio_buf
*pbuf
;
1632 unsigned long old_free
;
1634 unsigned long extra
;
1635 unsigned long flags
;
1641 spin_lock_irqsave(&sc
->release_lock
, flags
);
1643 hw_free
= le64_to_cpu(*sc
->hw_free
); /* volatile read */
1644 old_free
= sc
->free
;
1645 extra
= (((hw_free
& CR_COUNTER_SMASK
) >> CR_COUNTER_SHIFT
)
1646 - (old_free
& CR_COUNTER_MASK
))
1648 free
= old_free
+ extra
;
1649 trace_hfi1_piofree(sc
, extra
);
1651 /* call sent buffer callbacks */
1652 code
= -1; /* code not yet set */
1653 head
= ACCESS_ONCE(sc
->sr_head
); /* snapshot the head */
1655 while (head
!= tail
) {
1656 pbuf
= &sc
->sr
[tail
].pbuf
;
1658 if (sent_before(free
, pbuf
->sent_at
)) {
1663 if (code
< 0) /* fill in code on first user */
1664 code
= fill_code(hw_free
);
1665 (*pbuf
->cb
)(pbuf
->arg
, code
);
1669 if (tail
>= sc
->sr_size
)
1673 /* make sure tail is updated before free */
1676 spin_unlock_irqrestore(&sc
->release_lock
, flags
);
1681 * Send context group releaser. Argument is the send context that caused
1682 * the interrupt. Called from the send context interrupt handler.
1684 * Call release on all contexts in the group.
1686 * This routine takes the sc_lock without an irqsave because it is only
1687 * called from an interrupt handler. Adjust if that changes.
1689 void sc_group_release_update(struct hfi1_devdata
*dd
, u32 hw_context
)
1691 struct send_context
*sc
;
1695 spin_lock(&dd
->sc_lock
);
1696 sw_index
= dd
->hw_to_sw
[hw_context
];
1697 if (unlikely(sw_index
>= dd
->num_send_contexts
)) {
1698 dd_dev_err(dd
, "%s: invalid hw (%u) to sw (%u) mapping\n",
1699 __func__
, hw_context
, sw_index
);
1702 sc
= dd
->send_contexts
[sw_index
].sc
;
1706 gc
= group_context(hw_context
, sc
->group
);
1707 gc_end
= gc
+ group_size(sc
->group
);
1708 for (; gc
< gc_end
; gc
++) {
1709 sw_index
= dd
->hw_to_sw
[gc
];
1710 if (unlikely(sw_index
>= dd
->num_send_contexts
)) {
1712 "%s: invalid hw (%u) to sw (%u) mapping\n",
1713 __func__
, hw_context
, sw_index
);
1716 sc_release_update(dd
->send_contexts
[sw_index
].sc
);
1719 spin_unlock(&dd
->sc_lock
);
1723 * pio_select_send_context_vl() - select send context
1725 * @selector: a spreading factor
1728 * This function returns a send context based on the selector and a vl.
1729 * The mapping fields are protected by RCU
1731 struct send_context
*pio_select_send_context_vl(struct hfi1_devdata
*dd
,
1732 u32 selector
, u8 vl
)
1734 struct pio_vl_map
*m
;
1735 struct pio_map_elem
*e
;
1736 struct send_context
*rval
;
1739 * NOTE This should only happen if SC->VL changed after the initial
1740 * checks on the QP/AH
1741 * Default will return VL0's send context below
1743 if (unlikely(vl
>= num_vls
)) {
1749 m
= rcu_dereference(dd
->pio_map
);
1752 return dd
->vld
[0].sc
;
1754 e
= m
->map
[vl
& m
->mask
];
1755 rval
= e
->ksc
[selector
& e
->mask
];
1759 rval
= !rval
? dd
->vld
[0].sc
: rval
;
1764 * pio_select_send_context_sc() - select send context
1766 * @selector: a spreading factor
1767 * @sc5: the 5 bit sc
1769 * This function returns an send context based on the selector and an sc
1771 struct send_context
*pio_select_send_context_sc(struct hfi1_devdata
*dd
,
1772 u32 selector
, u8 sc5
)
1774 u8 vl
= sc_to_vlt(dd
, sc5
);
1776 return pio_select_send_context_vl(dd
, selector
, vl
);
1780 * Free the indicated map struct
1782 static void pio_map_free(struct pio_vl_map
*m
)
1786 for (i
= 0; m
&& i
< m
->actual_vls
; i
++)
1792 * Handle RCU callback
1794 static void pio_map_rcu_callback(struct rcu_head
*list
)
1796 struct pio_vl_map
*m
= container_of(list
, struct pio_vl_map
, list
);
1802 * Set credit return threshold for the kernel send context
1804 static void set_threshold(struct hfi1_devdata
*dd
, int scontext
, int i
)
1808 thres
= min(sc_percent_to_threshold(dd
->kernel_send_context
[scontext
],
1810 sc_mtu_to_threshold(dd
->kernel_send_context
[scontext
],
1812 dd
->rcd
[0]->rcvhdrqentsize
));
1813 sc_set_cr_threshold(dd
->kernel_send_context
[scontext
], thres
);
1817 * pio_map_init - called when #vls change
1819 * @port: port number
1820 * @num_vls: number of vls
1821 * @vl_scontexts: per vl send context mapping (optional)
1823 * This routine changes the mapping based on the number of vls.
1825 * vl_scontexts is used to specify a non-uniform vl/send context
1826 * loading. NULL implies auto computing the loading and giving each
1827 * VL an uniform distribution of send contexts per VL.
1829 * The auto algorithm computers the sc_per_vl and the number of extra
1830 * send contexts. Any extra send contexts are added from the last VL
1833 * rcu locking is used here to control access to the mapping fields.
1835 * If either the num_vls or num_send_contexts are non-power of 2, the
1836 * array sizes in the struct pio_vl_map and the struct pio_map_elem are
1837 * rounded up to the next highest power of 2 and the first entry is
1838 * reused in a round robin fashion.
1840 * If an error occurs the map change is not done and the mapping is not
1844 int pio_map_init(struct hfi1_devdata
*dd
, u8 port
, u8 num_vls
, u8
*vl_scontexts
)
1847 int extra
, sc_per_vl
;
1849 int num_kernel_send_contexts
= 0;
1850 u8 lvl_scontexts
[OPA_MAX_VLS
];
1851 struct pio_vl_map
*oldmap
, *newmap
;
1853 if (!vl_scontexts
) {
1854 for (i
= 0; i
< dd
->num_send_contexts
; i
++)
1855 if (dd
->send_contexts
[i
].type
== SC_KERNEL
)
1856 num_kernel_send_contexts
++;
1857 /* truncate divide */
1858 sc_per_vl
= num_kernel_send_contexts
/ num_vls
;
1860 extra
= num_kernel_send_contexts
% num_vls
;
1861 vl_scontexts
= lvl_scontexts
;
1862 /* add extras from last vl down */
1863 for (i
= num_vls
- 1; i
>= 0; i
--, extra
--)
1864 vl_scontexts
[i
] = sc_per_vl
+ (extra
> 0 ? 1 : 0);
1867 newmap
= kzalloc(sizeof(*newmap
) +
1868 roundup_pow_of_two(num_vls
) *
1869 sizeof(struct pio_map_elem
*),
1873 newmap
->actual_vls
= num_vls
;
1874 newmap
->vls
= roundup_pow_of_two(num_vls
);
1875 newmap
->mask
= (1 << ilog2(newmap
->vls
)) - 1;
1876 for (i
= 0; i
< newmap
->vls
; i
++) {
1877 /* save for wrap around */
1878 int first_scontext
= scontext
;
1880 if (i
< newmap
->actual_vls
) {
1881 int sz
= roundup_pow_of_two(vl_scontexts
[i
]);
1883 /* only allocate once */
1884 newmap
->map
[i
] = kzalloc(sizeof(*newmap
->map
[i
]) +
1888 if (!newmap
->map
[i
])
1890 newmap
->map
[i
]->mask
= (1 << ilog2(sz
)) - 1;
1892 * assign send contexts and
1893 * adjust credit return threshold
1895 for (j
= 0; j
< sz
; j
++) {
1896 if (dd
->kernel_send_context
[scontext
]) {
1897 newmap
->map
[i
]->ksc
[j
] =
1898 dd
->kernel_send_context
[scontext
];
1899 set_threshold(dd
, scontext
, i
);
1901 if (++scontext
>= first_scontext
+
1903 /* wrap back to first send context */
1904 scontext
= first_scontext
;
1907 /* just re-use entry without allocating */
1908 newmap
->map
[i
] = newmap
->map
[i
% num_vls
];
1910 scontext
= first_scontext
+ vl_scontexts
[i
];
1912 /* newmap in hand, save old map */
1913 spin_lock_irq(&dd
->pio_map_lock
);
1914 oldmap
= rcu_dereference_protected(dd
->pio_map
,
1915 lockdep_is_held(&dd
->pio_map_lock
));
1917 /* publish newmap */
1918 rcu_assign_pointer(dd
->pio_map
, newmap
);
1920 spin_unlock_irq(&dd
->pio_map_lock
);
1921 /* success, free any old map after grace period */
1923 call_rcu(&oldmap
->list
, pio_map_rcu_callback
);
1926 /* free any partial allocation */
1927 pio_map_free(newmap
);
1931 void free_pio_map(struct hfi1_devdata
*dd
)
1933 /* Free PIO map if allocated */
1934 if (rcu_access_pointer(dd
->pio_map
)) {
1935 spin_lock_irq(&dd
->pio_map_lock
);
1936 pio_map_free(rcu_access_pointer(dd
->pio_map
));
1937 RCU_INIT_POINTER(dd
->pio_map
, NULL
);
1938 spin_unlock_irq(&dd
->pio_map_lock
);
1941 kfree(dd
->kernel_send_context
);
1942 dd
->kernel_send_context
= NULL
;
1945 int init_pervl_scs(struct hfi1_devdata
*dd
)
1948 u64 mask
, all_vl_mask
= (u64
)0x80ff; /* VLs 0-7, 15 */
1949 u64 data_vls_mask
= (u64
)0x00ff; /* VLs 0-7 */
1951 struct hfi1_pportdata
*ppd
= dd
->pport
;
1953 dd
->vld
[15].sc
= sc_alloc(dd
, SC_VL15
,
1954 dd
->rcd
[0]->rcvhdrqentsize
, dd
->node
);
1955 if (!dd
->vld
[15].sc
)
1958 hfi1_init_ctxt(dd
->vld
[15].sc
);
1959 dd
->vld
[15].mtu
= enum_to_mtu(OPA_MTU_2048
);
1961 dd
->kernel_send_context
= kzalloc_node(dd
->num_send_contexts
*
1962 sizeof(struct send_context
*),
1963 GFP_KERNEL
, dd
->node
);
1964 if (!dd
->kernel_send_context
)
1967 dd
->kernel_send_context
[0] = dd
->vld
[15].sc
;
1969 for (i
= 0; i
< num_vls
; i
++) {
1971 * Since this function does not deal with a specific
1972 * receive context but we need the RcvHdrQ entry size,
1973 * use the size from rcd[0]. It is guaranteed to be
1974 * valid at this point and will remain the same for all
1977 dd
->vld
[i
].sc
= sc_alloc(dd
, SC_KERNEL
,
1978 dd
->rcd
[0]->rcvhdrqentsize
, dd
->node
);
1981 dd
->kernel_send_context
[i
+ 1] = dd
->vld
[i
].sc
;
1982 hfi1_init_ctxt(dd
->vld
[i
].sc
);
1983 /* non VL15 start with the max MTU */
1984 dd
->vld
[i
].mtu
= hfi1_max_mtu
;
1986 for (i
= num_vls
; i
< INIT_SC_PER_VL
* num_vls
; i
++) {
1987 dd
->kernel_send_context
[i
+ 1] =
1988 sc_alloc(dd
, SC_KERNEL
, dd
->rcd
[0]->rcvhdrqentsize
, dd
->node
);
1989 if (!dd
->kernel_send_context
[i
+ 1])
1991 hfi1_init_ctxt(dd
->kernel_send_context
[i
+ 1]);
1994 sc_enable(dd
->vld
[15].sc
);
1995 ctxt
= dd
->vld
[15].sc
->hw_context
;
1996 mask
= all_vl_mask
& ~(1LL << 15);
1997 write_kctxt_csr(dd
, ctxt
, SC(CHECK_VL
), mask
);
1999 "Using send context %u(%u) for VL15\n",
2000 dd
->vld
[15].sc
->sw_index
, ctxt
);
2002 for (i
= 0; i
< num_vls
; i
++) {
2003 sc_enable(dd
->vld
[i
].sc
);
2004 ctxt
= dd
->vld
[i
].sc
->hw_context
;
2005 mask
= all_vl_mask
& ~(data_vls_mask
);
2006 write_kctxt_csr(dd
, ctxt
, SC(CHECK_VL
), mask
);
2008 for (i
= num_vls
; i
< INIT_SC_PER_VL
* num_vls
; i
++) {
2009 sc_enable(dd
->kernel_send_context
[i
+ 1]);
2010 ctxt
= dd
->kernel_send_context
[i
+ 1]->hw_context
;
2011 mask
= all_vl_mask
& ~(data_vls_mask
);
2012 write_kctxt_csr(dd
, ctxt
, SC(CHECK_VL
), mask
);
2015 if (pio_map_init(dd
, ppd
->port
- 1, num_vls
, NULL
))
2020 for (i
= 0; i
< num_vls
; i
++) {
2021 sc_free(dd
->vld
[i
].sc
);
2022 dd
->vld
[i
].sc
= NULL
;
2025 for (i
= num_vls
; i
< INIT_SC_PER_VL
* num_vls
; i
++)
2026 sc_free(dd
->kernel_send_context
[i
+ 1]);
2028 kfree(dd
->kernel_send_context
);
2029 dd
->kernel_send_context
= NULL
;
2032 sc_free(dd
->vld
[15].sc
);
2036 int init_credit_return(struct hfi1_devdata
*dd
)
2041 dd
->cr_base
= kcalloc(
2042 node_affinity
.num_possible_nodes
,
2043 sizeof(struct credit_return_base
),
2049 for_each_node_with_cpus(i
) {
2050 int bytes
= TXE_NUM_CONTEXTS
* sizeof(struct credit_return
);
2052 set_dev_node(&dd
->pcidev
->dev
, i
);
2053 dd
->cr_base
[i
].va
= dma_zalloc_coherent(
2056 &dd
->cr_base
[i
].dma
,
2058 if (!dd
->cr_base
[i
].va
) {
2059 set_dev_node(&dd
->pcidev
->dev
, dd
->node
);
2061 "Unable to allocate credit return DMA range for NUMA %d\n",
2067 set_dev_node(&dd
->pcidev
->dev
, dd
->node
);
2074 void free_credit_return(struct hfi1_devdata
*dd
)
2080 for (i
= 0; i
< node_affinity
.num_possible_nodes
; i
++) {
2081 if (dd
->cr_base
[i
].va
) {
2082 dma_free_coherent(&dd
->pcidev
->dev
,
2084 sizeof(struct credit_return
),
2086 dd
->cr_base
[i
].dma
);