drivers/infiniband/hw/hfi1/twsi.c

   1 /*
   2  * Copyright(c) 2015, 2016 Intel Corporation.
   3  *
   4  * This file is provided under a dual BSD/GPLv2 license.  When using or
   5  * redistributing this file, you may do so under either license.
   6  *
   7  * GPL LICENSE SUMMARY
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of version 2 of the GNU General Public License as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * BSD LICENSE
  19  *
  20  * Redistribution and use in source and binary forms, with or without
  21  * modification, are permitted provided that the following conditions
  22  * are met:
  23  *
  24  *  - Redistributions of source code must retain the above copyright
  25  *    notice, this list of conditions and the following disclaimer.
  26  *  - Redistributions in binary form must reproduce the above copyright
  27  *    notice, this list of conditions and the following disclaimer in
  28  *    the documentation and/or other materials provided with the
  29  *    distribution.
  30  *  - Neither the name of Intel Corporation nor the names of its
  31  *    contributors may be used to endorse or promote products derived
  32  *    from this software without specific prior written permission.
  33  *
  34  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  35  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  36  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  37  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  38  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  39  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  40  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  41  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  42  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  43  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  44  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  45  *
  46  */
  47
  48 #include <linux/delay.h>
  49 #include <linux/pci.h>
  50 #include <linux/vmalloc.h>
  51
  52 #include "hfi.h"
  53 #include "twsi.h"
  54
  55 /*
  56  * "Two Wire Serial Interface" support.
  57  *
  58  * Originally written for a not-quite-i2c serial eeprom, which is
  59  * still used on some supported boards. Later boards have added a
  60  * variety of other uses, most board-specific, so the bit-boffing
  61  * part has been split off to this file, while the other parts
  62  * have been moved to chip-specific files.
  63  *
  64  * We have also dropped all pretense of fully generic (e.g. pretend
  65  * we don't know whether '1' is the higher voltage) interface, as
  66  * the restrictions of the generic i2c interface (e.g. no access from
  67  * driver itself) make it unsuitable for this use.
  68  */
  69
  70 #define READ_CMD 1
  71 #define WRITE_CMD 0
  72
  73 /**
  74  * i2c_wait_for_writes - wait for a write
  75  * @dd: the hfi1_ib device
  76  *
  77  * We use this instead of udelay directly, so we can make sure
  78  * that previous register writes have been flushed all the way
  79  * to the chip.  Since we are delaying anyway, the cost doesn't
  80  * hurt, and makes the bit twiddling more regular
  81  */
  82 static void i2c_wait_for_writes(struct hfi1_devdata *dd, u32 target)
  83 {
  84         /*
  85          * implicit read of EXTStatus is as good as explicit
  86          * read of scratch, if all we want to do is flush
  87          * writes.
  88          */
  89         hfi1_gpio_mod(dd, target, 0, 0, 0);
  90         rmb(); /* inlined, so prevent compiler reordering */
  91 }
  92
  93 /*
  94  * QSFP modules are allowed to hold SCL low for 500uSec. Allow twice that
  95  * for "almost compliant" modules
  96  */
  97 #define SCL_WAIT_USEC 1000
  98
  99 /* BUF_WAIT is time bus must be free between STOP or ACK and to next START.
 100  * Should be 20, but some chips need more.
 101  */
 102 #define TWSI_BUF_WAIT_USEC 60
 103
 104 static void scl_out(struct hfi1_devdata *dd, u32 target, u8 bit)
 105 {
 106         u32 mask;
 107
 108         udelay(1);
 109
 110         mask = QSFP_HFI0_I2CCLK;
 111
 112         /* SCL is meant to be bare-drain, so never set "OUT", just DIR */
 113         hfi1_gpio_mod(dd, target, 0, bit ? 0 : mask, mask);
 114
 115         /*
 116          * Allow for slow slaves by simple
 117          * delay for falling edge, sampling on rise.
 118          */
 119         if (!bit) {
 120                 udelay(2);
 121         } else {
 122                 int rise_usec;
 123
 124                 for (rise_usec = SCL_WAIT_USEC; rise_usec > 0; rise_usec -= 2) {
 125                         if (mask & hfi1_gpio_mod(dd, target, 0, 0, 0))
 126                                 break;
 127                         udelay(2);
 128                 }
 129                 if (rise_usec <= 0)
 130                         dd_dev_err(dd, "SCL interface stuck low > %d uSec\n",
 131                                    SCL_WAIT_USEC);
 132         }
 133         i2c_wait_for_writes(dd, target);
 134 }
 135
 136 static u8 scl_in(struct hfi1_devdata *dd, u32 target, int wait)
 137 {
 138         u32 read_val, mask;
 139
 140         mask = QSFP_HFI0_I2CCLK;
 141         /* SCL is meant to be bare-drain, so never set "OUT", just DIR */
 142         hfi1_gpio_mod(dd, target, 0, 0, mask);
 143         read_val = hfi1_gpio_mod(dd, target, 0, 0, 0);
 144         if (wait)
 145                 i2c_wait_for_writes(dd, target);
 146         return (read_val & mask) >> GPIO_SCL_NUM;
 147 }
 148
 149 static void sda_out(struct hfi1_devdata *dd, u32 target, u8 bit)
 150 {
 151         u32 mask;
 152
 153         mask = QSFP_HFI0_I2CDAT;
 154
 155         /* SDA is meant to be bare-drain, so never set "OUT", just DIR */
 156         hfi1_gpio_mod(dd, target, 0, bit ? 0 : mask, mask);
 157
 158         i2c_wait_for_writes(dd, target);
 159         udelay(2);
 160 }
 161
 162 static u8 sda_in(struct hfi1_devdata *dd, u32 target, int wait)
 163 {
 164         u32 read_val, mask;
 165
 166         mask = QSFP_HFI0_I2CDAT;
 167         /* SDA is meant to be bare-drain, so never set "OUT", just DIR */
 168         hfi1_gpio_mod(dd, target, 0, 0, mask);
 169         read_val = hfi1_gpio_mod(dd, target, 0, 0, 0);
 170         if (wait)
 171                 i2c_wait_for_writes(dd, target);
 172         return (read_val & mask) >> GPIO_SDA_NUM;
 173 }
 174
 175 /**
 176  * i2c_ackrcv - see if ack following write is true
 177  * @dd: the hfi1_ib device
 178  */
 179 static int i2c_ackrcv(struct hfi1_devdata *dd, u32 target)
 180 {
 181         u8 ack_received;
 182
 183         /* AT ENTRY SCL = LOW */
 184         /* change direction, ignore data */
 185         ack_received = sda_in(dd, target, 1);
 186         scl_out(dd, target, 1);
 187         ack_received = sda_in(dd, target, 1) == 0;
 188         scl_out(dd, target, 0);
 189         return ack_received;
 190 }
 191
 192 static void stop_cmd(struct hfi1_devdata *dd, u32 target);
 193
 194 /**
 195  * rd_byte - read a byte, sending STOP on last, else ACK
 196  * @dd: the hfi1_ib device
 197  *
 198  * Returns byte shifted out of device
 199  */
 200 static int rd_byte(struct hfi1_devdata *dd, u32 target, int last)
 201 {
 202         int bit_cntr, data;
 203
 204         data = 0;
 205
 206         for (bit_cntr = 7; bit_cntr >= 0; --bit_cntr) {
 207                 data <<= 1;
 208                 scl_out(dd, target, 1);
 209                 data |= sda_in(dd, target, 0);
 210                 scl_out(dd, target, 0);
 211         }
 212         if (last) {
 213                 scl_out(dd, target, 1);
 214                 stop_cmd(dd, target);
 215         } else {
 216                 sda_out(dd, target, 0);
 217                 scl_out(dd, target, 1);
 218                 scl_out(dd, target, 0);
 219                 sda_out(dd, target, 1);
 220         }
 221         return data;
 222 }
 223
 224 /**
 225  * wr_byte - write a byte, one bit at a time
 226  * @dd: the hfi1_ib device
 227  * @data: the byte to write
 228  *
 229  * Returns 0 if we got the following ack, otherwise 1
 230  */
 231 static int wr_byte(struct hfi1_devdata *dd, u32 target, u8 data)
 232 {
 233         int bit_cntr;
 234         u8 bit;
 235
 236         for (bit_cntr = 7; bit_cntr >= 0; bit_cntr--) {
 237                 bit = (data >> bit_cntr) & 1;
 238                 sda_out(dd, target, bit);
 239                 scl_out(dd, target, 1);
 240                 scl_out(dd, target, 0);
 241         }
 242         return (!i2c_ackrcv(dd, target)) ? 1 : 0;
 243 }
 244
 245 /*
 246  * issue TWSI start sequence:
 247  * (both clock/data high, clock high, data low while clock is high)
 248  */
 249 static void start_seq(struct hfi1_devdata *dd, u32 target)
 250 {
 251         sda_out(dd, target, 1);
 252         scl_out(dd, target, 1);
 253         sda_out(dd, target, 0);
 254         udelay(1);
 255         scl_out(dd, target, 0);
 256 }
 257
 258 /**
 259  * stop_seq - transmit the stop sequence
 260  * @dd: the hfi1_ib device
 261  *
 262  * (both clock/data low, clock high, data high while clock is high)
 263  */
 264 static void stop_seq(struct hfi1_devdata *dd, u32 target)
 265 {
 266         scl_out(dd, target, 0);
 267         sda_out(dd, target, 0);
 268         scl_out(dd, target, 1);
 269         sda_out(dd, target, 1);
 270 }
 271
 272 /**
 273  * stop_cmd - transmit the stop condition
 274  * @dd: the hfi1_ib device
 275  *
 276  * (both clock/data low, clock high, data high while clock is high)
 277  */
 278 static void stop_cmd(struct hfi1_devdata *dd, u32 target)
 279 {
 280         stop_seq(dd, target);
 281         udelay(TWSI_BUF_WAIT_USEC);
 282 }
 283
 284 /**
 285  * hfi1_twsi_reset - reset I2C communication
 286  * @dd: the hfi1_ib device
 287  * returns 0 if ok, -EIO on error
 288  */
 289 int hfi1_twsi_reset(struct hfi1_devdata *dd, u32 target)
 290 {
 291         int clock_cycles_left = 9;
 292         u32 mask;
 293
 294         /* Both SCL and SDA should be high. If not, there
 295          * is something wrong.
 296          */
 297         mask = QSFP_HFI0_I2CCLK | QSFP_HFI0_I2CDAT;
 298
 299         /*
 300          * Force pins to desired innocuous state.
 301          * This is the default power-on state with out=0 and dir=0,
 302          * So tri-stated and should be floating high (barring HW problems)
 303          */
 304         hfi1_gpio_mod(dd, target, 0, 0, mask);
 305
 306         /* Check if SCL is low, if it is low then we have a slave device
 307          * misbehaving and there is not much we can do.
 308          */
 309         if (!scl_in(dd, target, 0))
 310                 return -EIO;
 311
 312         /* Check if SDA is low, if it is low then we have to clock SDA
 313          * up to 9 times for the device to release the bus
 314          */
 315         while (clock_cycles_left--) {
 316                 if (sda_in(dd, target, 0))
 317                         return 0;
 318                 scl_out(dd, target, 0);
 319                 scl_out(dd, target, 1);
 320         }
 321
 322         return -EIO;
 323 }
 324
 325 #define HFI1_TWSI_START 0x100
 326 #define HFI1_TWSI_STOP 0x200
 327
 328 /* Write byte to TWSI, optionally prefixed with START or suffixed with
 329  * STOP.
 330  * returns 0 if OK (ACK received), else != 0
 331  */
 332 static int twsi_wr(struct hfi1_devdata *dd, u32 target, int data, int flags)
 333 {
 334         int ret = 1;
 335
 336         if (flags & HFI1_TWSI_START)
 337                 start_seq(dd, target);
 338
 339         /* Leaves SCL low (from i2c_ackrcv()) */
 340         ret = wr_byte(dd, target, data);
 341
 342         if (flags & HFI1_TWSI_STOP)
 343                 stop_cmd(dd, target);
 344         return ret;
 345 }
 346
 347 /* Added functionality for IBA7220-based cards */
 348 #define HFI1_TEMP_DEV 0x98
 349
 350 /*
 351  * hfi1_twsi_blk_rd
 352  * General interface for data transfer from twsi devices.
 353  * One vestige of its former role is that it recognizes a device
 354  * HFI1_TWSI_NO_DEV and does the correct operation for the legacy part,
 355  * which responded to all TWSI device codes, interpreting them as
 356  * address within device. On all other devices found on board handled by
 357  * this driver, the device is followed by a N-byte "address" which selects
 358  * the "register" or "offset" within the device from which data should
 359  * be read.
 360  */
 361 int hfi1_twsi_blk_rd(struct hfi1_devdata *dd, u32 target, int dev, int addr,
 362                      void *buffer, int len)
 363 {
 364         u8 *bp = buffer;
 365         int ret = 1;
 366         int i;
 367         int offset_size;
 368
 369         /* obtain the offset size, strip it from the device address */
 370         offset_size = (dev >> 8) & 0xff;
 371         dev &= 0xff;
 372
 373         /* allow at most a 2 byte offset */
 374         if (offset_size > 2)
 375                 goto bail;
 376
 377         if (dev == HFI1_TWSI_NO_DEV) {
 378                 /* legacy not-really-I2C */
 379                 addr = (addr << 1) | READ_CMD;
 380                 ret = twsi_wr(dd, target, addr, HFI1_TWSI_START);
 381         } else {
 382                 /* Actual I2C */
 383                 if (offset_size) {
 384                         ret = twsi_wr(dd, target,
 385                                       dev | WRITE_CMD, HFI1_TWSI_START);
 386                         if (ret) {
 387                                 stop_cmd(dd, target);
 388                                 goto bail;
 389                         }
 390
 391                         for (i = 0; i < offset_size; i++) {
 392                                 ret = twsi_wr(dd, target,
 393                                               (addr >> (i * 8)) & 0xff, 0);
 394                                 udelay(TWSI_BUF_WAIT_USEC);
 395                                 if (ret) {
 396                                         dd_dev_err(dd, "Failed to write byte %d of offset 0x%04X\n",
 397                                                    i, addr);
 398                                         goto bail;
 399                                 }
 400                         }
 401                 }
 402                 ret = twsi_wr(dd, target, dev | READ_CMD, HFI1_TWSI_START);
 403         }
 404         if (ret) {
 405                 stop_cmd(dd, target);
 406                 goto bail;
 407         }
 408
 409         /*
 410          * block devices keeps clocking data out as long as we ack,
 411          * automatically incrementing the address. Some have "pages"
 412          * whose boundaries will not be crossed, but the handling
 413          * of these is left to the caller, who is in a better
 414          * position to know.
 415          */
 416         while (len-- > 0) {
 417                 /*
 418                  * Get and store data, sending ACK if length remaining,
 419                  * else STOP
 420                  */
 421                 *bp++ = rd_byte(dd, target, !len);
 422         }
 423
 424         ret = 0;
 425
 426 bail:
 427         return ret;
 428 }
 429
 430 /*
 431  * hfi1_twsi_blk_wr
 432  * General interface for data transfer to twsi devices.
 433  * One vestige of its former role is that it recognizes a device
 434  * HFI1_TWSI_NO_DEV and does the correct operation for the legacy part,
 435  * which responded to all TWSI device codes, interpreting them as
 436  * address within device. On all other devices found on board handled by
 437  * this driver, the device is followed by a N-byte "address" which selects
 438  * the "register" or "offset" within the device to which data should
 439  * be written.
 440  */
 441 int hfi1_twsi_blk_wr(struct hfi1_devdata *dd, u32 target, int dev, int addr,
 442                      const void *buffer, int len)
 443 {
 444         const u8 *bp = buffer;
 445         int ret = 1;
 446         int i;
 447         int offset_size;
 448
 449         /* obtain the offset size, strip it from the device address */
 450         offset_size = (dev >> 8) & 0xff;
 451         dev &= 0xff;
 452
 453         /* allow at most a 2 byte offset */
 454         if (offset_size > 2)
 455                 goto bail;
 456
 457         if (dev == HFI1_TWSI_NO_DEV) {
 458                 if (twsi_wr(dd, target, (addr << 1) | WRITE_CMD,
 459                             HFI1_TWSI_START)) {
 460                         goto failed_write;
 461                 }
 462         } else {
 463                 /* Real I2C */
 464                 if (twsi_wr(dd, target, dev | WRITE_CMD, HFI1_TWSI_START))
 465                         goto failed_write;
 466         }
 467
 468         for (i = 0; i < offset_size; i++) {
 469                 ret = twsi_wr(dd, target, (addr >> (i * 8)) & 0xff, 0);
 470                 udelay(TWSI_BUF_WAIT_USEC);
 471                 if (ret) {
 472                         dd_dev_err(dd, "Failed to write byte %d of offset 0x%04X\n",
 473                                    i, addr);
 474                         goto bail;
 475                 }
 476         }
 477
 478         for (i = 0; i < len; i++)
 479                 if (twsi_wr(dd, target, *bp++, 0))
 480                         goto failed_write;
 481
 482         ret = 0;
 483
 484 failed_write:
 485         stop_cmd(dd, target);
 486
 487 bail:
 488         return ret;
 489 }