drivers/infiniband/hw/i40iw/i40iw_type.h

   1 /*******************************************************************************
   2 *
   3 * Copyright (c) 2015-2016 Intel Corporation.  All rights reserved.
   4 *
   5 * This software is available to you under a choice of one of two
   6 * licenses.  You may choose to be licensed under the terms of the GNU
   7 * General Public License (GPL) Version 2, available from the file
   8 * COPYING in the main directory of this source tree, or the
   9 * OpenFabrics.org BSD license below:
  10 *
  11 *   Redistribution and use in source and binary forms, with or
  12 *   without modification, are permitted provided that the following
  13 *   conditions are met:
  14 *
  15 *    - Redistributions of source code must retain the above
  16 *       copyright notice, this list of conditions and the following
  17 *       disclaimer.
  18 *
  19 *    - Redistributions in binary form must reproduce the above
  20 *       copyright notice, this list of conditions and the following
  21 *       disclaimer in the documentation and/or other materials
  22 *       provided with the distribution.
  23 *
  24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31 * SOFTWARE.
  32 *
  33 *******************************************************************************/
  34
  35 #ifndef I40IW_TYPE_H
  36 #define I40IW_TYPE_H
  37 #include "i40iw_user.h"
  38 #include "i40iw_hmc.h"
  39 #include "i40iw_vf.h"
  40 #include "i40iw_virtchnl.h"
  41
  42 struct i40iw_cqp_sq_wqe {
  43         u64 buf[I40IW_CQP_WQE_SIZE];
  44 };
  45
  46 struct i40iw_sc_aeqe {
  47         u64 buf[I40IW_AEQE_SIZE];
  48 };
  49
  50 struct i40iw_ceqe {
  51         u64 buf[I40IW_CEQE_SIZE];
  52 };
  53
  54 struct i40iw_cqp_ctx {
  55         u64 buf[I40IW_CQP_CTX_SIZE];
  56 };
  57
  58 struct i40iw_cq_shadow_area {
  59         u64 buf[I40IW_SHADOW_AREA_SIZE];
  60 };
  61
  62 struct i40iw_sc_dev;
  63 struct i40iw_hmc_info;
  64 struct i40iw_vsi_pestat;
  65
  66 struct i40iw_cqp_ops;
  67 struct i40iw_ccq_ops;
  68 struct i40iw_ceq_ops;
  69 struct i40iw_aeq_ops;
  70 struct i40iw_mr_ops;
  71 struct i40iw_cqp_misc_ops;
  72 struct i40iw_pd_ops;
  73 struct i40iw_priv_qp_ops;
  74 struct i40iw_priv_cq_ops;
  75 struct i40iw_hmc_ops;
  76
  77 enum i40iw_page_size {
  78         I40IW_PAGE_SIZE_4K,
  79         I40IW_PAGE_SIZE_2M
  80 };
  81
  82 enum i40iw_resource_indicator_type {
  83         I40IW_RSRC_INDICATOR_TYPE_ADAPTER = 0,
  84         I40IW_RSRC_INDICATOR_TYPE_CQ,
  85         I40IW_RSRC_INDICATOR_TYPE_QP,
  86         I40IW_RSRC_INDICATOR_TYPE_SRQ
  87 };
  88
  89 enum i40iw_hdrct_flags {
  90         DDP_LEN_FLAG = 0x80,
  91         DDP_HDR_FLAG = 0x40,
  92         RDMA_HDR_FLAG = 0x20
  93 };
  94
  95 enum i40iw_term_layers {
  96         LAYER_RDMA = 0,
  97         LAYER_DDP = 1,
  98         LAYER_MPA = 2
  99 };
 100
 101 enum i40iw_term_error_types {
 102         RDMAP_REMOTE_PROT = 1,
 103         RDMAP_REMOTE_OP = 2,
 104         DDP_CATASTROPHIC = 0,
 105         DDP_TAGGED_BUFFER = 1,
 106         DDP_UNTAGGED_BUFFER = 2,
 107         DDP_LLP = 3
 108 };
 109
 110 enum i40iw_term_rdma_errors {
 111         RDMAP_INV_STAG = 0x00,
 112         RDMAP_INV_BOUNDS = 0x01,
 113         RDMAP_ACCESS = 0x02,
 114         RDMAP_UNASSOC_STAG = 0x03,
 115         RDMAP_TO_WRAP = 0x04,
 116         RDMAP_INV_RDMAP_VER = 0x05,
 117         RDMAP_UNEXPECTED_OP = 0x06,
 118         RDMAP_CATASTROPHIC_LOCAL = 0x07,
 119         RDMAP_CATASTROPHIC_GLOBAL = 0x08,
 120         RDMAP_CANT_INV_STAG = 0x09,
 121         RDMAP_UNSPECIFIED = 0xff
 122 };
 123
 124 enum i40iw_term_ddp_errors {
 125         DDP_CATASTROPHIC_LOCAL = 0x00,
 126         DDP_TAGGED_INV_STAG = 0x00,
 127         DDP_TAGGED_BOUNDS = 0x01,
 128         DDP_TAGGED_UNASSOC_STAG = 0x02,
 129         DDP_TAGGED_TO_WRAP = 0x03,
 130         DDP_TAGGED_INV_DDP_VER = 0x04,
 131         DDP_UNTAGGED_INV_QN = 0x01,
 132         DDP_UNTAGGED_INV_MSN_NO_BUF = 0x02,
 133         DDP_UNTAGGED_INV_MSN_RANGE = 0x03,
 134         DDP_UNTAGGED_INV_MO = 0x04,
 135         DDP_UNTAGGED_INV_TOO_LONG = 0x05,
 136         DDP_UNTAGGED_INV_DDP_VER = 0x06
 137 };
 138
 139 enum i40iw_term_mpa_errors {
 140         MPA_CLOSED = 0x01,
 141         MPA_CRC = 0x02,
 142         MPA_MARKER = 0x03,
 143         MPA_REQ_RSP = 0x04,
 144 };
 145
 146 enum i40iw_flush_opcode {
 147         FLUSH_INVALID = 0,
 148         FLUSH_PROT_ERR,
 149         FLUSH_REM_ACCESS_ERR,
 150         FLUSH_LOC_QP_OP_ERR,
 151         FLUSH_REM_OP_ERR,
 152         FLUSH_LOC_LEN_ERR,
 153         FLUSH_GENERAL_ERR,
 154         FLUSH_FATAL_ERR
 155 };
 156
 157 enum i40iw_term_eventtypes {
 158         TERM_EVENT_QP_FATAL,
 159         TERM_EVENT_QP_ACCESS_ERR
 160 };
 161
 162 struct i40iw_terminate_hdr {
 163         u8 layer_etype;
 164         u8 error_code;
 165         u8 hdrct;
 166         u8 rsvd;
 167 };
 168
 169 enum i40iw_debug_flag {
 170         I40IW_DEBUG_NONE        = 0x00000000,
 171         I40IW_DEBUG_ERR         = 0x00000001,
 172         I40IW_DEBUG_INIT        = 0x00000002,
 173         I40IW_DEBUG_DEV         = 0x00000004,
 174         I40IW_DEBUG_CM          = 0x00000008,
 175         I40IW_DEBUG_VERBS       = 0x00000010,
 176         I40IW_DEBUG_PUDA        = 0x00000020,
 177         I40IW_DEBUG_ILQ         = 0x00000040,
 178         I40IW_DEBUG_IEQ         = 0x00000080,
 179         I40IW_DEBUG_QP          = 0x00000100,
 180         I40IW_DEBUG_CQ          = 0x00000200,
 181         I40IW_DEBUG_MR          = 0x00000400,
 182         I40IW_DEBUG_PBLE        = 0x00000800,
 183         I40IW_DEBUG_WQE         = 0x00001000,
 184         I40IW_DEBUG_AEQ         = 0x00002000,
 185         I40IW_DEBUG_CQP         = 0x00004000,
 186         I40IW_DEBUG_HMC         = 0x00008000,
 187         I40IW_DEBUG_USER        = 0x00010000,
 188         I40IW_DEBUG_VIRT        = 0x00020000,
 189         I40IW_DEBUG_DCB         = 0x00040000,
 190         I40IW_DEBUG_CQE         = 0x00800000,
 191         I40IW_DEBUG_ALL         = 0xFFFFFFFF
 192 };
 193
 194 enum i40iw_hw_stats_index_32b {
 195         I40IW_HW_STAT_INDEX_IP4RXDISCARD = 0,
 196         I40IW_HW_STAT_INDEX_IP4RXTRUNC,
 197         I40IW_HW_STAT_INDEX_IP4TXNOROUTE,
 198         I40IW_HW_STAT_INDEX_IP6RXDISCARD,
 199         I40IW_HW_STAT_INDEX_IP6RXTRUNC,
 200         I40IW_HW_STAT_INDEX_IP6TXNOROUTE,
 201         I40IW_HW_STAT_INDEX_TCPRTXSEG,
 202         I40IW_HW_STAT_INDEX_TCPRXOPTERR,
 203         I40IW_HW_STAT_INDEX_TCPRXPROTOERR,
 204         I40IW_HW_STAT_INDEX_MAX_32
 205 };
 206
 207 enum i40iw_hw_stats_index_64b {
 208         I40IW_HW_STAT_INDEX_IP4RXOCTS = 0,
 209         I40IW_HW_STAT_INDEX_IP4RXPKTS,
 210         I40IW_HW_STAT_INDEX_IP4RXFRAGS,
 211         I40IW_HW_STAT_INDEX_IP4RXMCPKTS,
 212         I40IW_HW_STAT_INDEX_IP4TXOCTS,
 213         I40IW_HW_STAT_INDEX_IP4TXPKTS,
 214         I40IW_HW_STAT_INDEX_IP4TXFRAGS,
 215         I40IW_HW_STAT_INDEX_IP4TXMCPKTS,
 216         I40IW_HW_STAT_INDEX_IP6RXOCTS,
 217         I40IW_HW_STAT_INDEX_IP6RXPKTS,
 218         I40IW_HW_STAT_INDEX_IP6RXFRAGS,
 219         I40IW_HW_STAT_INDEX_IP6RXMCPKTS,
 220         I40IW_HW_STAT_INDEX_IP6TXOCTS,
 221         I40IW_HW_STAT_INDEX_IP6TXPKTS,
 222         I40IW_HW_STAT_INDEX_IP6TXFRAGS,
 223         I40IW_HW_STAT_INDEX_IP6TXMCPKTS,
 224         I40IW_HW_STAT_INDEX_TCPRXSEGS,
 225         I40IW_HW_STAT_INDEX_TCPTXSEG,
 226         I40IW_HW_STAT_INDEX_RDMARXRDS,
 227         I40IW_HW_STAT_INDEX_RDMARXSNDS,
 228         I40IW_HW_STAT_INDEX_RDMARXWRS,
 229         I40IW_HW_STAT_INDEX_RDMATXRDS,
 230         I40IW_HW_STAT_INDEX_RDMATXSNDS,
 231         I40IW_HW_STAT_INDEX_RDMATXWRS,
 232         I40IW_HW_STAT_INDEX_RDMAVBND,
 233         I40IW_HW_STAT_INDEX_RDMAVINV,
 234         I40IW_HW_STAT_INDEX_MAX_64
 235 };
 236
 237 struct i40iw_dev_hw_stats_offsets {
 238         u32 stats_offset_32[I40IW_HW_STAT_INDEX_MAX_32];
 239         u32 stats_offset_64[I40IW_HW_STAT_INDEX_MAX_64];
 240 };
 241
 242 struct i40iw_dev_hw_stats {
 243         u64 stats_value_32[I40IW_HW_STAT_INDEX_MAX_32];
 244         u64 stats_value_64[I40IW_HW_STAT_INDEX_MAX_64];
 245 };
 246
 247 struct i40iw_vsi_pestat {
 248         struct i40iw_hw *hw;
 249         struct i40iw_dev_hw_stats hw_stats;
 250         struct i40iw_dev_hw_stats last_read_hw_stats;
 251         struct i40iw_dev_hw_stats_offsets hw_stats_offsets;
 252         struct timer_list stats_timer;
 253         spinlock_t lock; /* rdma stats lock */
 254 };
 255
 256 struct i40iw_hw {
 257         u8 __iomem *hw_addr;
 258         void *dev_context;
 259         struct i40iw_hmc_info hmc;
 260 };
 261
 262 struct i40iw_pfpdu {
 263         struct list_head rxlist;
 264         u32 rcv_nxt;
 265         u32 fps;
 266         u32 max_fpdu_data;
 267         bool mode;
 268         bool mpa_crc_err;
 269         u64 total_ieq_bufs;
 270         u64 fpdu_processed;
 271         u64 bad_seq_num;
 272         u64 crc_err;
 273         u64 no_tx_bufs;
 274         u64 tx_err;
 275         u64 out_of_order;
 276         u64 pmode_count;
 277 };
 278
 279 struct i40iw_sc_pd {
 280         u32 size;
 281         struct i40iw_sc_dev *dev;
 282         u16 pd_id;
 283         int abi_ver;
 284 };
 285
 286 struct i40iw_cqp_quanta {
 287         u64 elem[I40IW_CQP_WQE_SIZE];
 288 };
 289
 290 struct i40iw_sc_cqp {
 291         u32 size;
 292         u64 sq_pa;
 293         u64 host_ctx_pa;
 294         void *back_cqp;
 295         struct i40iw_sc_dev *dev;
 296         enum i40iw_status_code (*process_cqp_sds)(struct i40iw_sc_dev *,
 297                                                   struct i40iw_update_sds_info *);
 298         struct i40iw_dma_mem sdbuf;
 299         struct i40iw_ring sq_ring;
 300         struct i40iw_cqp_quanta *sq_base;
 301         u64 *host_ctx;
 302         u64 *scratch_array;
 303         u32 cqp_id;
 304         u32 sq_size;
 305         u32 hw_sq_size;
 306         u8 struct_ver;
 307         u8 polarity;
 308         bool en_datacenter_tcp;
 309         u8 hmc_profile;
 310         u8 enabled_vf_count;
 311         u8 timeout_count;
 312 };
 313
 314 struct i40iw_sc_aeq {
 315         u32 size;
 316         u64 aeq_elem_pa;
 317         struct i40iw_sc_dev *dev;
 318         struct i40iw_sc_aeqe *aeqe_base;
 319         void *pbl_list;
 320         u32 elem_cnt;
 321         struct i40iw_ring aeq_ring;
 322         bool virtual_map;
 323         u8 pbl_chunk_size;
 324         u32 first_pm_pbl_idx;
 325         u8 polarity;
 326 };
 327
 328 struct i40iw_sc_ceq {
 329         u32 size;
 330         u64 ceq_elem_pa;
 331         struct i40iw_sc_dev *dev;
 332         struct i40iw_ceqe *ceqe_base;
 333         void *pbl_list;
 334         u32 ceq_id;
 335         u32 elem_cnt;
 336         struct i40iw_ring ceq_ring;
 337         bool virtual_map;
 338         u8 pbl_chunk_size;
 339         bool tph_en;
 340         u8 tph_val;
 341         u32 first_pm_pbl_idx;
 342         u8 polarity;
 343 };
 344
 345 struct i40iw_sc_cq {
 346         struct i40iw_cq_uk cq_uk;
 347         u64 cq_pa;
 348         u64 shadow_area_pa;
 349         struct i40iw_sc_dev *dev;
 350         struct i40iw_sc_vsi *vsi;
 351         void *pbl_list;
 352         void *back_cq;
 353         u32 ceq_id;
 354         u32 shadow_read_threshold;
 355         bool ceqe_mask;
 356         bool virtual_map;
 357         u8 pbl_chunk_size;
 358         u8 cq_type;
 359         bool ceq_id_valid;
 360         bool tph_en;
 361         u8 tph_val;
 362         u32 first_pm_pbl_idx;
 363         bool check_overflow;
 364 };
 365
 366 struct i40iw_sc_qp {
 367         struct i40iw_qp_uk qp_uk;
 368         u64 sq_pa;
 369         u64 rq_pa;
 370         u64 hw_host_ctx_pa;
 371         u64 shadow_area_pa;
 372         u64 q2_pa;
 373         struct i40iw_sc_dev *dev;
 374         struct i40iw_sc_vsi *vsi;
 375         struct i40iw_sc_pd *pd;
 376         u64 *hw_host_ctx;
 377         void *llp_stream_handle;
 378         void *back_qp;
 379         struct i40iw_pfpdu pfpdu;
 380         u8 *q2_buf;
 381         u64 qp_compl_ctx;
 382         u16 qs_handle;
 383         u16 exception_lan_queue;
 384         u16 push_idx;
 385         u8 sq_tph_val;
 386         u8 rq_tph_val;
 387         u8 qp_state;
 388         u8 qp_type;
 389         u8 hw_sq_size;
 390         u8 hw_rq_size;
 391         u8 src_mac_addr_idx;
 392         bool sq_tph_en;
 393         bool rq_tph_en;
 394         bool rcv_tph_en;
 395         bool xmit_tph_en;
 396         bool virtual_map;
 397         bool flush_sq;
 398         bool flush_rq;
 399         u8 user_pri;
 400         struct list_head list;
 401         bool on_qoslist;
 402         bool sq_flush;
 403         enum i40iw_flush_opcode flush_code;
 404         enum i40iw_term_eventtypes eventtype;
 405         u8 term_flags;
 406 };
 407
 408 struct i40iw_hmc_fpm_misc {
 409         u32 max_ceqs;
 410         u32 max_sds;
 411         u32 xf_block_size;
 412         u32 q1_block_size;
 413         u32 ht_multiplier;
 414         u32 timer_bucket;
 415 };
 416
 417 struct i40iw_vchnl_if {
 418         enum i40iw_status_code (*vchnl_recv)(struct i40iw_sc_dev *, u32, u8 *, u16);
 419         enum i40iw_status_code (*vchnl_send)(struct i40iw_sc_dev *dev, u32, u8 *, u16);
 420 };
 421
 422 #define I40IW_VCHNL_MAX_VF_MSG_SIZE 512
 423
 424 struct i40iw_vchnl_vf_msg_buffer {
 425         struct i40iw_virtchnl_op_buf vchnl_msg;
 426         char parm_buffer[I40IW_VCHNL_MAX_VF_MSG_SIZE - 1];
 427 };
 428
 429 struct i40iw_qos {
 430         struct list_head qplist;
 431         spinlock_t lock;        /* qos list */
 432         u16 qs_handle;
 433 };
 434
 435 struct i40iw_vfdev {
 436         struct i40iw_sc_dev *pf_dev;
 437         u8 *hmc_info_mem;
 438         struct i40iw_vsi_pestat pestat;
 439         struct i40iw_hmc_pble_info *pble_info;
 440         struct i40iw_hmc_info hmc_info;
 441         struct i40iw_vchnl_vf_msg_buffer vf_msg_buffer;
 442         u64 fpm_query_buf_pa;
 443         u64 *fpm_query_buf;
 444         u32 vf_id;
 445         u32 msg_count;
 446         bool pf_hmc_initialized;
 447         u16 pmf_index;
 448         u16 iw_vf_idx;          /* VF Device table index */
 449         bool stats_initialized;
 450 };
 451
 452 #define I40IW_INVALID_FCN_ID 0xff
 453 struct i40iw_sc_vsi {
 454         struct i40iw_sc_dev *dev;
 455         void *back_vsi; /* Owned by OS */
 456         u32 ilq_count;
 457         struct i40iw_virt_mem ilq_mem;
 458         struct i40iw_puda_rsrc *ilq;
 459         u32 ieq_count;
 460         struct i40iw_virt_mem ieq_mem;
 461         struct i40iw_puda_rsrc *ieq;
 462         u16 mss;
 463         u8 fcn_id;
 464         bool stats_fcn_id_alloc;
 465         struct i40iw_qos qos[I40IW_MAX_USER_PRIORITY];
 466         struct i40iw_vsi_pestat *pestat;
 467 };
 468
 469 struct i40iw_sc_dev {
 470         struct list_head cqp_cmd_head;  /* head of the CQP command list */
 471         spinlock_t cqp_lock; /* cqp list sync */
 472         struct i40iw_dev_uk dev_uk;
 473         bool fcn_id_array[I40IW_MAX_STATS_COUNT];
 474         struct i40iw_dma_mem vf_fpm_query_buf[I40IW_MAX_PE_ENABLED_VF_COUNT];
 475         u64 fpm_query_buf_pa;
 476         u64 fpm_commit_buf_pa;
 477         u64 *fpm_query_buf;
 478         u64 *fpm_commit_buf;
 479         void *back_dev;
 480         struct i40iw_hw *hw;
 481         u8 __iomem *db_addr;
 482         struct i40iw_hmc_info *hmc_info;
 483         struct i40iw_hmc_pble_info *pble_info;
 484         struct i40iw_vfdev *vf_dev[I40IW_MAX_PE_ENABLED_VF_COUNT];
 485         struct i40iw_sc_cqp *cqp;
 486         struct i40iw_sc_aeq *aeq;
 487         struct i40iw_sc_ceq *ceq[I40IW_CEQ_MAX_COUNT];
 488         struct i40iw_sc_cq *ccq;
 489         struct i40iw_cqp_ops *cqp_ops;
 490         struct i40iw_ccq_ops *ccq_ops;
 491         struct i40iw_ceq_ops *ceq_ops;
 492         struct i40iw_aeq_ops *aeq_ops;
 493         struct i40iw_pd_ops *iw_pd_ops;
 494         struct i40iw_priv_qp_ops *iw_priv_qp_ops;
 495         struct i40iw_priv_cq_ops *iw_priv_cq_ops;
 496         struct i40iw_mr_ops *mr_ops;
 497         struct i40iw_cqp_misc_ops *cqp_misc_ops;
 498         struct i40iw_hmc_ops *hmc_ops;
 499         struct i40iw_vchnl_if vchnl_if;
 500         const struct i40iw_vf_cqp_ops *iw_vf_cqp_ops;
 501
 502         struct i40iw_hmc_fpm_misc hmc_fpm_misc;
 503         u32 debug_mask;
 504         u16 exception_lan_queue;
 505         u8 hmc_fn_id;
 506         bool is_pf;
 507         bool vchnl_up;
 508         u8 vf_id;
 509         wait_queue_head_t vf_reqs;
 510         u64 cqp_cmd_stats[OP_SIZE_CQP_STAT_ARRAY];
 511         struct i40iw_vchnl_vf_msg_buffer vchnl_vf_msg_buf;
 512         u8 hw_rev;
 513 };
 514
 515 struct i40iw_modify_cq_info {
 516         u64 cq_pa;
 517         struct i40iw_cqe *cq_base;
 518         void *pbl_list;
 519         u32 ceq_id;
 520         u32 cq_size;
 521         u32 shadow_read_threshold;
 522         bool virtual_map;
 523         u8 pbl_chunk_size;
 524         bool check_overflow;
 525         bool cq_resize;
 526         bool ceq_change;
 527         bool check_overflow_change;
 528         u32 first_pm_pbl_idx;
 529         bool ceq_valid;
 530 };
 531
 532 struct i40iw_create_qp_info {
 533         u8 next_iwarp_state;
 534         bool ord_valid;
 535         bool tcp_ctx_valid;
 536         bool cq_num_valid;
 537         bool static_rsrc;
 538         bool arp_cache_idx_valid;
 539 };
 540
 541 struct i40iw_modify_qp_info {
 542         u64 rx_win0;
 543         u64 rx_win1;
 544         u16 new_mss;
 545         u8 next_iwarp_state;
 546         u8 termlen;
 547         bool ord_valid;
 548         bool tcp_ctx_valid;
 549         bool cq_num_valid;
 550         bool static_rsrc;
 551         bool arp_cache_idx_valid;
 552         bool reset_tcp_conn;
 553         bool remove_hash_idx;
 554         bool dont_send_term;
 555         bool dont_send_fin;
 556         bool cached_var_valid;
 557         bool mss_change;
 558         bool force_loopback;
 559 };
 560
 561 struct i40iw_ccq_cqe_info {
 562         struct i40iw_sc_cqp *cqp;
 563         u64 scratch;
 564         u32 op_ret_val;
 565         u16 maj_err_code;
 566         u16 min_err_code;
 567         u8 op_code;
 568         bool error;
 569 };
 570
 571 struct i40iw_l2params {
 572         u16 qs_handle_list[I40IW_MAX_USER_PRIORITY];
 573         u16 mss;
 574 };
 575
 576 struct i40iw_vsi_init_info {
 577         struct i40iw_sc_dev *dev;
 578         void  *back_vsi;
 579         struct i40iw_l2params *params;
 580 };
 581
 582 struct i40iw_vsi_stats_info {
 583         struct i40iw_vsi_pestat *pestat;
 584         u8 fcn_id;
 585         bool alloc_fcn_id;
 586         bool stats_initialize;
 587 };
 588
 589 struct i40iw_device_init_info {
 590         u64 fpm_query_buf_pa;
 591         u64 fpm_commit_buf_pa;
 592         u64 *fpm_query_buf;
 593         u64 *fpm_commit_buf;
 594         struct i40iw_hw *hw;
 595         void __iomem *bar0;
 596         enum i40iw_status_code (*vchnl_send)(struct i40iw_sc_dev *, u32, u8 *, u16);
 597         u16 exception_lan_queue;
 598         u8 hmc_fn_id;
 599         bool is_pf;
 600         u32 debug_mask;
 601 };
 602
 603 enum i40iw_cqp_hmc_profile {
 604         I40IW_HMC_PROFILE_DEFAULT = 1,
 605         I40IW_HMC_PROFILE_FAVOR_VF = 2,
 606         I40IW_HMC_PROFILE_EQUAL = 3,
 607 };
 608
 609 struct i40iw_cqp_init_info {
 610         u64 cqp_compl_ctx;
 611         u64 host_ctx_pa;
 612         u64 sq_pa;
 613         struct i40iw_sc_dev *dev;
 614         struct i40iw_cqp_quanta *sq;
 615         u64 *host_ctx;
 616         u64 *scratch_array;
 617         u32 sq_size;
 618         u8 struct_ver;
 619         bool en_datacenter_tcp;
 620         u8 hmc_profile;
 621         u8 enabled_vf_count;
 622 };
 623
 624 struct i40iw_ceq_init_info {
 625         u64 ceqe_pa;
 626         struct i40iw_sc_dev *dev;
 627         u64 *ceqe_base;
 628         void *pbl_list;
 629         u32 elem_cnt;
 630         u32 ceq_id;
 631         bool virtual_map;
 632         u8 pbl_chunk_size;
 633         bool tph_en;
 634         u8 tph_val;
 635         u32 first_pm_pbl_idx;
 636 };
 637
 638 struct i40iw_aeq_init_info {
 639         u64 aeq_elem_pa;
 640         struct i40iw_sc_dev *dev;
 641         u32 *aeqe_base;
 642         void *pbl_list;
 643         u32 elem_cnt;
 644         bool virtual_map;
 645         u8 pbl_chunk_size;
 646         u32 first_pm_pbl_idx;
 647 };
 648
 649 struct i40iw_ccq_init_info {
 650         u64 cq_pa;
 651         u64 shadow_area_pa;
 652         struct i40iw_sc_dev *dev;
 653         struct i40iw_cqe *cq_base;
 654         u64 *shadow_area;
 655         void *pbl_list;
 656         u32 num_elem;
 657         u32 ceq_id;
 658         u32 shadow_read_threshold;
 659         bool ceqe_mask;
 660         bool ceq_id_valid;
 661         bool tph_en;
 662         u8 tph_val;
 663         bool avoid_mem_cflct;
 664         bool virtual_map;
 665         u8 pbl_chunk_size;
 666         u32 first_pm_pbl_idx;
 667 };
 668
 669 struct i40iwarp_offload_info {
 670         u16 rcv_mark_offset;
 671         u16 snd_mark_offset;
 672         u16 pd_id;
 673         u8 ddp_ver;
 674         u8 rdmap_ver;
 675         u8 ord_size;
 676         u8 ird_size;
 677         bool wr_rdresp_en;
 678         bool rd_enable;
 679         bool snd_mark_en;
 680         bool rcv_mark_en;
 681         bool bind_en;
 682         bool fast_reg_en;
 683         bool priv_mode_en;
 684         bool lsmm_present;
 685         u8 iwarp_mode;
 686         bool align_hdrs;
 687         bool rcv_no_mpa_crc;
 688
 689         u8 last_byte_sent;
 690 };
 691
 692 struct i40iw_tcp_offload_info {
 693         bool ipv4;
 694         bool no_nagle;
 695         bool insert_vlan_tag;
 696         bool time_stamp;
 697         u8 cwnd_inc_limit;
 698         bool drop_ooo_seg;
 699         u8 dup_ack_thresh;
 700         u8 ttl;
 701         u8 src_mac_addr_idx;
 702         bool avoid_stretch_ack;
 703         u8 tos;
 704         u16 src_port;
 705         u16 dst_port;
 706         u32 dest_ip_addr0;
 707         u32 dest_ip_addr1;
 708         u32 dest_ip_addr2;
 709         u32 dest_ip_addr3;
 710         u32 snd_mss;
 711         u16 vlan_tag;
 712         u16 arp_idx;
 713         u32 flow_label;
 714         bool wscale;
 715         u8 tcp_state;
 716         u8 snd_wscale;
 717         u8 rcv_wscale;
 718         u32 time_stamp_recent;
 719         u32 time_stamp_age;
 720         u32 snd_nxt;
 721         u32 snd_wnd;
 722         u32 rcv_nxt;
 723         u32 rcv_wnd;
 724         u32 snd_max;
 725         u32 snd_una;
 726         u32 srtt;
 727         u32 rtt_var;
 728         u32 ss_thresh;
 729         u32 cwnd;
 730         u32 snd_wl1;
 731         u32 snd_wl2;
 732         u32 max_snd_window;
 733         u8 rexmit_thresh;
 734         u32 local_ipaddr0;
 735         u32 local_ipaddr1;
 736         u32 local_ipaddr2;
 737         u32 local_ipaddr3;
 738         bool ignore_tcp_opt;
 739         bool ignore_tcp_uns_opt;
 740 };
 741
 742 struct i40iw_qp_host_ctx_info {
 743         u64 qp_compl_ctx;
 744         struct i40iw_tcp_offload_info *tcp_info;
 745         struct i40iwarp_offload_info *iwarp_info;
 746         u32 send_cq_num;
 747         u32 rcv_cq_num;
 748         u16 push_idx;
 749         bool push_mode_en;
 750         bool tcp_info_valid;
 751         bool iwarp_info_valid;
 752         bool err_rq_idx_valid;
 753         u16 err_rq_idx;
 754         bool add_to_qoslist;
 755         u8 user_pri;
 756 };
 757
 758 struct i40iw_aeqe_info {
 759         u64 compl_ctx;
 760         u32 qp_cq_id;
 761         u16 ae_id;
 762         u16 wqe_idx;
 763         u8 tcp_state;
 764         u8 iwarp_state;
 765         bool qp;
 766         bool cq;
 767         bool sq;
 768         bool in_rdrsp_wr;
 769         bool out_rdrsp;
 770         u8 q2_data_written;
 771         bool aeqe_overflow;
 772 };
 773
 774 struct i40iw_allocate_stag_info {
 775         u64 total_len;
 776         u32 chunk_size;
 777         u32 stag_idx;
 778         u32 page_size;
 779         u16 pd_id;
 780         u16 access_rights;
 781         bool remote_access;
 782         bool use_hmc_fcn_index;
 783         u8 hmc_fcn_index;
 784         bool use_pf_rid;
 785 };
 786
 787 struct i40iw_reg_ns_stag_info {
 788         u64 reg_addr_pa;
 789         u64 fbo;
 790         void *va;
 791         u64 total_len;
 792         u32 page_size;
 793         u32 chunk_size;
 794         u32 first_pm_pbl_index;
 795         enum i40iw_addressing_type addr_type;
 796         i40iw_stag_index stag_idx;
 797         u16 access_rights;
 798         u16 pd_id;
 799         i40iw_stag_key stag_key;
 800         bool use_hmc_fcn_index;
 801         u8 hmc_fcn_index;
 802         bool use_pf_rid;
 803 };
 804
 805 struct i40iw_fast_reg_stag_info {
 806         u64 wr_id;
 807         u64 reg_addr_pa;
 808         u64 fbo;
 809         void *va;
 810         u64 total_len;
 811         u32 page_size;
 812         u32 chunk_size;
 813         u32 first_pm_pbl_index;
 814         enum i40iw_addressing_type addr_type;
 815         i40iw_stag_index stag_idx;
 816         u16 access_rights;
 817         u16 pd_id;
 818         i40iw_stag_key stag_key;
 819         bool local_fence;
 820         bool read_fence;
 821         bool signaled;
 822         bool use_hmc_fcn_index;
 823         u8 hmc_fcn_index;
 824         bool use_pf_rid;
 825         bool defer_flag;
 826 };
 827
 828 struct i40iw_dealloc_stag_info {
 829         u32 stag_idx;
 830         u16 pd_id;
 831         bool mr;
 832         bool dealloc_pbl;
 833 };
 834
 835 struct i40iw_register_shared_stag {
 836         void *va;
 837         enum i40iw_addressing_type addr_type;
 838         i40iw_stag_index new_stag_idx;
 839         i40iw_stag_index parent_stag_idx;
 840         u32 access_rights;
 841         u16 pd_id;
 842         i40iw_stag_key new_stag_key;
 843 };
 844
 845 struct i40iw_qp_init_info {
 846         struct i40iw_qp_uk_init_info qp_uk_init_info;
 847         struct i40iw_sc_pd *pd;
 848         struct i40iw_sc_vsi *vsi;
 849         u64 *host_ctx;
 850         u8 *q2;
 851         u64 sq_pa;
 852         u64 rq_pa;
 853         u64 host_ctx_pa;
 854         u64 q2_pa;
 855         u64 shadow_area_pa;
 856         int abi_ver;
 857         u8 sq_tph_val;
 858         u8 rq_tph_val;
 859         u8 type;
 860         bool sq_tph_en;
 861         bool rq_tph_en;
 862         bool rcv_tph_en;
 863         bool xmit_tph_en;
 864         bool virtual_map;
 865 };
 866
 867 struct i40iw_cq_init_info {
 868         struct i40iw_sc_dev *dev;
 869         u64 cq_base_pa;
 870         u64 shadow_area_pa;
 871         u32 ceq_id;
 872         u32 shadow_read_threshold;
 873         bool virtual_map;
 874         bool ceqe_mask;
 875         u8 pbl_chunk_size;
 876         u32 first_pm_pbl_idx;
 877         bool ceq_id_valid;
 878         bool tph_en;
 879         u8 tph_val;
 880         u8 type;
 881         struct i40iw_cq_uk_init_info cq_uk_init_info;
 882 };
 883
 884 struct i40iw_upload_context_info {
 885         u64 buf_pa;
 886         bool freeze_qp;
 887         bool raw_format;
 888         u32 qp_id;
 889         u8 qp_type;
 890 };
 891
 892 struct i40iw_add_arp_cache_entry_info {
 893         u8 mac_addr[6];
 894         u32 reach_max;
 895         u16 arp_index;
 896         bool permanent;
 897 };
 898
 899 struct i40iw_apbvt_info {
 900         u16 port;
 901         bool add;
 902 };
 903
 904 enum i40iw_quad_entry_type {
 905         I40IW_QHASH_TYPE_TCP_ESTABLISHED = 1,
 906         I40IW_QHASH_TYPE_TCP_SYN,
 907 };
 908
 909 enum i40iw_quad_hash_manage_type {
 910         I40IW_QHASH_MANAGE_TYPE_DELETE = 0,
 911         I40IW_QHASH_MANAGE_TYPE_ADD,
 912         I40IW_QHASH_MANAGE_TYPE_MODIFY
 913 };
 914
 915 struct i40iw_qhash_table_info {
 916         struct i40iw_sc_vsi *vsi;
 917         enum i40iw_quad_hash_manage_type manage;
 918         enum i40iw_quad_entry_type entry_type;
 919         bool vlan_valid;
 920         bool ipv4_valid;
 921         u8 mac_addr[6];
 922         u16 vlan_id;
 923         u8 user_pri;
 924         u32 qp_num;
 925         u32 dest_ip[4];
 926         u32 src_ip[4];
 927         u16 dest_port;
 928         u16 src_port;
 929 };
 930
 931 struct i40iw_local_mac_ipaddr_entry_info {
 932         u8 mac_addr[6];
 933         u8 entry_idx;
 934 };
 935
 936 struct i40iw_cqp_manage_push_page_info {
 937         u32 push_idx;
 938         u16 qs_handle;
 939         u8 free_page;
 940 };
 941
 942 struct i40iw_qp_flush_info {
 943         u16 sq_minor_code;
 944         u16 sq_major_code;
 945         u16 rq_minor_code;
 946         u16 rq_major_code;
 947         u16 ae_code;
 948         u8 ae_source;
 949         bool sq;
 950         bool rq;
 951         bool userflushcode;
 952         bool generate_ae;
 953 };
 954
 955 struct i40iw_cqp_commit_fpm_values {
 956         u64 qp_base;
 957         u64 cq_base;
 958         u32 hte_base;
 959         u32 arp_base;
 960         u32 apbvt_inuse_base;
 961         u32 mr_base;
 962         u32 xf_base;
 963         u32 xffl_base;
 964         u32 q1_base;
 965         u32 q1fl_base;
 966         u32 fsimc_base;
 967         u32 fsiav_base;
 968         u32 pbl_base;
 969
 970         u32 qp_cnt;
 971         u32 cq_cnt;
 972         u32 hte_cnt;
 973         u32 arp_cnt;
 974         u32 mr_cnt;
 975         u32 xf_cnt;
 976         u32 xffl_cnt;
 977         u32 q1_cnt;
 978         u32 q1fl_cnt;
 979         u32 fsimc_cnt;
 980         u32 fsiav_cnt;
 981         u32 pbl_cnt;
 982 };
 983
 984 struct i40iw_cqp_query_fpm_values {
 985         u16 first_pe_sd_index;
 986         u32 qp_objsize;
 987         u32 cq_objsize;
 988         u32 hte_objsize;
 989         u32 arp_objsize;
 990         u32 mr_objsize;
 991         u32 xf_objsize;
 992         u32 q1_objsize;
 993         u32 fsimc_objsize;
 994         u32 fsiav_objsize;
 995
 996         u32 qp_max;
 997         u32 cq_max;
 998         u32 hte_max;
 999         u32 arp_max;
1000         u32 mr_max;
1001         u32 xf_max;
1002         u32 xffl_max;
1003         u32 q1_max;
1004         u32 q1fl_max;
1005         u32 fsimc_max;
1006         u32 fsiav_max;
1007         u32 pbl_max;
1008 };
1009
1010 struct i40iw_cqp_ops {
1011         enum i40iw_status_code (*cqp_init)(struct i40iw_sc_cqp *,
1012                                            struct i40iw_cqp_init_info *);
1013         enum i40iw_status_code (*cqp_create)(struct i40iw_sc_cqp *, u16 *, u16 *);
1014         void (*cqp_post_sq)(struct i40iw_sc_cqp *);
1015         u64 *(*cqp_get_next_send_wqe)(struct i40iw_sc_cqp *, u64 scratch);
1016         enum i40iw_status_code (*cqp_destroy)(struct i40iw_sc_cqp *);
1017         enum i40iw_status_code (*poll_for_cqp_op_done)(struct i40iw_sc_cqp *, u8,
1018                                                        struct i40iw_ccq_cqe_info *);
1019 };
1020
1021 struct i40iw_ccq_ops {
1022         enum i40iw_status_code (*ccq_init)(struct i40iw_sc_cq *,
1023                                            struct i40iw_ccq_init_info *);
1024         enum i40iw_status_code (*ccq_create)(struct i40iw_sc_cq *, u64, bool, bool);
1025         enum i40iw_status_code (*ccq_destroy)(struct i40iw_sc_cq *, u64, bool);
1026         enum i40iw_status_code (*ccq_create_done)(struct i40iw_sc_cq *);
1027         enum i40iw_status_code (*ccq_get_cqe_info)(struct i40iw_sc_cq *,
1028                                                    struct i40iw_ccq_cqe_info *);
1029         void (*ccq_arm)(struct i40iw_sc_cq *);
1030 };
1031
1032 struct i40iw_ceq_ops {
1033         enum i40iw_status_code (*ceq_init)(struct i40iw_sc_ceq *,
1034                                            struct i40iw_ceq_init_info *);
1035         enum i40iw_status_code (*ceq_create)(struct i40iw_sc_ceq *, u64, bool);
1036         enum i40iw_status_code (*cceq_create_done)(struct i40iw_sc_ceq *);
1037         enum i40iw_status_code (*cceq_destroy_done)(struct i40iw_sc_ceq *);
1038         enum i40iw_status_code (*cceq_create)(struct i40iw_sc_ceq *, u64);
1039         enum i40iw_status_code (*ceq_destroy)(struct i40iw_sc_ceq *, u64, bool);
1040         void *(*process_ceq)(struct i40iw_sc_dev *, struct i40iw_sc_ceq *);
1041 };
1042
1043 struct i40iw_aeq_ops {
1044         enum i40iw_status_code (*aeq_init)(struct i40iw_sc_aeq *,
1045                                            struct i40iw_aeq_init_info *);
1046         enum i40iw_status_code (*aeq_create)(struct i40iw_sc_aeq *, u64, bool);
1047         enum i40iw_status_code (*aeq_destroy)(struct i40iw_sc_aeq *, u64, bool);
1048         enum i40iw_status_code (*get_next_aeqe)(struct i40iw_sc_aeq *,
1049                                                 struct i40iw_aeqe_info *);
1050         enum i40iw_status_code (*repost_aeq_entries)(struct i40iw_sc_dev *, u32);
1051         enum i40iw_status_code (*aeq_create_done)(struct i40iw_sc_aeq *);
1052         enum i40iw_status_code (*aeq_destroy_done)(struct i40iw_sc_aeq *);
1053 };
1054
1055 struct i40iw_pd_ops {
1056         void (*pd_init)(struct i40iw_sc_dev *, struct i40iw_sc_pd *, u16, int);
1057 };
1058
1059 struct i40iw_priv_qp_ops {
1060         enum i40iw_status_code (*qp_init)(struct i40iw_sc_qp *, struct i40iw_qp_init_info *);
1061         enum i40iw_status_code (*qp_create)(struct i40iw_sc_qp *,
1062                                             struct i40iw_create_qp_info *, u64, bool);
1063         enum i40iw_status_code (*qp_modify)(struct i40iw_sc_qp *,
1064                                             struct i40iw_modify_qp_info *, u64, bool);
1065         enum i40iw_status_code (*qp_destroy)(struct i40iw_sc_qp *, u64, bool, bool, bool);
1066         enum i40iw_status_code (*qp_flush_wqes)(struct i40iw_sc_qp *,
1067                                                 struct i40iw_qp_flush_info *, u64, bool);
1068         enum i40iw_status_code (*qp_upload_context)(struct i40iw_sc_dev *,
1069                                                     struct i40iw_upload_context_info *,
1070                                                     u64, bool);
1071         enum i40iw_status_code (*qp_setctx)(struct i40iw_sc_qp *, u64 *,
1072                                             struct i40iw_qp_host_ctx_info *);
1073
1074         void (*qp_send_lsmm)(struct i40iw_sc_qp *, void *, u32, i40iw_stag);
1075         void (*qp_send_lsmm_nostag)(struct i40iw_sc_qp *, void *, u32);
1076         void (*qp_send_rtt)(struct i40iw_sc_qp *, bool);
1077         enum i40iw_status_code (*qp_post_wqe0)(struct i40iw_sc_qp *, u8);
1078         enum i40iw_status_code (*iw_mr_fast_register)(struct i40iw_sc_qp *,
1079                                                       struct i40iw_fast_reg_stag_info *,
1080                                                       bool);
1081 };
1082
1083 struct i40iw_priv_cq_ops {
1084         enum i40iw_status_code (*cq_init)(struct i40iw_sc_cq *, struct i40iw_cq_init_info *);
1085         enum i40iw_status_code (*cq_create)(struct i40iw_sc_cq *, u64, bool, bool);
1086         enum i40iw_status_code (*cq_destroy)(struct i40iw_sc_cq *, u64, bool);
1087         enum i40iw_status_code (*cq_modify)(struct i40iw_sc_cq *,
1088                                             struct i40iw_modify_cq_info *, u64, bool);
1089 };
1090
1091 struct i40iw_mr_ops {
1092         enum i40iw_status_code (*alloc_stag)(struct i40iw_sc_dev *,
1093                                              struct i40iw_allocate_stag_info *, u64, bool);
1094         enum i40iw_status_code (*mr_reg_non_shared)(struct i40iw_sc_dev *,
1095                                                     struct i40iw_reg_ns_stag_info *,
1096                                                     u64, bool);
1097         enum i40iw_status_code (*mr_reg_shared)(struct i40iw_sc_dev *,
1098                                                 struct i40iw_register_shared_stag *,
1099                                                 u64, bool);
1100         enum i40iw_status_code (*dealloc_stag)(struct i40iw_sc_dev *,
1101                                                struct i40iw_dealloc_stag_info *,
1102                                                u64, bool);
1103         enum i40iw_status_code (*query_stag)(struct i40iw_sc_dev *, u64, u32, bool);
1104         enum i40iw_status_code (*mw_alloc)(struct i40iw_sc_dev *, u64, u32, u16, bool);
1105 };
1106
1107 struct i40iw_cqp_misc_ops {
1108         enum i40iw_status_code (*manage_push_page)(struct i40iw_sc_cqp *,
1109                                                    struct i40iw_cqp_manage_push_page_info *,
1110                                                    u64, bool);
1111         enum i40iw_status_code (*manage_hmc_pm_func_table)(struct i40iw_sc_cqp *,
1112                                                            u64, u8, bool, bool);
1113         enum i40iw_status_code (*set_hmc_resource_profile)(struct i40iw_sc_cqp *,
1114                                                            u64, u8, u8, bool, bool);
1115         enum i40iw_status_code (*commit_fpm_values)(struct i40iw_sc_cqp *, u64, u8,
1116                                                     struct i40iw_dma_mem *, bool, u8);
1117         enum i40iw_status_code (*query_fpm_values)(struct i40iw_sc_cqp *, u64, u8,
1118                                                    struct i40iw_dma_mem *, bool, u8);
1119         enum i40iw_status_code (*static_hmc_pages_allocated)(struct i40iw_sc_cqp *,
1120                                                              u64, u8, bool, bool);
1121         enum i40iw_status_code (*add_arp_cache_entry)(struct i40iw_sc_cqp *,
1122                                                       struct i40iw_add_arp_cache_entry_info *,
1123                                                       u64, bool);
1124         enum i40iw_status_code (*del_arp_cache_entry)(struct i40iw_sc_cqp *, u64, u16, bool);
1125         enum i40iw_status_code (*query_arp_cache_entry)(struct i40iw_sc_cqp *, u64, u16, bool);
1126         enum i40iw_status_code (*manage_apbvt_entry)(struct i40iw_sc_cqp *,
1127                                                      struct i40iw_apbvt_info *, u64, bool);
1128         enum i40iw_status_code (*manage_qhash_table_entry)(struct i40iw_sc_cqp *,
1129                                                            struct i40iw_qhash_table_info *, u64, bool);
1130         enum i40iw_status_code (*alloc_local_mac_ipaddr_table_entry)(struct i40iw_sc_cqp *, u64, bool);
1131         enum i40iw_status_code (*add_local_mac_ipaddr_entry)(struct i40iw_sc_cqp *,
1132                                                              struct i40iw_local_mac_ipaddr_entry_info *,
1133                                                              u64, bool);
1134         enum i40iw_status_code (*del_local_mac_ipaddr_entry)(struct i40iw_sc_cqp *, u64, u8, u8, bool);
1135         enum i40iw_status_code (*cqp_nop)(struct i40iw_sc_cqp *, u64, bool);
1136         enum i40iw_status_code (*commit_fpm_values_done)(struct i40iw_sc_cqp
1137                                                           *);
1138         enum i40iw_status_code (*query_fpm_values_done)(struct i40iw_sc_cqp *);
1139         enum i40iw_status_code (*manage_hmc_pm_func_table_done)(struct i40iw_sc_cqp *);
1140         enum i40iw_status_code (*update_suspend_qp)(struct i40iw_sc_cqp *, struct i40iw_sc_qp *, u64);
1141         enum i40iw_status_code (*update_resume_qp)(struct i40iw_sc_cqp *, struct i40iw_sc_qp *, u64);
1142 };
1143
1144 struct i40iw_hmc_ops {
1145         enum i40iw_status_code (*init_iw_hmc)(struct i40iw_sc_dev *, u8);
1146         enum i40iw_status_code (*parse_fpm_query_buf)(u64 *, struct i40iw_hmc_info *,
1147                                                       struct i40iw_hmc_fpm_misc *);
1148         enum i40iw_status_code (*configure_iw_fpm)(struct i40iw_sc_dev *, u8);
1149         enum i40iw_status_code (*parse_fpm_commit_buf)(u64 *, struct i40iw_hmc_obj_info *, u32 *sd);
1150         enum i40iw_status_code (*create_hmc_object)(struct i40iw_sc_dev *dev,
1151                                                     struct i40iw_hmc_create_obj_info *);
1152         enum i40iw_status_code (*del_hmc_object)(struct i40iw_sc_dev *dev,
1153                                                  struct i40iw_hmc_del_obj_info *,
1154                                                  bool reset);
1155         enum i40iw_status_code (*pf_init_vfhmc)(struct i40iw_sc_dev *, u8, u32 *);
1156         enum i40iw_status_code (*vf_configure_vffpm)(struct i40iw_sc_dev *, u32 *);
1157 };
1158
1159 struct cqp_info {
1160         union {
1161                 struct {
1162                         struct i40iw_sc_qp *qp;
1163                         struct i40iw_create_qp_info info;
1164                         u64 scratch;
1165                 } qp_create;
1166
1167                 struct {
1168                         struct i40iw_sc_qp *qp;
1169                         struct i40iw_modify_qp_info info;
1170                         u64 scratch;
1171                 } qp_modify;
1172
1173                 struct {
1174                         struct i40iw_sc_qp *qp;
1175                         u64 scratch;
1176                         bool remove_hash_idx;
1177                         bool ignore_mw_bnd;
1178                 } qp_destroy;
1179
1180                 struct {
1181                         struct i40iw_sc_cq *cq;
1182                         u64 scratch;
1183                         bool check_overflow;
1184                 } cq_create;
1185
1186                 struct {
1187                         struct i40iw_sc_cq *cq;
1188                         u64 scratch;
1189                 } cq_destroy;
1190
1191                 struct {
1192                         struct i40iw_sc_dev *dev;
1193                         struct i40iw_allocate_stag_info info;
1194                         u64 scratch;
1195                 } alloc_stag;
1196
1197                 struct {
1198                         struct i40iw_sc_dev *dev;
1199                         u64 scratch;
1200                         u32 mw_stag_index;
1201                         u16 pd_id;
1202                 } mw_alloc;
1203
1204                 struct {
1205                         struct i40iw_sc_dev *dev;
1206                         struct i40iw_reg_ns_stag_info info;
1207                         u64 scratch;
1208                 } mr_reg_non_shared;
1209
1210                 struct {
1211                         struct i40iw_sc_dev *dev;
1212                         struct i40iw_dealloc_stag_info info;
1213                         u64 scratch;
1214                 } dealloc_stag;
1215
1216                 struct {
1217                         struct i40iw_sc_cqp *cqp;
1218                         struct i40iw_local_mac_ipaddr_entry_info info;
1219                         u64 scratch;
1220                 } add_local_mac_ipaddr_entry;
1221
1222                 struct {
1223                         struct i40iw_sc_cqp *cqp;
1224                         struct i40iw_add_arp_cache_entry_info info;
1225                         u64 scratch;
1226                 } add_arp_cache_entry;
1227
1228                 struct {
1229                         struct i40iw_sc_cqp *cqp;
1230                         u64 scratch;
1231                         u8 entry_idx;
1232                         u8 ignore_ref_count;
1233                 } del_local_mac_ipaddr_entry;
1234
1235                 struct {
1236                         struct i40iw_sc_cqp *cqp;
1237                         u64 scratch;
1238                         u16 arp_index;
1239                 } del_arp_cache_entry;
1240
1241                 struct {
1242                         struct i40iw_sc_cqp *cqp;
1243                         struct i40iw_manage_vf_pble_info info;
1244                         u64 scratch;
1245                 } manage_vf_pble_bp;
1246
1247                 struct {
1248                         struct i40iw_sc_cqp *cqp;
1249                         struct i40iw_cqp_manage_push_page_info info;
1250                         u64 scratch;
1251                 } manage_push_page;
1252
1253                 struct {
1254                         struct i40iw_sc_dev *dev;
1255                         struct i40iw_upload_context_info info;
1256                         u64 scratch;
1257                 } qp_upload_context;
1258
1259                 struct {
1260                         struct i40iw_sc_cqp *cqp;
1261                         u64 scratch;
1262                 } alloc_local_mac_ipaddr_entry;
1263
1264                 struct {
1265                         struct i40iw_sc_dev *dev;
1266                         struct i40iw_hmc_fcn_info info;
1267                         u64 scratch;
1268                 } manage_hmc_pm;
1269
1270                 struct {
1271                         struct i40iw_sc_ceq *ceq;
1272                         u64 scratch;
1273                 } ceq_create;
1274
1275                 struct {
1276                         struct i40iw_sc_ceq *ceq;
1277                         u64 scratch;
1278                 } ceq_destroy;
1279
1280                 struct {
1281                         struct i40iw_sc_aeq *aeq;
1282                         u64 scratch;
1283                 } aeq_create;
1284
1285                 struct {
1286                         struct i40iw_sc_aeq *aeq;
1287                         u64 scratch;
1288                 } aeq_destroy;
1289
1290                 struct {
1291                         struct i40iw_sc_qp *qp;
1292                         struct i40iw_qp_flush_info info;
1293                         u64 scratch;
1294                 } qp_flush_wqes;
1295
1296                 struct {
1297                         struct i40iw_sc_cqp *cqp;
1298                         void *fpm_values_va;
1299                         u64 fpm_values_pa;
1300                         u8 hmc_fn_id;
1301                         u64 scratch;
1302                 } query_fpm_values;
1303
1304                 struct {
1305                         struct i40iw_sc_cqp *cqp;
1306                         void *fpm_values_va;
1307                         u64 fpm_values_pa;
1308                         u8 hmc_fn_id;
1309                         u64 scratch;
1310                 } commit_fpm_values;
1311
1312                 struct {
1313                         struct i40iw_sc_cqp *cqp;
1314                         struct i40iw_apbvt_info info;
1315                         u64 scratch;
1316                 } manage_apbvt_entry;
1317
1318                 struct {
1319                         struct i40iw_sc_cqp *cqp;
1320                         struct i40iw_qhash_table_info info;
1321                         u64 scratch;
1322                 } manage_qhash_table_entry;
1323
1324                 struct {
1325                         struct i40iw_sc_dev *dev;
1326                         struct i40iw_update_sds_info info;
1327                         u64 scratch;
1328                 } update_pe_sds;
1329
1330                 struct {
1331                         struct i40iw_sc_cqp *cqp;
1332                         struct i40iw_sc_qp *qp;
1333                         u64 scratch;
1334                 } suspend_resume;
1335         } u;
1336 };
1337
1338 struct cqp_commands_info {
1339         struct list_head cqp_cmd_entry;
1340         u8 cqp_cmd;
1341         u8 post_sq;
1342         struct cqp_info in;
1343 };
1344
1345 struct i40iw_virtchnl_work_info {
1346         void (*callback_fcn)(void *vf_dev);
1347         void *worker_vf_dev;
1348 };
1349
1350 #endif