1 /*******************************************************************************
3 * Copyright (c) 2015-2016 Intel Corporation. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenFabrics.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 *******************************************************************************/
37 #include "i40iw_user.h"
38 #include "i40iw_hmc.h"
40 #include "i40iw_virtchnl.h"
42 struct i40iw_cqp_sq_wqe
{
43 u64 buf
[I40IW_CQP_WQE_SIZE
];
46 struct i40iw_sc_aeqe
{
47 u64 buf
[I40IW_AEQE_SIZE
];
51 u64 buf
[I40IW_CEQE_SIZE
];
54 struct i40iw_cqp_ctx
{
55 u64 buf
[I40IW_CQP_CTX_SIZE
];
58 struct i40iw_cq_shadow_area
{
59 u64 buf
[I40IW_SHADOW_AREA_SIZE
];
63 struct i40iw_hmc_info
;
64 struct i40iw_vsi_pestat
;
71 struct i40iw_cqp_misc_ops
;
73 struct i40iw_priv_qp_ops
;
74 struct i40iw_priv_cq_ops
;
77 enum i40iw_page_size
{
82 enum i40iw_resource_indicator_type
{
83 I40IW_RSRC_INDICATOR_TYPE_ADAPTER
= 0,
84 I40IW_RSRC_INDICATOR_TYPE_CQ
,
85 I40IW_RSRC_INDICATOR_TYPE_QP
,
86 I40IW_RSRC_INDICATOR_TYPE_SRQ
89 enum i40iw_hdrct_flags
{
95 enum i40iw_term_layers
{
101 enum i40iw_term_error_types
{
102 RDMAP_REMOTE_PROT
= 1,
104 DDP_CATASTROPHIC
= 0,
105 DDP_TAGGED_BUFFER
= 1,
106 DDP_UNTAGGED_BUFFER
= 2,
110 enum i40iw_term_rdma_errors
{
111 RDMAP_INV_STAG
= 0x00,
112 RDMAP_INV_BOUNDS
= 0x01,
114 RDMAP_UNASSOC_STAG
= 0x03,
115 RDMAP_TO_WRAP
= 0x04,
116 RDMAP_INV_RDMAP_VER
= 0x05,
117 RDMAP_UNEXPECTED_OP
= 0x06,
118 RDMAP_CATASTROPHIC_LOCAL
= 0x07,
119 RDMAP_CATASTROPHIC_GLOBAL
= 0x08,
120 RDMAP_CANT_INV_STAG
= 0x09,
121 RDMAP_UNSPECIFIED
= 0xff
124 enum i40iw_term_ddp_errors
{
125 DDP_CATASTROPHIC_LOCAL
= 0x00,
126 DDP_TAGGED_INV_STAG
= 0x00,
127 DDP_TAGGED_BOUNDS
= 0x01,
128 DDP_TAGGED_UNASSOC_STAG
= 0x02,
129 DDP_TAGGED_TO_WRAP
= 0x03,
130 DDP_TAGGED_INV_DDP_VER
= 0x04,
131 DDP_UNTAGGED_INV_QN
= 0x01,
132 DDP_UNTAGGED_INV_MSN_NO_BUF
= 0x02,
133 DDP_UNTAGGED_INV_MSN_RANGE
= 0x03,
134 DDP_UNTAGGED_INV_MO
= 0x04,
135 DDP_UNTAGGED_INV_TOO_LONG
= 0x05,
136 DDP_UNTAGGED_INV_DDP_VER
= 0x06
139 enum i40iw_term_mpa_errors
{
146 enum i40iw_flush_opcode
{
149 FLUSH_REM_ACCESS_ERR
,
157 enum i40iw_term_eventtypes
{
159 TERM_EVENT_QP_ACCESS_ERR
162 struct i40iw_terminate_hdr
{
169 enum i40iw_debug_flag
{
170 I40IW_DEBUG_NONE
= 0x00000000,
171 I40IW_DEBUG_ERR
= 0x00000001,
172 I40IW_DEBUG_INIT
= 0x00000002,
173 I40IW_DEBUG_DEV
= 0x00000004,
174 I40IW_DEBUG_CM
= 0x00000008,
175 I40IW_DEBUG_VERBS
= 0x00000010,
176 I40IW_DEBUG_PUDA
= 0x00000020,
177 I40IW_DEBUG_ILQ
= 0x00000040,
178 I40IW_DEBUG_IEQ
= 0x00000080,
179 I40IW_DEBUG_QP
= 0x00000100,
180 I40IW_DEBUG_CQ
= 0x00000200,
181 I40IW_DEBUG_MR
= 0x00000400,
182 I40IW_DEBUG_PBLE
= 0x00000800,
183 I40IW_DEBUG_WQE
= 0x00001000,
184 I40IW_DEBUG_AEQ
= 0x00002000,
185 I40IW_DEBUG_CQP
= 0x00004000,
186 I40IW_DEBUG_HMC
= 0x00008000,
187 I40IW_DEBUG_USER
= 0x00010000,
188 I40IW_DEBUG_VIRT
= 0x00020000,
189 I40IW_DEBUG_DCB
= 0x00040000,
190 I40IW_DEBUG_CQE
= 0x00800000,
191 I40IW_DEBUG_ALL
= 0xFFFFFFFF
194 enum i40iw_hw_stats_index_32b
{
195 I40IW_HW_STAT_INDEX_IP4RXDISCARD
= 0,
196 I40IW_HW_STAT_INDEX_IP4RXTRUNC
,
197 I40IW_HW_STAT_INDEX_IP4TXNOROUTE
,
198 I40IW_HW_STAT_INDEX_IP6RXDISCARD
,
199 I40IW_HW_STAT_INDEX_IP6RXTRUNC
,
200 I40IW_HW_STAT_INDEX_IP6TXNOROUTE
,
201 I40IW_HW_STAT_INDEX_TCPRTXSEG
,
202 I40IW_HW_STAT_INDEX_TCPRXOPTERR
,
203 I40IW_HW_STAT_INDEX_TCPRXPROTOERR
,
204 I40IW_HW_STAT_INDEX_MAX_32
207 enum i40iw_hw_stats_index_64b
{
208 I40IW_HW_STAT_INDEX_IP4RXOCTS
= 0,
209 I40IW_HW_STAT_INDEX_IP4RXPKTS
,
210 I40IW_HW_STAT_INDEX_IP4RXFRAGS
,
211 I40IW_HW_STAT_INDEX_IP4RXMCPKTS
,
212 I40IW_HW_STAT_INDEX_IP4TXOCTS
,
213 I40IW_HW_STAT_INDEX_IP4TXPKTS
,
214 I40IW_HW_STAT_INDEX_IP4TXFRAGS
,
215 I40IW_HW_STAT_INDEX_IP4TXMCPKTS
,
216 I40IW_HW_STAT_INDEX_IP6RXOCTS
,
217 I40IW_HW_STAT_INDEX_IP6RXPKTS
,
218 I40IW_HW_STAT_INDEX_IP6RXFRAGS
,
219 I40IW_HW_STAT_INDEX_IP6RXMCPKTS
,
220 I40IW_HW_STAT_INDEX_IP6TXOCTS
,
221 I40IW_HW_STAT_INDEX_IP6TXPKTS
,
222 I40IW_HW_STAT_INDEX_IP6TXFRAGS
,
223 I40IW_HW_STAT_INDEX_IP6TXMCPKTS
,
224 I40IW_HW_STAT_INDEX_TCPRXSEGS
,
225 I40IW_HW_STAT_INDEX_TCPTXSEG
,
226 I40IW_HW_STAT_INDEX_RDMARXRDS
,
227 I40IW_HW_STAT_INDEX_RDMARXSNDS
,
228 I40IW_HW_STAT_INDEX_RDMARXWRS
,
229 I40IW_HW_STAT_INDEX_RDMATXRDS
,
230 I40IW_HW_STAT_INDEX_RDMATXSNDS
,
231 I40IW_HW_STAT_INDEX_RDMATXWRS
,
232 I40IW_HW_STAT_INDEX_RDMAVBND
,
233 I40IW_HW_STAT_INDEX_RDMAVINV
,
234 I40IW_HW_STAT_INDEX_MAX_64
237 struct i40iw_dev_hw_stats_offsets
{
238 u32 stats_offset_32
[I40IW_HW_STAT_INDEX_MAX_32
];
239 u32 stats_offset_64
[I40IW_HW_STAT_INDEX_MAX_64
];
242 struct i40iw_dev_hw_stats
{
243 u64 stats_value_32
[I40IW_HW_STAT_INDEX_MAX_32
];
244 u64 stats_value_64
[I40IW_HW_STAT_INDEX_MAX_64
];
247 struct i40iw_vsi_pestat
{
249 struct i40iw_dev_hw_stats hw_stats
;
250 struct i40iw_dev_hw_stats last_read_hw_stats
;
251 struct i40iw_dev_hw_stats_offsets hw_stats_offsets
;
252 struct timer_list stats_timer
;
253 spinlock_t lock
; /* rdma stats lock */
259 struct i40iw_hmc_info hmc
;
263 struct list_head rxlist
;
281 struct i40iw_sc_dev
*dev
;
286 struct i40iw_cqp_quanta
{
287 u64 elem
[I40IW_CQP_WQE_SIZE
];
290 struct i40iw_sc_cqp
{
295 struct i40iw_sc_dev
*dev
;
296 enum i40iw_status_code (*process_cqp_sds
)(struct i40iw_sc_dev
*,
297 struct i40iw_update_sds_info
*);
298 struct i40iw_dma_mem sdbuf
;
299 struct i40iw_ring sq_ring
;
300 struct i40iw_cqp_quanta
*sq_base
;
308 bool en_datacenter_tcp
;
314 struct i40iw_sc_aeq
{
317 struct i40iw_sc_dev
*dev
;
318 struct i40iw_sc_aeqe
*aeqe_base
;
321 struct i40iw_ring aeq_ring
;
324 u32 first_pm_pbl_idx
;
328 struct i40iw_sc_ceq
{
331 struct i40iw_sc_dev
*dev
;
332 struct i40iw_ceqe
*ceqe_base
;
336 struct i40iw_ring ceq_ring
;
341 u32 first_pm_pbl_idx
;
346 struct i40iw_cq_uk cq_uk
;
349 struct i40iw_sc_dev
*dev
;
350 struct i40iw_sc_vsi
*vsi
;
354 u32 shadow_read_threshold
;
362 u32 first_pm_pbl_idx
;
367 struct i40iw_qp_uk qp_uk
;
373 struct i40iw_sc_dev
*dev
;
374 struct i40iw_sc_vsi
*vsi
;
375 struct i40iw_sc_pd
*pd
;
377 void *llp_stream_handle
;
379 struct i40iw_pfpdu pfpdu
;
383 u16 exception_lan_queue
;
400 struct list_head list
;
403 enum i40iw_flush_opcode flush_code
;
404 enum i40iw_term_eventtypes eventtype
;
408 struct i40iw_hmc_fpm_misc
{
417 struct i40iw_vchnl_if
{
418 enum i40iw_status_code (*vchnl_recv
)(struct i40iw_sc_dev
*, u32
, u8
*, u16
);
419 enum i40iw_status_code (*vchnl_send
)(struct i40iw_sc_dev
*dev
, u32
, u8
*, u16
);
422 #define I40IW_VCHNL_MAX_VF_MSG_SIZE 512
424 struct i40iw_vchnl_vf_msg_buffer
{
425 struct i40iw_virtchnl_op_buf vchnl_msg
;
426 char parm_buffer
[I40IW_VCHNL_MAX_VF_MSG_SIZE
- 1];
430 struct list_head qplist
;
431 spinlock_t lock
; /* qos list */
436 struct i40iw_sc_dev
*pf_dev
;
438 struct i40iw_vsi_pestat pestat
;
439 struct i40iw_hmc_pble_info
*pble_info
;
440 struct i40iw_hmc_info hmc_info
;
441 struct i40iw_vchnl_vf_msg_buffer vf_msg_buffer
;
442 u64 fpm_query_buf_pa
;
446 bool pf_hmc_initialized
;
448 u16 iw_vf_idx
; /* VF Device table index */
449 bool stats_initialized
;
452 #define I40IW_INVALID_FCN_ID 0xff
453 struct i40iw_sc_vsi
{
454 struct i40iw_sc_dev
*dev
;
455 void *back_vsi
; /* Owned by OS */
457 struct i40iw_virt_mem ilq_mem
;
458 struct i40iw_puda_rsrc
*ilq
;
460 struct i40iw_virt_mem ieq_mem
;
461 struct i40iw_puda_rsrc
*ieq
;
464 bool stats_fcn_id_alloc
;
465 struct i40iw_qos qos
[I40IW_MAX_USER_PRIORITY
];
466 struct i40iw_vsi_pestat
*pestat
;
469 struct i40iw_sc_dev
{
470 struct list_head cqp_cmd_head
; /* head of the CQP command list */
471 spinlock_t cqp_lock
; /* cqp list sync */
472 struct i40iw_dev_uk dev_uk
;
473 bool fcn_id_array
[I40IW_MAX_STATS_COUNT
];
474 struct i40iw_dma_mem vf_fpm_query_buf
[I40IW_MAX_PE_ENABLED_VF_COUNT
];
475 u64 fpm_query_buf_pa
;
476 u64 fpm_commit_buf_pa
;
482 struct i40iw_hmc_info
*hmc_info
;
483 struct i40iw_hmc_pble_info
*pble_info
;
484 struct i40iw_vfdev
*vf_dev
[I40IW_MAX_PE_ENABLED_VF_COUNT
];
485 struct i40iw_sc_cqp
*cqp
;
486 struct i40iw_sc_aeq
*aeq
;
487 struct i40iw_sc_ceq
*ceq
[I40IW_CEQ_MAX_COUNT
];
488 struct i40iw_sc_cq
*ccq
;
489 struct i40iw_cqp_ops
*cqp_ops
;
490 struct i40iw_ccq_ops
*ccq_ops
;
491 struct i40iw_ceq_ops
*ceq_ops
;
492 struct i40iw_aeq_ops
*aeq_ops
;
493 struct i40iw_pd_ops
*iw_pd_ops
;
494 struct i40iw_priv_qp_ops
*iw_priv_qp_ops
;
495 struct i40iw_priv_cq_ops
*iw_priv_cq_ops
;
496 struct i40iw_mr_ops
*mr_ops
;
497 struct i40iw_cqp_misc_ops
*cqp_misc_ops
;
498 struct i40iw_hmc_ops
*hmc_ops
;
499 struct i40iw_vchnl_if vchnl_if
;
500 const struct i40iw_vf_cqp_ops
*iw_vf_cqp_ops
;
502 struct i40iw_hmc_fpm_misc hmc_fpm_misc
;
504 u16 exception_lan_queue
;
509 wait_queue_head_t vf_reqs
;
510 u64 cqp_cmd_stats
[OP_SIZE_CQP_STAT_ARRAY
];
511 struct i40iw_vchnl_vf_msg_buffer vchnl_vf_msg_buf
;
515 struct i40iw_modify_cq_info
{
517 struct i40iw_cqe
*cq_base
;
521 u32 shadow_read_threshold
;
527 bool check_overflow_change
;
528 u32 first_pm_pbl_idx
;
532 struct i40iw_create_qp_info
{
538 bool arp_cache_idx_valid
;
541 struct i40iw_modify_qp_info
{
550 bool arp_cache_idx_valid
;
552 bool remove_hash_idx
;
555 bool cached_var_valid
;
559 struct i40iw_ccq_cqe_info
{
560 struct i40iw_sc_cqp
*cqp
;
569 struct i40iw_l2params
{
570 u16 qs_handle_list
[I40IW_MAX_USER_PRIORITY
];
574 struct i40iw_vsi_init_info
{
575 struct i40iw_sc_dev
*dev
;
577 struct i40iw_l2params
*params
;
580 struct i40iw_vsi_stats_info
{
581 struct i40iw_vsi_pestat
*pestat
;
584 bool stats_initialize
;
587 struct i40iw_device_init_info
{
588 u64 fpm_query_buf_pa
;
589 u64 fpm_commit_buf_pa
;
594 enum i40iw_status_code (*vchnl_send
)(struct i40iw_sc_dev
*, u32
, u8
*, u16
);
595 u16 exception_lan_queue
;
601 enum i40iw_cqp_hmc_profile
{
602 I40IW_HMC_PROFILE_DEFAULT
= 1,
603 I40IW_HMC_PROFILE_FAVOR_VF
= 2,
604 I40IW_HMC_PROFILE_EQUAL
= 3,
607 struct i40iw_cqp_init_info
{
611 struct i40iw_sc_dev
*dev
;
612 struct i40iw_cqp_quanta
*sq
;
617 bool en_datacenter_tcp
;
622 struct i40iw_ceq_init_info
{
624 struct i40iw_sc_dev
*dev
;
633 u32 first_pm_pbl_idx
;
636 struct i40iw_aeq_init_info
{
638 struct i40iw_sc_dev
*dev
;
644 u32 first_pm_pbl_idx
;
647 struct i40iw_ccq_init_info
{
650 struct i40iw_sc_dev
*dev
;
651 struct i40iw_cqe
*cq_base
;
656 u32 shadow_read_threshold
;
661 bool avoid_mem_cflct
;
664 u32 first_pm_pbl_idx
;
667 struct i40iwarp_offload_info
{
690 struct i40iw_tcp_offload_info
{
693 bool insert_vlan_tag
;
700 bool avoid_stretch_ack
;
716 u32 time_stamp_recent
;
737 bool ignore_tcp_uns_opt
;
740 struct i40iw_qp_host_ctx_info
{
742 struct i40iw_tcp_offload_info
*tcp_info
;
743 struct i40iwarp_offload_info
*iwarp_info
;
749 bool iwarp_info_valid
;
750 bool err_rq_idx_valid
;
756 struct i40iw_aeqe_info
{
772 struct i40iw_allocate_stag_info
{
780 bool use_hmc_fcn_index
;
785 struct i40iw_reg_ns_stag_info
{
792 u32 first_pm_pbl_index
;
793 enum i40iw_addressing_type addr_type
;
794 i40iw_stag_index stag_idx
;
797 i40iw_stag_key stag_key
;
798 bool use_hmc_fcn_index
;
803 struct i40iw_fast_reg_stag_info
{
811 u32 first_pm_pbl_index
;
812 enum i40iw_addressing_type addr_type
;
813 i40iw_stag_index stag_idx
;
816 i40iw_stag_key stag_key
;
820 bool use_hmc_fcn_index
;
826 struct i40iw_dealloc_stag_info
{
833 struct i40iw_register_shared_stag
{
835 enum i40iw_addressing_type addr_type
;
836 i40iw_stag_index new_stag_idx
;
837 i40iw_stag_index parent_stag_idx
;
840 i40iw_stag_key new_stag_key
;
843 struct i40iw_qp_init_info
{
844 struct i40iw_qp_uk_init_info qp_uk_init_info
;
845 struct i40iw_sc_pd
*pd
;
846 struct i40iw_sc_vsi
*vsi
;
865 struct i40iw_cq_init_info
{
866 struct i40iw_sc_dev
*dev
;
870 u32 shadow_read_threshold
;
874 u32 first_pm_pbl_idx
;
879 struct i40iw_cq_uk_init_info cq_uk_init_info
;
882 struct i40iw_upload_context_info
{
890 struct i40iw_add_arp_cache_entry_info
{
897 struct i40iw_apbvt_info
{
902 enum i40iw_quad_entry_type
{
903 I40IW_QHASH_TYPE_TCP_ESTABLISHED
= 1,
904 I40IW_QHASH_TYPE_TCP_SYN
,
907 enum i40iw_quad_hash_manage_type
{
908 I40IW_QHASH_MANAGE_TYPE_DELETE
= 0,
909 I40IW_QHASH_MANAGE_TYPE_ADD
,
910 I40IW_QHASH_MANAGE_TYPE_MODIFY
913 struct i40iw_qhash_table_info
{
914 struct i40iw_sc_vsi
*vsi
;
915 enum i40iw_quad_hash_manage_type manage
;
916 enum i40iw_quad_entry_type entry_type
;
929 struct i40iw_local_mac_ipaddr_entry_info
{
934 struct i40iw_cqp_manage_push_page_info
{
940 struct i40iw_qp_flush_info
{
953 struct i40iw_cqp_commit_fpm_values
{
958 u32 apbvt_inuse_base
;
982 struct i40iw_cqp_query_fpm_values
{
983 u16 first_pe_sd_index
;
1008 struct i40iw_cqp_ops
{
1009 enum i40iw_status_code (*cqp_init
)(struct i40iw_sc_cqp
*,
1010 struct i40iw_cqp_init_info
*);
1011 enum i40iw_status_code (*cqp_create
)(struct i40iw_sc_cqp
*, u16
*, u16
*);
1012 void (*cqp_post_sq
)(struct i40iw_sc_cqp
*);
1013 u64
*(*cqp_get_next_send_wqe
)(struct i40iw_sc_cqp
*, u64 scratch
);
1014 enum i40iw_status_code (*cqp_destroy
)(struct i40iw_sc_cqp
*);
1015 enum i40iw_status_code (*poll_for_cqp_op_done
)(struct i40iw_sc_cqp
*, u8
,
1016 struct i40iw_ccq_cqe_info
*);
1019 struct i40iw_ccq_ops
{
1020 enum i40iw_status_code (*ccq_init
)(struct i40iw_sc_cq
*,
1021 struct i40iw_ccq_init_info
*);
1022 enum i40iw_status_code (*ccq_create
)(struct i40iw_sc_cq
*, u64
, bool, bool);
1023 enum i40iw_status_code (*ccq_destroy
)(struct i40iw_sc_cq
*, u64
, bool);
1024 enum i40iw_status_code (*ccq_create_done
)(struct i40iw_sc_cq
*);
1025 enum i40iw_status_code (*ccq_get_cqe_info
)(struct i40iw_sc_cq
*,
1026 struct i40iw_ccq_cqe_info
*);
1027 void (*ccq_arm
)(struct i40iw_sc_cq
*);
1030 struct i40iw_ceq_ops
{
1031 enum i40iw_status_code (*ceq_init
)(struct i40iw_sc_ceq
*,
1032 struct i40iw_ceq_init_info
*);
1033 enum i40iw_status_code (*ceq_create
)(struct i40iw_sc_ceq
*, u64
, bool);
1034 enum i40iw_status_code (*cceq_create_done
)(struct i40iw_sc_ceq
*);
1035 enum i40iw_status_code (*cceq_destroy_done
)(struct i40iw_sc_ceq
*);
1036 enum i40iw_status_code (*cceq_create
)(struct i40iw_sc_ceq
*, u64
);
1037 enum i40iw_status_code (*ceq_destroy
)(struct i40iw_sc_ceq
*, u64
, bool);
1038 void *(*process_ceq
)(struct i40iw_sc_dev
*, struct i40iw_sc_ceq
*);
1041 struct i40iw_aeq_ops
{
1042 enum i40iw_status_code (*aeq_init
)(struct i40iw_sc_aeq
*,
1043 struct i40iw_aeq_init_info
*);
1044 enum i40iw_status_code (*aeq_create
)(struct i40iw_sc_aeq
*, u64
, bool);
1045 enum i40iw_status_code (*aeq_destroy
)(struct i40iw_sc_aeq
*, u64
, bool);
1046 enum i40iw_status_code (*get_next_aeqe
)(struct i40iw_sc_aeq
*,
1047 struct i40iw_aeqe_info
*);
1048 enum i40iw_status_code (*repost_aeq_entries
)(struct i40iw_sc_dev
*, u32
);
1049 enum i40iw_status_code (*aeq_create_done
)(struct i40iw_sc_aeq
*);
1050 enum i40iw_status_code (*aeq_destroy_done
)(struct i40iw_sc_aeq
*);
1053 struct i40iw_pd_ops
{
1054 void (*pd_init
)(struct i40iw_sc_dev
*, struct i40iw_sc_pd
*, u16
, int);
1057 struct i40iw_priv_qp_ops
{
1058 enum i40iw_status_code (*qp_init
)(struct i40iw_sc_qp
*, struct i40iw_qp_init_info
*);
1059 enum i40iw_status_code (*qp_create
)(struct i40iw_sc_qp
*,
1060 struct i40iw_create_qp_info
*, u64
, bool);
1061 enum i40iw_status_code (*qp_modify
)(struct i40iw_sc_qp
*,
1062 struct i40iw_modify_qp_info
*, u64
, bool);
1063 enum i40iw_status_code (*qp_destroy
)(struct i40iw_sc_qp
*, u64
, bool, bool, bool);
1064 enum i40iw_status_code (*qp_flush_wqes
)(struct i40iw_sc_qp
*,
1065 struct i40iw_qp_flush_info
*, u64
, bool);
1066 enum i40iw_status_code (*qp_upload_context
)(struct i40iw_sc_dev
*,
1067 struct i40iw_upload_context_info
*,
1069 enum i40iw_status_code (*qp_setctx
)(struct i40iw_sc_qp
*, u64
*,
1070 struct i40iw_qp_host_ctx_info
*);
1072 void (*qp_send_lsmm
)(struct i40iw_sc_qp
*, void *, u32
, i40iw_stag
);
1073 void (*qp_send_lsmm_nostag
)(struct i40iw_sc_qp
*, void *, u32
);
1074 void (*qp_send_rtt
)(struct i40iw_sc_qp
*, bool);
1075 enum i40iw_status_code (*qp_post_wqe0
)(struct i40iw_sc_qp
*, u8
);
1076 enum i40iw_status_code (*iw_mr_fast_register
)(struct i40iw_sc_qp
*,
1077 struct i40iw_fast_reg_stag_info
*,
1081 struct i40iw_priv_cq_ops
{
1082 enum i40iw_status_code (*cq_init
)(struct i40iw_sc_cq
*, struct i40iw_cq_init_info
*);
1083 enum i40iw_status_code (*cq_create
)(struct i40iw_sc_cq
*, u64
, bool, bool);
1084 enum i40iw_status_code (*cq_destroy
)(struct i40iw_sc_cq
*, u64
, bool);
1085 enum i40iw_status_code (*cq_modify
)(struct i40iw_sc_cq
*,
1086 struct i40iw_modify_cq_info
*, u64
, bool);
1089 struct i40iw_mr_ops
{
1090 enum i40iw_status_code (*alloc_stag
)(struct i40iw_sc_dev
*,
1091 struct i40iw_allocate_stag_info
*, u64
, bool);
1092 enum i40iw_status_code (*mr_reg_non_shared
)(struct i40iw_sc_dev
*,
1093 struct i40iw_reg_ns_stag_info
*,
1095 enum i40iw_status_code (*mr_reg_shared
)(struct i40iw_sc_dev
*,
1096 struct i40iw_register_shared_stag
*,
1098 enum i40iw_status_code (*dealloc_stag
)(struct i40iw_sc_dev
*,
1099 struct i40iw_dealloc_stag_info
*,
1101 enum i40iw_status_code (*query_stag
)(struct i40iw_sc_dev
*, u64
, u32
, bool);
1102 enum i40iw_status_code (*mw_alloc
)(struct i40iw_sc_dev
*, u64
, u32
, u16
, bool);
1105 struct i40iw_cqp_misc_ops
{
1106 enum i40iw_status_code (*manage_push_page
)(struct i40iw_sc_cqp
*,
1107 struct i40iw_cqp_manage_push_page_info
*,
1109 enum i40iw_status_code (*manage_hmc_pm_func_table
)(struct i40iw_sc_cqp
*,
1110 u64
, u8
, bool, bool);
1111 enum i40iw_status_code (*set_hmc_resource_profile
)(struct i40iw_sc_cqp
*,
1112 u64
, u8
, u8
, bool, bool);
1113 enum i40iw_status_code (*commit_fpm_values
)(struct i40iw_sc_cqp
*, u64
, u8
,
1114 struct i40iw_dma_mem
*, bool, u8
);
1115 enum i40iw_status_code (*query_fpm_values
)(struct i40iw_sc_cqp
*, u64
, u8
,
1116 struct i40iw_dma_mem
*, bool, u8
);
1117 enum i40iw_status_code (*static_hmc_pages_allocated
)(struct i40iw_sc_cqp
*,
1118 u64
, u8
, bool, bool);
1119 enum i40iw_status_code (*add_arp_cache_entry
)(struct i40iw_sc_cqp
*,
1120 struct i40iw_add_arp_cache_entry_info
*,
1122 enum i40iw_status_code (*del_arp_cache_entry
)(struct i40iw_sc_cqp
*, u64
, u16
, bool);
1123 enum i40iw_status_code (*query_arp_cache_entry
)(struct i40iw_sc_cqp
*, u64
, u16
, bool);
1124 enum i40iw_status_code (*manage_apbvt_entry
)(struct i40iw_sc_cqp
*,
1125 struct i40iw_apbvt_info
*, u64
, bool);
1126 enum i40iw_status_code (*manage_qhash_table_entry
)(struct i40iw_sc_cqp
*,
1127 struct i40iw_qhash_table_info
*, u64
, bool);
1128 enum i40iw_status_code (*alloc_local_mac_ipaddr_table_entry
)(struct i40iw_sc_cqp
*, u64
, bool);
1129 enum i40iw_status_code (*add_local_mac_ipaddr_entry
)(struct i40iw_sc_cqp
*,
1130 struct i40iw_local_mac_ipaddr_entry_info
*,
1132 enum i40iw_status_code (*del_local_mac_ipaddr_entry
)(struct i40iw_sc_cqp
*, u64
, u8
, u8
, bool);
1133 enum i40iw_status_code (*cqp_nop
)(struct i40iw_sc_cqp
*, u64
, bool);
1134 enum i40iw_status_code (*commit_fpm_values_done
)(struct i40iw_sc_cqp
1136 enum i40iw_status_code (*query_fpm_values_done
)(struct i40iw_sc_cqp
*);
1137 enum i40iw_status_code (*manage_hmc_pm_func_table_done
)(struct i40iw_sc_cqp
*);
1138 enum i40iw_status_code (*update_suspend_qp
)(struct i40iw_sc_cqp
*, struct i40iw_sc_qp
*, u64
);
1139 enum i40iw_status_code (*update_resume_qp
)(struct i40iw_sc_cqp
*, struct i40iw_sc_qp
*, u64
);
1142 struct i40iw_hmc_ops
{
1143 enum i40iw_status_code (*init_iw_hmc
)(struct i40iw_sc_dev
*, u8
);
1144 enum i40iw_status_code (*parse_fpm_query_buf
)(u64
*, struct i40iw_hmc_info
*,
1145 struct i40iw_hmc_fpm_misc
*);
1146 enum i40iw_status_code (*configure_iw_fpm
)(struct i40iw_sc_dev
*, u8
);
1147 enum i40iw_status_code (*parse_fpm_commit_buf
)(u64
*, struct i40iw_hmc_obj_info
*, u32
*sd
);
1148 enum i40iw_status_code (*create_hmc_object
)(struct i40iw_sc_dev
*dev
,
1149 struct i40iw_hmc_create_obj_info
*);
1150 enum i40iw_status_code (*del_hmc_object
)(struct i40iw_sc_dev
*dev
,
1151 struct i40iw_hmc_del_obj_info
*,
1153 enum i40iw_status_code (*pf_init_vfhmc
)(struct i40iw_sc_dev
*, u8
, u32
*);
1154 enum i40iw_status_code (*vf_configure_vffpm
)(struct i40iw_sc_dev
*, u32
*);
1160 struct i40iw_sc_qp
*qp
;
1161 struct i40iw_create_qp_info info
;
1166 struct i40iw_sc_qp
*qp
;
1167 struct i40iw_modify_qp_info info
;
1172 struct i40iw_sc_qp
*qp
;
1174 bool remove_hash_idx
;
1179 struct i40iw_sc_cq
*cq
;
1181 bool check_overflow
;
1185 struct i40iw_sc_cq
*cq
;
1190 struct i40iw_sc_dev
*dev
;
1191 struct i40iw_allocate_stag_info info
;
1196 struct i40iw_sc_dev
*dev
;
1203 struct i40iw_sc_dev
*dev
;
1204 struct i40iw_reg_ns_stag_info info
;
1206 } mr_reg_non_shared
;
1209 struct i40iw_sc_dev
*dev
;
1210 struct i40iw_dealloc_stag_info info
;
1215 struct i40iw_sc_cqp
*cqp
;
1216 struct i40iw_local_mac_ipaddr_entry_info info
;
1218 } add_local_mac_ipaddr_entry
;
1221 struct i40iw_sc_cqp
*cqp
;
1222 struct i40iw_add_arp_cache_entry_info info
;
1224 } add_arp_cache_entry
;
1227 struct i40iw_sc_cqp
*cqp
;
1230 u8 ignore_ref_count
;
1231 } del_local_mac_ipaddr_entry
;
1234 struct i40iw_sc_cqp
*cqp
;
1237 } del_arp_cache_entry
;
1240 struct i40iw_sc_cqp
*cqp
;
1241 struct i40iw_manage_vf_pble_info info
;
1243 } manage_vf_pble_bp
;
1246 struct i40iw_sc_cqp
*cqp
;
1247 struct i40iw_cqp_manage_push_page_info info
;
1252 struct i40iw_sc_dev
*dev
;
1253 struct i40iw_upload_context_info info
;
1255 } qp_upload_context
;
1258 struct i40iw_sc_cqp
*cqp
;
1260 } alloc_local_mac_ipaddr_entry
;
1263 struct i40iw_sc_dev
*dev
;
1264 struct i40iw_hmc_fcn_info info
;
1269 struct i40iw_sc_ceq
*ceq
;
1274 struct i40iw_sc_ceq
*ceq
;
1279 struct i40iw_sc_aeq
*aeq
;
1284 struct i40iw_sc_aeq
*aeq
;
1289 struct i40iw_sc_qp
*qp
;
1290 struct i40iw_qp_flush_info info
;
1295 struct i40iw_sc_cqp
*cqp
;
1296 void *fpm_values_va
;
1303 struct i40iw_sc_cqp
*cqp
;
1304 void *fpm_values_va
;
1308 } commit_fpm_values
;
1311 struct i40iw_sc_cqp
*cqp
;
1312 struct i40iw_apbvt_info info
;
1314 } manage_apbvt_entry
;
1317 struct i40iw_sc_cqp
*cqp
;
1318 struct i40iw_qhash_table_info info
;
1320 } manage_qhash_table_entry
;
1323 struct i40iw_sc_dev
*dev
;
1324 struct i40iw_update_sds_info info
;
1329 struct i40iw_sc_cqp
*cqp
;
1330 struct i40iw_sc_qp
*qp
;
1336 struct cqp_commands_info
{
1337 struct list_head cqp_cmd_entry
;
1343 struct i40iw_virtchnl_work_info
{
1344 void (*callback_fcn
)(void *vf_dev
);
1345 void *worker_vf_dev
;