drivers/infiniband/hw/ipath/ipath_iba6120.c

   1 /*
   2  * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved.
   3  * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33 /*
  34  * This file contains all of the code that is specific to the
  35  * InfiniPath PCIe chip.
  36  */
  37
  38 #include <linux/interrupt.h>
  39 #include <linux/pci.h>
  40 #include <linux/delay.h>
  41
  42
  43 #include "ipath_kernel.h"
  44 #include "ipath_registers.h"
  45
  46 static void ipath_setup_pe_setextled(struct ipath_devdata *, u64, u64);
  47
  48 /*
  49  * This file contains all the chip-specific register information and
  50  * access functions for the QLogic InfiniPath PCI-Express chip.
  51  *
  52  * This lists the InfiniPath registers, in the actual chip layout.
  53  * This structure should never be directly accessed.
  54  */
  55 struct _infinipath_do_not_use_kernel_regs {
  56         unsigned long long Revision;
  57         unsigned long long Control;
  58         unsigned long long PageAlign;
  59         unsigned long long PortCnt;
  60         unsigned long long DebugPortSelect;
  61         unsigned long long Reserved0;
  62         unsigned long long SendRegBase;
  63         unsigned long long UserRegBase;
  64         unsigned long long CounterRegBase;
  65         unsigned long long Scratch;
  66         unsigned long long Reserved1;
  67         unsigned long long Reserved2;
  68         unsigned long long IntBlocked;
  69         unsigned long long IntMask;
  70         unsigned long long IntStatus;
  71         unsigned long long IntClear;
  72         unsigned long long ErrorMask;
  73         unsigned long long ErrorStatus;
  74         unsigned long long ErrorClear;
  75         unsigned long long HwErrMask;
  76         unsigned long long HwErrStatus;
  77         unsigned long long HwErrClear;
  78         unsigned long long HwDiagCtrl;
  79         unsigned long long MDIO;
  80         unsigned long long IBCStatus;
  81         unsigned long long IBCCtrl;
  82         unsigned long long ExtStatus;
  83         unsigned long long ExtCtrl;
  84         unsigned long long GPIOOut;
  85         unsigned long long GPIOMask;
  86         unsigned long long GPIOStatus;
  87         unsigned long long GPIOClear;
  88         unsigned long long RcvCtrl;
  89         unsigned long long RcvBTHQP;
  90         unsigned long long RcvHdrSize;
  91         unsigned long long RcvHdrCnt;
  92         unsigned long long RcvHdrEntSize;
  93         unsigned long long RcvTIDBase;
  94         unsigned long long RcvTIDCnt;
  95         unsigned long long RcvEgrBase;
  96         unsigned long long RcvEgrCnt;
  97         unsigned long long RcvBufBase;
  98         unsigned long long RcvBufSize;
  99         unsigned long long RxIntMemBase;
 100         unsigned long long RxIntMemSize;
 101         unsigned long long RcvPartitionKey;
 102         unsigned long long Reserved3;
 103         unsigned long long RcvPktLEDCnt;
 104         unsigned long long Reserved4[8];
 105         unsigned long long SendCtrl;
 106         unsigned long long SendPIOBufBase;
 107         unsigned long long SendPIOSize;
 108         unsigned long long SendPIOBufCnt;
 109         unsigned long long SendPIOAvailAddr;
 110         unsigned long long TxIntMemBase;
 111         unsigned long long TxIntMemSize;
 112         unsigned long long Reserved5;
 113         unsigned long long PCIeRBufTestReg0;
 114         unsigned long long PCIeRBufTestReg1;
 115         unsigned long long Reserved51[6];
 116         unsigned long long SendBufferError;
 117         unsigned long long SendBufferErrorCONT1;
 118         unsigned long long Reserved6SBE[6];
 119         unsigned long long RcvHdrAddr0;
 120         unsigned long long RcvHdrAddr1;
 121         unsigned long long RcvHdrAddr2;
 122         unsigned long long RcvHdrAddr3;
 123         unsigned long long RcvHdrAddr4;
 124         unsigned long long Reserved7RHA[11];
 125         unsigned long long RcvHdrTailAddr0;
 126         unsigned long long RcvHdrTailAddr1;
 127         unsigned long long RcvHdrTailAddr2;
 128         unsigned long long RcvHdrTailAddr3;
 129         unsigned long long RcvHdrTailAddr4;
 130         unsigned long long Reserved8RHTA[11];
 131         unsigned long long Reserved9SW[8];
 132         unsigned long long SerdesConfig0;
 133         unsigned long long SerdesConfig1;
 134         unsigned long long SerdesStatus;
 135         unsigned long long XGXSConfig;
 136         unsigned long long IBPLLCfg;
 137         unsigned long long Reserved10SW2[3];
 138         unsigned long long PCIEQ0SerdesConfig0;
 139         unsigned long long PCIEQ0SerdesConfig1;
 140         unsigned long long PCIEQ0SerdesStatus;
 141         unsigned long long Reserved11;
 142         unsigned long long PCIEQ1SerdesConfig0;
 143         unsigned long long PCIEQ1SerdesConfig1;
 144         unsigned long long PCIEQ1SerdesStatus;
 145         unsigned long long Reserved12;
 146 };
 147
 148 #define IPATH_KREG_OFFSET(field) (offsetof(struct \
 149     _infinipath_do_not_use_kernel_regs, field) / sizeof(u64))
 150 #define IPATH_CREG_OFFSET(field) (offsetof( \
 151     struct infinipath_counters, field) / sizeof(u64))
 152
 153 static const struct ipath_kregs ipath_pe_kregs = {
 154         .kr_control = IPATH_KREG_OFFSET(Control),
 155         .kr_counterregbase = IPATH_KREG_OFFSET(CounterRegBase),
 156         .kr_debugportselect = IPATH_KREG_OFFSET(DebugPortSelect),
 157         .kr_errorclear = IPATH_KREG_OFFSET(ErrorClear),
 158         .kr_errormask = IPATH_KREG_OFFSET(ErrorMask),
 159         .kr_errorstatus = IPATH_KREG_OFFSET(ErrorStatus),
 160         .kr_extctrl = IPATH_KREG_OFFSET(ExtCtrl),
 161         .kr_extstatus = IPATH_KREG_OFFSET(ExtStatus),
 162         .kr_gpio_clear = IPATH_KREG_OFFSET(GPIOClear),
 163         .kr_gpio_mask = IPATH_KREG_OFFSET(GPIOMask),
 164         .kr_gpio_out = IPATH_KREG_OFFSET(GPIOOut),
 165         .kr_gpio_status = IPATH_KREG_OFFSET(GPIOStatus),
 166         .kr_hwdiagctrl = IPATH_KREG_OFFSET(HwDiagCtrl),
 167         .kr_hwerrclear = IPATH_KREG_OFFSET(HwErrClear),
 168         .kr_hwerrmask = IPATH_KREG_OFFSET(HwErrMask),
 169         .kr_hwerrstatus = IPATH_KREG_OFFSET(HwErrStatus),
 170         .kr_ibcctrl = IPATH_KREG_OFFSET(IBCCtrl),
 171         .kr_ibcstatus = IPATH_KREG_OFFSET(IBCStatus),
 172         .kr_intblocked = IPATH_KREG_OFFSET(IntBlocked),
 173         .kr_intclear = IPATH_KREG_OFFSET(IntClear),
 174         .kr_intmask = IPATH_KREG_OFFSET(IntMask),
 175         .kr_intstatus = IPATH_KREG_OFFSET(IntStatus),
 176         .kr_mdio = IPATH_KREG_OFFSET(MDIO),
 177         .kr_pagealign = IPATH_KREG_OFFSET(PageAlign),
 178         .kr_partitionkey = IPATH_KREG_OFFSET(RcvPartitionKey),
 179         .kr_portcnt = IPATH_KREG_OFFSET(PortCnt),
 180         .kr_rcvbthqp = IPATH_KREG_OFFSET(RcvBTHQP),
 181         .kr_rcvbufbase = IPATH_KREG_OFFSET(RcvBufBase),
 182         .kr_rcvbufsize = IPATH_KREG_OFFSET(RcvBufSize),
 183         .kr_rcvctrl = IPATH_KREG_OFFSET(RcvCtrl),
 184         .kr_rcvegrbase = IPATH_KREG_OFFSET(RcvEgrBase),
 185         .kr_rcvegrcnt = IPATH_KREG_OFFSET(RcvEgrCnt),
 186         .kr_rcvhdrcnt = IPATH_KREG_OFFSET(RcvHdrCnt),
 187         .kr_rcvhdrentsize = IPATH_KREG_OFFSET(RcvHdrEntSize),
 188         .kr_rcvhdrsize = IPATH_KREG_OFFSET(RcvHdrSize),
 189         .kr_rcvintmembase = IPATH_KREG_OFFSET(RxIntMemBase),
 190         .kr_rcvintmemsize = IPATH_KREG_OFFSET(RxIntMemSize),
 191         .kr_rcvtidbase = IPATH_KREG_OFFSET(RcvTIDBase),
 192         .kr_rcvtidcnt = IPATH_KREG_OFFSET(RcvTIDCnt),
 193         .kr_revision = IPATH_KREG_OFFSET(Revision),
 194         .kr_scratch = IPATH_KREG_OFFSET(Scratch),
 195         .kr_sendbuffererror = IPATH_KREG_OFFSET(SendBufferError),
 196         .kr_sendctrl = IPATH_KREG_OFFSET(SendCtrl),
 197         .kr_sendpioavailaddr = IPATH_KREG_OFFSET(SendPIOAvailAddr),
 198         .kr_sendpiobufbase = IPATH_KREG_OFFSET(SendPIOBufBase),
 199         .kr_sendpiobufcnt = IPATH_KREG_OFFSET(SendPIOBufCnt),
 200         .kr_sendpiosize = IPATH_KREG_OFFSET(SendPIOSize),
 201         .kr_sendregbase = IPATH_KREG_OFFSET(SendRegBase),
 202         .kr_txintmembase = IPATH_KREG_OFFSET(TxIntMemBase),
 203         .kr_txintmemsize = IPATH_KREG_OFFSET(TxIntMemSize),
 204         .kr_userregbase = IPATH_KREG_OFFSET(UserRegBase),
 205         .kr_serdesconfig0 = IPATH_KREG_OFFSET(SerdesConfig0),
 206         .kr_serdesconfig1 = IPATH_KREG_OFFSET(SerdesConfig1),
 207         .kr_serdesstatus = IPATH_KREG_OFFSET(SerdesStatus),
 208         .kr_xgxsconfig = IPATH_KREG_OFFSET(XGXSConfig),
 209         .kr_ibpllcfg = IPATH_KREG_OFFSET(IBPLLCfg),
 210
 211         /*
 212          * These should not be used directly via ipath_write_kreg64(),
 213          * use them with ipath_write_kreg64_port(),
 214          */
 215         .kr_rcvhdraddr = IPATH_KREG_OFFSET(RcvHdrAddr0),
 216         .kr_rcvhdrtailaddr = IPATH_KREG_OFFSET(RcvHdrTailAddr0),
 217
 218         /* The rcvpktled register controls one of the debug port signals, so
 219          * a packet activity LED can be connected to it. */
 220         .kr_rcvpktledcnt = IPATH_KREG_OFFSET(RcvPktLEDCnt),
 221         .kr_pcierbuftestreg0 = IPATH_KREG_OFFSET(PCIeRBufTestReg0),
 222         .kr_pcierbuftestreg1 = IPATH_KREG_OFFSET(PCIeRBufTestReg1),
 223         .kr_pcieq0serdesconfig0 = IPATH_KREG_OFFSET(PCIEQ0SerdesConfig0),
 224         .kr_pcieq0serdesconfig1 = IPATH_KREG_OFFSET(PCIEQ0SerdesConfig1),
 225         .kr_pcieq0serdesstatus = IPATH_KREG_OFFSET(PCIEQ0SerdesStatus),
 226         .kr_pcieq1serdesconfig0 = IPATH_KREG_OFFSET(PCIEQ1SerdesConfig0),
 227         .kr_pcieq1serdesconfig1 = IPATH_KREG_OFFSET(PCIEQ1SerdesConfig1),
 228         .kr_pcieq1serdesstatus = IPATH_KREG_OFFSET(PCIEQ1SerdesStatus)
 229 };
 230
 231 static const struct ipath_cregs ipath_pe_cregs = {
 232         .cr_badformatcnt = IPATH_CREG_OFFSET(RxBadFormatCnt),
 233         .cr_erricrccnt = IPATH_CREG_OFFSET(RxICRCErrCnt),
 234         .cr_errlinkcnt = IPATH_CREG_OFFSET(RxLinkProblemCnt),
 235         .cr_errlpcrccnt = IPATH_CREG_OFFSET(RxLPCRCErrCnt),
 236         .cr_errpkey = IPATH_CREG_OFFSET(RxPKeyMismatchCnt),
 237         .cr_errrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowCtrlErrCnt),
 238         .cr_err_rlencnt = IPATH_CREG_OFFSET(RxLenErrCnt),
 239         .cr_errslencnt = IPATH_CREG_OFFSET(TxLenErrCnt),
 240         .cr_errtidfull = IPATH_CREG_OFFSET(RxTIDFullErrCnt),
 241         .cr_errtidvalid = IPATH_CREG_OFFSET(RxTIDValidErrCnt),
 242         .cr_errvcrccnt = IPATH_CREG_OFFSET(RxVCRCErrCnt),
 243         .cr_ibstatuschange = IPATH_CREG_OFFSET(IBStatusChangeCnt),
 244         .cr_intcnt = IPATH_CREG_OFFSET(LBIntCnt),
 245         .cr_invalidrlencnt = IPATH_CREG_OFFSET(RxMaxMinLenErrCnt),
 246         .cr_invalidslencnt = IPATH_CREG_OFFSET(TxMaxMinLenErrCnt),
 247         .cr_lbflowstallcnt = IPATH_CREG_OFFSET(LBFlowStallCnt),
 248         .cr_pktrcvcnt = IPATH_CREG_OFFSET(RxDataPktCnt),
 249         .cr_pktrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowPktCnt),
 250         .cr_pktsendcnt = IPATH_CREG_OFFSET(TxDataPktCnt),
 251         .cr_pktsendflowcnt = IPATH_CREG_OFFSET(TxFlowPktCnt),
 252         .cr_portovflcnt = IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt),
 253         .cr_rcvebpcnt = IPATH_CREG_OFFSET(RxEBPCnt),
 254         .cr_rcvovflcnt = IPATH_CREG_OFFSET(RxBufOvflCnt),
 255         .cr_senddropped = IPATH_CREG_OFFSET(TxDroppedPktCnt),
 256         .cr_sendstallcnt = IPATH_CREG_OFFSET(TxFlowStallCnt),
 257         .cr_sendunderruncnt = IPATH_CREG_OFFSET(TxUnderrunCnt),
 258         .cr_wordrcvcnt = IPATH_CREG_OFFSET(RxDwordCnt),
 259         .cr_wordsendcnt = IPATH_CREG_OFFSET(TxDwordCnt),
 260         .cr_unsupvlcnt = IPATH_CREG_OFFSET(TxUnsupVLErrCnt),
 261         .cr_rxdroppktcnt = IPATH_CREG_OFFSET(RxDroppedPktCnt),
 262         .cr_iblinkerrrecovcnt = IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt),
 263         .cr_iblinkdowncnt = IPATH_CREG_OFFSET(IBLinkDownedCnt),
 264         .cr_ibsymbolerrcnt = IPATH_CREG_OFFSET(IBSymbolErrCnt)
 265 };
 266
 267 /* kr_intstatus, kr_intclear, kr_intmask bits */
 268 #define INFINIPATH_I_RCVURG_MASK ((1U<<5)-1)
 269 #define INFINIPATH_I_RCVAVAIL_MASK ((1U<<5)-1)
 270
 271 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
 272 #define INFINIPATH_HWE_PCIEMEMPARITYERR_MASK  0x000000000000003fULL
 273 #define INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT 0
 274 #define INFINIPATH_HWE_PCIEPOISONEDTLP      0x0000000010000000ULL
 275 #define INFINIPATH_HWE_PCIECPLTIMEOUT       0x0000000020000000ULL
 276 #define INFINIPATH_HWE_PCIEBUSPARITYXTLH    0x0000000040000000ULL
 277 #define INFINIPATH_HWE_PCIEBUSPARITYXADM    0x0000000080000000ULL
 278 #define INFINIPATH_HWE_PCIEBUSPARITYRADM    0x0000000100000000ULL
 279 #define INFINIPATH_HWE_COREPLL_FBSLIP       0x0080000000000000ULL
 280 #define INFINIPATH_HWE_COREPLL_RFSLIP       0x0100000000000000ULL
 281 #define INFINIPATH_HWE_PCIE1PLLFAILED       0x0400000000000000ULL
 282 #define INFINIPATH_HWE_PCIE0PLLFAILED       0x0800000000000000ULL
 283 #define INFINIPATH_HWE_SERDESPLLFAILED      0x1000000000000000ULL
 284
 285 /* kr_extstatus bits */
 286 #define INFINIPATH_EXTS_FREQSEL 0x2
 287 #define INFINIPATH_EXTS_SERDESSEL 0x4
 288 #define INFINIPATH_EXTS_MEMBIST_ENDTEST     0x0000000000004000
 289 #define INFINIPATH_EXTS_MEMBIST_FOUND       0x0000000000008000
 290
 291 #define _IPATH_GPIO_SDA_NUM 1
 292 #define _IPATH_GPIO_SCL_NUM 0
 293
 294 #define IPATH_GPIO_SDA (1ULL << \
 295         (_IPATH_GPIO_SDA_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
 296 #define IPATH_GPIO_SCL (1ULL << \
 297         (_IPATH_GPIO_SCL_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
 298
 299 /* 6120 specific hardware errors... */
 300 static const struct ipath_hwerror_msgs ipath_6120_hwerror_msgs[] = {
 301         INFINIPATH_HWE_MSG(PCIEPOISONEDTLP, "PCIe Poisoned TLP"),
 302         INFINIPATH_HWE_MSG(PCIECPLTIMEOUT, "PCIe completion timeout"),
 303         /*
 304          * In practice, it's unlikely wthat we'll see PCIe PLL, or bus
 305          * parity or memory parity error failures, because most likely we
 306          * won't be able to talk to the core of the chip.  Nonetheless, we
 307          * might see them, if they are in parts of the PCIe core that aren't
 308          * essential.
 309          */
 310         INFINIPATH_HWE_MSG(PCIE1PLLFAILED, "PCIePLL1"),
 311         INFINIPATH_HWE_MSG(PCIE0PLLFAILED, "PCIePLL0"),
 312         INFINIPATH_HWE_MSG(PCIEBUSPARITYXTLH, "PCIe XTLH core parity"),
 313         INFINIPATH_HWE_MSG(PCIEBUSPARITYXADM, "PCIe ADM TX core parity"),
 314         INFINIPATH_HWE_MSG(PCIEBUSPARITYRADM, "PCIe ADM RX core parity"),
 315         INFINIPATH_HWE_MSG(RXDSYNCMEMPARITYERR, "Rx Dsync"),
 316         INFINIPATH_HWE_MSG(SERDESPLLFAILED, "SerDes PLL"),
 317 };
 318
 319 #define TXE_PIO_PARITY ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF | \
 320                         INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC) \
 321                         << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT)
 322
 323 static int ipath_pe_txe_recover(struct ipath_devdata *);
 324 static void ipath_pe_put_tid_2(struct ipath_devdata *, u64 __iomem *,
 325                                u32, unsigned long);
 326
 327 /**
 328  * ipath_pe_handle_hwerrors - display hardware errors.
 329  * @dd: the infinipath device
 330  * @msg: the output buffer
 331  * @msgl: the size of the output buffer
 332  *
 333  * Use same msg buffer as regular errors to avoid excessive stack
 334  * use.  Most hardware errors are catastrophic, but for right now,
 335  * we'll print them and continue.  We reuse the same message buffer as
 336  * ipath_handle_errors() to avoid excessive stack usage.
 337  */
 338 static void ipath_pe_handle_hwerrors(struct ipath_devdata *dd, char *msg,
 339                                      size_t msgl)
 340 {
 341         ipath_err_t hwerrs;
 342         u32 bits, ctrl;
 343         int isfatal = 0;
 344         char bitsmsg[64];
 345         int log_idx;
 346
 347         hwerrs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus);
 348         if (!hwerrs) {
 349                 /*
 350                  * better than printing cofusing messages
 351                  * This seems to be related to clearing the crc error, or
 352                  * the pll error during init.
 353                  */
 354                 ipath_cdbg(VERBOSE, "Called but no hardware errors set\n");
 355                 return;
 356         } else if (hwerrs == ~0ULL) {
 357                 ipath_dev_err(dd, "Read of hardware error status failed "
 358                               "(all bits set); ignoring\n");
 359                 return;
 360         }
 361         ipath_stats.sps_hwerrs++;
 362
 363         /* Always clear the error status register, except MEMBISTFAIL,
 364          * regardless of whether we continue or stop using the chip.
 365          * We want that set so we know it failed, even across driver reload.
 366          * We'll still ignore it in the hwerrmask.  We do this partly for
 367          * diagnostics, but also for support */
 368         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
 369                          hwerrs&~INFINIPATH_HWE_MEMBISTFAILED);
 370
 371         hwerrs &= dd->ipath_hwerrmask;
 372
 373         /* We log some errors to EEPROM, check if we have any of those. */
 374         for (log_idx = 0; log_idx < IPATH_EEP_LOG_CNT; ++log_idx)
 375                 if (hwerrs & dd->ipath_eep_st_masks[log_idx].hwerrs_to_log)
 376                         ipath_inc_eeprom_err(dd, log_idx, 1);
 377
 378         /*
 379          * make sure we get this much out, unless told to be quiet,
 380          * or it's occurred within the last 5 seconds
 381          */
 382         if ((hwerrs & ~(dd->ipath_lasthwerror |
 383                         ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF |
 384                           INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC)
 385                          << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT))) ||
 386             (ipath_debug & __IPATH_VERBDBG))
 387                 dev_info(&dd->pcidev->dev, "Hardware error: hwerr=0x%llx "
 388                          "(cleared)\n", (unsigned long long) hwerrs);
 389         dd->ipath_lasthwerror |= hwerrs;
 390
 391         if (hwerrs & ~dd->ipath_hwe_bitsextant)
 392                 ipath_dev_err(dd, "hwerror interrupt with unknown errors "
 393                               "%llx set\n", (unsigned long long)
 394                               (hwerrs & ~dd->ipath_hwe_bitsextant));
 395
 396         ctrl = ipath_read_kreg32(dd, dd->ipath_kregs->kr_control);
 397         if (ctrl & INFINIPATH_C_FREEZEMODE) {
 398                 /*
 399                  * parity errors in send memory are recoverable,
 400                  * just cancel the send (if indicated in * sendbuffererror),
 401                  * count the occurrence, unfreeze (if no other handled
 402                  * hardware error bits are set), and continue. They can
 403                  * occur if a processor speculative read is done to the PIO
 404                  * buffer while we are sending a packet, for example.
 405                  */
 406                 if ((hwerrs & TXE_PIO_PARITY) && ipath_pe_txe_recover(dd))
 407                         hwerrs &= ~TXE_PIO_PARITY;
 408                 if (hwerrs) {
 409                         /*
 410                          * if any set that we aren't ignoring only make the
 411                          * complaint once, in case it's stuck or recurring,
 412                          * and we get here multiple times
 413                          * Force link down, so switch knows, and
 414                          * LEDs are turned off
 415                          */
 416                         if (dd->ipath_flags & IPATH_INITTED) {
 417                                 ipath_set_linkstate(dd, IPATH_IB_LINKDOWN);
 418                                 ipath_setup_pe_setextled(dd,
 419                                         INFINIPATH_IBCS_L_STATE_DOWN,
 420                                         INFINIPATH_IBCS_LT_STATE_DISABLED);
 421                                 ipath_dev_err(dd, "Fatal Hardware Error (freeze "
 422                                               "mode), no longer usable, SN %.16s\n",
 423                                                   dd->ipath_serial);
 424                                 isfatal = 1;
 425                         }
 426                         /*
 427                          * Mark as having had an error for driver, and also
 428                          * for /sys and status word mapped to user programs.
 429                          * This marks unit as not usable, until reset
 430                          */
 431                         *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
 432                         *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
 433                         dd->ipath_flags &= ~IPATH_INITTED;
 434                 } else {
 435                         static u32 freeze_cnt;
 436
 437                         freeze_cnt++;
 438                         ipath_dbg("Clearing freezemode on ignored or recovered "
 439                                   "hardware error (%u)\n", freeze_cnt);
 440                         ipath_clear_freeze(dd);
 441                 }
 442         }
 443
 444         *msg = '\0';
 445
 446         if (hwerrs & INFINIPATH_HWE_MEMBISTFAILED) {
 447                 strlcat(msg, "[Memory BIST test failed, InfiniPath hardware unusable]",
 448                         msgl);
 449                 /* ignore from now on, so disable until driver reloaded */
 450                 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
 451                 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_MEMBISTFAILED;
 452                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 453                                  dd->ipath_hwerrmask);
 454         }
 455
 456         ipath_format_hwerrors(hwerrs,
 457                               ipath_6120_hwerror_msgs,
 458                               sizeof(ipath_6120_hwerror_msgs)/
 459                               sizeof(ipath_6120_hwerror_msgs[0]),
 460                               msg, msgl);
 461
 462         if (hwerrs & (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK
 463                       << INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT)) {
 464                 bits = (u32) ((hwerrs >>
 465                                INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) &
 466                               INFINIPATH_HWE_PCIEMEMPARITYERR_MASK);
 467                 snprintf(bitsmsg, sizeof bitsmsg,
 468                          "[PCIe Mem Parity Errs %x] ", bits);
 469                 strlcat(msg, bitsmsg, msgl);
 470         }
 471
 472 #define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP |        \
 473                          INFINIPATH_HWE_COREPLL_RFSLIP )
 474
 475         if (hwerrs & _IPATH_PLL_FAIL) {
 476                 snprintf(bitsmsg, sizeof bitsmsg,
 477                          "[PLL failed (%llx), InfiniPath hardware unusable]",
 478                          (unsigned long long) hwerrs & _IPATH_PLL_FAIL);
 479                 strlcat(msg, bitsmsg, msgl);
 480                 /* ignore from now on, so disable until driver reloaded */
 481                 dd->ipath_hwerrmask &= ~(hwerrs & _IPATH_PLL_FAIL);
 482                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 483                                  dd->ipath_hwerrmask);
 484         }
 485
 486         if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED) {
 487                 /*
 488                  * If it occurs, it is left masked since the eternal
 489                  * interface is unused
 490                  */
 491                 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_SERDESPLLFAILED;
 492                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 493                                  dd->ipath_hwerrmask);
 494         }
 495
 496         if (*msg)
 497                 ipath_dev_err(dd, "%s hardware error\n", msg);
 498         if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg) {
 499                 /*
 500                  * for /sys status file ; if no trailing } is copied, we'll
 501                  * know it was truncated.
 502                  */
 503                 snprintf(dd->ipath_freezemsg, dd->ipath_freezelen,
 504                          "{%s}", msg);
 505         }
 506 }
 507
 508 /**
 509  * ipath_pe_boardname - fill in the board name
 510  * @dd: the infinipath device
 511  * @name: the output buffer
 512  * @namelen: the size of the output buffer
 513  *
 514  * info is based on the board revision register
 515  */
 516 static int ipath_pe_boardname(struct ipath_devdata *dd, char *name,
 517                               size_t namelen)
 518 {
 519         char *n = NULL;
 520         u8 boardrev = dd->ipath_boardrev;
 521         int ret;
 522
 523         switch (boardrev) {
 524         case 0:
 525                 n = "InfiniPath_Emulation";
 526                 break;
 527         case 1:
 528                 n = "InfiniPath_QLE7140-Bringup";
 529                 break;
 530         case 2:
 531                 n = "InfiniPath_QLE7140";
 532                 break;
 533         case 3:
 534                 n = "InfiniPath_QMI7140";
 535                 break;
 536         case 4:
 537                 n = "InfiniPath_QEM7140";
 538                 break;
 539         case 5:
 540                 n = "InfiniPath_QMH7140";
 541                 break;
 542         case 6:
 543                 n = "InfiniPath_QLE7142";
 544                 break;
 545         default:
 546                 ipath_dev_err(dd,
 547                               "Don't yet know about board with ID %u\n",
 548                               boardrev);
 549                 snprintf(name, namelen, "Unknown_InfiniPath_PCIe_%u",
 550                          boardrev);
 551                 break;
 552         }
 553         if (n)
 554                 snprintf(name, namelen, "%s", n);
 555
 556         if (dd->ipath_majrev != 4 || !dd->ipath_minrev || dd->ipath_minrev>2) {
 557                 ipath_dev_err(dd, "Unsupported InfiniPath hardware revision %u.%u!\n",
 558                               dd->ipath_majrev, dd->ipath_minrev);
 559                 ret = 1;
 560         } else {
 561                 ret = 0;
 562                 if (dd->ipath_minrev >= 2)
 563                         dd->ipath_f_put_tid = ipath_pe_put_tid_2;
 564         }
 565
 566         return ret;
 567 }
 568
 569 /**
 570  * ipath_pe_init_hwerrors - enable hardware errors
 571  * @dd: the infinipath device
 572  *
 573  * now that we have finished initializing everything that might reasonably
 574  * cause a hardware error, and cleared those errors bits as they occur,
 575  * we can enable hardware errors in the mask (potentially enabling
 576  * freeze mode), and enable hardware errors as errors (along with
 577  * everything else) in errormask
 578  */
 579 static void ipath_pe_init_hwerrors(struct ipath_devdata *dd)
 580 {
 581         ipath_err_t val;
 582         u64 extsval;
 583
 584         extsval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
 585
 586         if (!(extsval & INFINIPATH_EXTS_MEMBIST_ENDTEST))
 587                 ipath_dev_err(dd, "MemBIST did not complete!\n");
 588         if (extsval & INFINIPATH_EXTS_MEMBIST_FOUND)
 589                 ipath_dbg("MemBIST corrected\n");
 590
 591         val = ~0ULL;    /* barring bugs, all hwerrors become interrupts, */
 592
 593         if (!dd->ipath_boardrev)        // no PLL for Emulator
 594                 val &= ~INFINIPATH_HWE_SERDESPLLFAILED;
 595
 596         if (dd->ipath_minrev < 2) {
 597                 /* workaround bug 9460 in internal interface bus parity
 598                  * checking. Fixed (HW bug 9490) in Rev2.
 599                  */
 600                 val &= ~INFINIPATH_HWE_PCIEBUSPARITYRADM;
 601         }
 602         dd->ipath_hwerrmask = val;
 603 }
 604
 605 /**
 606  * ipath_pe_bringup_serdes - bring up the serdes
 607  * @dd: the infinipath device
 608  */
 609 static int ipath_pe_bringup_serdes(struct ipath_devdata *dd)
 610 {
 611         u64 val, config1, prev_val;
 612         int ret = 0;
 613
 614         ipath_dbg("Trying to bringup serdes\n");
 615
 616         if (ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus) &
 617             INFINIPATH_HWE_SERDESPLLFAILED) {
 618                 ipath_dbg("At start, serdes PLL failed bit set "
 619                           "in hwerrstatus, clearing and continuing\n");
 620                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
 621                                  INFINIPATH_HWE_SERDESPLLFAILED);
 622         }
 623
 624         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
 625         config1 = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig1);
 626
 627         ipath_cdbg(VERBOSE, "SerDes status config0=%llx config1=%llx, "
 628                    "xgxsconfig %llx\n", (unsigned long long) val,
 629                    (unsigned long long) config1, (unsigned long long)
 630                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
 631
 632         /*
 633          * Force reset on, also set rxdetect enable.  Must do before reading
 634          * serdesstatus at least for simulation, or some of the bits in
 635          * serdes status will come back as undefined and cause simulation
 636          * failures
 637          */
 638         val |= INFINIPATH_SERDC0_RESET_PLL | INFINIPATH_SERDC0_RXDETECT_EN
 639                 | INFINIPATH_SERDC0_L1PWR_DN;
 640         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
 641         /* be sure chip saw it */
 642         ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
 643         udelay(5);              /* need pll reset set at least for a bit */
 644         /*
 645          * after PLL is reset, set the per-lane Resets and TxIdle and
 646          * clear the PLL reset and rxdetect (to get falling edge).
 647          * Leave L1PWR bits set (permanently)
 648          */
 649         val &= ~(INFINIPATH_SERDC0_RXDETECT_EN | INFINIPATH_SERDC0_RESET_PLL
 650                  | INFINIPATH_SERDC0_L1PWR_DN);
 651         val |= INFINIPATH_SERDC0_RESET_MASK | INFINIPATH_SERDC0_TXIDLE;
 652         ipath_cdbg(VERBOSE, "Clearing pll reset and setting lane resets "
 653                    "and txidle (%llx)\n", (unsigned long long) val);
 654         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
 655         /* be sure chip saw it */
 656         ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
 657         /* need PLL reset clear for at least 11 usec before lane
 658          * resets cleared; give it a few more to be sure */
 659         udelay(15);
 660         val &= ~(INFINIPATH_SERDC0_RESET_MASK | INFINIPATH_SERDC0_TXIDLE);
 661
 662         ipath_cdbg(VERBOSE, "Clearing lane resets and txidle "
 663                    "(writing %llx)\n", (unsigned long long) val);
 664         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
 665         /* be sure chip saw it */
 666         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
 667
 668         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
 669         prev_val = val;
 670         if (((val >> INFINIPATH_XGXS_MDIOADDR_SHIFT) &
 671              INFINIPATH_XGXS_MDIOADDR_MASK) != 3) {
 672                 val &=
 673                         ~(INFINIPATH_XGXS_MDIOADDR_MASK <<
 674                           INFINIPATH_XGXS_MDIOADDR_SHIFT);
 675                 /* MDIO address 3 */
 676                 val |= 3ULL << INFINIPATH_XGXS_MDIOADDR_SHIFT;
 677         }
 678         if (val & INFINIPATH_XGXS_RESET) {
 679                 val &= ~INFINIPATH_XGXS_RESET;
 680         }
 681         if (((val >> INFINIPATH_XGXS_RX_POL_SHIFT) &
 682              INFINIPATH_XGXS_RX_POL_MASK) != dd->ipath_rx_pol_inv ) {
 683                 /* need to compensate for Tx inversion in partner */
 684                 val &= ~(INFINIPATH_XGXS_RX_POL_MASK <<
 685                          INFINIPATH_XGXS_RX_POL_SHIFT);
 686                 val |= dd->ipath_rx_pol_inv <<
 687                         INFINIPATH_XGXS_RX_POL_SHIFT;
 688         }
 689         if (val != prev_val)
 690                 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
 691
 692         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
 693
 694         /* clear current and de-emphasis bits */
 695         config1 &= ~0x0ffffffff00ULL;
 696         /* set current to 20ma */
 697         config1 |= 0x00000000000ULL;
 698         /* set de-emphasis to -5.68dB */
 699         config1 |= 0x0cccc000000ULL;
 700         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig1, config1);
 701
 702         ipath_cdbg(VERBOSE, "done: SerDes status config0=%llx "
 703                    "config1=%llx, sstatus=%llx xgxs=%llx\n",
 704                    (unsigned long long) val, (unsigned long long) config1,
 705                    (unsigned long long)
 706                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
 707                    (unsigned long long)
 708                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
 709
 710         if (!ipath_waitfor_mdio_cmdready(dd)) {
 711                 ipath_write_kreg(
 712                         dd, dd->ipath_kregs->kr_mdio,
 713                         ipath_mdio_req(IPATH_MDIO_CMD_READ, 31,
 714                                        IPATH_MDIO_CTRL_XGXS_REG_8, 0));
 715                 if (ipath_waitfor_complete(dd, dd->ipath_kregs->kr_mdio,
 716                                            IPATH_MDIO_DATAVALID, &val))
 717                         ipath_dbg("Never got MDIO data for XGXS "
 718                                   "status read\n");
 719                 else
 720                         ipath_cdbg(VERBOSE, "MDIO Read reg8, "
 721                                    "'bank' 31 %x\n", (u32) val);
 722         } else
 723                 ipath_dbg("Never got MDIO cmdready for XGXS status read\n");
 724
 725         return ret;
 726 }
 727
 728 /**
 729  * ipath_pe_quiet_serdes - set serdes to txidle
 730  * @dd: the infinipath device
 731  * Called when driver is being unloaded
 732  */
 733 static void ipath_pe_quiet_serdes(struct ipath_devdata *dd)
 734 {
 735         u64 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
 736
 737         val |= INFINIPATH_SERDC0_TXIDLE;
 738         ipath_dbg("Setting TxIdleEn on serdes (config0 = %llx)\n",
 739                   (unsigned long long) val);
 740         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
 741 }
 742
 743 static int ipath_pe_intconfig(struct ipath_devdata *dd)
 744 {
 745         u32 chiprev;
 746
 747         /*
 748          * If the chip supports added error indication via GPIO pins,
 749          * enable interrupts on those bits so the interrupt routine
 750          * can count the events. Also set flag so interrupt routine
 751          * can know they are expected.
 752          */
 753         chiprev = dd->ipath_revision >> INFINIPATH_R_CHIPREVMINOR_SHIFT;
 754         if ((chiprev & INFINIPATH_R_CHIPREVMINOR_MASK) > 1) {
 755                 /* Rev2+ reports extra errors via internal GPIO pins */
 756                 dd->ipath_flags |= IPATH_GPIO_ERRINTRS;
 757                 dd->ipath_gpio_mask |= IPATH_GPIO_ERRINTR_MASK;
 758                 ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_mask,
 759                                  dd->ipath_gpio_mask);
 760         }
 761         return 0;
 762 }
 763
 764 /**
 765  * ipath_setup_pe_setextled - set the state of the two external LEDs
 766  * @dd: the infinipath device
 767  * @lst: the L state
 768  * @ltst: the LT state
 769
 770  * These LEDs indicate the physical and logical state of IB link.
 771  * For this chip (at least with recommended board pinouts), LED1
 772  * is Yellow (logical state) and LED2 is Green (physical state),
 773  *
 774  * Note:  We try to match the Mellanox HCA LED behavior as best
 775  * we can.  Green indicates physical link state is OK (something is
 776  * plugged in, and we can train).
 777  * Amber indicates the link is logically up (ACTIVE).
 778  * Mellanox further blinks the amber LED to indicate data packet
 779  * activity, but we have no hardware support for that, so it would
 780  * require waking up every 10-20 msecs and checking the counters
 781  * on the chip, and then turning the LED off if appropriate.  That's
 782  * visible overhead, so not something we will do.
 783  *
 784  */
 785 static void ipath_setup_pe_setextled(struct ipath_devdata *dd, u64 lst,
 786                                      u64 ltst)
 787 {
 788         u64 extctl;
 789         unsigned long flags = 0;
 790
 791         /* the diags use the LED to indicate diag info, so we leave
 792          * the external LED alone when the diags are running */
 793         if (ipath_diag_inuse)
 794                 return;
 795
 796         /* Allow override of LED display for, e.g. Locating system in rack */
 797         if (dd->ipath_led_override) {
 798                 ltst = (dd->ipath_led_override & IPATH_LED_PHYS)
 799                         ? INFINIPATH_IBCS_LT_STATE_LINKUP
 800                         : INFINIPATH_IBCS_LT_STATE_DISABLED;
 801                 lst = (dd->ipath_led_override & IPATH_LED_LOG)
 802                         ? INFINIPATH_IBCS_L_STATE_ACTIVE
 803                         : INFINIPATH_IBCS_L_STATE_DOWN;
 804         }
 805
 806         spin_lock_irqsave(&dd->ipath_gpio_lock, flags);
 807         extctl = dd->ipath_extctrl & ~(INFINIPATH_EXTC_LED1PRIPORT_ON |
 808                                        INFINIPATH_EXTC_LED2PRIPORT_ON);
 809
 810         if (ltst & INFINIPATH_IBCS_LT_STATE_LINKUP)
 811                 extctl |= INFINIPATH_EXTC_LED2PRIPORT_ON;
 812         if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
 813                 extctl |= INFINIPATH_EXTC_LED1PRIPORT_ON;
 814         dd->ipath_extctrl = extctl;
 815         ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, extctl);
 816         spin_unlock_irqrestore(&dd->ipath_gpio_lock, flags);
 817 }
 818
 819 /**
 820  * ipath_setup_pe_cleanup - clean up any per-chip chip-specific stuff
 821  * @dd: the infinipath device
 822  *
 823  * This is called during driver unload.
 824  * We do the pci_disable_msi here, not in generic code, because it
 825  * isn't used for the HT chips. If we do end up needing pci_enable_msi
 826  * at some point in the future for HT, we'll move the call back
 827  * into the main init_one code.
 828  */
 829 static void ipath_setup_pe_cleanup(struct ipath_devdata *dd)
 830 {
 831         dd->ipath_msi_lo = 0;   /* just in case unload fails */
 832         pci_disable_msi(dd->pcidev);
 833 }
 834
 835 /**
 836  * ipath_setup_pe_config - setup PCIe config related stuff
 837  * @dd: the infinipath device
 838  * @pdev: the PCI device
 839  *
 840  * The pci_enable_msi() call will fail on systems with MSI quirks
 841  * such as those with AMD8131, even if the device of interest is not
 842  * attached to that device, (in the 2.6.13 - 2.6.15 kernels, at least, fixed
 843  * late in 2.6.16).
 844  * All that can be done is to edit the kernel source to remove the quirk
 845  * check until that is fixed.
 846  * We do not need to call enable_msi() for our HyperTransport chip,
 847  * even though it uses MSI, and we want to avoid the quirk warning, so
 848  * So we call enable_msi only for PCIe.  If we do end up needing
 849  * pci_enable_msi at some point in the future for HT, we'll move the
 850  * call back into the main init_one code.
 851  * We save the msi lo and hi values, so we can restore them after
 852  * chip reset (the kernel PCI infrastructure doesn't yet handle that
 853  * correctly).
 854  */
 855 static int ipath_setup_pe_config(struct ipath_devdata *dd,
 856                                  struct pci_dev *pdev)
 857 {
 858         int pos, ret;
 859
 860         dd->ipath_msi_lo = 0;   /* used as a flag during reset processing */
 861         ret = pci_enable_msi(dd->pcidev);
 862         if (ret)
 863                 ipath_dev_err(dd, "pci_enable_msi failed: %d, "
 864                               "interrupts may not work\n", ret);
 865         /* continue even if it fails, we may still be OK... */
 866         dd->ipath_irq = pdev->irq;
 867
 868         if ((pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI))) {
 869                 u16 control;
 870                 pci_read_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
 871                                       &dd->ipath_msi_lo);
 872                 pci_read_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
 873                                       &dd->ipath_msi_hi);
 874                 pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
 875                                      &control);
 876                 /* now save the data (vector) info */
 877                 pci_read_config_word(dd->pcidev,
 878                                      pos + ((control & PCI_MSI_FLAGS_64BIT)
 879                                             ? 12 : 8),
 880                                      &dd->ipath_msi_data);
 881                 ipath_cdbg(VERBOSE, "Read msi data 0x%x from config offset "
 882                            "0x%x, control=0x%x\n", dd->ipath_msi_data,
 883                            pos + ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
 884                            control);
 885                 /* we save the cachelinesize also, although it doesn't
 886                  * really matter */
 887                 pci_read_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE,
 888                                      &dd->ipath_pci_cacheline);
 889         } else
 890                 ipath_dev_err(dd, "Can't find MSI capability, "
 891                               "can't save MSI settings for reset\n");
 892         if ((pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_EXP))) {
 893                 u16 linkstat;
 894                 pci_read_config_word(dd->pcidev, pos + PCI_EXP_LNKSTA,
 895                                      &linkstat);
 896                 linkstat >>= 4;
 897                 linkstat &= 0x1f;
 898                 if (linkstat != 8)
 899                         ipath_dev_err(dd, "PCIe width %u, "
 900                                       "performance reduced\n", linkstat);
 901         }
 902         else
 903                 ipath_dev_err(dd, "Can't find PCI Express "
 904                               "capability!\n");
 905         return 0;
 906 }
 907
 908 static void ipath_init_pe_variables(struct ipath_devdata *dd)
 909 {
 910         /*
 911          * bits for selecting i2c direction and values,
 912          * used for I2C serial flash
 913          */
 914         dd->ipath_gpio_sda_num = _IPATH_GPIO_SDA_NUM;
 915         dd->ipath_gpio_scl_num = _IPATH_GPIO_SCL_NUM;
 916         dd->ipath_gpio_sda = IPATH_GPIO_SDA;
 917         dd->ipath_gpio_scl = IPATH_GPIO_SCL;
 918
 919         /* variables for sanity checking interrupt and errors */
 920         dd->ipath_hwe_bitsextant =
 921                 (INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
 922                  INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) |
 923                 (INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
 924                  INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) |
 925                 (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK <<
 926                  INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) |
 927                 INFINIPATH_HWE_PCIE1PLLFAILED |
 928                 INFINIPATH_HWE_PCIE0PLLFAILED |
 929                 INFINIPATH_HWE_PCIEPOISONEDTLP |
 930                 INFINIPATH_HWE_PCIECPLTIMEOUT |
 931                 INFINIPATH_HWE_PCIEBUSPARITYXTLH |
 932                 INFINIPATH_HWE_PCIEBUSPARITYXADM |
 933                 INFINIPATH_HWE_PCIEBUSPARITYRADM |
 934                 INFINIPATH_HWE_MEMBISTFAILED |
 935                 INFINIPATH_HWE_COREPLL_FBSLIP |
 936                 INFINIPATH_HWE_COREPLL_RFSLIP |
 937                 INFINIPATH_HWE_SERDESPLLFAILED |
 938                 INFINIPATH_HWE_IBCBUSTOSPCPARITYERR |
 939                 INFINIPATH_HWE_IBCBUSFRSPCPARITYERR;
 940         dd->ipath_i_bitsextant =
 941                 (INFINIPATH_I_RCVURG_MASK << INFINIPATH_I_RCVURG_SHIFT) |
 942                 (INFINIPATH_I_RCVAVAIL_MASK <<
 943                  INFINIPATH_I_RCVAVAIL_SHIFT) |
 944                 INFINIPATH_I_ERROR | INFINIPATH_I_SPIOSENT |
 945                 INFINIPATH_I_SPIOBUFAVAIL | INFINIPATH_I_GPIO;
 946         dd->ipath_e_bitsextant =
 947                 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RVCRC |
 948                 INFINIPATH_E_RICRC | INFINIPATH_E_RMINPKTLEN |
 949                 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RLONGPKTLEN |
 950                 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RUNEXPCHAR |
 951                 INFINIPATH_E_RUNSUPVL | INFINIPATH_E_REBP |
 952                 INFINIPATH_E_RIBFLOW | INFINIPATH_E_RBADVERSION |
 953                 INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL |
 954                 INFINIPATH_E_RBADTID | INFINIPATH_E_RHDRLEN |
 955                 INFINIPATH_E_RHDR | INFINIPATH_E_RIBLOSTLINK |
 956                 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SMAXPKTLEN |
 957                 INFINIPATH_E_SUNDERRUN | INFINIPATH_E_SPKTLEN |
 958                 INFINIPATH_E_SDROPPEDSMPPKT | INFINIPATH_E_SDROPPEDDATAPKT |
 959                 INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM |
 960                 INFINIPATH_E_SUNSUPVL | INFINIPATH_E_IBSTATUSCHANGED |
 961                 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET |
 962                 INFINIPATH_E_HARDWARE;
 963
 964         dd->ipath_i_rcvavail_mask = INFINIPATH_I_RCVAVAIL_MASK;
 965         dd->ipath_i_rcvurg_mask = INFINIPATH_I_RCVURG_MASK;
 966
 967         /*
 968          * EEPROM error log 0 is TXE Parity errors. 1 is RXE Parity.
 969          * 2 is Some Misc, 3 is reserved for future.
 970          */
 971         dd->ipath_eep_st_masks[0].hwerrs_to_log =
 972                 INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
 973                 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT;
 974
 975         /* Ignore errors in PIO/PBC on systems with unordered write-combining */
 976         if (ipath_unordered_wc())
 977                 dd->ipath_eep_st_masks[0].hwerrs_to_log &= ~TXE_PIO_PARITY;
 978
 979         dd->ipath_eep_st_masks[1].hwerrs_to_log =
 980                 INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
 981                 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT;
 982
 983         dd->ipath_eep_st_masks[2].errs_to_log =
 984                 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET;
 985
 986
 987 }
 988
 989 /* setup the MSI stuff again after a reset.  I'd like to just call
 990  * pci_enable_msi() and request_irq() again, but when I do that,
 991  * the MSI enable bit doesn't get set in the command word, and
 992  * we switch to to a different interrupt vector, which is confusing,
 993  * so I instead just do it all inline.  Perhaps somehow can tie this
 994  * into the PCIe hotplug support at some point
 995  * Note, because I'm doing it all here, I don't call pci_disable_msi()
 996  * or free_irq() at the start of ipath_setup_pe_reset().
 997  */
 998 static int ipath_reinit_msi(struct ipath_devdata *dd)
 999 {
1000         int pos;
1001         u16 control;
1002         int ret;
1003
1004         if (!dd->ipath_msi_lo) {
1005                 dev_info(&dd->pcidev->dev, "Can't restore MSI config, "
1006                          "initial setup failed?\n");
1007                 ret = 0;
1008                 goto bail;
1009         }
1010
1011         if (!(pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI))) {
1012                 ipath_dev_err(dd, "Can't find MSI capability, "
1013                               "can't restore MSI settings\n");
1014                 ret = 0;
1015                 goto bail;
1016         }
1017         ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n",
1018                    dd->ipath_msi_lo, pos + PCI_MSI_ADDRESS_LO);
1019         pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
1020                                dd->ipath_msi_lo);
1021         ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n",
1022                    dd->ipath_msi_hi, pos + PCI_MSI_ADDRESS_HI);
1023         pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
1024                                dd->ipath_msi_hi);
1025         pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, &control);
1026         if (!(control & PCI_MSI_FLAGS_ENABLE)) {
1027                 ipath_cdbg(VERBOSE, "MSI control at off %x was %x, "
1028                            "setting MSI enable (%x)\n", pos + PCI_MSI_FLAGS,
1029                            control, control | PCI_MSI_FLAGS_ENABLE);
1030                 control |= PCI_MSI_FLAGS_ENABLE;
1031                 pci_write_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
1032                                       control);
1033         }
1034         /* now rewrite the data (vector) info */
1035         pci_write_config_word(dd->pcidev, pos +
1036                               ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
1037                               dd->ipath_msi_data);
1038         /* we restore the cachelinesize also, although it doesn't really
1039          * matter */
1040         pci_write_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE,
1041                               dd->ipath_pci_cacheline);
1042         /* and now set the pci master bit again */
1043         pci_set_master(dd->pcidev);
1044         ret = 1;
1045
1046 bail:
1047         return ret;
1048 }
1049
1050 /* This routine sleeps, so it can only be called from user context, not
1051  * from interrupt context.  If we need interrupt context, we can split
1052  * it into two routines.
1053 */
1054 static int ipath_setup_pe_reset(struct ipath_devdata *dd)
1055 {
1056         u64 val;
1057         int i;
1058         int ret;
1059
1060         /* Use ERROR so it shows up in logs, etc. */
1061         ipath_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->ipath_unit);
1062         /* keep chip from being accessed in a few places */
1063         dd->ipath_flags &= ~(IPATH_INITTED|IPATH_PRESENT);
1064         val = dd->ipath_control | INFINIPATH_C_RESET;
1065         ipath_write_kreg(dd, dd->ipath_kregs->kr_control, val);
1066         mb();
1067
1068         for (i = 1; i <= 5; i++) {
1069                 int r;
1070                 /* allow MBIST, etc. to complete; longer on each retry.
1071                  * We sometimes get machine checks from bus timeout if no
1072                  * response, so for now, make it *really* long.
1073                  */
1074                 msleep(1000 + (1 + i) * 2000);
1075                 if ((r =
1076                      pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
1077                                             dd->ipath_pcibar0)))
1078                         ipath_dev_err(dd, "rewrite of BAR0 failed: %d\n",
1079                                       r);
1080                 if ((r =
1081                      pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1,
1082                                             dd->ipath_pcibar1)))
1083                         ipath_dev_err(dd, "rewrite of BAR1 failed: %d\n",
1084                                       r);
1085                 /* now re-enable memory access */
1086                 if ((r = pci_enable_device(dd->pcidev)))
1087                         ipath_dev_err(dd, "pci_enable_device failed after "
1088                                       "reset: %d\n", r);
1089                 /* whether it worked or not, mark as present, again */
1090                 dd->ipath_flags |= IPATH_PRESENT;
1091                 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision);
1092                 if (val == dd->ipath_revision) {
1093                         ipath_cdbg(VERBOSE, "Got matching revision "
1094                                    "register %llx on try %d\n",
1095                                    (unsigned long long) val, i);
1096                         ret = ipath_reinit_msi(dd);
1097                         goto bail;
1098                 }
1099                 /* Probably getting -1 back */
1100                 ipath_dbg("Didn't get expected revision register, "
1101                           "got %llx, try %d\n", (unsigned long long) val,
1102                           i + 1);
1103         }
1104         ret = 0; /* failed */
1105
1106 bail:
1107         return ret;
1108 }
1109
1110 /**
1111  * ipath_pe_put_tid - write a TID in chip
1112  * @dd: the infinipath device
1113  * @tidptr: pointer to the expected TID (in chip) to udpate
1114  * @tidtype: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0) for expected
1115  * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1116  *
1117  * This exists as a separate routine to allow for special locking etc.
1118  * It's used for both the full cleanup on exit, as well as the normal
1119  * setup and teardown.
1120  */
1121 static void ipath_pe_put_tid(struct ipath_devdata *dd, u64 __iomem *tidptr,
1122                              u32 type, unsigned long pa)
1123 {
1124         u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
1125         unsigned long flags = 0; /* keep gcc quiet */
1126
1127         if (pa != dd->ipath_tidinvalid) {
1128                 if (pa & ((1U << 11) - 1)) {
1129                         dev_info(&dd->pcidev->dev, "BUG: physaddr %lx "
1130                                  "not 4KB aligned!\n", pa);
1131                         return;
1132                 }
1133                 pa >>= 11;
1134                 /* paranoia check */
1135                 if (pa & (7<<29))
1136                         ipath_dev_err(dd,
1137                                       "BUG: Physical page address 0x%lx "
1138                                       "has bits set in 31-29\n", pa);
1139
1140                 if (type == RCVHQ_RCV_TYPE_EAGER)
1141                         pa |= dd->ipath_tidtemplate;
1142                 else /* for now, always full 4KB page */
1143                         pa |= 2 << 29;
1144         }
1145
1146         /*
1147          * Workaround chip bug 9437 by writing the scratch register
1148          * before and after the TID, and with an io write barrier.
1149          * We use a spinlock around the writes, so they can't intermix
1150          * with other TID (eager or expected) writes (the chip bug
1151          * is triggered by back to back TID writes). Unfortunately, this
1152          * call can be done from interrupt level for the port 0 eager TIDs,
1153          * so we have to use irqsave locks.
1154          */
1155         spin_lock_irqsave(&dd->ipath_tid_lock, flags);
1156         ipath_write_kreg(dd, dd->ipath_kregs->kr_scratch, 0xfeeddeaf);
1157         if (dd->ipath_kregbase)
1158                 writel(pa, tidp32);
1159         ipath_write_kreg(dd, dd->ipath_kregs->kr_scratch, 0xdeadbeef);
1160         mmiowb();
1161         spin_unlock_irqrestore(&dd->ipath_tid_lock, flags);
1162 }
1163 /**
1164  * ipath_pe_put_tid_2 - write a TID in chip, Revision 2 or higher
1165  * @dd: the infinipath device
1166  * @tidptr: pointer to the expected TID (in chip) to udpate
1167  * @tidtype: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0) for expected
1168  * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1169  *
1170  * This exists as a separate routine to allow for selection of the
1171  * appropriate "flavor". The static calls in cleanup just use the
1172  * revision-agnostic form, as they are not performance critical.
1173  */
1174 static void ipath_pe_put_tid_2(struct ipath_devdata *dd, u64 __iomem *tidptr,
1175                              u32 type, unsigned long pa)
1176 {
1177         u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
1178
1179         if (pa != dd->ipath_tidinvalid) {
1180                 if (pa & ((1U << 11) - 1)) {
1181                         dev_info(&dd->pcidev->dev, "BUG: physaddr %lx "
1182                                  "not 2KB aligned!\n", pa);
1183                         return;
1184                 }
1185                 pa >>= 11;
1186                 /* paranoia check */
1187                 if (pa & (7<<29))
1188                         ipath_dev_err(dd,
1189                                       "BUG: Physical page address 0x%lx "
1190                                       "has bits set in 31-29\n", pa);
1191
1192                 if (type == RCVHQ_RCV_TYPE_EAGER)
1193                         pa |= dd->ipath_tidtemplate;
1194                 else /* for now, always full 4KB page */
1195                         pa |= 2 << 29;
1196         }
1197         if (dd->ipath_kregbase)
1198                 writel(pa, tidp32);
1199         mmiowb();
1200 }
1201
1202
1203 /**
1204  * ipath_pe_clear_tid - clear all TID entries for a port, expected and eager
1205  * @dd: the infinipath device
1206  * @port: the port
1207  *
1208  * clear all TID entries for a port, expected and eager.
1209  * Used from ipath_close().  On this chip, TIDs are only 32 bits,
1210  * not 64, but they are still on 64 bit boundaries, so tidbase
1211  * is declared as u64 * for the pointer math, even though we write 32 bits
1212  */
1213 static void ipath_pe_clear_tids(struct ipath_devdata *dd, unsigned port)
1214 {
1215         u64 __iomem *tidbase;
1216         unsigned long tidinv;
1217         int i;
1218
1219         if (!dd->ipath_kregbase)
1220                 return;
1221
1222         ipath_cdbg(VERBOSE, "Invalidate TIDs for port %u\n", port);
1223
1224         tidinv = dd->ipath_tidinvalid;
1225         tidbase = (u64 __iomem *)
1226                 ((char __iomem *)(dd->ipath_kregbase) +
1227                  dd->ipath_rcvtidbase +
1228                  port * dd->ipath_rcvtidcnt * sizeof(*tidbase));
1229
1230         for (i = 0; i < dd->ipath_rcvtidcnt; i++)
1231                 dd->ipath_f_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
1232                                  tidinv);
1233
1234         tidbase = (u64 __iomem *)
1235                 ((char __iomem *)(dd->ipath_kregbase) +
1236                  dd->ipath_rcvegrbase +
1237                  port * dd->ipath_rcvegrcnt * sizeof(*tidbase));
1238
1239         for (i = 0; i < dd->ipath_rcvegrcnt; i++)
1240                 dd->ipath_f_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER,
1241                                  tidinv);
1242 }
1243
1244 /**
1245  * ipath_pe_tidtemplate - setup constants for TID updates
1246  * @dd: the infinipath device
1247  *
1248  * We setup stuff that we use a lot, to avoid calculating each time
1249  */
1250 static void ipath_pe_tidtemplate(struct ipath_devdata *dd)
1251 {
1252         u32 egrsize = dd->ipath_rcvegrbufsize;
1253
1254         /* For now, we always allocate 4KB buffers (at init) so we can
1255          * receive max size packets.  We may want a module parameter to
1256          * specify 2KB or 4KB and/or make be per port instead of per device
1257          * for those who want to reduce memory footprint.  Note that the
1258          * ipath_rcvhdrentsize size must be large enough to hold the largest
1259          * IB header (currently 96 bytes) that we expect to handle (plus of
1260          * course the 2 dwords of RHF).
1261          */
1262         if (egrsize == 2048)
1263                 dd->ipath_tidtemplate = 1U << 29;
1264         else if (egrsize == 4096)
1265                 dd->ipath_tidtemplate = 2U << 29;
1266         else {
1267                 egrsize = 4096;
1268                 dev_info(&dd->pcidev->dev, "BUG: unsupported egrbufsize "
1269                          "%u, using %u\n", dd->ipath_rcvegrbufsize,
1270                          egrsize);
1271                 dd->ipath_tidtemplate = 2U << 29;
1272         }
1273         dd->ipath_tidinvalid = 0;
1274 }
1275
1276 static int ipath_pe_early_init(struct ipath_devdata *dd)
1277 {
1278         dd->ipath_flags |= IPATH_4BYTE_TID;
1279         if (ipath_unordered_wc())
1280                 dd->ipath_flags |= IPATH_PIO_FLUSH_WC;
1281
1282         /*
1283          * For openfabrics, we need to be able to handle an IB header of
1284          * 24 dwords.  HT chip has arbitrary sized receive buffers, so we
1285          * made them the same size as the PIO buffers.  This chip does not
1286          * handle arbitrary size buffers, so we need the header large enough
1287          * to handle largest IB header, but still have room for a 2KB MTU
1288          * standard IB packet.
1289          */
1290         dd->ipath_rcvhdrentsize = 24;
1291         dd->ipath_rcvhdrsize = IPATH_DFLT_RCVHDRSIZE;
1292
1293         /*
1294          * To truly support a 4KB MTU (for usermode), we need to
1295          * bump this to a larger value.  For now, we use them for
1296          * the kernel only.
1297          */
1298         dd->ipath_rcvegrbufsize = 2048;
1299         /*
1300          * the min() check here is currently a nop, but it may not always
1301          * be, depending on just how we do ipath_rcvegrbufsize
1302          */
1303         dd->ipath_ibmaxlen = min(dd->ipath_piosize2k,
1304                                  dd->ipath_rcvegrbufsize +
1305                                  (dd->ipath_rcvhdrentsize << 2));
1306         dd->ipath_init_ibmaxlen = dd->ipath_ibmaxlen;
1307
1308         /*
1309          * We can request a receive interrupt for 1 or
1310          * more packets from current offset.  For now, we set this
1311          * up for a single packet.
1312          */
1313         dd->ipath_rhdrhead_intr_off = 1ULL<<32;
1314
1315         ipath_get_eeprom_info(dd);
1316
1317         return 0;
1318 }
1319
1320 int __attribute__((weak)) ipath_unordered_wc(void)
1321 {
1322         return 0;
1323 }
1324
1325 /**
1326  * ipath_init_pe_get_base_info - set chip-specific flags for user code
1327  * @pd: the infinipath port
1328  * @kbase: ipath_base_info pointer
1329  *
1330  * We set the PCIE flag because the lower bandwidth on PCIe vs
1331  * HyperTransport can affect some user packet algorithms.
1332  */
1333 static int ipath_pe_get_base_info(struct ipath_portdata *pd, void *kbase)
1334 {
1335         struct ipath_base_info *kinfo = kbase;
1336         struct ipath_devdata *dd;
1337
1338         if (ipath_unordered_wc()) {
1339                 kinfo->spi_runtime_flags |= IPATH_RUNTIME_FORCE_WC_ORDER;
1340                 ipath_cdbg(PROC, "Intel processor, forcing WC order\n");
1341         }
1342         else
1343                 ipath_cdbg(PROC, "Not Intel processor, WC ordered\n");
1344
1345         if (pd == NULL)
1346                 goto done;
1347
1348         dd = pd->port_dd;
1349
1350 done:
1351         kinfo->spi_runtime_flags |= IPATH_RUNTIME_PCIE |
1352                 IPATH_RUNTIME_FORCE_PIOAVAIL | IPATH_RUNTIME_PIO_REGSWAPPED;
1353         return 0;
1354 }
1355
1356 static void ipath_pe_free_irq(struct ipath_devdata *dd)
1357 {
1358         free_irq(dd->ipath_irq, dd);
1359         dd->ipath_irq = 0;
1360 }
1361
1362 /*
1363  * On platforms using this chip, and not having ordered WC stores, we
1364  * can get TXE parity errors due to speculative reads to the PIO buffers,
1365  * and this, due to a chip bug can result in (many) false parity error
1366  * reports.  So it's a debug print on those, and an info print on systems
1367  * where the speculative reads don't occur.
1368  * Because we can get lots of false errors, we have no upper limit
1369  * on recovery attempts on those platforms.
1370  */
1371 static int ipath_pe_txe_recover(struct ipath_devdata *dd)
1372 {
1373         if (ipath_unordered_wc())
1374                 ipath_dbg("Recovering from TXE PIO parity error\n");
1375         else {
1376                 int cnt = ++ipath_stats.sps_txeparity;
1377                 if (cnt >= IPATH_MAX_PARITY_ATTEMPTS)  {
1378                         if (cnt == IPATH_MAX_PARITY_ATTEMPTS)
1379                                 ipath_dev_err(dd,
1380                                         "Too many attempts to recover from "
1381                                         "TXE parity, giving up\n");
1382                         return 0;
1383                 }
1384                 dev_info(&dd->pcidev->dev,
1385                         "Recovering from TXE PIO parity error\n");
1386         }
1387         return 1;
1388 }
1389
1390 /**
1391  * ipath_init_iba6120_funcs - set up the chip-specific function pointers
1392  * @dd: the infinipath device
1393  *
1394  * This is global, and is called directly at init to set up the
1395  * chip-specific function pointers for later use.
1396  */
1397 void ipath_init_iba6120_funcs(struct ipath_devdata *dd)
1398 {
1399         dd->ipath_f_intrsetup = ipath_pe_intconfig;
1400         dd->ipath_f_bus = ipath_setup_pe_config;
1401         dd->ipath_f_reset = ipath_setup_pe_reset;
1402         dd->ipath_f_get_boardname = ipath_pe_boardname;
1403         dd->ipath_f_init_hwerrors = ipath_pe_init_hwerrors;
1404         dd->ipath_f_early_init = ipath_pe_early_init;
1405         dd->ipath_f_handle_hwerrors = ipath_pe_handle_hwerrors;
1406         dd->ipath_f_quiet_serdes = ipath_pe_quiet_serdes;
1407         dd->ipath_f_bringup_serdes = ipath_pe_bringup_serdes;
1408         dd->ipath_f_clear_tids = ipath_pe_clear_tids;
1409         /*
1410          * this may get changed after we read the chip revision,
1411          * but we start with the safe version for all revs
1412          */
1413         dd->ipath_f_put_tid = ipath_pe_put_tid;
1414         dd->ipath_f_cleanup = ipath_setup_pe_cleanup;
1415         dd->ipath_f_setextled = ipath_setup_pe_setextled;
1416         dd->ipath_f_get_base_info = ipath_pe_get_base_info;
1417         dd->ipath_f_free_irq = ipath_pe_free_irq;
1418
1419         /* initialize chip-specific variables */
1420         dd->ipath_f_tidtemplate = ipath_pe_tidtemplate;
1421
1422         /*
1423          * setup the register offsets, since they are different for each
1424          * chip
1425          */
1426         dd->ipath_kregs = &ipath_pe_kregs;
1427         dd->ipath_cregs = &ipath_pe_cregs;
1428
1429         ipath_init_pe_variables(dd);
1430 }
1431