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1 /*
2 * Copyright (c) 2006 QLogic, Inc. All rights reserved.
3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34 #include <linux/pci.h>
35
36 #include "ipath_kernel.h"
37 #include "ipath_verbs.h"
38 #include "ipath_common.h"
39
40 /* These are all rcv-related errors which we want to count for stats */
41 #define E_SUM_PKTERRS \
42 (INFINIPATH_E_RHDRLEN | INFINIPATH_E_RBADTID | \
43 INFINIPATH_E_RBADVERSION | INFINIPATH_E_RHDR | \
44 INFINIPATH_E_RLONGPKTLEN | INFINIPATH_E_RSHORTPKTLEN | \
45 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RMINPKTLEN | \
46 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RUNSUPVL | \
47 INFINIPATH_E_RUNEXPCHAR | INFINIPATH_E_REBP)
48
49 /* These are all send-related errors which we want to count for stats */
50 #define E_SUM_ERRS \
51 (INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM | \
52 INFINIPATH_E_SDROPPEDDATAPKT | INFINIPATH_E_SDROPPEDSMPPKT | \
53 INFINIPATH_E_SMAXPKTLEN | INFINIPATH_E_SUNSUPVL | \
54 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SPKTLEN | \
55 INFINIPATH_E_INVALIDADDR)
56
57 /*
58 * these are errors that can occur when the link changes state while
59 * a packet is being sent or received. This doesn't cover things
60 * like EBP or VCRC that can be the result of a sending having the
61 * link change state, so we receive a "known bad" packet.
62 */
63 #define E_SUM_LINK_PKTERRS \
64 (INFINIPATH_E_SDROPPEDDATAPKT | INFINIPATH_E_SDROPPEDSMPPKT | \
65 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SPKTLEN | \
66 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RMINPKTLEN | \
67 INFINIPATH_E_RUNEXPCHAR)
68
69 static u64 handle_e_sum_errs(struct ipath_devdata *dd, ipath_err_t errs)
70 {
71 unsigned long sbuf[4];
72 u64 ignore_this_time = 0;
73 u32 piobcnt;
74
75 /* if possible that sendbuffererror could be valid */
76 piobcnt = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k;
77 /* read these before writing errorclear */
78 sbuf[0] = ipath_read_kreg64(
79 dd, dd->ipath_kregs->kr_sendbuffererror);
80 sbuf[1] = ipath_read_kreg64(
81 dd, dd->ipath_kregs->kr_sendbuffererror + 1);
82 if (piobcnt > 128) {
83 sbuf[2] = ipath_read_kreg64(
84 dd, dd->ipath_kregs->kr_sendbuffererror + 2);
85 sbuf[3] = ipath_read_kreg64(
86 dd, dd->ipath_kregs->kr_sendbuffererror + 3);
87 }
88
89 if (sbuf[0] || sbuf[1] || (piobcnt > 128 && (sbuf[2] || sbuf[3]))) {
90 int i;
91
92 ipath_cdbg(PKT, "SendbufErrs %lx %lx ", sbuf[0], sbuf[1]);
93 if (ipath_debug & __IPATH_PKTDBG && piobcnt > 128)
94 printk("%lx %lx ", sbuf[2], sbuf[3]);
95 for (i = 0; i < piobcnt; i++) {
96 if (test_bit(i, sbuf)) {
97 u32 __iomem *piobuf;
98 if (i < dd->ipath_piobcnt2k)
99 piobuf = (u32 __iomem *)
100 (dd->ipath_pio2kbase +
101 i * dd->ipath_palign);
102 else
103 piobuf = (u32 __iomem *)
104 (dd->ipath_pio4kbase +
105 (i - dd->ipath_piobcnt2k) *
106 dd->ipath_4kalign);
107
108 ipath_cdbg(PKT,
109 "PIObuf[%u] @%p pbc is %x; ",
110 i, piobuf, readl(piobuf));
111
112 ipath_disarm_piobufs(dd, i, 1);
113 }
114 }
115 if (ipath_debug & __IPATH_PKTDBG)
116 printk("\n");
117 }
118 if ((errs & E_SUM_LINK_PKTERRS) &&
119 !(dd->ipath_flags & IPATH_LINKACTIVE)) {
120 /*
121 * This can happen when SMA is trying to bring the link
122 * up, but the IB link changes state at the "wrong" time.
123 * The IB logic then complains that the packet isn't
124 * valid. We don't want to confuse people, so we just
125 * don't print them, except at debug
126 */
127 ipath_dbg("Ignoring packet errors %llx, because link not "
128 "ACTIVE\n", (unsigned long long) errs);
129 ignore_this_time = errs & E_SUM_LINK_PKTERRS;
130 }
131
132 return ignore_this_time;
133 }
134
135 /* generic hw error messages... */
136 #define INFINIPATH_HWE_TXEMEMPARITYERR_MSG(a) \
137 { \
138 .mask = ( INFINIPATH_HWE_TXEMEMPARITYERR_##a << \
139 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT ), \
140 .msg = "TXE " #a " Memory Parity" \
141 }
142 #define INFINIPATH_HWE_RXEMEMPARITYERR_MSG(a) \
143 { \
144 .mask = ( INFINIPATH_HWE_RXEMEMPARITYERR_##a << \
145 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT ), \
146 .msg = "RXE " #a " Memory Parity" \
147 }
148
149 static const struct ipath_hwerror_msgs ipath_generic_hwerror_msgs[] = {
150 INFINIPATH_HWE_MSG(IBCBUSFRSPCPARITYERR, "IPATH2IB Parity"),
151 INFINIPATH_HWE_MSG(IBCBUSTOSPCPARITYERR, "IB2IPATH Parity"),
152
153 INFINIPATH_HWE_TXEMEMPARITYERR_MSG(PIOBUF),
154 INFINIPATH_HWE_TXEMEMPARITYERR_MSG(PIOPBC),
155 INFINIPATH_HWE_TXEMEMPARITYERR_MSG(PIOLAUNCHFIFO),
156
157 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(RCVBUF),
158 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(LOOKUPQ),
159 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(EAGERTID),
160 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(EXPTID),
161 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(FLAGBUF),
162 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(DATAINFO),
163 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(HDRINFO),
164 };
165
166 /**
167 * ipath_format_hwmsg - format a single hwerror message
168 * @msg message buffer
169 * @msgl length of message buffer
170 * @hwmsg message to add to message buffer
171 */
172 static void ipath_format_hwmsg(char *msg, size_t msgl, const char *hwmsg)
173 {
174 strlcat(msg, "[", msgl);
175 strlcat(msg, hwmsg, msgl);
176 strlcat(msg, "]", msgl);
177 }
178
179 /**
180 * ipath_format_hwerrors - format hardware error messages for display
181 * @hwerrs hardware errors bit vector
182 * @hwerrmsgs hardware error descriptions
183 * @nhwerrmsgs number of hwerrmsgs
184 * @msg message buffer
185 * @msgl message buffer length
186 */
187 void ipath_format_hwerrors(u64 hwerrs,
188 const struct ipath_hwerror_msgs *hwerrmsgs,
189 size_t nhwerrmsgs,
190 char *msg, size_t msgl)
191 {
192 int i;
193 const int glen =
194 sizeof(ipath_generic_hwerror_msgs) /
195 sizeof(ipath_generic_hwerror_msgs[0]);
196
197 for (i=0; i<glen; i++) {
198 if (hwerrs & ipath_generic_hwerror_msgs[i].mask) {
199 ipath_format_hwmsg(msg, msgl,
200 ipath_generic_hwerror_msgs[i].msg);
201 }
202 }
203
204 for (i=0; i<nhwerrmsgs; i++) {
205 if (hwerrs & hwerrmsgs[i].mask) {
206 ipath_format_hwmsg(msg, msgl, hwerrmsgs[i].msg);
207 }
208 }
209 }
210
211 /* return the strings for the most common link states */
212 static char *ib_linkstate(u32 linkstate)
213 {
214 char *ret;
215
216 switch (linkstate) {
217 case IPATH_IBSTATE_INIT:
218 ret = "Init";
219 break;
220 case IPATH_IBSTATE_ARM:
221 ret = "Arm";
222 break;
223 case IPATH_IBSTATE_ACTIVE:
224 ret = "Active";
225 break;
226 default:
227 ret = "Down";
228 }
229
230 return ret;
231 }
232
233 static void handle_e_ibstatuschanged(struct ipath_devdata *dd,
234 ipath_err_t errs, int noprint)
235 {
236 u64 val;
237 u32 ltstate, lstate;
238
239 /*
240 * even if diags are enabled, we want to notice LINKINIT, etc.
241 * We just don't want to change the LED state, or
242 * dd->ipath_kregs->kr_ibcctrl
243 */
244 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus);
245 lstate = val & IPATH_IBSTATE_MASK;
246
247 /*
248 * this is confusing enough when it happens that I want to always put it
249 * on the console and in the logs. If it was a requested state change,
250 * we'll have already cleared the flags, so we won't print this warning
251 */
252 if ((lstate != IPATH_IBSTATE_ARM && lstate != IPATH_IBSTATE_ACTIVE)
253 && (dd->ipath_flags & (IPATH_LINKARMED | IPATH_LINKACTIVE))) {
254 dev_info(&dd->pcidev->dev, "Link state changed from %s to %s\n",
255 (dd->ipath_flags & IPATH_LINKARMED) ? "ARM" : "ACTIVE",
256 ib_linkstate(lstate));
257 /*
258 * Flush all queued sends when link went to DOWN or INIT,
259 * to be sure that they don't block SMA and other MAD packets
260 */
261 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
262 INFINIPATH_S_ABORT);
263 ipath_disarm_piobufs(dd, dd->ipath_lastport_piobuf,
264 (unsigned)(dd->ipath_piobcnt2k +
265 dd->ipath_piobcnt4k) -
266 dd->ipath_lastport_piobuf);
267 }
268 else if (lstate == IPATH_IBSTATE_INIT || lstate == IPATH_IBSTATE_ARM ||
269 lstate == IPATH_IBSTATE_ACTIVE) {
270 /*
271 * only print at SMA if there is a change, debug if not
272 * (sometimes we want to know that, usually not).
273 */
274 if (lstate == ((unsigned) dd->ipath_lastibcstat
275 & IPATH_IBSTATE_MASK)) {
276 ipath_dbg("Status change intr but no change (%s)\n",
277 ib_linkstate(lstate));
278 }
279 else
280 ipath_cdbg(VERBOSE, "Unit %u link state %s, last "
281 "was %s\n", dd->ipath_unit,
282 ib_linkstate(lstate),
283 ib_linkstate((unsigned)
284 dd->ipath_lastibcstat
285 & IPATH_IBSTATE_MASK));
286 }
287 else {
288 lstate = dd->ipath_lastibcstat & IPATH_IBSTATE_MASK;
289 if (lstate == IPATH_IBSTATE_INIT ||
290 lstate == IPATH_IBSTATE_ARM ||
291 lstate == IPATH_IBSTATE_ACTIVE)
292 ipath_cdbg(VERBOSE, "Unit %u link state down"
293 " (state 0x%x), from %s\n",
294 dd->ipath_unit,
295 (u32)val & IPATH_IBSTATE_MASK,
296 ib_linkstate(lstate));
297 else
298 ipath_cdbg(VERBOSE, "Unit %u link state changed "
299 "to 0x%x from down (%x)\n",
300 dd->ipath_unit, (u32) val, lstate);
301 }
302 ltstate = (val >> INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) &
303 INFINIPATH_IBCS_LINKTRAININGSTATE_MASK;
304 lstate = (val >> INFINIPATH_IBCS_LINKSTATE_SHIFT) &
305 INFINIPATH_IBCS_LINKSTATE_MASK;
306
307 if (ltstate == INFINIPATH_IBCS_LT_STATE_POLLACTIVE ||
308 ltstate == INFINIPATH_IBCS_LT_STATE_POLLQUIET) {
309 u32 last_ltstate;
310
311 /*
312 * Ignore cycling back and forth from Polling.Active
313 * to Polling.Quiet while waiting for the other end of
314 * the link to come up. We will cycle back and forth
315 * between them if no cable is plugged in,
316 * the other device is powered off or disabled, etc.
317 */
318 last_ltstate = (dd->ipath_lastibcstat >>
319 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT)
320 & INFINIPATH_IBCS_LINKTRAININGSTATE_MASK;
321 if (last_ltstate == INFINIPATH_IBCS_LT_STATE_POLLACTIVE
322 || last_ltstate ==
323 INFINIPATH_IBCS_LT_STATE_POLLQUIET) {
324 if (dd->ipath_ibpollcnt > 40) {
325 dd->ipath_flags |= IPATH_NOCABLE;
326 *dd->ipath_statusp |=
327 IPATH_STATUS_IB_NOCABLE;
328 } else
329 dd->ipath_ibpollcnt++;
330 goto skip_ibchange;
331 }
332 }
333 dd->ipath_ibpollcnt = 0; /* some state other than 2 or 3 */
334 ipath_stats.sps_iblink++;
335 if (ltstate != INFINIPATH_IBCS_LT_STATE_LINKUP) {
336 dd->ipath_flags |= IPATH_LINKDOWN;
337 dd->ipath_flags &= ~(IPATH_LINKUNK | IPATH_LINKINIT
338 | IPATH_LINKACTIVE |
339 IPATH_LINKARMED);
340 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
341 dd->ipath_lli_counter = 0;
342 if (!noprint) {
343 if (((dd->ipath_lastibcstat >>
344 INFINIPATH_IBCS_LINKSTATE_SHIFT) &
345 INFINIPATH_IBCS_LINKSTATE_MASK)
346 == INFINIPATH_IBCS_L_STATE_ACTIVE)
347 /* if from up to down be more vocal */
348 ipath_cdbg(VERBOSE,
349 "Unit %u link now down (%s)\n",
350 dd->ipath_unit,
351 ipath_ibcstatus_str[ltstate]);
352 else
353 ipath_cdbg(VERBOSE, "Unit %u link is "
354 "down (%s)\n", dd->ipath_unit,
355 ipath_ibcstatus_str[ltstate]);
356 }
357
358 dd->ipath_f_setextled(dd, lstate, ltstate);
359 } else if ((val & IPATH_IBSTATE_MASK) == IPATH_IBSTATE_ACTIVE) {
360 dd->ipath_flags |= IPATH_LINKACTIVE;
361 dd->ipath_flags &=
362 ~(IPATH_LINKUNK | IPATH_LINKINIT | IPATH_LINKDOWN |
363 IPATH_LINKARMED | IPATH_NOCABLE);
364 *dd->ipath_statusp &= ~IPATH_STATUS_IB_NOCABLE;
365 *dd->ipath_statusp |=
366 IPATH_STATUS_IB_READY | IPATH_STATUS_IB_CONF;
367 dd->ipath_f_setextled(dd, lstate, ltstate);
368 } else if ((val & IPATH_IBSTATE_MASK) == IPATH_IBSTATE_INIT) {
369 /*
370 * set INIT and DOWN. Down is checked by most of the other
371 * code, but INIT is useful to know in a few places.
372 */
373 dd->ipath_flags |= IPATH_LINKINIT | IPATH_LINKDOWN;
374 dd->ipath_flags &=
375 ~(IPATH_LINKUNK | IPATH_LINKACTIVE | IPATH_LINKARMED
376 | IPATH_NOCABLE);
377 *dd->ipath_statusp &= ~(IPATH_STATUS_IB_NOCABLE
378 | IPATH_STATUS_IB_READY);
379 dd->ipath_f_setextled(dd, lstate, ltstate);
380 } else if ((val & IPATH_IBSTATE_MASK) == IPATH_IBSTATE_ARM) {
381 dd->ipath_flags |= IPATH_LINKARMED;
382 dd->ipath_flags &=
383 ~(IPATH_LINKUNK | IPATH_LINKDOWN | IPATH_LINKINIT |
384 IPATH_LINKACTIVE | IPATH_NOCABLE);
385 *dd->ipath_statusp &= ~(IPATH_STATUS_IB_NOCABLE
386 | IPATH_STATUS_IB_READY);
387 dd->ipath_f_setextled(dd, lstate, ltstate);
388 } else {
389 if (!noprint)
390 ipath_dbg("IBstatuschange unit %u: %s (%x)\n",
391 dd->ipath_unit,
392 ipath_ibcstatus_str[ltstate], ltstate);
393 }
394 skip_ibchange:
395 dd->ipath_lastibcstat = val;
396 }
397
398 static void handle_supp_msgs(struct ipath_devdata *dd,
399 unsigned supp_msgs, char msg[512])
400 {
401 /*
402 * Print the message unless it's ibc status change only, which
403 * happens so often we never want to count it.
404 */
405 if (dd->ipath_lasterror & ~INFINIPATH_E_IBSTATUSCHANGED) {
406 ipath_decode_err(msg, sizeof msg, dd->ipath_lasterror &
407 ~INFINIPATH_E_IBSTATUSCHANGED);
408 if (dd->ipath_lasterror &
409 ~(INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL))
410 ipath_dev_err(dd, "Suppressed %u messages for "
411 "fast-repeating errors (%s) (%llx)\n",
412 supp_msgs, msg,
413 (unsigned long long)
414 dd->ipath_lasterror);
415 else {
416 /*
417 * rcvegrfull and rcvhdrqfull are "normal", for some
418 * types of processes (mostly benchmarks) that send
419 * huge numbers of messages, while not processing
420 * them. So only complain about these at debug
421 * level.
422 */
423 ipath_dbg("Suppressed %u messages for %s\n",
424 supp_msgs, msg);
425 }
426 }
427 }
428
429 static unsigned handle_frequent_errors(struct ipath_devdata *dd,
430 ipath_err_t errs, char msg[512],
431 int *noprint)
432 {
433 unsigned long nc;
434 static unsigned long nextmsg_time;
435 static unsigned nmsgs, supp_msgs;
436
437 /*
438 * Throttle back "fast" messages to no more than 10 per 5 seconds.
439 * This isn't perfect, but it's a reasonable heuristic. If we get
440 * more than 10, give a 6x longer delay.
441 */
442 nc = jiffies;
443 if (nmsgs > 10) {
444 if (time_before(nc, nextmsg_time)) {
445 *noprint = 1;
446 if (!supp_msgs++)
447 nextmsg_time = nc + HZ * 3;
448 }
449 else if (supp_msgs) {
450 handle_supp_msgs(dd, supp_msgs, msg);
451 supp_msgs = 0;
452 nmsgs = 0;
453 }
454 }
455 else if (!nmsgs++ || time_after(nc, nextmsg_time))
456 nextmsg_time = nc + HZ / 2;
457
458 return supp_msgs;
459 }
460
461 static int handle_errors(struct ipath_devdata *dd, ipath_err_t errs)
462 {
463 char msg[512];
464 u64 ignore_this_time = 0;
465 int i;
466 int chkerrpkts = 0, noprint = 0;
467 unsigned supp_msgs;
468
469 supp_msgs = handle_frequent_errors(dd, errs, msg, &noprint);
470
471 /*
472 * don't report errors that are masked (includes those always
473 * ignored)
474 */
475 errs &= ~dd->ipath_maskederrs;
476
477 /* do these first, they are most important */
478 if (errs & INFINIPATH_E_HARDWARE) {
479 /* reuse same msg buf */
480 dd->ipath_f_handle_hwerrors(dd, msg, sizeof msg);
481 }
482
483 if (!noprint && (errs & ~dd->ipath_e_bitsextant))
484 ipath_dev_err(dd, "error interrupt with unknown errors "
485 "%llx set\n", (unsigned long long)
486 (errs & ~dd->ipath_e_bitsextant));
487
488 if (errs & E_SUM_ERRS)
489 ignore_this_time = handle_e_sum_errs(dd, errs);
490 else if ((errs & E_SUM_LINK_PKTERRS) &&
491 !(dd->ipath_flags & IPATH_LINKACTIVE)) {
492 /*
493 * This can happen when SMA is trying to bring the link
494 * up, but the IB link changes state at the "wrong" time.
495 * The IB logic then complains that the packet isn't
496 * valid. We don't want to confuse people, so we just
497 * don't print them, except at debug
498 */
499 ipath_dbg("Ignoring packet errors %llx, because link not "
500 "ACTIVE\n", (unsigned long long) errs);
501 ignore_this_time = errs & E_SUM_LINK_PKTERRS;
502 }
503
504 if (supp_msgs == 250000) {
505 /*
506 * It's not entirely reasonable assuming that the errors set
507 * in the last clear period are all responsible for the
508 * problem, but the alternative is to assume it's the only
509 * ones on this particular interrupt, which also isn't great
510 */
511 dd->ipath_maskederrs |= dd->ipath_lasterror | errs;
512 ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
513 ~dd->ipath_maskederrs);
514 ipath_decode_err(msg, sizeof msg,
515 (dd->ipath_maskederrs & ~dd->
516 ipath_ignorederrs));
517
518 if ((dd->ipath_maskederrs & ~dd->ipath_ignorederrs) &
519 ~(INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL))
520 ipath_dev_err(dd, "Disabling error(s) %llx because "
521 "occurring too frequently (%s)\n",
522 (unsigned long long)
523 (dd->ipath_maskederrs &
524 ~dd->ipath_ignorederrs), msg);
525 else {
526 /*
527 * rcvegrfull and rcvhdrqfull are "normal",
528 * for some types of processes (mostly benchmarks)
529 * that send huge numbers of messages, while not
530 * processing them. So only complain about
531 * these at debug level.
532 */
533 ipath_dbg("Disabling frequent queue full errors "
534 "(%s)\n", msg);
535 }
536
537 /*
538 * Re-enable the masked errors after around 3 minutes. in
539 * ipath_get_faststats(). If we have a series of fast
540 * repeating but different errors, the interval will keep
541 * stretching out, but that's OK, as that's pretty
542 * catastrophic.
543 */
544 dd->ipath_unmasktime = jiffies + HZ * 180;
545 }
546
547 ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, errs);
548 if (ignore_this_time)
549 errs &= ~ignore_this_time;
550 if (errs & ~dd->ipath_lasterror) {
551 errs &= ~dd->ipath_lasterror;
552 /* never suppress duplicate hwerrors or ibstatuschange */
553 dd->ipath_lasterror |= errs &
554 ~(INFINIPATH_E_HARDWARE |
555 INFINIPATH_E_IBSTATUSCHANGED);
556 }
557 if (!errs)
558 return 0;
559
560 if (!noprint)
561 /*
562 * the ones we mask off are handled specially below or above
563 */
564 ipath_decode_err(msg, sizeof msg,
565 errs & ~(INFINIPATH_E_IBSTATUSCHANGED |
566 INFINIPATH_E_RRCVEGRFULL |
567 INFINIPATH_E_RRCVHDRFULL |
568 INFINIPATH_E_HARDWARE));
569 else
570 /* so we don't need if (!noprint) at strlcat's below */
571 *msg = 0;
572
573 if (errs & E_SUM_PKTERRS) {
574 ipath_stats.sps_pkterrs++;
575 chkerrpkts = 1;
576 }
577 if (errs & E_SUM_ERRS)
578 ipath_stats.sps_errs++;
579
580 if (errs & (INFINIPATH_E_RICRC | INFINIPATH_E_RVCRC)) {
581 ipath_stats.sps_crcerrs++;
582 chkerrpkts = 1;
583 }
584
585 /*
586 * We don't want to print these two as they happen, or we can make
587 * the situation even worse, because it takes so long to print
588 * messages to serial consoles. Kernel ports get printed from
589 * fast_stats, no more than every 5 seconds, user ports get printed
590 * on close
591 */
592 if (errs & INFINIPATH_E_RRCVHDRFULL) {
593 int any;
594 u32 hd, tl;
595 ipath_stats.sps_hdrqfull++;
596 for (any = i = 0; i < dd->ipath_cfgports; i++) {
597 struct ipath_portdata *pd = dd->ipath_pd[i];
598 if (i == 0) {
599 hd = dd->ipath_port0head;
600 tl = (u32) le64_to_cpu(
601 *dd->ipath_hdrqtailptr);
602 } else if (pd && pd->port_cnt &&
603 pd->port_rcvhdrtail_kvaddr) {
604 /*
605 * don't report same point multiple times,
606 * except kernel
607 */
608 tl = *(u64 *) pd->port_rcvhdrtail_kvaddr;
609 if (tl == dd->ipath_lastrcvhdrqtails[i])
610 continue;
611 hd = ipath_read_ureg32(dd, ur_rcvhdrhead,
612 i);
613 } else
614 continue;
615 if (hd == (tl + 1) ||
616 (!hd && tl == dd->ipath_hdrqlast)) {
617 if (i == 0)
618 chkerrpkts = 1;
619 dd->ipath_lastrcvhdrqtails[i] = tl;
620 pd->port_hdrqfull++;
621 }
622 }
623 }
624 if (errs & INFINIPATH_E_RRCVEGRFULL) {
625 /*
626 * since this is of less importance and not likely to
627 * happen without also getting hdrfull, only count
628 * occurrences; don't check each port (or even the kernel
629 * vs user)
630 */
631 ipath_stats.sps_etidfull++;
632 if (dd->ipath_port0head !=
633 (u32) le64_to_cpu(*dd->ipath_hdrqtailptr))
634 chkerrpkts = 1;
635 }
636
637 /*
638 * do this before IBSTATUSCHANGED, in case both bits set in a single
639 * interrupt; we want the STATUSCHANGE to "win", so we do our
640 * internal copy of state machine correctly
641 */
642 if (errs & INFINIPATH_E_RIBLOSTLINK) {
643 /*
644 * force through block below
645 */
646 errs |= INFINIPATH_E_IBSTATUSCHANGED;
647 ipath_stats.sps_iblink++;
648 dd->ipath_flags |= IPATH_LINKDOWN;
649 dd->ipath_flags &= ~(IPATH_LINKUNK | IPATH_LINKINIT
650 | IPATH_LINKARMED | IPATH_LINKACTIVE);
651 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
652 if (!noprint) {
653 u64 st = ipath_read_kreg64(
654 dd, dd->ipath_kregs->kr_ibcstatus);
655
656 ipath_dbg("Lost link, link now down (%s)\n",
657 ipath_ibcstatus_str[st & 0xf]);
658 }
659 }
660 if (errs & INFINIPATH_E_IBSTATUSCHANGED)
661 handle_e_ibstatuschanged(dd, errs, noprint);
662
663 if (errs & INFINIPATH_E_RESET) {
664 if (!noprint)
665 ipath_dev_err(dd, "Got reset, requires re-init "
666 "(unload and reload driver)\n");
667 dd->ipath_flags &= ~IPATH_INITTED; /* needs re-init */
668 /* mark as having had error */
669 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
670 *dd->ipath_statusp &= ~IPATH_STATUS_IB_CONF;
671 }
672
673 if (!noprint && *msg)
674 ipath_dev_err(dd, "%s error\n", msg);
675 if (dd->ipath_state_wanted & dd->ipath_flags) {
676 ipath_cdbg(VERBOSE, "driver wanted state %x, iflags now %x, "
677 "waking\n", dd->ipath_state_wanted,
678 dd->ipath_flags);
679 wake_up_interruptible(&ipath_state_wait);
680 }
681
682 return chkerrpkts;
683 }
684
685 /* this is separate to allow for better optimization of ipath_intr() */
686
687 static void ipath_bad_intr(struct ipath_devdata *dd, u32 * unexpectp)
688 {
689 /*
690 * sometimes happen during driver init and unload, don't want
691 * to process any interrupts at that point
692 */
693
694 /* this is just a bandaid, not a fix, if something goes badly
695 * wrong */
696 if (++*unexpectp > 100) {
697 if (++*unexpectp > 105) {
698 /*
699 * ok, we must be taking somebody else's interrupts,
700 * due to a messed up mptable and/or PIRQ table, so
701 * unregister the interrupt. We've seen this during
702 * linuxbios development work, and it may happen in
703 * the future again.
704 */
705 if (dd->pcidev && dd->pcidev->irq) {
706 ipath_dev_err(dd, "Now %u unexpected "
707 "interrupts, unregistering "
708 "interrupt handler\n",
709 *unexpectp);
710 ipath_dbg("free_irq of irq %x\n",
711 dd->pcidev->irq);
712 free_irq(dd->pcidev->irq, dd);
713 }
714 }
715 if (ipath_read_kreg32(dd, dd->ipath_kregs->kr_intmask)) {
716 ipath_dev_err(dd, "%u unexpected interrupts, "
717 "disabling interrupts completely\n",
718 *unexpectp);
719 /*
720 * disable all interrupts, something is very wrong
721 */
722 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask,
723 0ULL);
724 }
725 } else if (*unexpectp > 1)
726 ipath_dbg("Interrupt when not ready, should not happen, "
727 "ignoring\n");
728 }
729
730 static void ipath_bad_regread(struct ipath_devdata *dd)
731 {
732 static int allbits;
733
734 /* separate routine, for better optimization of ipath_intr() */
735
736 /*
737 * We print the message and disable interrupts, in hope of
738 * having a better chance of debugging the problem.
739 */
740 ipath_dev_err(dd,
741 "Read of interrupt status failed (all bits set)\n");
742 if (allbits++) {
743 /* disable all interrupts, something is very wrong */
744 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 0ULL);
745 if (allbits == 2) {
746 ipath_dev_err(dd, "Still bad interrupt status, "
747 "unregistering interrupt\n");
748 free_irq(dd->pcidev->irq, dd);
749 } else if (allbits > 2) {
750 if ((allbits % 10000) == 0)
751 printk(".");
752 } else
753 ipath_dev_err(dd, "Disabling interrupts, "
754 "multiple errors\n");
755 }
756 }
757
758 static void handle_port_pioavail(struct ipath_devdata *dd)
759 {
760 u32 i;
761 /*
762 * start from port 1, since for now port 0 is never using
763 * wait_event for PIO
764 */
765 for (i = 1; dd->ipath_portpiowait && i < dd->ipath_cfgports; i++) {
766 struct ipath_portdata *pd = dd->ipath_pd[i];
767
768 if (pd && pd->port_cnt &&
769 dd->ipath_portpiowait & (1U << i)) {
770 clear_bit(i, &dd->ipath_portpiowait);
771 if (test_bit(IPATH_PORT_WAITING_PIO,
772 &pd->port_flag)) {
773 clear_bit(IPATH_PORT_WAITING_PIO,
774 &pd->port_flag);
775 wake_up_interruptible(&pd->port_wait);
776 }
777 }
778 }
779 }
780
781 static void handle_layer_pioavail(struct ipath_devdata *dd)
782 {
783 int ret;
784
785 ret = ipath_ib_piobufavail(dd->verbs_dev);
786 if (ret > 0)
787 goto set;
788
789 return;
790 set:
791 set_bit(IPATH_S_PIOINTBUFAVAIL, &dd->ipath_sendctrl);
792 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
793 dd->ipath_sendctrl);
794 }
795
796 /*
797 * Handle receive interrupts for user ports; this means a user
798 * process was waiting for a packet to arrive, and didn't want
799 * to poll
800 */
801 static void handle_urcv(struct ipath_devdata *dd, u32 istat)
802 {
803 u64 portr;
804 int i;
805 int rcvdint = 0;
806
807 portr = ((istat >> INFINIPATH_I_RCVAVAIL_SHIFT) &
808 dd->ipath_i_rcvavail_mask)
809 | ((istat >> INFINIPATH_I_RCVURG_SHIFT) &
810 dd->ipath_i_rcvurg_mask);
811 for (i = 1; i < dd->ipath_cfgports; i++) {
812 struct ipath_portdata *pd = dd->ipath_pd[i];
813 if (portr & (1 << i) && pd && pd->port_cnt &&
814 test_bit(IPATH_PORT_WAITING_RCV, &pd->port_flag)) {
815 int rcbit;
816 clear_bit(IPATH_PORT_WAITING_RCV,
817 &pd->port_flag);
818 rcbit = i + INFINIPATH_R_INTRAVAIL_SHIFT;
819 clear_bit(1UL << rcbit, &dd->ipath_rcvctrl);
820 wake_up_interruptible(&pd->port_wait);
821 rcvdint = 1;
822 }
823 }
824 if (rcvdint) {
825 /* only want to take one interrupt, so turn off the rcv
826 * interrupt for all the ports that we did the wakeup on
827 * (but never for kernel port)
828 */
829 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
830 dd->ipath_rcvctrl);
831 }
832 }
833
834 irqreturn_t ipath_intr(int irq, void *data, struct pt_regs *regs)
835 {
836 struct ipath_devdata *dd = data;
837 u32 istat, chk0rcv = 0;
838 ipath_err_t estat = 0;
839 irqreturn_t ret;
840 u32 oldhead, curtail;
841 static unsigned unexpected = 0;
842 static const u32 port0rbits = (1U<<INFINIPATH_I_RCVAVAIL_SHIFT) |
843 (1U<<INFINIPATH_I_RCVURG_SHIFT);
844
845 ipath_stats.sps_ints++;
846
847 if (!(dd->ipath_flags & IPATH_PRESENT)) {
848 /*
849 * This return value is not great, but we do not want the
850 * interrupt core code to remove our interrupt handler
851 * because we don't appear to be handling an interrupt
852 * during a chip reset.
853 */
854 return IRQ_HANDLED;
855 }
856
857 /*
858 * this needs to be flags&initted, not statusp, so we keep
859 * taking interrupts even after link goes down, etc.
860 * Also, we *must* clear the interrupt at some point, or we won't
861 * take it again, which can be real bad for errors, etc...
862 */
863
864 if (!(dd->ipath_flags & IPATH_INITTED)) {
865 ipath_bad_intr(dd, &unexpected);
866 ret = IRQ_NONE;
867 goto bail;
868 }
869
870 /*
871 * We try to avoid reading the interrupt status register, since
872 * that's a PIO read, and stalls the processor for up to about
873 * ~0.25 usec. The idea is that if we processed a port0 packet,
874 * we blindly clear the port 0 receive interrupt bits, and nothing
875 * else, then return. If other interrupts are pending, the chip
876 * will re-interrupt us as soon as we write the intclear register.
877 * We then won't process any more kernel packets (if not the 2nd
878 * time, then the 3rd or 4th) and we'll then handle the other
879 * interrupts. We clear the interrupts first so that we don't
880 * lose intr for later packets that arrive while we are processing.
881 */
882 oldhead = dd->ipath_port0head;
883 curtail = (u32)le64_to_cpu(*dd->ipath_hdrqtailptr);
884 if (oldhead != curtail) {
885 if (dd->ipath_flags & IPATH_GPIO_INTR) {
886 ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_clear,
887 (u64) (1 << IPATH_GPIO_PORT0_BIT));
888 istat = port0rbits | INFINIPATH_I_GPIO;
889 }
890 else
891 istat = port0rbits;
892 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, istat);
893 ipath_kreceive(dd);
894 if (oldhead != dd->ipath_port0head) {
895 ipath_stats.sps_fastrcvint++;
896 goto done;
897 }
898 }
899
900 istat = ipath_read_kreg32(dd, dd->ipath_kregs->kr_intstatus);
901
902 if (unlikely(!istat)) {
903 ipath_stats.sps_nullintr++;
904 ret = IRQ_NONE; /* not our interrupt, or already handled */
905 goto bail;
906 }
907 if (unlikely(istat == -1)) {
908 ipath_bad_regread(dd);
909 /* don't know if it was our interrupt or not */
910 ret = IRQ_NONE;
911 goto bail;
912 }
913
914 if (unexpected)
915 unexpected = 0;
916
917 if (unlikely(istat & ~dd->ipath_i_bitsextant))
918 ipath_dev_err(dd,
919 "interrupt with unknown interrupts %x set\n",
920 istat & (u32) ~ dd->ipath_i_bitsextant);
921 else
922 ipath_cdbg(VERBOSE, "intr stat=0x%x\n", istat);
923
924 if (unlikely(istat & INFINIPATH_I_ERROR)) {
925 ipath_stats.sps_errints++;
926 estat = ipath_read_kreg64(dd,
927 dd->ipath_kregs->kr_errorstatus);
928 if (!estat)
929 dev_info(&dd->pcidev->dev, "error interrupt (%x), "
930 "but no error bits set!\n", istat);
931 else if (estat == -1LL)
932 /*
933 * should we try clearing all, or hope next read
934 * works?
935 */
936 ipath_dev_err(dd, "Read of error status failed "
937 "(all bits set); ignoring\n");
938 else
939 if (handle_errors(dd, estat))
940 /* force calling ipath_kreceive() */
941 chk0rcv = 1;
942 }
943
944 if (istat & INFINIPATH_I_GPIO) {
945 /*
946 * GPIO interrupts fall in two broad classes:
947 * GPIO_2 indicates (on some HT4xx boards) that a packet
948 * has arrived for Port 0. Checking for this
949 * is controlled by flag IPATH_GPIO_INTR.
950 * GPIO_3..5 on IBA6120 Rev2 chips indicate errors
951 * that we need to count. Checking for this
952 * is controlled by flag IPATH_GPIO_ERRINTRS.
953 */
954 u32 gpiostatus;
955 u32 to_clear = 0;
956
957 gpiostatus = ipath_read_kreg32(
958 dd, dd->ipath_kregs->kr_gpio_status);
959 /* First the error-counter case.
960 */
961 if ((gpiostatus & IPATH_GPIO_ERRINTR_MASK) &&
962 (dd->ipath_flags & IPATH_GPIO_ERRINTRS)) {
963 /* want to clear the bits we see asserted. */
964 to_clear |= (gpiostatus & IPATH_GPIO_ERRINTR_MASK);
965
966 /*
967 * Count appropriately, clear bits out of our copy,
968 * as they have been "handled".
969 */
970 if (gpiostatus & (1 << IPATH_GPIO_RXUVL_BIT)) {
971 ipath_dbg("FlowCtl on UnsupVL\n");
972 dd->ipath_rxfc_unsupvl_errs++;
973 }
974 if (gpiostatus & (1 << IPATH_GPIO_OVRUN_BIT)) {
975 ipath_dbg("Overrun Threshold exceeded\n");
976 dd->ipath_overrun_thresh_errs++;
977 }
978 if (gpiostatus & (1 << IPATH_GPIO_LLI_BIT)) {
979 ipath_dbg("Local Link Integrity error\n");
980 dd->ipath_lli_errs++;
981 }
982 gpiostatus &= ~IPATH_GPIO_ERRINTR_MASK;
983 }
984 /* Now the Port0 Receive case */
985 if ((gpiostatus & (1 << IPATH_GPIO_PORT0_BIT)) &&
986 (dd->ipath_flags & IPATH_GPIO_INTR)) {
987 /*
988 * GPIO status bit 2 is set, and we expected it.
989 * clear it and indicate in p0bits.
990 * This probably only happens if a Port0 pkt
991 * arrives at _just_ the wrong time, and we
992 * handle that by seting chk0rcv;
993 */
994 to_clear |= (1 << IPATH_GPIO_PORT0_BIT);
995 gpiostatus &= ~(1 << IPATH_GPIO_PORT0_BIT);
996 chk0rcv = 1;
997 }
998 if (unlikely(gpiostatus)) {
999 /*
1000 * Some unexpected bits remain. If they could have
1001 * caused the interrupt, complain and clear.
1002 * MEA: this is almost certainly non-ideal.
1003 * we should look into auto-disable of unexpected
1004 * GPIO interrupts, possibly on a "three strikes"
1005 * basis.
1006 */
1007 u32 mask;
1008 mask = ipath_read_kreg32(
1009 dd, dd->ipath_kregs->kr_gpio_mask);
1010 if (mask & gpiostatus) {
1011 ipath_dbg("Unexpected GPIO IRQ bits %x\n",
1012 gpiostatus & mask);
1013 to_clear |= (gpiostatus & mask);
1014 }
1015 }
1016 if (to_clear) {
1017 ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_clear,
1018 (u64) to_clear);
1019 }
1020 }
1021 chk0rcv |= istat & port0rbits;
1022
1023 /*
1024 * Clear the interrupt bits we found set, unless they are receive
1025 * related, in which case we already cleared them above, and don't
1026 * want to clear them again, because we might lose an interrupt.
1027 * Clear it early, so we "know" know the chip will have seen this by
1028 * the time we process the queue, and will re-interrupt if necessary.
1029 * The processor itself won't take the interrupt again until we return.
1030 */
1031 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, istat);
1032
1033 /*
1034 * handle port0 receive before checking for pio buffers available,
1035 * since receives can overflow; piobuf waiters can afford a few
1036 * extra cycles, since they were waiting anyway, and user's waiting
1037 * for receive are at the bottom.
1038 */
1039 if (chk0rcv) {
1040 ipath_kreceive(dd);
1041 istat &= ~port0rbits;
1042 }
1043
1044 if (istat & ((dd->ipath_i_rcvavail_mask <<
1045 INFINIPATH_I_RCVAVAIL_SHIFT)
1046 | (dd->ipath_i_rcvurg_mask <<
1047 INFINIPATH_I_RCVURG_SHIFT)))
1048 handle_urcv(dd, istat);
1049
1050 if (istat & INFINIPATH_I_SPIOBUFAVAIL) {
1051 clear_bit(IPATH_S_PIOINTBUFAVAIL, &dd->ipath_sendctrl);
1052 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1053 dd->ipath_sendctrl);
1054
1055 if (dd->ipath_portpiowait)
1056 handle_port_pioavail(dd);
1057
1058 handle_layer_pioavail(dd);
1059 }
1060
1061 done:
1062 ret = IRQ_HANDLED;
1063
1064 bail:
1065 return ret;
1066 }