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[mirror_ubuntu-artful-kernel.git] / drivers / infiniband / hw / mlx4 / cq.c
1 /*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34 #include <linux/mlx4/cq.h>
35 #include <linux/mlx4/qp.h>
36 #include <linux/mlx4/srq.h>
37 #include <linux/slab.h>
38
39 #include "mlx4_ib.h"
40 #include "user.h"
41
42 static void mlx4_ib_cq_comp(struct mlx4_cq *cq)
43 {
44 struct ib_cq *ibcq = &to_mibcq(cq)->ibcq;
45 ibcq->comp_handler(ibcq, ibcq->cq_context);
46 }
47
48 static void mlx4_ib_cq_event(struct mlx4_cq *cq, enum mlx4_event type)
49 {
50 struct ib_event event;
51 struct ib_cq *ibcq;
52
53 if (type != MLX4_EVENT_TYPE_CQ_ERROR) {
54 pr_warn("Unexpected event type %d "
55 "on CQ %06x\n", type, cq->cqn);
56 return;
57 }
58
59 ibcq = &to_mibcq(cq)->ibcq;
60 if (ibcq->event_handler) {
61 event.device = ibcq->device;
62 event.event = IB_EVENT_CQ_ERR;
63 event.element.cq = ibcq;
64 ibcq->event_handler(&event, ibcq->cq_context);
65 }
66 }
67
68 static void *get_cqe_from_buf(struct mlx4_ib_cq_buf *buf, int n)
69 {
70 return mlx4_buf_offset(&buf->buf, n * buf->entry_size);
71 }
72
73 static void *get_cqe(struct mlx4_ib_cq *cq, int n)
74 {
75 return get_cqe_from_buf(&cq->buf, n);
76 }
77
78 static void *get_sw_cqe(struct mlx4_ib_cq *cq, int n)
79 {
80 struct mlx4_cqe *cqe = get_cqe(cq, n & cq->ibcq.cqe);
81 struct mlx4_cqe *tcqe = ((cq->buf.entry_size == 64) ? (cqe + 1) : cqe);
82
83 return (!!(tcqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^
84 !!(n & (cq->ibcq.cqe + 1))) ? NULL : cqe;
85 }
86
87 static struct mlx4_cqe *next_cqe_sw(struct mlx4_ib_cq *cq)
88 {
89 return get_sw_cqe(cq, cq->mcq.cons_index);
90 }
91
92 int mlx4_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
93 {
94 struct mlx4_ib_cq *mcq = to_mcq(cq);
95 struct mlx4_ib_dev *dev = to_mdev(cq->device);
96
97 return mlx4_cq_modify(dev->dev, &mcq->mcq, cq_count, cq_period);
98 }
99
100 static int mlx4_ib_alloc_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf *buf, int nent)
101 {
102 int err;
103
104 err = mlx4_buf_alloc(dev->dev, nent * dev->dev->caps.cqe_size,
105 PAGE_SIZE * 2, &buf->buf);
106
107 if (err)
108 goto out;
109
110 buf->entry_size = dev->dev->caps.cqe_size;
111 err = mlx4_mtt_init(dev->dev, buf->buf.npages, buf->buf.page_shift,
112 &buf->mtt);
113 if (err)
114 goto err_buf;
115
116 err = mlx4_buf_write_mtt(dev->dev, &buf->mtt, &buf->buf);
117 if (err)
118 goto err_mtt;
119
120 return 0;
121
122 err_mtt:
123 mlx4_mtt_cleanup(dev->dev, &buf->mtt);
124
125 err_buf:
126 mlx4_buf_free(dev->dev, nent * buf->entry_size, &buf->buf);
127
128 out:
129 return err;
130 }
131
132 static void mlx4_ib_free_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf *buf, int cqe)
133 {
134 mlx4_buf_free(dev->dev, (cqe + 1) * buf->entry_size, &buf->buf);
135 }
136
137 static int mlx4_ib_get_cq_umem(struct mlx4_ib_dev *dev, struct ib_ucontext *context,
138 struct mlx4_ib_cq_buf *buf, struct ib_umem **umem,
139 u64 buf_addr, int cqe)
140 {
141 int err;
142 int cqe_size = dev->dev->caps.cqe_size;
143
144 *umem = ib_umem_get(context, buf_addr, cqe * cqe_size,
145 IB_ACCESS_LOCAL_WRITE, 1);
146 if (IS_ERR(*umem))
147 return PTR_ERR(*umem);
148
149 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(*umem),
150 ilog2((*umem)->page_size), &buf->mtt);
151 if (err)
152 goto err_buf;
153
154 err = mlx4_ib_umem_write_mtt(dev, &buf->mtt, *umem);
155 if (err)
156 goto err_mtt;
157
158 return 0;
159
160 err_mtt:
161 mlx4_mtt_cleanup(dev->dev, &buf->mtt);
162
163 err_buf:
164 ib_umem_release(*umem);
165
166 return err;
167 }
168
169 struct ib_cq *mlx4_ib_create_cq(struct ib_device *ibdev, int entries, int vector,
170 struct ib_ucontext *context,
171 struct ib_udata *udata)
172 {
173 struct mlx4_ib_dev *dev = to_mdev(ibdev);
174 struct mlx4_ib_cq *cq;
175 struct mlx4_uar *uar;
176 int err;
177
178 if (entries < 1 || entries > dev->dev->caps.max_cqes)
179 return ERR_PTR(-EINVAL);
180
181 cq = kmalloc(sizeof *cq, GFP_KERNEL);
182 if (!cq)
183 return ERR_PTR(-ENOMEM);
184
185 entries = roundup_pow_of_two(entries + 1);
186 cq->ibcq.cqe = entries - 1;
187 mutex_init(&cq->resize_mutex);
188 spin_lock_init(&cq->lock);
189 cq->resize_buf = NULL;
190 cq->resize_umem = NULL;
191
192 if (context) {
193 struct mlx4_ib_create_cq ucmd;
194
195 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
196 err = -EFAULT;
197 goto err_cq;
198 }
199
200 err = mlx4_ib_get_cq_umem(dev, context, &cq->buf, &cq->umem,
201 ucmd.buf_addr, entries);
202 if (err)
203 goto err_cq;
204
205 err = mlx4_ib_db_map_user(to_mucontext(context), ucmd.db_addr,
206 &cq->db);
207 if (err)
208 goto err_mtt;
209
210 uar = &to_mucontext(context)->uar;
211 } else {
212 err = mlx4_db_alloc(dev->dev, &cq->db, 1);
213 if (err)
214 goto err_cq;
215
216 cq->mcq.set_ci_db = cq->db.db;
217 cq->mcq.arm_db = cq->db.db + 1;
218 *cq->mcq.set_ci_db = 0;
219 *cq->mcq.arm_db = 0;
220
221 err = mlx4_ib_alloc_cq_buf(dev, &cq->buf, entries);
222 if (err)
223 goto err_db;
224
225 uar = &dev->priv_uar;
226 }
227
228 if (dev->eq_table)
229 vector = dev->eq_table[vector % ibdev->num_comp_vectors];
230
231 err = mlx4_cq_alloc(dev->dev, entries, &cq->buf.mtt, uar,
232 cq->db.dma, &cq->mcq, vector, 0, 0);
233 if (err)
234 goto err_dbmap;
235
236 cq->mcq.comp = mlx4_ib_cq_comp;
237 cq->mcq.event = mlx4_ib_cq_event;
238
239 if (context)
240 if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof (__u32))) {
241 err = -EFAULT;
242 goto err_dbmap;
243 }
244
245 return &cq->ibcq;
246
247 err_dbmap:
248 if (context)
249 mlx4_ib_db_unmap_user(to_mucontext(context), &cq->db);
250
251 err_mtt:
252 mlx4_mtt_cleanup(dev->dev, &cq->buf.mtt);
253
254 if (context)
255 ib_umem_release(cq->umem);
256 else
257 mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe);
258
259 err_db:
260 if (!context)
261 mlx4_db_free(dev->dev, &cq->db);
262
263 err_cq:
264 kfree(cq);
265
266 return ERR_PTR(err);
267 }
268
269 static int mlx4_alloc_resize_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq *cq,
270 int entries)
271 {
272 int err;
273
274 if (cq->resize_buf)
275 return -EBUSY;
276
277 cq->resize_buf = kmalloc(sizeof *cq->resize_buf, GFP_ATOMIC);
278 if (!cq->resize_buf)
279 return -ENOMEM;
280
281 err = mlx4_ib_alloc_cq_buf(dev, &cq->resize_buf->buf, entries);
282 if (err) {
283 kfree(cq->resize_buf);
284 cq->resize_buf = NULL;
285 return err;
286 }
287
288 cq->resize_buf->cqe = entries - 1;
289
290 return 0;
291 }
292
293 static int mlx4_alloc_resize_umem(struct mlx4_ib_dev *dev, struct mlx4_ib_cq *cq,
294 int entries, struct ib_udata *udata)
295 {
296 struct mlx4_ib_resize_cq ucmd;
297 int err;
298
299 if (cq->resize_umem)
300 return -EBUSY;
301
302 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd))
303 return -EFAULT;
304
305 cq->resize_buf = kmalloc(sizeof *cq->resize_buf, GFP_ATOMIC);
306 if (!cq->resize_buf)
307 return -ENOMEM;
308
309 err = mlx4_ib_get_cq_umem(dev, cq->umem->context, &cq->resize_buf->buf,
310 &cq->resize_umem, ucmd.buf_addr, entries);
311 if (err) {
312 kfree(cq->resize_buf);
313 cq->resize_buf = NULL;
314 return err;
315 }
316
317 cq->resize_buf->cqe = entries - 1;
318
319 return 0;
320 }
321
322 static int mlx4_ib_get_outstanding_cqes(struct mlx4_ib_cq *cq)
323 {
324 u32 i;
325
326 i = cq->mcq.cons_index;
327 while (get_sw_cqe(cq, i))
328 ++i;
329
330 return i - cq->mcq.cons_index;
331 }
332
333 static void mlx4_ib_cq_resize_copy_cqes(struct mlx4_ib_cq *cq)
334 {
335 struct mlx4_cqe *cqe, *new_cqe;
336 int i;
337 int cqe_size = cq->buf.entry_size;
338 int cqe_inc = cqe_size == 64 ? 1 : 0;
339
340 i = cq->mcq.cons_index;
341 cqe = get_cqe(cq, i & cq->ibcq.cqe);
342 cqe += cqe_inc;
343
344 while ((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) != MLX4_CQE_OPCODE_RESIZE) {
345 new_cqe = get_cqe_from_buf(&cq->resize_buf->buf,
346 (i + 1) & cq->resize_buf->cqe);
347 memcpy(new_cqe, get_cqe(cq, i & cq->ibcq.cqe), cqe_size);
348 new_cqe += cqe_inc;
349
350 new_cqe->owner_sr_opcode = (cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK) |
351 (((i + 1) & (cq->resize_buf->cqe + 1)) ? MLX4_CQE_OWNER_MASK : 0);
352 cqe = get_cqe(cq, ++i & cq->ibcq.cqe);
353 cqe += cqe_inc;
354 }
355 ++cq->mcq.cons_index;
356 }
357
358 int mlx4_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata)
359 {
360 struct mlx4_ib_dev *dev = to_mdev(ibcq->device);
361 struct mlx4_ib_cq *cq = to_mcq(ibcq);
362 struct mlx4_mtt mtt;
363 int outst_cqe;
364 int err;
365
366 mutex_lock(&cq->resize_mutex);
367
368 if (entries < 1) {
369 err = -EINVAL;
370 goto out;
371 }
372
373 entries = roundup_pow_of_two(entries + 1);
374 if (entries == ibcq->cqe + 1) {
375 err = 0;
376 goto out;
377 }
378
379 if (entries > dev->dev->caps.max_cqes) {
380 err = -EINVAL;
381 goto out;
382 }
383
384 if (ibcq->uobject) {
385 err = mlx4_alloc_resize_umem(dev, cq, entries, udata);
386 if (err)
387 goto out;
388 } else {
389 /* Can't be smaller than the number of outstanding CQEs */
390 outst_cqe = mlx4_ib_get_outstanding_cqes(cq);
391 if (entries < outst_cqe + 1) {
392 err = 0;
393 goto out;
394 }
395
396 err = mlx4_alloc_resize_buf(dev, cq, entries);
397 if (err)
398 goto out;
399 }
400
401 mtt = cq->buf.mtt;
402
403 err = mlx4_cq_resize(dev->dev, &cq->mcq, entries, &cq->resize_buf->buf.mtt);
404 if (err)
405 goto err_buf;
406
407 mlx4_mtt_cleanup(dev->dev, &mtt);
408 if (ibcq->uobject) {
409 cq->buf = cq->resize_buf->buf;
410 cq->ibcq.cqe = cq->resize_buf->cqe;
411 ib_umem_release(cq->umem);
412 cq->umem = cq->resize_umem;
413
414 kfree(cq->resize_buf);
415 cq->resize_buf = NULL;
416 cq->resize_umem = NULL;
417 } else {
418 struct mlx4_ib_cq_buf tmp_buf;
419 int tmp_cqe = 0;
420
421 spin_lock_irq(&cq->lock);
422 if (cq->resize_buf) {
423 mlx4_ib_cq_resize_copy_cqes(cq);
424 tmp_buf = cq->buf;
425 tmp_cqe = cq->ibcq.cqe;
426 cq->buf = cq->resize_buf->buf;
427 cq->ibcq.cqe = cq->resize_buf->cqe;
428
429 kfree(cq->resize_buf);
430 cq->resize_buf = NULL;
431 }
432 spin_unlock_irq(&cq->lock);
433
434 if (tmp_cqe)
435 mlx4_ib_free_cq_buf(dev, &tmp_buf, tmp_cqe);
436 }
437
438 goto out;
439
440 err_buf:
441 mlx4_mtt_cleanup(dev->dev, &cq->resize_buf->buf.mtt);
442 if (!ibcq->uobject)
443 mlx4_ib_free_cq_buf(dev, &cq->resize_buf->buf,
444 cq->resize_buf->cqe);
445
446 kfree(cq->resize_buf);
447 cq->resize_buf = NULL;
448
449 if (cq->resize_umem) {
450 ib_umem_release(cq->resize_umem);
451 cq->resize_umem = NULL;
452 }
453
454 out:
455 mutex_unlock(&cq->resize_mutex);
456
457 return err;
458 }
459
460 int mlx4_ib_destroy_cq(struct ib_cq *cq)
461 {
462 struct mlx4_ib_dev *dev = to_mdev(cq->device);
463 struct mlx4_ib_cq *mcq = to_mcq(cq);
464
465 mlx4_cq_free(dev->dev, &mcq->mcq);
466 mlx4_mtt_cleanup(dev->dev, &mcq->buf.mtt);
467
468 if (cq->uobject) {
469 mlx4_ib_db_unmap_user(to_mucontext(cq->uobject->context), &mcq->db);
470 ib_umem_release(mcq->umem);
471 } else {
472 mlx4_ib_free_cq_buf(dev, &mcq->buf, cq->cqe);
473 mlx4_db_free(dev->dev, &mcq->db);
474 }
475
476 kfree(mcq);
477
478 return 0;
479 }
480
481 static void dump_cqe(void *cqe)
482 {
483 __be32 *buf = cqe;
484
485 pr_debug("CQE contents %08x %08x %08x %08x %08x %08x %08x %08x\n",
486 be32_to_cpu(buf[0]), be32_to_cpu(buf[1]), be32_to_cpu(buf[2]),
487 be32_to_cpu(buf[3]), be32_to_cpu(buf[4]), be32_to_cpu(buf[5]),
488 be32_to_cpu(buf[6]), be32_to_cpu(buf[7]));
489 }
490
491 static void mlx4_ib_handle_error_cqe(struct mlx4_err_cqe *cqe,
492 struct ib_wc *wc)
493 {
494 if (cqe->syndrome == MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR) {
495 pr_debug("local QP operation err "
496 "(QPN %06x, WQE index %x, vendor syndrome %02x, "
497 "opcode = %02x)\n",
498 be32_to_cpu(cqe->my_qpn), be16_to_cpu(cqe->wqe_index),
499 cqe->vendor_err_syndrome,
500 cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK);
501 dump_cqe(cqe);
502 }
503
504 switch (cqe->syndrome) {
505 case MLX4_CQE_SYNDROME_LOCAL_LENGTH_ERR:
506 wc->status = IB_WC_LOC_LEN_ERR;
507 break;
508 case MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR:
509 wc->status = IB_WC_LOC_QP_OP_ERR;
510 break;
511 case MLX4_CQE_SYNDROME_LOCAL_PROT_ERR:
512 wc->status = IB_WC_LOC_PROT_ERR;
513 break;
514 case MLX4_CQE_SYNDROME_WR_FLUSH_ERR:
515 wc->status = IB_WC_WR_FLUSH_ERR;
516 break;
517 case MLX4_CQE_SYNDROME_MW_BIND_ERR:
518 wc->status = IB_WC_MW_BIND_ERR;
519 break;
520 case MLX4_CQE_SYNDROME_BAD_RESP_ERR:
521 wc->status = IB_WC_BAD_RESP_ERR;
522 break;
523 case MLX4_CQE_SYNDROME_LOCAL_ACCESS_ERR:
524 wc->status = IB_WC_LOC_ACCESS_ERR;
525 break;
526 case MLX4_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
527 wc->status = IB_WC_REM_INV_REQ_ERR;
528 break;
529 case MLX4_CQE_SYNDROME_REMOTE_ACCESS_ERR:
530 wc->status = IB_WC_REM_ACCESS_ERR;
531 break;
532 case MLX4_CQE_SYNDROME_REMOTE_OP_ERR:
533 wc->status = IB_WC_REM_OP_ERR;
534 break;
535 case MLX4_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
536 wc->status = IB_WC_RETRY_EXC_ERR;
537 break;
538 case MLX4_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
539 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
540 break;
541 case MLX4_CQE_SYNDROME_REMOTE_ABORTED_ERR:
542 wc->status = IB_WC_REM_ABORT_ERR;
543 break;
544 default:
545 wc->status = IB_WC_GENERAL_ERR;
546 break;
547 }
548
549 wc->vendor_err = cqe->vendor_err_syndrome;
550 }
551
552 static int mlx4_ib_ipoib_csum_ok(__be16 status, __be16 checksum)
553 {
554 return ((status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
555 MLX4_CQE_STATUS_IPV4F |
556 MLX4_CQE_STATUS_IPV4OPT |
557 MLX4_CQE_STATUS_IPV6 |
558 MLX4_CQE_STATUS_IPOK)) ==
559 cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
560 MLX4_CQE_STATUS_IPOK)) &&
561 (status & cpu_to_be16(MLX4_CQE_STATUS_UDP |
562 MLX4_CQE_STATUS_TCP)) &&
563 checksum == cpu_to_be16(0xffff);
564 }
565
566 static int use_tunnel_data(struct mlx4_ib_qp *qp, struct mlx4_ib_cq *cq, struct ib_wc *wc,
567 unsigned tail, struct mlx4_cqe *cqe, int is_eth)
568 {
569 struct mlx4_ib_proxy_sqp_hdr *hdr;
570
571 ib_dma_sync_single_for_cpu(qp->ibqp.device,
572 qp->sqp_proxy_rcv[tail].map,
573 sizeof (struct mlx4_ib_proxy_sqp_hdr),
574 DMA_FROM_DEVICE);
575 hdr = (struct mlx4_ib_proxy_sqp_hdr *) (qp->sqp_proxy_rcv[tail].addr);
576 wc->pkey_index = be16_to_cpu(hdr->tun.pkey_index);
577 wc->src_qp = be32_to_cpu(hdr->tun.flags_src_qp) & 0xFFFFFF;
578 wc->wc_flags |= (hdr->tun.g_ml_path & 0x80) ? (IB_WC_GRH) : 0;
579 wc->dlid_path_bits = 0;
580
581 if (is_eth) {
582 wc->vlan_id = be16_to_cpu(hdr->tun.sl_vid);
583 memcpy(&(wc->smac[0]), (char *)&hdr->tun.mac_31_0, 4);
584 memcpy(&(wc->smac[4]), (char *)&hdr->tun.slid_mac_47_32, 2);
585 wc->wc_flags |= (IB_WC_WITH_VLAN | IB_WC_WITH_SMAC);
586 } else {
587 wc->slid = be16_to_cpu(hdr->tun.slid_mac_47_32);
588 wc->sl = (u8) (be16_to_cpu(hdr->tun.sl_vid) >> 12);
589 }
590
591 return 0;
592 }
593
594 static int mlx4_ib_poll_one(struct mlx4_ib_cq *cq,
595 struct mlx4_ib_qp **cur_qp,
596 struct ib_wc *wc)
597 {
598 struct mlx4_cqe *cqe;
599 struct mlx4_qp *mqp;
600 struct mlx4_ib_wq *wq;
601 struct mlx4_ib_srq *srq;
602 struct mlx4_srq *msrq = NULL;
603 int is_send;
604 int is_error;
605 int is_eth;
606 u32 g_mlpath_rqpn;
607 u16 wqe_ctr;
608 unsigned tail = 0;
609
610 repoll:
611 cqe = next_cqe_sw(cq);
612 if (!cqe)
613 return -EAGAIN;
614
615 if (cq->buf.entry_size == 64)
616 cqe++;
617
618 ++cq->mcq.cons_index;
619
620 /*
621 * Make sure we read CQ entry contents after we've checked the
622 * ownership bit.
623 */
624 rmb();
625
626 is_send = cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK;
627 is_error = (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
628 MLX4_CQE_OPCODE_ERROR;
629
630 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == MLX4_OPCODE_NOP &&
631 is_send)) {
632 pr_warn("Completion for NOP opcode detected!\n");
633 return -EINVAL;
634 }
635
636 /* Resize CQ in progress */
637 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == MLX4_CQE_OPCODE_RESIZE)) {
638 if (cq->resize_buf) {
639 struct mlx4_ib_dev *dev = to_mdev(cq->ibcq.device);
640
641 mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe);
642 cq->buf = cq->resize_buf->buf;
643 cq->ibcq.cqe = cq->resize_buf->cqe;
644
645 kfree(cq->resize_buf);
646 cq->resize_buf = NULL;
647 }
648
649 goto repoll;
650 }
651
652 if (!*cur_qp ||
653 (be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) != (*cur_qp)->mqp.qpn) {
654 /*
655 * We do not have to take the QP table lock here,
656 * because CQs will be locked while QPs are removed
657 * from the table.
658 */
659 mqp = __mlx4_qp_lookup(to_mdev(cq->ibcq.device)->dev,
660 be32_to_cpu(cqe->vlan_my_qpn));
661 if (unlikely(!mqp)) {
662 pr_warn("CQ %06x with entry for unknown QPN %06x\n",
663 cq->mcq.cqn, be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK);
664 return -EINVAL;
665 }
666
667 *cur_qp = to_mibqp(mqp);
668 }
669
670 wc->qp = &(*cur_qp)->ibqp;
671
672 if (wc->qp->qp_type == IB_QPT_XRC_TGT) {
673 u32 srq_num;
674 g_mlpath_rqpn = be32_to_cpu(cqe->g_mlpath_rqpn);
675 srq_num = g_mlpath_rqpn & 0xffffff;
676 /* SRQ is also in the radix tree */
677 msrq = mlx4_srq_lookup(to_mdev(cq->ibcq.device)->dev,
678 srq_num);
679 if (unlikely(!msrq)) {
680 pr_warn("CQ %06x with entry for unknown SRQN %06x\n",
681 cq->mcq.cqn, srq_num);
682 return -EINVAL;
683 }
684 }
685
686 if (is_send) {
687 wq = &(*cur_qp)->sq;
688 if (!(*cur_qp)->sq_signal_bits) {
689 wqe_ctr = be16_to_cpu(cqe->wqe_index);
690 wq->tail += (u16) (wqe_ctr - (u16) wq->tail);
691 }
692 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
693 ++wq->tail;
694 } else if ((*cur_qp)->ibqp.srq) {
695 srq = to_msrq((*cur_qp)->ibqp.srq);
696 wqe_ctr = be16_to_cpu(cqe->wqe_index);
697 wc->wr_id = srq->wrid[wqe_ctr];
698 mlx4_ib_free_srq_wqe(srq, wqe_ctr);
699 } else if (msrq) {
700 srq = to_mibsrq(msrq);
701 wqe_ctr = be16_to_cpu(cqe->wqe_index);
702 wc->wr_id = srq->wrid[wqe_ctr];
703 mlx4_ib_free_srq_wqe(srq, wqe_ctr);
704 } else {
705 wq = &(*cur_qp)->rq;
706 tail = wq->tail & (wq->wqe_cnt - 1);
707 wc->wr_id = wq->wrid[tail];
708 ++wq->tail;
709 }
710
711 if (unlikely(is_error)) {
712 mlx4_ib_handle_error_cqe((struct mlx4_err_cqe *) cqe, wc);
713 return 0;
714 }
715
716 wc->status = IB_WC_SUCCESS;
717
718 if (is_send) {
719 wc->wc_flags = 0;
720 switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) {
721 case MLX4_OPCODE_RDMA_WRITE_IMM:
722 wc->wc_flags |= IB_WC_WITH_IMM;
723 case MLX4_OPCODE_RDMA_WRITE:
724 wc->opcode = IB_WC_RDMA_WRITE;
725 break;
726 case MLX4_OPCODE_SEND_IMM:
727 wc->wc_flags |= IB_WC_WITH_IMM;
728 case MLX4_OPCODE_SEND:
729 case MLX4_OPCODE_SEND_INVAL:
730 wc->opcode = IB_WC_SEND;
731 break;
732 case MLX4_OPCODE_RDMA_READ:
733 wc->opcode = IB_WC_RDMA_READ;
734 wc->byte_len = be32_to_cpu(cqe->byte_cnt);
735 break;
736 case MLX4_OPCODE_ATOMIC_CS:
737 wc->opcode = IB_WC_COMP_SWAP;
738 wc->byte_len = 8;
739 break;
740 case MLX4_OPCODE_ATOMIC_FA:
741 wc->opcode = IB_WC_FETCH_ADD;
742 wc->byte_len = 8;
743 break;
744 case MLX4_OPCODE_MASKED_ATOMIC_CS:
745 wc->opcode = IB_WC_MASKED_COMP_SWAP;
746 wc->byte_len = 8;
747 break;
748 case MLX4_OPCODE_MASKED_ATOMIC_FA:
749 wc->opcode = IB_WC_MASKED_FETCH_ADD;
750 wc->byte_len = 8;
751 break;
752 case MLX4_OPCODE_BIND_MW:
753 wc->opcode = IB_WC_BIND_MW;
754 break;
755 case MLX4_OPCODE_LSO:
756 wc->opcode = IB_WC_LSO;
757 break;
758 case MLX4_OPCODE_FMR:
759 wc->opcode = IB_WC_FAST_REG_MR;
760 break;
761 case MLX4_OPCODE_LOCAL_INVAL:
762 wc->opcode = IB_WC_LOCAL_INV;
763 break;
764 }
765 } else {
766 wc->byte_len = be32_to_cpu(cqe->byte_cnt);
767
768 switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) {
769 case MLX4_RECV_OPCODE_RDMA_WRITE_IMM:
770 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
771 wc->wc_flags = IB_WC_WITH_IMM;
772 wc->ex.imm_data = cqe->immed_rss_invalid;
773 break;
774 case MLX4_RECV_OPCODE_SEND_INVAL:
775 wc->opcode = IB_WC_RECV;
776 wc->wc_flags = IB_WC_WITH_INVALIDATE;
777 wc->ex.invalidate_rkey = be32_to_cpu(cqe->immed_rss_invalid);
778 break;
779 case MLX4_RECV_OPCODE_SEND:
780 wc->opcode = IB_WC_RECV;
781 wc->wc_flags = 0;
782 break;
783 case MLX4_RECV_OPCODE_SEND_IMM:
784 wc->opcode = IB_WC_RECV;
785 wc->wc_flags = IB_WC_WITH_IMM;
786 wc->ex.imm_data = cqe->immed_rss_invalid;
787 break;
788 }
789
790 is_eth = (rdma_port_get_link_layer(wc->qp->device,
791 (*cur_qp)->port) ==
792 IB_LINK_LAYER_ETHERNET);
793 if (mlx4_is_mfunc(to_mdev(cq->ibcq.device)->dev)) {
794 if ((*cur_qp)->mlx4_ib_qp_type &
795 (MLX4_IB_QPT_PROXY_SMI_OWNER |
796 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
797 return use_tunnel_data(*cur_qp, cq, wc, tail,
798 cqe, is_eth);
799 }
800
801 wc->slid = be16_to_cpu(cqe->rlid);
802 g_mlpath_rqpn = be32_to_cpu(cqe->g_mlpath_rqpn);
803 wc->src_qp = g_mlpath_rqpn & 0xffffff;
804 wc->dlid_path_bits = (g_mlpath_rqpn >> 24) & 0x7f;
805 wc->wc_flags |= g_mlpath_rqpn & 0x80000000 ? IB_WC_GRH : 0;
806 wc->pkey_index = be32_to_cpu(cqe->immed_rss_invalid) & 0x7f;
807 wc->wc_flags |= mlx4_ib_ipoib_csum_ok(cqe->status,
808 cqe->checksum) ? IB_WC_IP_CSUM_OK : 0;
809 if (is_eth) {
810 wc->sl = be16_to_cpu(cqe->sl_vid) >> 13;
811 if (be32_to_cpu(cqe->vlan_my_qpn) &
812 MLX4_CQE_VLAN_PRESENT_MASK) {
813 wc->vlan_id = be16_to_cpu(cqe->sl_vid) &
814 MLX4_CQE_VID_MASK;
815 } else {
816 wc->vlan_id = 0xffff;
817 }
818 memcpy(wc->smac, cqe->smac, ETH_ALEN);
819 wc->wc_flags |= (IB_WC_WITH_VLAN | IB_WC_WITH_SMAC);
820 } else {
821 wc->sl = be16_to_cpu(cqe->sl_vid) >> 12;
822 wc->vlan_id = 0xffff;
823 }
824 }
825
826 return 0;
827 }
828
829 int mlx4_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
830 {
831 struct mlx4_ib_cq *cq = to_mcq(ibcq);
832 struct mlx4_ib_qp *cur_qp = NULL;
833 unsigned long flags;
834 int npolled;
835 int err = 0;
836
837 spin_lock_irqsave(&cq->lock, flags);
838
839 for (npolled = 0; npolled < num_entries; ++npolled) {
840 err = mlx4_ib_poll_one(cq, &cur_qp, wc + npolled);
841 if (err)
842 break;
843 }
844
845 mlx4_cq_set_ci(&cq->mcq);
846
847 spin_unlock_irqrestore(&cq->lock, flags);
848
849 if (err == 0 || err == -EAGAIN)
850 return npolled;
851 else
852 return err;
853 }
854
855 int mlx4_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
856 {
857 mlx4_cq_arm(&to_mcq(ibcq)->mcq,
858 (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
859 MLX4_CQ_DB_REQ_NOT_SOL : MLX4_CQ_DB_REQ_NOT,
860 to_mdev(ibcq->device)->uar_map,
861 MLX4_GET_DOORBELL_LOCK(&to_mdev(ibcq->device)->uar_lock));
862
863 return 0;
864 }
865
866 void __mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq)
867 {
868 u32 prod_index;
869 int nfreed = 0;
870 struct mlx4_cqe *cqe, *dest;
871 u8 owner_bit;
872 int cqe_inc = cq->buf.entry_size == 64 ? 1 : 0;
873
874 /*
875 * First we need to find the current producer index, so we
876 * know where to start cleaning from. It doesn't matter if HW
877 * adds new entries after this loop -- the QP we're worried
878 * about is already in RESET, so the new entries won't come
879 * from our QP and therefore don't need to be checked.
880 */
881 for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); ++prod_index)
882 if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe)
883 break;
884
885 /*
886 * Now sweep backwards through the CQ, removing CQ entries
887 * that match our QP by copying older entries on top of them.
888 */
889 while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) {
890 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe);
891 cqe += cqe_inc;
892
893 if ((be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) == qpn) {
894 if (srq && !(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK))
895 mlx4_ib_free_srq_wqe(srq, be16_to_cpu(cqe->wqe_index));
896 ++nfreed;
897 } else if (nfreed) {
898 dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe);
899 dest += cqe_inc;
900
901 owner_bit = dest->owner_sr_opcode & MLX4_CQE_OWNER_MASK;
902 memcpy(dest, cqe, sizeof *cqe);
903 dest->owner_sr_opcode = owner_bit |
904 (dest->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK);
905 }
906 }
907
908 if (nfreed) {
909 cq->mcq.cons_index += nfreed;
910 /*
911 * Make sure update of buffer contents is done before
912 * updating consumer index.
913 */
914 wmb();
915 mlx4_cq_set_ci(&cq->mcq);
916 }
917 }
918
919 void mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq)
920 {
921 spin_lock_irq(&cq->lock);
922 __mlx4_ib_cq_clean(cq, qpn, srq);
923 spin_unlock_irq(&cq->lock);
924 }
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