2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/log2.h>
35 #include <linux/slab.h>
37 #include <rdma/ib_cache.h>
38 #include <rdma/ib_pack.h>
40 #include <linux/mlx4/qp.h>
46 MLX4_IB_ACK_REQ_FREQ
= 8,
50 MLX4_IB_DEFAULT_SCHED_QUEUE
= 0x83,
51 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE
= 0x3f
56 * Largest possible UD header: send with GRH and immediate data.
58 MLX4_IB_UD_HEADER_SIZE
= 72,
59 MLX4_IB_LSO_HEADER_SPARE
= 128,
67 struct ib_ud_header ud_header
;
68 u8 header_buf
[MLX4_IB_UD_HEADER_SIZE
];
72 MLX4_IB_MIN_SQ_STRIDE
= 6,
73 MLX4_IB_CACHE_LINE_SIZE
= 64,
76 static const __be32 mlx4_ib_opcode
[] = {
77 [IB_WR_SEND
] = cpu_to_be32(MLX4_OPCODE_SEND
),
78 [IB_WR_LSO
] = cpu_to_be32(MLX4_OPCODE_LSO
),
79 [IB_WR_SEND_WITH_IMM
] = cpu_to_be32(MLX4_OPCODE_SEND_IMM
),
80 [IB_WR_RDMA_WRITE
] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE
),
81 [IB_WR_RDMA_WRITE_WITH_IMM
] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM
),
82 [IB_WR_RDMA_READ
] = cpu_to_be32(MLX4_OPCODE_RDMA_READ
),
83 [IB_WR_ATOMIC_CMP_AND_SWP
] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS
),
84 [IB_WR_ATOMIC_FETCH_AND_ADD
] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA
),
85 [IB_WR_SEND_WITH_INV
] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL
),
86 [IB_WR_LOCAL_INV
] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL
),
87 [IB_WR_FAST_REG_MR
] = cpu_to_be32(MLX4_OPCODE_FMR
),
90 static struct mlx4_ib_sqp
*to_msqp(struct mlx4_ib_qp
*mqp
)
92 return container_of(mqp
, struct mlx4_ib_sqp
, qp
);
95 static int is_sqp(struct mlx4_ib_dev
*dev
, struct mlx4_ib_qp
*qp
)
97 return qp
->mqp
.qpn
>= dev
->dev
->caps
.sqp_start
&&
98 qp
->mqp
.qpn
<= dev
->dev
->caps
.sqp_start
+ 3;
101 static int is_qp0(struct mlx4_ib_dev
*dev
, struct mlx4_ib_qp
*qp
)
103 return qp
->mqp
.qpn
>= dev
->dev
->caps
.sqp_start
&&
104 qp
->mqp
.qpn
<= dev
->dev
->caps
.sqp_start
+ 1;
107 static void *get_wqe(struct mlx4_ib_qp
*qp
, int offset
)
109 return mlx4_buf_offset(&qp
->buf
, offset
);
112 static void *get_recv_wqe(struct mlx4_ib_qp
*qp
, int n
)
114 return get_wqe(qp
, qp
->rq
.offset
+ (n
<< qp
->rq
.wqe_shift
));
117 static void *get_send_wqe(struct mlx4_ib_qp
*qp
, int n
)
119 return get_wqe(qp
, qp
->sq
.offset
+ (n
<< qp
->sq
.wqe_shift
));
123 * Stamp a SQ WQE so that it is invalid if prefetched by marking the
124 * first four bytes of every 64 byte chunk with
125 * 0x7FFFFFF | (invalid_ownership_value << 31).
127 * When the max work request size is less than or equal to the WQE
128 * basic block size, as an optimization, we can stamp all WQEs with
129 * 0xffffffff, and skip the very first chunk of each WQE.
131 static void stamp_send_wqe(struct mlx4_ib_qp
*qp
, int n
, int size
)
139 struct mlx4_wqe_ctrl_seg
*ctrl
;
141 if (qp
->sq_max_wqes_per_wr
> 1) {
142 s
= roundup(size
, 1U << qp
->sq
.wqe_shift
);
143 for (i
= 0; i
< s
; i
+= 64) {
144 ind
= (i
>> qp
->sq
.wqe_shift
) + n
;
145 stamp
= ind
& qp
->sq
.wqe_cnt
? cpu_to_be32(0x7fffffff) :
146 cpu_to_be32(0xffffffff);
147 buf
= get_send_wqe(qp
, ind
& (qp
->sq
.wqe_cnt
- 1));
148 wqe
= buf
+ (i
& ((1 << qp
->sq
.wqe_shift
) - 1));
152 ctrl
= buf
= get_send_wqe(qp
, n
& (qp
->sq
.wqe_cnt
- 1));
153 s
= (ctrl
->fence_size
& 0x3f) << 4;
154 for (i
= 64; i
< s
; i
+= 64) {
156 *wqe
= cpu_to_be32(0xffffffff);
161 static void post_nop_wqe(struct mlx4_ib_qp
*qp
, int n
, int size
)
163 struct mlx4_wqe_ctrl_seg
*ctrl
;
164 struct mlx4_wqe_inline_seg
*inl
;
168 ctrl
= wqe
= get_send_wqe(qp
, n
& (qp
->sq
.wqe_cnt
- 1));
169 s
= sizeof(struct mlx4_wqe_ctrl_seg
);
171 if (qp
->ibqp
.qp_type
== IB_QPT_UD
) {
172 struct mlx4_wqe_datagram_seg
*dgram
= wqe
+ sizeof *ctrl
;
173 struct mlx4_av
*av
= (struct mlx4_av
*)dgram
->av
;
174 memset(dgram
, 0, sizeof *dgram
);
175 av
->port_pd
= cpu_to_be32((qp
->port
<< 24) | to_mpd(qp
->ibqp
.pd
)->pdn
);
176 s
+= sizeof(struct mlx4_wqe_datagram_seg
);
179 /* Pad the remainder of the WQE with an inline data segment. */
182 inl
->byte_count
= cpu_to_be32(1 << 31 | (size
- s
- sizeof *inl
));
184 ctrl
->srcrb_flags
= 0;
185 ctrl
->fence_size
= size
/ 16;
187 * Make sure descriptor is fully written before setting ownership bit
188 * (because HW can start executing as soon as we do).
192 ctrl
->owner_opcode
= cpu_to_be32(MLX4_OPCODE_NOP
| MLX4_WQE_CTRL_NEC
) |
193 (n
& qp
->sq
.wqe_cnt
? cpu_to_be32(1 << 31) : 0);
195 stamp_send_wqe(qp
, n
+ qp
->sq_spare_wqes
, size
);
198 /* Post NOP WQE to prevent wrap-around in the middle of WR */
199 static inline unsigned pad_wraparound(struct mlx4_ib_qp
*qp
, int ind
)
201 unsigned s
= qp
->sq
.wqe_cnt
- (ind
& (qp
->sq
.wqe_cnt
- 1));
202 if (unlikely(s
< qp
->sq_max_wqes_per_wr
)) {
203 post_nop_wqe(qp
, ind
, s
<< qp
->sq
.wqe_shift
);
209 static void mlx4_ib_qp_event(struct mlx4_qp
*qp
, enum mlx4_event type
)
211 struct ib_event event
;
212 struct ib_qp
*ibqp
= &to_mibqp(qp
)->ibqp
;
214 if (type
== MLX4_EVENT_TYPE_PATH_MIG
)
215 to_mibqp(qp
)->port
= to_mibqp(qp
)->alt_port
;
217 if (ibqp
->event_handler
) {
218 event
.device
= ibqp
->device
;
219 event
.element
.qp
= ibqp
;
221 case MLX4_EVENT_TYPE_PATH_MIG
:
222 event
.event
= IB_EVENT_PATH_MIG
;
224 case MLX4_EVENT_TYPE_COMM_EST
:
225 event
.event
= IB_EVENT_COMM_EST
;
227 case MLX4_EVENT_TYPE_SQ_DRAINED
:
228 event
.event
= IB_EVENT_SQ_DRAINED
;
230 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE
:
231 event
.event
= IB_EVENT_QP_LAST_WQE_REACHED
;
233 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR
:
234 event
.event
= IB_EVENT_QP_FATAL
;
236 case MLX4_EVENT_TYPE_PATH_MIG_FAILED
:
237 event
.event
= IB_EVENT_PATH_MIG_ERR
;
239 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR
:
240 event
.event
= IB_EVENT_QP_REQ_ERR
;
242 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR
:
243 event
.event
= IB_EVENT_QP_ACCESS_ERR
;
246 printk(KERN_WARNING
"mlx4_ib: Unexpected event type %d "
247 "on QP %06x\n", type
, qp
->qpn
);
251 ibqp
->event_handler(&event
, ibqp
->qp_context
);
255 static int send_wqe_overhead(enum ib_qp_type type
, u32 flags
)
258 * UD WQEs must have a datagram segment.
259 * RC and UC WQEs might have a remote address segment.
260 * MLX WQEs need two extra inline data segments (for the UD
261 * header and space for the ICRC).
265 return sizeof (struct mlx4_wqe_ctrl_seg
) +
266 sizeof (struct mlx4_wqe_datagram_seg
) +
267 ((flags
& MLX4_IB_QP_LSO
) ? MLX4_IB_LSO_HEADER_SPARE
: 0);
269 return sizeof (struct mlx4_wqe_ctrl_seg
) +
270 sizeof (struct mlx4_wqe_raddr_seg
);
272 return sizeof (struct mlx4_wqe_ctrl_seg
) +
273 sizeof (struct mlx4_wqe_atomic_seg
) +
274 sizeof (struct mlx4_wqe_raddr_seg
);
277 return sizeof (struct mlx4_wqe_ctrl_seg
) +
278 ALIGN(MLX4_IB_UD_HEADER_SIZE
+
279 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE
,
281 sizeof (struct mlx4_wqe_inline_seg
),
282 sizeof (struct mlx4_wqe_data_seg
)) +
284 sizeof (struct mlx4_wqe_inline_seg
),
285 sizeof (struct mlx4_wqe_data_seg
));
287 return sizeof (struct mlx4_wqe_ctrl_seg
);
291 static int set_rq_size(struct mlx4_ib_dev
*dev
, struct ib_qp_cap
*cap
,
292 int is_user
, int has_srq
, struct mlx4_ib_qp
*qp
)
294 /* Sanity check RQ size before proceeding */
295 if (cap
->max_recv_wr
> dev
->dev
->caps
.max_wqes
||
296 cap
->max_recv_sge
> dev
->dev
->caps
.max_rq_sg
)
300 /* QPs attached to an SRQ should have no RQ */
301 if (cap
->max_recv_wr
)
304 qp
->rq
.wqe_cnt
= qp
->rq
.max_gs
= 0;
306 /* HW requires >= 1 RQ entry with >= 1 gather entry */
307 if (is_user
&& (!cap
->max_recv_wr
|| !cap
->max_recv_sge
))
310 qp
->rq
.wqe_cnt
= roundup_pow_of_two(max(1U, cap
->max_recv_wr
));
311 qp
->rq
.max_gs
= roundup_pow_of_two(max(1U, cap
->max_recv_sge
));
312 qp
->rq
.wqe_shift
= ilog2(qp
->rq
.max_gs
* sizeof (struct mlx4_wqe_data_seg
));
315 cap
->max_recv_wr
= qp
->rq
.max_post
= qp
->rq
.wqe_cnt
;
316 cap
->max_recv_sge
= qp
->rq
.max_gs
;
321 static int set_kernel_sq_size(struct mlx4_ib_dev
*dev
, struct ib_qp_cap
*cap
,
322 enum ib_qp_type type
, struct mlx4_ib_qp
*qp
)
326 /* Sanity check SQ size before proceeding */
327 if (cap
->max_send_wr
> dev
->dev
->caps
.max_wqes
||
328 cap
->max_send_sge
> dev
->dev
->caps
.max_sq_sg
||
329 cap
->max_inline_data
+ send_wqe_overhead(type
, qp
->flags
) +
330 sizeof (struct mlx4_wqe_inline_seg
) > dev
->dev
->caps
.max_sq_desc_sz
)
334 * For MLX transport we need 2 extra S/G entries:
335 * one for the header and one for the checksum at the end
337 if ((type
== IB_QPT_SMI
|| type
== IB_QPT_GSI
) &&
338 cap
->max_send_sge
+ 2 > dev
->dev
->caps
.max_sq_sg
)
341 s
= max(cap
->max_send_sge
* sizeof (struct mlx4_wqe_data_seg
),
342 cap
->max_inline_data
+ sizeof (struct mlx4_wqe_inline_seg
)) +
343 send_wqe_overhead(type
, qp
->flags
);
345 if (s
> dev
->dev
->caps
.max_sq_desc_sz
)
349 * Hermon supports shrinking WQEs, such that a single work
350 * request can include multiple units of 1 << wqe_shift. This
351 * way, work requests can differ in size, and do not have to
352 * be a power of 2 in size, saving memory and speeding up send
353 * WR posting. Unfortunately, if we do this then the
354 * wqe_index field in CQEs can't be used to look up the WR ID
355 * anymore, so we do this only if selective signaling is off.
357 * Further, on 32-bit platforms, we can't use vmap() to make
358 * the QP buffer virtually contiguous. Thus we have to use
359 * constant-sized WRs to make sure a WR is always fully within
360 * a single page-sized chunk.
362 * Finally, we use NOP work requests to pad the end of the
363 * work queue, to avoid wrap-around in the middle of WR. We
364 * set NEC bit to avoid getting completions with error for
365 * these NOP WRs, but since NEC is only supported starting
366 * with firmware 2.2.232, we use constant-sized WRs for older
369 * And, since MLX QPs only support SEND, we use constant-sized
372 * We look for the smallest value of wqe_shift such that the
373 * resulting number of wqes does not exceed device
376 * We set WQE size to at least 64 bytes, this way stamping
377 * invalidates each WQE.
379 if (dev
->dev
->caps
.fw_ver
>= MLX4_FW_VER_WQE_CTRL_NEC
&&
380 qp
->sq_signal_bits
&& BITS_PER_LONG
== 64 &&
381 type
!= IB_QPT_SMI
&& type
!= IB_QPT_GSI
)
382 qp
->sq
.wqe_shift
= ilog2(64);
384 qp
->sq
.wqe_shift
= ilog2(roundup_pow_of_two(s
));
387 qp
->sq_max_wqes_per_wr
= DIV_ROUND_UP(s
, 1U << qp
->sq
.wqe_shift
);
390 * We need to leave 2 KB + 1 WR of headroom in the SQ to
391 * allow HW to prefetch.
393 qp
->sq_spare_wqes
= (2048 >> qp
->sq
.wqe_shift
) + qp
->sq_max_wqes_per_wr
;
394 qp
->sq
.wqe_cnt
= roundup_pow_of_two(cap
->max_send_wr
*
395 qp
->sq_max_wqes_per_wr
+
398 if (qp
->sq
.wqe_cnt
<= dev
->dev
->caps
.max_wqes
)
401 if (qp
->sq_max_wqes_per_wr
<= 1)
407 qp
->sq
.max_gs
= (min(dev
->dev
->caps
.max_sq_desc_sz
,
408 (qp
->sq_max_wqes_per_wr
<< qp
->sq
.wqe_shift
)) -
409 send_wqe_overhead(type
, qp
->flags
)) /
410 sizeof (struct mlx4_wqe_data_seg
);
412 qp
->buf_size
= (qp
->rq
.wqe_cnt
<< qp
->rq
.wqe_shift
) +
413 (qp
->sq
.wqe_cnt
<< qp
->sq
.wqe_shift
);
414 if (qp
->rq
.wqe_shift
> qp
->sq
.wqe_shift
) {
416 qp
->sq
.offset
= qp
->rq
.wqe_cnt
<< qp
->rq
.wqe_shift
;
418 qp
->rq
.offset
= qp
->sq
.wqe_cnt
<< qp
->sq
.wqe_shift
;
422 cap
->max_send_wr
= qp
->sq
.max_post
=
423 (qp
->sq
.wqe_cnt
- qp
->sq_spare_wqes
) / qp
->sq_max_wqes_per_wr
;
424 cap
->max_send_sge
= min(qp
->sq
.max_gs
,
425 min(dev
->dev
->caps
.max_sq_sg
,
426 dev
->dev
->caps
.max_rq_sg
));
427 /* We don't support inline sends for kernel QPs (yet) */
428 cap
->max_inline_data
= 0;
433 static int set_user_sq_size(struct mlx4_ib_dev
*dev
,
434 struct mlx4_ib_qp
*qp
,
435 struct mlx4_ib_create_qp
*ucmd
)
437 /* Sanity check SQ size before proceeding */
438 if ((1 << ucmd
->log_sq_bb_count
) > dev
->dev
->caps
.max_wqes
||
439 ucmd
->log_sq_stride
>
440 ilog2(roundup_pow_of_two(dev
->dev
->caps
.max_sq_desc_sz
)) ||
441 ucmd
->log_sq_stride
< MLX4_IB_MIN_SQ_STRIDE
)
444 qp
->sq
.wqe_cnt
= 1 << ucmd
->log_sq_bb_count
;
445 qp
->sq
.wqe_shift
= ucmd
->log_sq_stride
;
447 qp
->buf_size
= (qp
->rq
.wqe_cnt
<< qp
->rq
.wqe_shift
) +
448 (qp
->sq
.wqe_cnt
<< qp
->sq
.wqe_shift
);
453 static int create_qp_common(struct mlx4_ib_dev
*dev
, struct ib_pd
*pd
,
454 struct ib_qp_init_attr
*init_attr
,
455 struct ib_udata
*udata
, int sqpn
, struct mlx4_ib_qp
*qp
)
460 mutex_init(&qp
->mutex
);
461 spin_lock_init(&qp
->sq
.lock
);
462 spin_lock_init(&qp
->rq
.lock
);
464 qp
->state
= IB_QPS_RESET
;
465 if (init_attr
->sq_sig_type
== IB_SIGNAL_ALL_WR
)
466 qp
->sq_signal_bits
= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE
);
468 err
= set_rq_size(dev
, &init_attr
->cap
, !!pd
->uobject
, !!init_attr
->srq
, qp
);
473 struct mlx4_ib_create_qp ucmd
;
475 if (ib_copy_from_udata(&ucmd
, udata
, sizeof ucmd
)) {
480 qp
->sq_no_prefetch
= ucmd
.sq_no_prefetch
;
482 err
= set_user_sq_size(dev
, qp
, &ucmd
);
486 qp
->umem
= ib_umem_get(pd
->uobject
->context
, ucmd
.buf_addr
,
488 if (IS_ERR(qp
->umem
)) {
489 err
= PTR_ERR(qp
->umem
);
493 err
= mlx4_mtt_init(dev
->dev
, ib_umem_page_count(qp
->umem
),
494 ilog2(qp
->umem
->page_size
), &qp
->mtt
);
498 err
= mlx4_ib_umem_write_mtt(dev
, &qp
->mtt
, qp
->umem
);
502 if (!init_attr
->srq
) {
503 err
= mlx4_ib_db_map_user(to_mucontext(pd
->uobject
->context
),
504 ucmd
.db_addr
, &qp
->db
);
509 qp
->sq_no_prefetch
= 0;
511 if (init_attr
->create_flags
& IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK
)
512 qp
->flags
|= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK
;
514 if (init_attr
->create_flags
& IB_QP_CREATE_IPOIB_UD_LSO
)
515 qp
->flags
|= MLX4_IB_QP_LSO
;
517 err
= set_kernel_sq_size(dev
, &init_attr
->cap
, init_attr
->qp_type
, qp
);
521 if (!init_attr
->srq
) {
522 err
= mlx4_db_alloc(dev
->dev
, &qp
->db
, 0);
529 if (mlx4_buf_alloc(dev
->dev
, qp
->buf_size
, PAGE_SIZE
* 2, &qp
->buf
)) {
534 err
= mlx4_mtt_init(dev
->dev
, qp
->buf
.npages
, qp
->buf
.page_shift
,
539 err
= mlx4_buf_write_mtt(dev
->dev
, &qp
->mtt
, &qp
->buf
);
543 qp
->sq
.wrid
= kmalloc(qp
->sq
.wqe_cnt
* sizeof (u64
), GFP_KERNEL
);
544 qp
->rq
.wrid
= kmalloc(qp
->rq
.wqe_cnt
* sizeof (u64
), GFP_KERNEL
);
546 if (!qp
->sq
.wrid
|| !qp
->rq
.wrid
) {
555 err
= mlx4_qp_reserve_range(dev
->dev
, 1, 1, &qpn
);
560 err
= mlx4_qp_alloc(dev
->dev
, qpn
, &qp
->mqp
);
565 * Hardware wants QPN written in big-endian order (after
566 * shifting) for send doorbell. Precompute this value to save
567 * a little bit when posting sends.
569 qp
->doorbell_qpn
= swab32(qp
->mqp
.qpn
<< 8);
571 qp
->mqp
.event
= mlx4_ib_qp_event
;
577 mlx4_qp_release_range(dev
->dev
, qpn
, 1);
582 mlx4_ib_db_unmap_user(to_mucontext(pd
->uobject
->context
),
590 mlx4_mtt_cleanup(dev
->dev
, &qp
->mtt
);
594 ib_umem_release(qp
->umem
);
596 mlx4_buf_free(dev
->dev
, qp
->buf_size
, &qp
->buf
);
599 if (!pd
->uobject
&& !init_attr
->srq
)
600 mlx4_db_free(dev
->dev
, &qp
->db
);
606 static enum mlx4_qp_state
to_mlx4_state(enum ib_qp_state state
)
609 case IB_QPS_RESET
: return MLX4_QP_STATE_RST
;
610 case IB_QPS_INIT
: return MLX4_QP_STATE_INIT
;
611 case IB_QPS_RTR
: return MLX4_QP_STATE_RTR
;
612 case IB_QPS_RTS
: return MLX4_QP_STATE_RTS
;
613 case IB_QPS_SQD
: return MLX4_QP_STATE_SQD
;
614 case IB_QPS_SQE
: return MLX4_QP_STATE_SQER
;
615 case IB_QPS_ERR
: return MLX4_QP_STATE_ERR
;
620 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq
*send_cq
, struct mlx4_ib_cq
*recv_cq
)
621 __acquires(&send_cq
->lock
) __acquires(&recv_cq
->lock
)
623 if (send_cq
== recv_cq
) {
624 spin_lock_irq(&send_cq
->lock
);
625 __acquire(&recv_cq
->lock
);
626 } else if (send_cq
->mcq
.cqn
< recv_cq
->mcq
.cqn
) {
627 spin_lock_irq(&send_cq
->lock
);
628 spin_lock_nested(&recv_cq
->lock
, SINGLE_DEPTH_NESTING
);
630 spin_lock_irq(&recv_cq
->lock
);
631 spin_lock_nested(&send_cq
->lock
, SINGLE_DEPTH_NESTING
);
635 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq
*send_cq
, struct mlx4_ib_cq
*recv_cq
)
636 __releases(&send_cq
->lock
) __releases(&recv_cq
->lock
)
638 if (send_cq
== recv_cq
) {
639 __release(&recv_cq
->lock
);
640 spin_unlock_irq(&send_cq
->lock
);
641 } else if (send_cq
->mcq
.cqn
< recv_cq
->mcq
.cqn
) {
642 spin_unlock(&recv_cq
->lock
);
643 spin_unlock_irq(&send_cq
->lock
);
645 spin_unlock(&send_cq
->lock
);
646 spin_unlock_irq(&recv_cq
->lock
);
650 static void destroy_qp_common(struct mlx4_ib_dev
*dev
, struct mlx4_ib_qp
*qp
,
653 struct mlx4_ib_cq
*send_cq
, *recv_cq
;
655 if (qp
->state
!= IB_QPS_RESET
)
656 if (mlx4_qp_modify(dev
->dev
, NULL
, to_mlx4_state(qp
->state
),
657 MLX4_QP_STATE_RST
, NULL
, 0, 0, &qp
->mqp
))
658 printk(KERN_WARNING
"mlx4_ib: modify QP %06x to RESET failed.\n",
661 send_cq
= to_mcq(qp
->ibqp
.send_cq
);
662 recv_cq
= to_mcq(qp
->ibqp
.recv_cq
);
664 mlx4_ib_lock_cqs(send_cq
, recv_cq
);
667 __mlx4_ib_cq_clean(recv_cq
, qp
->mqp
.qpn
,
668 qp
->ibqp
.srq
? to_msrq(qp
->ibqp
.srq
): NULL
);
669 if (send_cq
!= recv_cq
)
670 __mlx4_ib_cq_clean(send_cq
, qp
->mqp
.qpn
, NULL
);
673 mlx4_qp_remove(dev
->dev
, &qp
->mqp
);
675 mlx4_ib_unlock_cqs(send_cq
, recv_cq
);
677 mlx4_qp_free(dev
->dev
, &qp
->mqp
);
679 if (!is_sqp(dev
, qp
))
680 mlx4_qp_release_range(dev
->dev
, qp
->mqp
.qpn
, 1);
682 mlx4_mtt_cleanup(dev
->dev
, &qp
->mtt
);
686 mlx4_ib_db_unmap_user(to_mucontext(qp
->ibqp
.uobject
->context
),
688 ib_umem_release(qp
->umem
);
692 mlx4_buf_free(dev
->dev
, qp
->buf_size
, &qp
->buf
);
694 mlx4_db_free(dev
->dev
, &qp
->db
);
698 struct ib_qp
*mlx4_ib_create_qp(struct ib_pd
*pd
,
699 struct ib_qp_init_attr
*init_attr
,
700 struct ib_udata
*udata
)
702 struct mlx4_ib_dev
*dev
= to_mdev(pd
->device
);
703 struct mlx4_ib_sqp
*sqp
;
704 struct mlx4_ib_qp
*qp
;
708 * We only support LSO and multicast loopback blocking, and
709 * only for kernel UD QPs.
711 if (init_attr
->create_flags
& ~(IB_QP_CREATE_IPOIB_UD_LSO
|
712 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK
))
713 return ERR_PTR(-EINVAL
);
715 if (init_attr
->create_flags
&&
716 (pd
->uobject
|| init_attr
->qp_type
!= IB_QPT_UD
))
717 return ERR_PTR(-EINVAL
);
719 switch (init_attr
->qp_type
) {
724 qp
= kzalloc(sizeof *qp
, GFP_KERNEL
);
726 return ERR_PTR(-ENOMEM
);
728 err
= create_qp_common(dev
, pd
, init_attr
, udata
, 0, qp
);
734 qp
->ibqp
.qp_num
= qp
->mqp
.qpn
;
741 /* Userspace is not allowed to create special QPs: */
743 return ERR_PTR(-EINVAL
);
745 sqp
= kzalloc(sizeof *sqp
, GFP_KERNEL
);
747 return ERR_PTR(-ENOMEM
);
751 err
= create_qp_common(dev
, pd
, init_attr
, udata
,
752 dev
->dev
->caps
.sqp_start
+
753 (init_attr
->qp_type
== IB_QPT_SMI
? 0 : 2) +
754 init_attr
->port_num
- 1,
761 qp
->port
= init_attr
->port_num
;
762 qp
->ibqp
.qp_num
= init_attr
->qp_type
== IB_QPT_SMI
? 0 : 1;
767 /* Don't support raw QPs */
768 return ERR_PTR(-EINVAL
);
774 int mlx4_ib_destroy_qp(struct ib_qp
*qp
)
776 struct mlx4_ib_dev
*dev
= to_mdev(qp
->device
);
777 struct mlx4_ib_qp
*mqp
= to_mqp(qp
);
779 if (is_qp0(dev
, mqp
))
780 mlx4_CLOSE_PORT(dev
->dev
, mqp
->port
);
782 destroy_qp_common(dev
, mqp
, !!qp
->pd
->uobject
);
784 if (is_sqp(dev
, mqp
))
792 static int to_mlx4_st(enum ib_qp_type type
)
795 case IB_QPT_RC
: return MLX4_QP_ST_RC
;
796 case IB_QPT_UC
: return MLX4_QP_ST_UC
;
797 case IB_QPT_UD
: return MLX4_QP_ST_UD
;
799 case IB_QPT_GSI
: return MLX4_QP_ST_MLX
;
804 static __be32
to_mlx4_access_flags(struct mlx4_ib_qp
*qp
, const struct ib_qp_attr
*attr
,
809 u32 hw_access_flags
= 0;
811 if (attr_mask
& IB_QP_MAX_DEST_RD_ATOMIC
)
812 dest_rd_atomic
= attr
->max_dest_rd_atomic
;
814 dest_rd_atomic
= qp
->resp_depth
;
816 if (attr_mask
& IB_QP_ACCESS_FLAGS
)
817 access_flags
= attr
->qp_access_flags
;
819 access_flags
= qp
->atomic_rd_en
;
822 access_flags
&= IB_ACCESS_REMOTE_WRITE
;
824 if (access_flags
& IB_ACCESS_REMOTE_READ
)
825 hw_access_flags
|= MLX4_QP_BIT_RRE
;
826 if (access_flags
& IB_ACCESS_REMOTE_ATOMIC
)
827 hw_access_flags
|= MLX4_QP_BIT_RAE
;
828 if (access_flags
& IB_ACCESS_REMOTE_WRITE
)
829 hw_access_flags
|= MLX4_QP_BIT_RWE
;
831 return cpu_to_be32(hw_access_flags
);
834 static void store_sqp_attrs(struct mlx4_ib_sqp
*sqp
, const struct ib_qp_attr
*attr
,
837 if (attr_mask
& IB_QP_PKEY_INDEX
)
838 sqp
->pkey_index
= attr
->pkey_index
;
839 if (attr_mask
& IB_QP_QKEY
)
840 sqp
->qkey
= attr
->qkey
;
841 if (attr_mask
& IB_QP_SQ_PSN
)
842 sqp
->send_psn
= attr
->sq_psn
;
845 static void mlx4_set_sched(struct mlx4_qp_path
*path
, u8 port
)
847 path
->sched_queue
= (path
->sched_queue
& 0xbf) | ((port
- 1) << 6);
850 static int mlx4_set_path(struct mlx4_ib_dev
*dev
, const struct ib_ah_attr
*ah
,
851 struct mlx4_qp_path
*path
, u8 port
)
853 path
->grh_mylmc
= ah
->src_path_bits
& 0x7f;
854 path
->rlid
= cpu_to_be16(ah
->dlid
);
855 if (ah
->static_rate
) {
856 path
->static_rate
= ah
->static_rate
+ MLX4_STAT_RATE_OFFSET
;
857 while (path
->static_rate
> IB_RATE_2_5_GBPS
+ MLX4_STAT_RATE_OFFSET
&&
858 !(1 << path
->static_rate
& dev
->dev
->caps
.stat_rate_support
))
861 path
->static_rate
= 0;
862 path
->counter_index
= 0xff;
864 if (ah
->ah_flags
& IB_AH_GRH
) {
865 if (ah
->grh
.sgid_index
>= dev
->dev
->caps
.gid_table_len
[port
]) {
866 printk(KERN_ERR
"sgid_index (%u) too large. max is %d\n",
867 ah
->grh
.sgid_index
, dev
->dev
->caps
.gid_table_len
[port
] - 1);
871 path
->grh_mylmc
|= 1 << 7;
872 path
->mgid_index
= ah
->grh
.sgid_index
;
873 path
->hop_limit
= ah
->grh
.hop_limit
;
874 path
->tclass_flowlabel
=
875 cpu_to_be32((ah
->grh
.traffic_class
<< 20) |
876 (ah
->grh
.flow_label
));
877 memcpy(path
->rgid
, ah
->grh
.dgid
.raw
, 16);
880 path
->sched_queue
= MLX4_IB_DEFAULT_SCHED_QUEUE
|
881 ((port
- 1) << 6) | ((ah
->sl
& 0xf) << 2);
886 static int __mlx4_ib_modify_qp(struct ib_qp
*ibqp
,
887 const struct ib_qp_attr
*attr
, int attr_mask
,
888 enum ib_qp_state cur_state
, enum ib_qp_state new_state
)
890 struct mlx4_ib_dev
*dev
= to_mdev(ibqp
->device
);
891 struct mlx4_ib_qp
*qp
= to_mqp(ibqp
);
892 struct mlx4_qp_context
*context
;
893 enum mlx4_qp_optpar optpar
= 0;
897 context
= kzalloc(sizeof *context
, GFP_KERNEL
);
901 context
->flags
= cpu_to_be32((to_mlx4_state(new_state
) << 28) |
902 (to_mlx4_st(ibqp
->qp_type
) << 16));
904 if (!(attr_mask
& IB_QP_PATH_MIG_STATE
))
905 context
->flags
|= cpu_to_be32(MLX4_QP_PM_MIGRATED
<< 11);
907 optpar
|= MLX4_QP_OPTPAR_PM_STATE
;
908 switch (attr
->path_mig_state
) {
909 case IB_MIG_MIGRATED
:
910 context
->flags
|= cpu_to_be32(MLX4_QP_PM_MIGRATED
<< 11);
913 context
->flags
|= cpu_to_be32(MLX4_QP_PM_REARM
<< 11);
916 context
->flags
|= cpu_to_be32(MLX4_QP_PM_ARMED
<< 11);
921 if (ibqp
->qp_type
== IB_QPT_GSI
|| ibqp
->qp_type
== IB_QPT_SMI
)
922 context
->mtu_msgmax
= (IB_MTU_4096
<< 5) | 11;
923 else if (ibqp
->qp_type
== IB_QPT_UD
) {
924 if (qp
->flags
& MLX4_IB_QP_LSO
)
925 context
->mtu_msgmax
= (IB_MTU_4096
<< 5) |
926 ilog2(dev
->dev
->caps
.max_gso_sz
);
928 context
->mtu_msgmax
= (IB_MTU_4096
<< 5) | 12;
929 } else if (attr_mask
& IB_QP_PATH_MTU
) {
930 if (attr
->path_mtu
< IB_MTU_256
|| attr
->path_mtu
> IB_MTU_4096
) {
931 printk(KERN_ERR
"path MTU (%u) is invalid\n",
935 context
->mtu_msgmax
= (attr
->path_mtu
<< 5) |
936 ilog2(dev
->dev
->caps
.max_msg_sz
);
940 context
->rq_size_stride
= ilog2(qp
->rq
.wqe_cnt
) << 3;
941 context
->rq_size_stride
|= qp
->rq
.wqe_shift
- 4;
944 context
->sq_size_stride
= ilog2(qp
->sq
.wqe_cnt
) << 3;
945 context
->sq_size_stride
|= qp
->sq
.wqe_shift
- 4;
947 if (cur_state
== IB_QPS_RESET
&& new_state
== IB_QPS_INIT
)
948 context
->sq_size_stride
|= !!qp
->sq_no_prefetch
<< 7;
950 if (qp
->ibqp
.uobject
)
951 context
->usr_page
= cpu_to_be32(to_mucontext(ibqp
->uobject
->context
)->uar
.index
);
953 context
->usr_page
= cpu_to_be32(dev
->priv_uar
.index
);
955 if (attr_mask
& IB_QP_DEST_QPN
)
956 context
->remote_qpn
= cpu_to_be32(attr
->dest_qp_num
);
958 if (attr_mask
& IB_QP_PORT
) {
959 if (cur_state
== IB_QPS_SQD
&& new_state
== IB_QPS_SQD
&&
960 !(attr_mask
& IB_QP_AV
)) {
961 mlx4_set_sched(&context
->pri_path
, attr
->port_num
);
962 optpar
|= MLX4_QP_OPTPAR_SCHED_QUEUE
;
966 if (attr_mask
& IB_QP_PKEY_INDEX
) {
967 context
->pri_path
.pkey_index
= attr
->pkey_index
;
968 optpar
|= MLX4_QP_OPTPAR_PKEY_INDEX
;
971 if (attr_mask
& IB_QP_AV
) {
972 if (mlx4_set_path(dev
, &attr
->ah_attr
, &context
->pri_path
,
973 attr_mask
& IB_QP_PORT
? attr
->port_num
: qp
->port
))
976 optpar
|= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH
|
977 MLX4_QP_OPTPAR_SCHED_QUEUE
);
980 if (attr_mask
& IB_QP_TIMEOUT
) {
981 context
->pri_path
.ackto
= attr
->timeout
<< 3;
982 optpar
|= MLX4_QP_OPTPAR_ACK_TIMEOUT
;
985 if (attr_mask
& IB_QP_ALT_PATH
) {
986 if (attr
->alt_port_num
== 0 ||
987 attr
->alt_port_num
> dev
->dev
->caps
.num_ports
)
990 if (attr
->alt_pkey_index
>=
991 dev
->dev
->caps
.pkey_table_len
[attr
->alt_port_num
])
994 if (mlx4_set_path(dev
, &attr
->alt_ah_attr
, &context
->alt_path
,
998 context
->alt_path
.pkey_index
= attr
->alt_pkey_index
;
999 context
->alt_path
.ackto
= attr
->alt_timeout
<< 3;
1000 optpar
|= MLX4_QP_OPTPAR_ALT_ADDR_PATH
;
1003 context
->pd
= cpu_to_be32(to_mpd(ibqp
->pd
)->pdn
);
1004 context
->params1
= cpu_to_be32(MLX4_IB_ACK_REQ_FREQ
<< 28);
1006 /* Set "fast registration enabled" for all kernel QPs */
1007 if (!qp
->ibqp
.uobject
)
1008 context
->params1
|= cpu_to_be32(1 << 11);
1010 if (attr_mask
& IB_QP_RNR_RETRY
) {
1011 context
->params1
|= cpu_to_be32(attr
->rnr_retry
<< 13);
1012 optpar
|= MLX4_QP_OPTPAR_RNR_RETRY
;
1015 if (attr_mask
& IB_QP_RETRY_CNT
) {
1016 context
->params1
|= cpu_to_be32(attr
->retry_cnt
<< 16);
1017 optpar
|= MLX4_QP_OPTPAR_RETRY_COUNT
;
1020 if (attr_mask
& IB_QP_MAX_QP_RD_ATOMIC
) {
1021 if (attr
->max_rd_atomic
)
1023 cpu_to_be32(fls(attr
->max_rd_atomic
- 1) << 21);
1024 optpar
|= MLX4_QP_OPTPAR_SRA_MAX
;
1027 if (attr_mask
& IB_QP_SQ_PSN
)
1028 context
->next_send_psn
= cpu_to_be32(attr
->sq_psn
);
1030 context
->cqn_send
= cpu_to_be32(to_mcq(ibqp
->send_cq
)->mcq
.cqn
);
1032 if (attr_mask
& IB_QP_MAX_DEST_RD_ATOMIC
) {
1033 if (attr
->max_dest_rd_atomic
)
1035 cpu_to_be32(fls(attr
->max_dest_rd_atomic
- 1) << 21);
1036 optpar
|= MLX4_QP_OPTPAR_RRA_MAX
;
1039 if (attr_mask
& (IB_QP_ACCESS_FLAGS
| IB_QP_MAX_DEST_RD_ATOMIC
)) {
1040 context
->params2
|= to_mlx4_access_flags(qp
, attr
, attr_mask
);
1041 optpar
|= MLX4_QP_OPTPAR_RWE
| MLX4_QP_OPTPAR_RRE
| MLX4_QP_OPTPAR_RAE
;
1045 context
->params2
|= cpu_to_be32(MLX4_QP_BIT_RIC
);
1047 if (attr_mask
& IB_QP_MIN_RNR_TIMER
) {
1048 context
->rnr_nextrecvpsn
|= cpu_to_be32(attr
->min_rnr_timer
<< 24);
1049 optpar
|= MLX4_QP_OPTPAR_RNR_TIMEOUT
;
1051 if (attr_mask
& IB_QP_RQ_PSN
)
1052 context
->rnr_nextrecvpsn
|= cpu_to_be32(attr
->rq_psn
);
1054 context
->cqn_recv
= cpu_to_be32(to_mcq(ibqp
->recv_cq
)->mcq
.cqn
);
1056 if (attr_mask
& IB_QP_QKEY
) {
1057 context
->qkey
= cpu_to_be32(attr
->qkey
);
1058 optpar
|= MLX4_QP_OPTPAR_Q_KEY
;
1062 context
->srqn
= cpu_to_be32(1 << 24 | to_msrq(ibqp
->srq
)->msrq
.srqn
);
1064 if (!ibqp
->srq
&& cur_state
== IB_QPS_RESET
&& new_state
== IB_QPS_INIT
)
1065 context
->db_rec_addr
= cpu_to_be64(qp
->db
.dma
);
1067 if (cur_state
== IB_QPS_INIT
&&
1068 new_state
== IB_QPS_RTR
&&
1069 (ibqp
->qp_type
== IB_QPT_GSI
|| ibqp
->qp_type
== IB_QPT_SMI
||
1070 ibqp
->qp_type
== IB_QPT_UD
)) {
1071 context
->pri_path
.sched_queue
= (qp
->port
- 1) << 6;
1072 if (is_qp0(dev
, qp
))
1073 context
->pri_path
.sched_queue
|= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE
;
1075 context
->pri_path
.sched_queue
|= MLX4_IB_DEFAULT_SCHED_QUEUE
;
1078 if (cur_state
== IB_QPS_RTS
&& new_state
== IB_QPS_SQD
&&
1079 attr_mask
& IB_QP_EN_SQD_ASYNC_NOTIFY
&& attr
->en_sqd_async_notify
)
1084 if (!ibqp
->uobject
&& cur_state
== IB_QPS_RESET
&& new_state
== IB_QPS_INIT
)
1085 context
->rlkey
|= (1 << 4);
1088 * Before passing a kernel QP to the HW, make sure that the
1089 * ownership bits of the send queue are set and the SQ
1090 * headroom is stamped so that the hardware doesn't start
1091 * processing stale work requests.
1093 if (!ibqp
->uobject
&& cur_state
== IB_QPS_RESET
&& new_state
== IB_QPS_INIT
) {
1094 struct mlx4_wqe_ctrl_seg
*ctrl
;
1097 for (i
= 0; i
< qp
->sq
.wqe_cnt
; ++i
) {
1098 ctrl
= get_send_wqe(qp
, i
);
1099 ctrl
->owner_opcode
= cpu_to_be32(1 << 31);
1100 if (qp
->sq_max_wqes_per_wr
== 1)
1101 ctrl
->fence_size
= 1 << (qp
->sq
.wqe_shift
- 4);
1103 stamp_send_wqe(qp
, i
, 1 << qp
->sq
.wqe_shift
);
1107 err
= mlx4_qp_modify(dev
->dev
, &qp
->mtt
, to_mlx4_state(cur_state
),
1108 to_mlx4_state(new_state
), context
, optpar
,
1109 sqd_event
, &qp
->mqp
);
1113 qp
->state
= new_state
;
1115 if (attr_mask
& IB_QP_ACCESS_FLAGS
)
1116 qp
->atomic_rd_en
= attr
->qp_access_flags
;
1117 if (attr_mask
& IB_QP_MAX_DEST_RD_ATOMIC
)
1118 qp
->resp_depth
= attr
->max_dest_rd_atomic
;
1119 if (attr_mask
& IB_QP_PORT
)
1120 qp
->port
= attr
->port_num
;
1121 if (attr_mask
& IB_QP_ALT_PATH
)
1122 qp
->alt_port
= attr
->alt_port_num
;
1124 if (is_sqp(dev
, qp
))
1125 store_sqp_attrs(to_msqp(qp
), attr
, attr_mask
);
1128 * If we moved QP0 to RTR, bring the IB link up; if we moved
1129 * QP0 to RESET or ERROR, bring the link back down.
1131 if (is_qp0(dev
, qp
)) {
1132 if (cur_state
!= IB_QPS_RTR
&& new_state
== IB_QPS_RTR
)
1133 if (mlx4_INIT_PORT(dev
->dev
, qp
->port
))
1134 printk(KERN_WARNING
"INIT_PORT failed for port %d\n",
1137 if (cur_state
!= IB_QPS_RESET
&& cur_state
!= IB_QPS_ERR
&&
1138 (new_state
== IB_QPS_RESET
|| new_state
== IB_QPS_ERR
))
1139 mlx4_CLOSE_PORT(dev
->dev
, qp
->port
);
1143 * If we moved a kernel QP to RESET, clean up all old CQ
1144 * entries and reinitialize the QP.
1146 if (new_state
== IB_QPS_RESET
&& !ibqp
->uobject
) {
1147 mlx4_ib_cq_clean(to_mcq(ibqp
->recv_cq
), qp
->mqp
.qpn
,
1148 ibqp
->srq
? to_msrq(ibqp
->srq
): NULL
);
1149 if (ibqp
->send_cq
!= ibqp
->recv_cq
)
1150 mlx4_ib_cq_clean(to_mcq(ibqp
->send_cq
), qp
->mqp
.qpn
, NULL
);
1156 qp
->sq_next_wqe
= 0;
1166 int mlx4_ib_modify_qp(struct ib_qp
*ibqp
, struct ib_qp_attr
*attr
,
1167 int attr_mask
, struct ib_udata
*udata
)
1169 struct mlx4_ib_dev
*dev
= to_mdev(ibqp
->device
);
1170 struct mlx4_ib_qp
*qp
= to_mqp(ibqp
);
1171 enum ib_qp_state cur_state
, new_state
;
1174 mutex_lock(&qp
->mutex
);
1176 cur_state
= attr_mask
& IB_QP_CUR_STATE
? attr
->cur_qp_state
: qp
->state
;
1177 new_state
= attr_mask
& IB_QP_STATE
? attr
->qp_state
: cur_state
;
1179 if (!ib_modify_qp_is_ok(cur_state
, new_state
, ibqp
->qp_type
, attr_mask
))
1182 if ((attr_mask
& IB_QP_PORT
) &&
1183 (attr
->port_num
== 0 || attr
->port_num
> dev
->dev
->caps
.num_ports
)) {
1187 if (attr_mask
& IB_QP_PKEY_INDEX
) {
1188 int p
= attr_mask
& IB_QP_PORT
? attr
->port_num
: qp
->port
;
1189 if (attr
->pkey_index
>= dev
->dev
->caps
.pkey_table_len
[p
])
1193 if (attr_mask
& IB_QP_MAX_QP_RD_ATOMIC
&&
1194 attr
->max_rd_atomic
> dev
->dev
->caps
.max_qp_init_rdma
) {
1198 if (attr_mask
& IB_QP_MAX_DEST_RD_ATOMIC
&&
1199 attr
->max_dest_rd_atomic
> dev
->dev
->caps
.max_qp_dest_rdma
) {
1203 if (cur_state
== new_state
&& cur_state
== IB_QPS_RESET
) {
1208 err
= __mlx4_ib_modify_qp(ibqp
, attr
, attr_mask
, cur_state
, new_state
);
1211 mutex_unlock(&qp
->mutex
);
1215 static int build_mlx_header(struct mlx4_ib_sqp
*sqp
, struct ib_send_wr
*wr
,
1216 void *wqe
, unsigned *mlx_seg_len
)
1218 struct ib_device
*ib_dev
= sqp
->qp
.ibqp
.device
;
1219 struct mlx4_wqe_mlx_seg
*mlx
= wqe
;
1220 struct mlx4_wqe_inline_seg
*inl
= wqe
+ sizeof *mlx
;
1221 struct mlx4_ib_ah
*ah
= to_mah(wr
->wr
.ud
.ah
);
1229 for (i
= 0; i
< wr
->num_sge
; ++i
)
1230 send_size
+= wr
->sg_list
[i
].length
;
1232 ib_ud_header_init(send_size
, mlx4_ib_ah_grh_present(ah
), 0, &sqp
->ud_header
);
1234 sqp
->ud_header
.lrh
.service_level
=
1235 be32_to_cpu(ah
->av
.sl_tclass_flowlabel
) >> 28;
1236 sqp
->ud_header
.lrh
.destination_lid
= ah
->av
.dlid
;
1237 sqp
->ud_header
.lrh
.source_lid
= cpu_to_be16(ah
->av
.g_slid
& 0x7f);
1238 if (mlx4_ib_ah_grh_present(ah
)) {
1239 sqp
->ud_header
.grh
.traffic_class
=
1240 (be32_to_cpu(ah
->av
.sl_tclass_flowlabel
) >> 20) & 0xff;
1241 sqp
->ud_header
.grh
.flow_label
=
1242 ah
->av
.sl_tclass_flowlabel
& cpu_to_be32(0xfffff);
1243 sqp
->ud_header
.grh
.hop_limit
= ah
->av
.hop_limit
;
1244 ib_get_cached_gid(ib_dev
, be32_to_cpu(ah
->av
.port_pd
) >> 24,
1245 ah
->av
.gid_index
, &sqp
->ud_header
.grh
.source_gid
);
1246 memcpy(sqp
->ud_header
.grh
.destination_gid
.raw
,
1250 mlx
->flags
&= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE
);
1251 mlx
->flags
|= cpu_to_be32((!sqp
->qp
.ibqp
.qp_num
? MLX4_WQE_MLX_VL15
: 0) |
1252 (sqp
->ud_header
.lrh
.destination_lid
==
1253 IB_LID_PERMISSIVE
? MLX4_WQE_MLX_SLR
: 0) |
1254 (sqp
->ud_header
.lrh
.service_level
<< 8));
1255 mlx
->rlid
= sqp
->ud_header
.lrh
.destination_lid
;
1257 switch (wr
->opcode
) {
1259 sqp
->ud_header
.bth
.opcode
= IB_OPCODE_UD_SEND_ONLY
;
1260 sqp
->ud_header
.immediate_present
= 0;
1262 case IB_WR_SEND_WITH_IMM
:
1263 sqp
->ud_header
.bth
.opcode
= IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE
;
1264 sqp
->ud_header
.immediate_present
= 1;
1265 sqp
->ud_header
.immediate_data
= wr
->ex
.imm_data
;
1271 sqp
->ud_header
.lrh
.virtual_lane
= !sqp
->qp
.ibqp
.qp_num
? 15 : 0;
1272 if (sqp
->ud_header
.lrh
.destination_lid
== IB_LID_PERMISSIVE
)
1273 sqp
->ud_header
.lrh
.source_lid
= IB_LID_PERMISSIVE
;
1274 sqp
->ud_header
.bth
.solicited_event
= !!(wr
->send_flags
& IB_SEND_SOLICITED
);
1275 if (!sqp
->qp
.ibqp
.qp_num
)
1276 ib_get_cached_pkey(ib_dev
, sqp
->qp
.port
, sqp
->pkey_index
, &pkey
);
1278 ib_get_cached_pkey(ib_dev
, sqp
->qp
.port
, wr
->wr
.ud
.pkey_index
, &pkey
);
1279 sqp
->ud_header
.bth
.pkey
= cpu_to_be16(pkey
);
1280 sqp
->ud_header
.bth
.destination_qpn
= cpu_to_be32(wr
->wr
.ud
.remote_qpn
);
1281 sqp
->ud_header
.bth
.psn
= cpu_to_be32((sqp
->send_psn
++) & ((1 << 24) - 1));
1282 sqp
->ud_header
.deth
.qkey
= cpu_to_be32(wr
->wr
.ud
.remote_qkey
& 0x80000000 ?
1283 sqp
->qkey
: wr
->wr
.ud
.remote_qkey
);
1284 sqp
->ud_header
.deth
.source_qpn
= cpu_to_be32(sqp
->qp
.ibqp
.qp_num
);
1286 header_size
= ib_ud_header_pack(&sqp
->ud_header
, sqp
->header_buf
);
1289 printk(KERN_ERR
"built UD header of size %d:\n", header_size
);
1290 for (i
= 0; i
< header_size
/ 4; ++i
) {
1292 printk(" [%02x] ", i
* 4);
1294 be32_to_cpu(((__be32
*) sqp
->header_buf
)[i
]));
1295 if ((i
+ 1) % 8 == 0)
1302 * Inline data segments may not cross a 64 byte boundary. If
1303 * our UD header is bigger than the space available up to the
1304 * next 64 byte boundary in the WQE, use two inline data
1305 * segments to hold the UD header.
1307 spc
= MLX4_INLINE_ALIGN
-
1308 ((unsigned long) (inl
+ 1) & (MLX4_INLINE_ALIGN
- 1));
1309 if (header_size
<= spc
) {
1310 inl
->byte_count
= cpu_to_be32(1 << 31 | header_size
);
1311 memcpy(inl
+ 1, sqp
->header_buf
, header_size
);
1314 inl
->byte_count
= cpu_to_be32(1 << 31 | spc
);
1315 memcpy(inl
+ 1, sqp
->header_buf
, spc
);
1317 inl
= (void *) (inl
+ 1) + spc
;
1318 memcpy(inl
+ 1, sqp
->header_buf
+ spc
, header_size
- spc
);
1320 * Need a barrier here to make sure all the data is
1321 * visible before the byte_count field is set.
1322 * Otherwise the HCA prefetcher could grab the 64-byte
1323 * chunk with this inline segment and get a valid (!=
1324 * 0xffffffff) byte count but stale data, and end up
1325 * generating a packet with bad headers.
1327 * The first inline segment's byte_count field doesn't
1328 * need a barrier, because it comes after a
1329 * control/MLX segment and therefore is at an offset
1333 inl
->byte_count
= cpu_to_be32(1 << 31 | (header_size
- spc
));
1338 ALIGN(i
* sizeof (struct mlx4_wqe_inline_seg
) + header_size
, 16);
1342 static int mlx4_wq_overflow(struct mlx4_ib_wq
*wq
, int nreq
, struct ib_cq
*ib_cq
)
1345 struct mlx4_ib_cq
*cq
;
1347 cur
= wq
->head
- wq
->tail
;
1348 if (likely(cur
+ nreq
< wq
->max_post
))
1352 spin_lock(&cq
->lock
);
1353 cur
= wq
->head
- wq
->tail
;
1354 spin_unlock(&cq
->lock
);
1356 return cur
+ nreq
>= wq
->max_post
;
1359 static __be32
convert_access(int acc
)
1361 return (acc
& IB_ACCESS_REMOTE_ATOMIC
? cpu_to_be32(MLX4_WQE_FMR_PERM_ATOMIC
) : 0) |
1362 (acc
& IB_ACCESS_REMOTE_WRITE
? cpu_to_be32(MLX4_WQE_FMR_PERM_REMOTE_WRITE
) : 0) |
1363 (acc
& IB_ACCESS_REMOTE_READ
? cpu_to_be32(MLX4_WQE_FMR_PERM_REMOTE_READ
) : 0) |
1364 (acc
& IB_ACCESS_LOCAL_WRITE
? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE
) : 0) |
1365 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ
);
1368 static void set_fmr_seg(struct mlx4_wqe_fmr_seg
*fseg
, struct ib_send_wr
*wr
)
1370 struct mlx4_ib_fast_reg_page_list
*mfrpl
= to_mfrpl(wr
->wr
.fast_reg
.page_list
);
1373 for (i
= 0; i
< wr
->wr
.fast_reg
.page_list_len
; ++i
)
1374 mfrpl
->mapped_page_list
[i
] =
1375 cpu_to_be64(wr
->wr
.fast_reg
.page_list
->page_list
[i
] |
1376 MLX4_MTT_FLAG_PRESENT
);
1378 fseg
->flags
= convert_access(wr
->wr
.fast_reg
.access_flags
);
1379 fseg
->mem_key
= cpu_to_be32(wr
->wr
.fast_reg
.rkey
);
1380 fseg
->buf_list
= cpu_to_be64(mfrpl
->map
);
1381 fseg
->start_addr
= cpu_to_be64(wr
->wr
.fast_reg
.iova_start
);
1382 fseg
->reg_len
= cpu_to_be64(wr
->wr
.fast_reg
.length
);
1383 fseg
->offset
= 0; /* XXX -- is this just for ZBVA? */
1384 fseg
->page_size
= cpu_to_be32(wr
->wr
.fast_reg
.page_shift
);
1385 fseg
->reserved
[0] = 0;
1386 fseg
->reserved
[1] = 0;
1389 static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg
*iseg
, u32 rkey
)
1392 iseg
->mem_key
= cpu_to_be32(rkey
);
1397 static __always_inline
void set_raddr_seg(struct mlx4_wqe_raddr_seg
*rseg
,
1398 u64 remote_addr
, u32 rkey
)
1400 rseg
->raddr
= cpu_to_be64(remote_addr
);
1401 rseg
->rkey
= cpu_to_be32(rkey
);
1405 static void set_atomic_seg(struct mlx4_wqe_atomic_seg
*aseg
, struct ib_send_wr
*wr
)
1407 if (wr
->opcode
== IB_WR_ATOMIC_CMP_AND_SWP
) {
1408 aseg
->swap_add
= cpu_to_be64(wr
->wr
.atomic
.swap
);
1409 aseg
->compare
= cpu_to_be64(wr
->wr
.atomic
.compare_add
);
1411 aseg
->swap_add
= cpu_to_be64(wr
->wr
.atomic
.compare_add
);
1417 static void set_datagram_seg(struct mlx4_wqe_datagram_seg
*dseg
,
1418 struct ib_send_wr
*wr
)
1420 memcpy(dseg
->av
, &to_mah(wr
->wr
.ud
.ah
)->av
, sizeof (struct mlx4_av
));
1421 dseg
->dqpn
= cpu_to_be32(wr
->wr
.ud
.remote_qpn
);
1422 dseg
->qkey
= cpu_to_be32(wr
->wr
.ud
.remote_qkey
);
1425 static void set_mlx_icrc_seg(void *dseg
)
1428 struct mlx4_wqe_inline_seg
*iseg
= dseg
;
1433 * Need a barrier here before writing the byte_count field to
1434 * make sure that all the data is visible before the
1435 * byte_count field is set. Otherwise, if the segment begins
1436 * a new cacheline, the HCA prefetcher could grab the 64-byte
1437 * chunk and get a valid (!= * 0xffffffff) byte count but
1438 * stale data, and end up sending the wrong data.
1442 iseg
->byte_count
= cpu_to_be32((1 << 31) | 4);
1445 static void set_data_seg(struct mlx4_wqe_data_seg
*dseg
, struct ib_sge
*sg
)
1447 dseg
->lkey
= cpu_to_be32(sg
->lkey
);
1448 dseg
->addr
= cpu_to_be64(sg
->addr
);
1451 * Need a barrier here before writing the byte_count field to
1452 * make sure that all the data is visible before the
1453 * byte_count field is set. Otherwise, if the segment begins
1454 * a new cacheline, the HCA prefetcher could grab the 64-byte
1455 * chunk and get a valid (!= * 0xffffffff) byte count but
1456 * stale data, and end up sending the wrong data.
1460 dseg
->byte_count
= cpu_to_be32(sg
->length
);
1463 static void __set_data_seg(struct mlx4_wqe_data_seg
*dseg
, struct ib_sge
*sg
)
1465 dseg
->byte_count
= cpu_to_be32(sg
->length
);
1466 dseg
->lkey
= cpu_to_be32(sg
->lkey
);
1467 dseg
->addr
= cpu_to_be64(sg
->addr
);
1470 static int build_lso_seg(struct mlx4_wqe_lso_seg
*wqe
, struct ib_send_wr
*wr
,
1471 struct mlx4_ib_qp
*qp
, unsigned *lso_seg_len
,
1472 __be32
*lso_hdr_sz
, __be32
*blh
)
1474 unsigned halign
= ALIGN(sizeof *wqe
+ wr
->wr
.ud
.hlen
, 16);
1476 if (unlikely(halign
> MLX4_IB_CACHE_LINE_SIZE
))
1477 *blh
= cpu_to_be32(1 << 6);
1479 if (unlikely(!(qp
->flags
& MLX4_IB_QP_LSO
) &&
1480 wr
->num_sge
> qp
->sq
.max_gs
- (halign
>> 4)))
1483 memcpy(wqe
->header
, wr
->wr
.ud
.header
, wr
->wr
.ud
.hlen
);
1485 *lso_hdr_sz
= cpu_to_be32((wr
->wr
.ud
.mss
- wr
->wr
.ud
.hlen
) << 16 |
1487 *lso_seg_len
= halign
;
1491 static __be32
send_ieth(struct ib_send_wr
*wr
)
1493 switch (wr
->opcode
) {
1494 case IB_WR_SEND_WITH_IMM
:
1495 case IB_WR_RDMA_WRITE_WITH_IMM
:
1496 return wr
->ex
.imm_data
;
1498 case IB_WR_SEND_WITH_INV
:
1499 return cpu_to_be32(wr
->ex
.invalidate_rkey
);
1506 int mlx4_ib_post_send(struct ib_qp
*ibqp
, struct ib_send_wr
*wr
,
1507 struct ib_send_wr
**bad_wr
)
1509 struct mlx4_ib_qp
*qp
= to_mqp(ibqp
);
1511 struct mlx4_wqe_ctrl_seg
*ctrl
;
1512 struct mlx4_wqe_data_seg
*dseg
;
1513 unsigned long flags
;
1517 int uninitialized_var(stamp
);
1518 int uninitialized_var(size
);
1519 unsigned uninitialized_var(seglen
);
1522 __be32
uninitialized_var(lso_hdr_sz
);
1526 spin_lock_irqsave(&qp
->sq
.lock
, flags
);
1528 ind
= qp
->sq_next_wqe
;
1530 for (nreq
= 0; wr
; ++nreq
, wr
= wr
->next
) {
1534 if (mlx4_wq_overflow(&qp
->sq
, nreq
, qp
->ibqp
.send_cq
)) {
1540 if (unlikely(wr
->num_sge
> qp
->sq
.max_gs
)) {
1546 ctrl
= wqe
= get_send_wqe(qp
, ind
& (qp
->sq
.wqe_cnt
- 1));
1547 qp
->sq
.wrid
[(qp
->sq
.head
+ nreq
) & (qp
->sq
.wqe_cnt
- 1)] = wr
->wr_id
;
1550 (wr
->send_flags
& IB_SEND_SIGNALED
?
1551 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE
) : 0) |
1552 (wr
->send_flags
& IB_SEND_SOLICITED
?
1553 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED
) : 0) |
1554 ((wr
->send_flags
& IB_SEND_IP_CSUM
) ?
1555 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM
|
1556 MLX4_WQE_CTRL_TCP_UDP_CSUM
) : 0) |
1559 ctrl
->imm
= send_ieth(wr
);
1561 wqe
+= sizeof *ctrl
;
1562 size
= sizeof *ctrl
/ 16;
1564 switch (ibqp
->qp_type
) {
1567 switch (wr
->opcode
) {
1568 case IB_WR_ATOMIC_CMP_AND_SWP
:
1569 case IB_WR_ATOMIC_FETCH_AND_ADD
:
1570 set_raddr_seg(wqe
, wr
->wr
.atomic
.remote_addr
,
1571 wr
->wr
.atomic
.rkey
);
1572 wqe
+= sizeof (struct mlx4_wqe_raddr_seg
);
1574 set_atomic_seg(wqe
, wr
);
1575 wqe
+= sizeof (struct mlx4_wqe_atomic_seg
);
1577 size
+= (sizeof (struct mlx4_wqe_raddr_seg
) +
1578 sizeof (struct mlx4_wqe_atomic_seg
)) / 16;
1582 case IB_WR_RDMA_READ
:
1583 case IB_WR_RDMA_WRITE
:
1584 case IB_WR_RDMA_WRITE_WITH_IMM
:
1585 set_raddr_seg(wqe
, wr
->wr
.rdma
.remote_addr
,
1587 wqe
+= sizeof (struct mlx4_wqe_raddr_seg
);
1588 size
+= sizeof (struct mlx4_wqe_raddr_seg
) / 16;
1591 case IB_WR_LOCAL_INV
:
1592 ctrl
->srcrb_flags
|=
1593 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER
);
1594 set_local_inv_seg(wqe
, wr
->ex
.invalidate_rkey
);
1595 wqe
+= sizeof (struct mlx4_wqe_local_inval_seg
);
1596 size
+= sizeof (struct mlx4_wqe_local_inval_seg
) / 16;
1599 case IB_WR_FAST_REG_MR
:
1600 ctrl
->srcrb_flags
|=
1601 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER
);
1602 set_fmr_seg(wqe
, wr
);
1603 wqe
+= sizeof (struct mlx4_wqe_fmr_seg
);
1604 size
+= sizeof (struct mlx4_wqe_fmr_seg
) / 16;
1608 /* No extra segments required for sends */
1614 set_datagram_seg(wqe
, wr
);
1615 wqe
+= sizeof (struct mlx4_wqe_datagram_seg
);
1616 size
+= sizeof (struct mlx4_wqe_datagram_seg
) / 16;
1618 if (wr
->opcode
== IB_WR_LSO
) {
1619 err
= build_lso_seg(wqe
, wr
, qp
, &seglen
, &lso_hdr_sz
, &blh
);
1620 if (unlikely(err
)) {
1624 lso_wqe
= (__be32
*) wqe
;
1626 size
+= seglen
/ 16;
1632 err
= build_mlx_header(to_msqp(qp
), wr
, ctrl
, &seglen
);
1633 if (unlikely(err
)) {
1638 size
+= seglen
/ 16;
1646 * Write data segments in reverse order, so as to
1647 * overwrite cacheline stamp last within each
1648 * cacheline. This avoids issues with WQE
1653 dseg
+= wr
->num_sge
- 1;
1654 size
+= wr
->num_sge
* (sizeof (struct mlx4_wqe_data_seg
) / 16);
1656 /* Add one more inline data segment for ICRC for MLX sends */
1657 if (unlikely(qp
->ibqp
.qp_type
== IB_QPT_SMI
||
1658 qp
->ibqp
.qp_type
== IB_QPT_GSI
)) {
1659 set_mlx_icrc_seg(dseg
+ 1);
1660 size
+= sizeof (struct mlx4_wqe_data_seg
) / 16;
1663 for (i
= wr
->num_sge
- 1; i
>= 0; --i
, --dseg
)
1664 set_data_seg(dseg
, wr
->sg_list
+ i
);
1667 * Possibly overwrite stamping in cacheline with LSO
1668 * segment only after making sure all data segments
1672 *lso_wqe
= lso_hdr_sz
;
1674 ctrl
->fence_size
= (wr
->send_flags
& IB_SEND_FENCE
?
1675 MLX4_WQE_CTRL_FENCE
: 0) | size
;
1678 * Make sure descriptor is fully written before
1679 * setting ownership bit (because HW can start
1680 * executing as soon as we do).
1684 if (wr
->opcode
< 0 || wr
->opcode
>= ARRAY_SIZE(mlx4_ib_opcode
)) {
1689 ctrl
->owner_opcode
= mlx4_ib_opcode
[wr
->opcode
] |
1690 (ind
& qp
->sq
.wqe_cnt
? cpu_to_be32(1 << 31) : 0) | blh
;
1692 stamp
= ind
+ qp
->sq_spare_wqes
;
1693 ind
+= DIV_ROUND_UP(size
* 16, 1U << qp
->sq
.wqe_shift
);
1696 * We can improve latency by not stamping the last
1697 * send queue WQE until after ringing the doorbell, so
1698 * only stamp here if there are still more WQEs to post.
1700 * Same optimization applies to padding with NOP wqe
1701 * in case of WQE shrinking (used to prevent wrap-around
1702 * in the middle of WR).
1705 stamp_send_wqe(qp
, stamp
, size
* 16);
1706 ind
= pad_wraparound(qp
, ind
);
1712 qp
->sq
.head
+= nreq
;
1715 * Make sure that descriptors are written before
1720 writel(qp
->doorbell_qpn
,
1721 to_mdev(ibqp
->device
)->uar_map
+ MLX4_SEND_DOORBELL
);
1724 * Make sure doorbells don't leak out of SQ spinlock
1725 * and reach the HCA out of order.
1729 stamp_send_wqe(qp
, stamp
, size
* 16);
1731 ind
= pad_wraparound(qp
, ind
);
1732 qp
->sq_next_wqe
= ind
;
1735 spin_unlock_irqrestore(&qp
->sq
.lock
, flags
);
1740 int mlx4_ib_post_recv(struct ib_qp
*ibqp
, struct ib_recv_wr
*wr
,
1741 struct ib_recv_wr
**bad_wr
)
1743 struct mlx4_ib_qp
*qp
= to_mqp(ibqp
);
1744 struct mlx4_wqe_data_seg
*scat
;
1745 unsigned long flags
;
1751 spin_lock_irqsave(&qp
->rq
.lock
, flags
);
1753 ind
= qp
->rq
.head
& (qp
->rq
.wqe_cnt
- 1);
1755 for (nreq
= 0; wr
; ++nreq
, wr
= wr
->next
) {
1756 if (mlx4_wq_overflow(&qp
->rq
, nreq
, qp
->ibqp
.recv_cq
)) {
1762 if (unlikely(wr
->num_sge
> qp
->rq
.max_gs
)) {
1768 scat
= get_recv_wqe(qp
, ind
);
1770 for (i
= 0; i
< wr
->num_sge
; ++i
)
1771 __set_data_seg(scat
+ i
, wr
->sg_list
+ i
);
1773 if (i
< qp
->rq
.max_gs
) {
1774 scat
[i
].byte_count
= 0;
1775 scat
[i
].lkey
= cpu_to_be32(MLX4_INVALID_LKEY
);
1779 qp
->rq
.wrid
[ind
] = wr
->wr_id
;
1781 ind
= (ind
+ 1) & (qp
->rq
.wqe_cnt
- 1);
1786 qp
->rq
.head
+= nreq
;
1789 * Make sure that descriptors are written before
1794 *qp
->db
.db
= cpu_to_be32(qp
->rq
.head
& 0xffff);
1797 spin_unlock_irqrestore(&qp
->rq
.lock
, flags
);
1802 static inline enum ib_qp_state
to_ib_qp_state(enum mlx4_qp_state mlx4_state
)
1804 switch (mlx4_state
) {
1805 case MLX4_QP_STATE_RST
: return IB_QPS_RESET
;
1806 case MLX4_QP_STATE_INIT
: return IB_QPS_INIT
;
1807 case MLX4_QP_STATE_RTR
: return IB_QPS_RTR
;
1808 case MLX4_QP_STATE_RTS
: return IB_QPS_RTS
;
1809 case MLX4_QP_STATE_SQ_DRAINING
:
1810 case MLX4_QP_STATE_SQD
: return IB_QPS_SQD
;
1811 case MLX4_QP_STATE_SQER
: return IB_QPS_SQE
;
1812 case MLX4_QP_STATE_ERR
: return IB_QPS_ERR
;
1817 static inline enum ib_mig_state
to_ib_mig_state(int mlx4_mig_state
)
1819 switch (mlx4_mig_state
) {
1820 case MLX4_QP_PM_ARMED
: return IB_MIG_ARMED
;
1821 case MLX4_QP_PM_REARM
: return IB_MIG_REARM
;
1822 case MLX4_QP_PM_MIGRATED
: return IB_MIG_MIGRATED
;
1827 static int to_ib_qp_access_flags(int mlx4_flags
)
1831 if (mlx4_flags
& MLX4_QP_BIT_RRE
)
1832 ib_flags
|= IB_ACCESS_REMOTE_READ
;
1833 if (mlx4_flags
& MLX4_QP_BIT_RWE
)
1834 ib_flags
|= IB_ACCESS_REMOTE_WRITE
;
1835 if (mlx4_flags
& MLX4_QP_BIT_RAE
)
1836 ib_flags
|= IB_ACCESS_REMOTE_ATOMIC
;
1841 static void to_ib_ah_attr(struct mlx4_dev
*dev
, struct ib_ah_attr
*ib_ah_attr
,
1842 struct mlx4_qp_path
*path
)
1844 memset(ib_ah_attr
, 0, sizeof *ib_ah_attr
);
1845 ib_ah_attr
->port_num
= path
->sched_queue
& 0x40 ? 2 : 1;
1847 if (ib_ah_attr
->port_num
== 0 || ib_ah_attr
->port_num
> dev
->caps
.num_ports
)
1850 ib_ah_attr
->dlid
= be16_to_cpu(path
->rlid
);
1851 ib_ah_attr
->sl
= (path
->sched_queue
>> 2) & 0xf;
1852 ib_ah_attr
->src_path_bits
= path
->grh_mylmc
& 0x7f;
1853 ib_ah_attr
->static_rate
= path
->static_rate
? path
->static_rate
- 5 : 0;
1854 ib_ah_attr
->ah_flags
= (path
->grh_mylmc
& (1 << 7)) ? IB_AH_GRH
: 0;
1855 if (ib_ah_attr
->ah_flags
) {
1856 ib_ah_attr
->grh
.sgid_index
= path
->mgid_index
;
1857 ib_ah_attr
->grh
.hop_limit
= path
->hop_limit
;
1858 ib_ah_attr
->grh
.traffic_class
=
1859 (be32_to_cpu(path
->tclass_flowlabel
) >> 20) & 0xff;
1860 ib_ah_attr
->grh
.flow_label
=
1861 be32_to_cpu(path
->tclass_flowlabel
) & 0xfffff;
1862 memcpy(ib_ah_attr
->grh
.dgid
.raw
,
1863 path
->rgid
, sizeof ib_ah_attr
->grh
.dgid
.raw
);
1867 int mlx4_ib_query_qp(struct ib_qp
*ibqp
, struct ib_qp_attr
*qp_attr
, int qp_attr_mask
,
1868 struct ib_qp_init_attr
*qp_init_attr
)
1870 struct mlx4_ib_dev
*dev
= to_mdev(ibqp
->device
);
1871 struct mlx4_ib_qp
*qp
= to_mqp(ibqp
);
1872 struct mlx4_qp_context context
;
1876 mutex_lock(&qp
->mutex
);
1878 if (qp
->state
== IB_QPS_RESET
) {
1879 qp_attr
->qp_state
= IB_QPS_RESET
;
1883 err
= mlx4_qp_query(dev
->dev
, &qp
->mqp
, &context
);
1889 mlx4_state
= be32_to_cpu(context
.flags
) >> 28;
1891 qp
->state
= to_ib_qp_state(mlx4_state
);
1892 qp_attr
->qp_state
= qp
->state
;
1893 qp_attr
->path_mtu
= context
.mtu_msgmax
>> 5;
1894 qp_attr
->path_mig_state
=
1895 to_ib_mig_state((be32_to_cpu(context
.flags
) >> 11) & 0x3);
1896 qp_attr
->qkey
= be32_to_cpu(context
.qkey
);
1897 qp_attr
->rq_psn
= be32_to_cpu(context
.rnr_nextrecvpsn
) & 0xffffff;
1898 qp_attr
->sq_psn
= be32_to_cpu(context
.next_send_psn
) & 0xffffff;
1899 qp_attr
->dest_qp_num
= be32_to_cpu(context
.remote_qpn
) & 0xffffff;
1900 qp_attr
->qp_access_flags
=
1901 to_ib_qp_access_flags(be32_to_cpu(context
.params2
));
1903 if (qp
->ibqp
.qp_type
== IB_QPT_RC
|| qp
->ibqp
.qp_type
== IB_QPT_UC
) {
1904 to_ib_ah_attr(dev
->dev
, &qp_attr
->ah_attr
, &context
.pri_path
);
1905 to_ib_ah_attr(dev
->dev
, &qp_attr
->alt_ah_attr
, &context
.alt_path
);
1906 qp_attr
->alt_pkey_index
= context
.alt_path
.pkey_index
& 0x7f;
1907 qp_attr
->alt_port_num
= qp_attr
->alt_ah_attr
.port_num
;
1910 qp_attr
->pkey_index
= context
.pri_path
.pkey_index
& 0x7f;
1911 if (qp_attr
->qp_state
== IB_QPS_INIT
)
1912 qp_attr
->port_num
= qp
->port
;
1914 qp_attr
->port_num
= context
.pri_path
.sched_queue
& 0x40 ? 2 : 1;
1916 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
1917 qp_attr
->sq_draining
= mlx4_state
== MLX4_QP_STATE_SQ_DRAINING
;
1919 qp_attr
->max_rd_atomic
= 1 << ((be32_to_cpu(context
.params1
) >> 21) & 0x7);
1921 qp_attr
->max_dest_rd_atomic
=
1922 1 << ((be32_to_cpu(context
.params2
) >> 21) & 0x7);
1923 qp_attr
->min_rnr_timer
=
1924 (be32_to_cpu(context
.rnr_nextrecvpsn
) >> 24) & 0x1f;
1925 qp_attr
->timeout
= context
.pri_path
.ackto
>> 3;
1926 qp_attr
->retry_cnt
= (be32_to_cpu(context
.params1
) >> 16) & 0x7;
1927 qp_attr
->rnr_retry
= (be32_to_cpu(context
.params1
) >> 13) & 0x7;
1928 qp_attr
->alt_timeout
= context
.alt_path
.ackto
>> 3;
1931 qp_attr
->cur_qp_state
= qp_attr
->qp_state
;
1932 qp_attr
->cap
.max_recv_wr
= qp
->rq
.wqe_cnt
;
1933 qp_attr
->cap
.max_recv_sge
= qp
->rq
.max_gs
;
1935 if (!ibqp
->uobject
) {
1936 qp_attr
->cap
.max_send_wr
= qp
->sq
.wqe_cnt
;
1937 qp_attr
->cap
.max_send_sge
= qp
->sq
.max_gs
;
1939 qp_attr
->cap
.max_send_wr
= 0;
1940 qp_attr
->cap
.max_send_sge
= 0;
1944 * We don't support inline sends for kernel QPs (yet), and we
1945 * don't know what userspace's value should be.
1947 qp_attr
->cap
.max_inline_data
= 0;
1949 qp_init_attr
->cap
= qp_attr
->cap
;
1951 qp_init_attr
->create_flags
= 0;
1952 if (qp
->flags
& MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK
)
1953 qp_init_attr
->create_flags
|= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK
;
1955 if (qp
->flags
& MLX4_IB_QP_LSO
)
1956 qp_init_attr
->create_flags
|= IB_QP_CREATE_IPOIB_UD_LSO
;
1959 mutex_unlock(&qp
->mutex
);