]> git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blob - drivers/infiniband/hw/mlx5/main.c
projects / mirror_ubuntu-jammy-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
RDMA: Globally allocate and release QP memory
[mirror_ubuntu-jammy-kernel.git] / drivers / infiniband / hw / mlx5 / main.c
1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2 /*
3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved.
4 * Copyright (c) 2020, Intel Corporation. All rights reserved.
5 */
6
7 #include <linux/debugfs.h>
8 #include <linux/highmem.h>
9 #include <linux/module.h>
10 #include <linux/init.h>
11 #include <linux/errno.h>
12 #include <linux/pci.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/slab.h>
15 #include <linux/bitmap.h>
16 #include <linux/sched.h>
17 #include <linux/sched/mm.h>
18 #include <linux/sched/task.h>
19 #include <linux/delay.h>
20 #include <rdma/ib_user_verbs.h>
21 #include <rdma/ib_addr.h>
22 #include <rdma/ib_cache.h>
23 #include <linux/mlx5/port.h>
24 #include <linux/mlx5/vport.h>
25 #include <linux/mlx5/fs.h>
26 #include <linux/mlx5/eswitch.h>
27 #include <linux/list.h>
28 #include <rdma/ib_smi.h>
29 #include <rdma/ib_umem.h>
30 #include <rdma/lag.h>
31 #include <linux/in.h>
32 #include <linux/etherdevice.h>
33 #include "mlx5_ib.h"
34 #include "ib_rep.h"
35 #include "cmd.h"
36 #include "devx.h"
37 #include "dm.h"
38 #include "fs.h"
39 #include "srq.h"
40 #include "qp.h"
41 #include "wr.h"
42 #include "restrack.h"
43 #include "counters.h"
44 #include <linux/mlx5/accel.h>
45 #include <rdma/uverbs_std_types.h>
46 #include <rdma/uverbs_ioctl.h>
47 #include <rdma/mlx5_user_ioctl_verbs.h>
48 #include <rdma/mlx5_user_ioctl_cmds.h>
49 #include <rdma/ib_umem_odp.h>
50
51 #define UVERBS_MODULE_NAME mlx5_ib
52 #include <rdma/uverbs_named_ioctl.h>
53
54 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
55 MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) IB driver");
56 MODULE_LICENSE("Dual BSD/GPL");
57
58 struct mlx5_ib_event_work {
59 struct work_struct work;
60 union {
61 struct mlx5_ib_dev *dev;
62 struct mlx5_ib_multiport_info *mpi;
63 };
64 bool is_slave;
65 unsigned int event;
66 void *param;
67 };
68
69 enum {
70 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
71 };
72
73 static struct workqueue_struct *mlx5_ib_event_wq;
74 static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
75 static LIST_HEAD(mlx5_ib_dev_list);
76 /*
77 * This mutex should be held when accessing either of the above lists
78 */
79 static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
80
81 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
82 {
83 struct mlx5_ib_dev *dev;
84
85 mutex_lock(&mlx5_ib_multiport_mutex);
86 dev = mpi->ibdev;
87 mutex_unlock(&mlx5_ib_multiport_mutex);
88 return dev;
89 }
90
91 static enum rdma_link_layer
92 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
93 {
94 switch (port_type_cap) {
95 case MLX5_CAP_PORT_TYPE_IB:
96 return IB_LINK_LAYER_INFINIBAND;
97 case MLX5_CAP_PORT_TYPE_ETH:
98 return IB_LINK_LAYER_ETHERNET;
99 default:
100 return IB_LINK_LAYER_UNSPECIFIED;
101 }
102 }
103
104 static enum rdma_link_layer
105 mlx5_ib_port_link_layer(struct ib_device *device, u32 port_num)
106 {
107 struct mlx5_ib_dev *dev = to_mdev(device);
108 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
109
110 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
111 }
112
113 static int get_port_state(struct ib_device *ibdev,
114 u32 port_num,
115 enum ib_port_state *state)
116 {
117 struct ib_port_attr attr;
118 int ret;
119
120 memset(&attr, 0, sizeof(attr));
121 ret = ibdev->ops.query_port(ibdev, port_num, &attr);
122 if (!ret)
123 *state = attr.state;
124 return ret;
125 }
126
127 static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev,
128 struct net_device *ndev,
129 u32 *port_num)
130 {
131 struct net_device *rep_ndev;
132 struct mlx5_ib_port *port;
133 int i;
134
135 for (i = 0; i < dev->num_ports; i++) {
136 port = &dev->port[i];
137 if (!port->rep)
138 continue;
139
140 read_lock(&port->roce.netdev_lock);
141 rep_ndev = mlx5_ib_get_rep_netdev(port->rep->esw,
142 port->rep->vport);
143 if (rep_ndev == ndev) {
144 read_unlock(&port->roce.netdev_lock);
145 *port_num = i + 1;
146 return &port->roce;
147 }
148 read_unlock(&port->roce.netdev_lock);
149 }
150
151 return NULL;
152 }
153
154 static int mlx5_netdev_event(struct notifier_block *this,
155 unsigned long event, void *ptr)
156 {
157 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
158 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
159 u32 port_num = roce->native_port_num;
160 struct mlx5_core_dev *mdev;
161 struct mlx5_ib_dev *ibdev;
162
163 ibdev = roce->dev;
164 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
165 if (!mdev)
166 return NOTIFY_DONE;
167
168 switch (event) {
169 case NETDEV_REGISTER:
170 /* Should already be registered during the load */
171 if (ibdev->is_rep)
172 break;
173 write_lock(&roce->netdev_lock);
174 if (ndev->dev.parent == mdev->device)
175 roce->netdev = ndev;
176 write_unlock(&roce->netdev_lock);
177 break;
178
179 case NETDEV_UNREGISTER:
180 /* In case of reps, ib device goes away before the netdevs */
181 write_lock(&roce->netdev_lock);
182 if (roce->netdev == ndev)
183 roce->netdev = NULL;
184 write_unlock(&roce->netdev_lock);
185 break;
186
187 case NETDEV_CHANGE:
188 case NETDEV_UP:
189 case NETDEV_DOWN: {
190 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
191 struct net_device *upper = NULL;
192
193 if (lag_ndev) {
194 upper = netdev_master_upper_dev_get(lag_ndev);
195 dev_put(lag_ndev);
196 }
197
198 if (ibdev->is_rep)
199 roce = mlx5_get_rep_roce(ibdev, ndev, &port_num);
200 if (!roce)
201 return NOTIFY_DONE;
202 if ((upper == ndev || (!upper && ndev == roce->netdev))
203 && ibdev->ib_active) {
204 struct ib_event ibev = { };
205 enum ib_port_state port_state;
206
207 if (get_port_state(&ibdev->ib_dev, port_num,
208 &port_state))
209 goto done;
210
211 if (roce->last_port_state == port_state)
212 goto done;
213
214 roce->last_port_state = port_state;
215 ibev.device = &ibdev->ib_dev;
216 if (port_state == IB_PORT_DOWN)
217 ibev.event = IB_EVENT_PORT_ERR;
218 else if (port_state == IB_PORT_ACTIVE)
219 ibev.event = IB_EVENT_PORT_ACTIVE;
220 else
221 goto done;
222
223 ibev.element.port_num = port_num;
224 ib_dispatch_event(&ibev);
225 }
226 break;
227 }
228
229 default:
230 break;
231 }
232 done:
233 mlx5_ib_put_native_port_mdev(ibdev, port_num);
234 return NOTIFY_DONE;
235 }
236
237 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
238 u32 port_num)
239 {
240 struct mlx5_ib_dev *ibdev = to_mdev(device);
241 struct net_device *ndev;
242 struct mlx5_core_dev *mdev;
243
244 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
245 if (!mdev)
246 return NULL;
247
248 ndev = mlx5_lag_get_roce_netdev(mdev);
249 if (ndev)
250 goto out;
251
252 /* Ensure ndev does not disappear before we invoke dev_hold()
253 */
254 read_lock(&ibdev->port[port_num - 1].roce.netdev_lock);
255 ndev = ibdev->port[port_num - 1].roce.netdev;
256 if (ndev)
257 dev_hold(ndev);
258 read_unlock(&ibdev->port[port_num - 1].roce.netdev_lock);
259
260 out:
261 mlx5_ib_put_native_port_mdev(ibdev, port_num);
262 return ndev;
263 }
264
265 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
266 u32 ib_port_num,
267 u32 *native_port_num)
268 {
269 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
270 ib_port_num);
271 struct mlx5_core_dev *mdev = NULL;
272 struct mlx5_ib_multiport_info *mpi;
273 struct mlx5_ib_port *port;
274
275 if (!mlx5_core_mp_enabled(ibdev->mdev) ||
276 ll != IB_LINK_LAYER_ETHERNET) {
277 if (native_port_num)
278 *native_port_num = ib_port_num;
279 return ibdev->mdev;
280 }
281
282 if (native_port_num)
283 *native_port_num = 1;
284
285 port = &ibdev->port[ib_port_num - 1];
286 spin_lock(&port->mp.mpi_lock);
287 mpi = ibdev->port[ib_port_num - 1].mp.mpi;
288 if (mpi && !mpi->unaffiliate) {
289 mdev = mpi->mdev;
290 /* If it's the master no need to refcount, it'll exist
291 * as long as the ib_dev exists.
292 */
293 if (!mpi->is_master)
294 mpi->mdev_refcnt++;
295 }
296 spin_unlock(&port->mp.mpi_lock);
297
298 return mdev;
299 }
300
301 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u32 port_num)
302 {
303 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
304 port_num);
305 struct mlx5_ib_multiport_info *mpi;
306 struct mlx5_ib_port *port;
307
308 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
309 return;
310
311 port = &ibdev->port[port_num - 1];
312
313 spin_lock(&port->mp.mpi_lock);
314 mpi = ibdev->port[port_num - 1].mp.mpi;
315 if (mpi->is_master)
316 goto out;
317
318 mpi->mdev_refcnt--;
319 if (mpi->unaffiliate)
320 complete(&mpi->unref_comp);
321 out:
322 spin_unlock(&port->mp.mpi_lock);
323 }
324
325 static int translate_eth_legacy_proto_oper(u32 eth_proto_oper,
326 u16 *active_speed, u8 *active_width)
327 {
328 switch (eth_proto_oper) {
329 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
330 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
331 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
332 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
333 *active_width = IB_WIDTH_1X;
334 *active_speed = IB_SPEED_SDR;
335 break;
336 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
337 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
338 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
339 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
340 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
341 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
342 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
343 *active_width = IB_WIDTH_1X;
344 *active_speed = IB_SPEED_QDR;
345 break;
346 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
347 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
348 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
349 *active_width = IB_WIDTH_1X;
350 *active_speed = IB_SPEED_EDR;
351 break;
352 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
353 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
354 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
355 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
356 *active_width = IB_WIDTH_4X;
357 *active_speed = IB_SPEED_QDR;
358 break;
359 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
360 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
361 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
362 *active_width = IB_WIDTH_1X;
363 *active_speed = IB_SPEED_HDR;
364 break;
365 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
366 *active_width = IB_WIDTH_4X;
367 *active_speed = IB_SPEED_FDR;
368 break;
369 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
370 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
371 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
372 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
373 *active_width = IB_WIDTH_4X;
374 *active_speed = IB_SPEED_EDR;
375 break;
376 default:
377 return -EINVAL;
378 }
379
380 return 0;
381 }
382
383 static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u16 *active_speed,
384 u8 *active_width)
385 {
386 switch (eth_proto_oper) {
387 case MLX5E_PROT_MASK(MLX5E_SGMII_100M):
388 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII):
389 *active_width = IB_WIDTH_1X;
390 *active_speed = IB_SPEED_SDR;
391 break;
392 case MLX5E_PROT_MASK(MLX5E_5GBASE_R):
393 *active_width = IB_WIDTH_1X;
394 *active_speed = IB_SPEED_DDR;
395 break;
396 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1):
397 *active_width = IB_WIDTH_1X;
398 *active_speed = IB_SPEED_QDR;
399 break;
400 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4):
401 *active_width = IB_WIDTH_4X;
402 *active_speed = IB_SPEED_QDR;
403 break;
404 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR):
405 *active_width = IB_WIDTH_1X;
406 *active_speed = IB_SPEED_EDR;
407 break;
408 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2):
409 *active_width = IB_WIDTH_2X;
410 *active_speed = IB_SPEED_EDR;
411 break;
412 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR):
413 *active_width = IB_WIDTH_1X;
414 *active_speed = IB_SPEED_HDR;
415 break;
416 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4):
417 *active_width = IB_WIDTH_4X;
418 *active_speed = IB_SPEED_EDR;
419 break;
420 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2):
421 *active_width = IB_WIDTH_2X;
422 *active_speed = IB_SPEED_HDR;
423 break;
424 case MLX5E_PROT_MASK(MLX5E_100GAUI_1_100GBASE_CR_KR):
425 *active_width = IB_WIDTH_1X;
426 *active_speed = IB_SPEED_NDR;
427 break;
428 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4):
429 *active_width = IB_WIDTH_4X;
430 *active_speed = IB_SPEED_HDR;
431 break;
432 case MLX5E_PROT_MASK(MLX5E_200GAUI_2_200GBASE_CR2_KR2):
433 *active_width = IB_WIDTH_2X;
434 *active_speed = IB_SPEED_NDR;
435 break;
436 case MLX5E_PROT_MASK(MLX5E_400GAUI_4_400GBASE_CR4_KR4):
437 *active_width = IB_WIDTH_4X;
438 *active_speed = IB_SPEED_NDR;
439 break;
440 default:
441 return -EINVAL;
442 }
443
444 return 0;
445 }
446
447 static int translate_eth_proto_oper(u32 eth_proto_oper, u16 *active_speed,
448 u8 *active_width, bool ext)
449 {
450 return ext ?
451 translate_eth_ext_proto_oper(eth_proto_oper, active_speed,
452 active_width) :
453 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed,
454 active_width);
455 }
456
457 static int mlx5_query_port_roce(struct ib_device *device, u32 port_num,
458 struct ib_port_attr *props)
459 {
460 struct mlx5_ib_dev *dev = to_mdev(device);
461 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
462 struct mlx5_core_dev *mdev;
463 struct net_device *ndev, *upper;
464 enum ib_mtu ndev_ib_mtu;
465 bool put_mdev = true;
466 u32 eth_prot_oper;
467 u32 mdev_port_num;
468 bool ext;
469 int err;
470
471 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
472 if (!mdev) {
473 /* This means the port isn't affiliated yet. Get the
474 * info for the master port instead.
475 */
476 put_mdev = false;
477 mdev = dev->mdev;
478 mdev_port_num = 1;
479 port_num = 1;
480 }
481
482 /* Possible bad flows are checked before filling out props so in case
483 * of an error it will still be zeroed out.
484 * Use native port in case of reps
485 */
486 if (dev->is_rep)
487 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
488 1);
489 else
490 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN,
491 mdev_port_num);
492 if (err)
493 goto out;
494 ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability);
495 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper);
496
497 props->active_width = IB_WIDTH_4X;
498 props->active_speed = IB_SPEED_QDR;
499
500 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
501 &props->active_width, ext);
502
503 if (!dev->is_rep && dev->mdev->roce.roce_en) {
504 u16 qkey_viol_cntr;
505
506 props->port_cap_flags |= IB_PORT_CM_SUP;
507 props->ip_gids = true;
508 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
509 roce_address_table_size);
510 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
511 props->qkey_viol_cntr = qkey_viol_cntr;
512 }
513 props->max_mtu = IB_MTU_4096;
514 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
515 props->pkey_tbl_len = 1;
516 props->state = IB_PORT_DOWN;
517 props->phys_state = IB_PORT_PHYS_STATE_DISABLED;
518
519 /* If this is a stub query for an unaffiliated port stop here */
520 if (!put_mdev)
521 goto out;
522
523 ndev = mlx5_ib_get_netdev(device, port_num);
524 if (!ndev)
525 goto out;
526
527 if (dev->lag_active) {
528 rcu_read_lock();
529 upper = netdev_master_upper_dev_get_rcu(ndev);
530 if (upper) {
531 dev_put(ndev);
532 ndev = upper;
533 dev_hold(ndev);
534 }
535 rcu_read_unlock();
536 }
537
538 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
539 props->state = IB_PORT_ACTIVE;
540 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP;
541 }
542
543 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
544
545 dev_put(ndev);
546
547 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
548 out:
549 if (put_mdev)
550 mlx5_ib_put_native_port_mdev(dev, port_num);
551 return err;
552 }
553
554 static int set_roce_addr(struct mlx5_ib_dev *dev, u32 port_num,
555 unsigned int index, const union ib_gid *gid,
556 const struct ib_gid_attr *attr)
557 {
558 enum ib_gid_type gid_type;
559 u16 vlan_id = 0xffff;
560 u8 roce_version = 0;
561 u8 roce_l3_type = 0;
562 u8 mac[ETH_ALEN];
563 int ret;
564
565 gid_type = attr->gid_type;
566 if (gid) {
567 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]);
568 if (ret)
569 return ret;
570 }
571
572 switch (gid_type) {
573 case IB_GID_TYPE_ROCE:
574 roce_version = MLX5_ROCE_VERSION_1;
575 break;
576 case IB_GID_TYPE_ROCE_UDP_ENCAP:
577 roce_version = MLX5_ROCE_VERSION_2;
578 if (gid && ipv6_addr_v4mapped((void *)gid))
579 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
580 else
581 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
582 break;
583
584 default:
585 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
586 }
587
588 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
589 roce_l3_type, gid->raw, mac,
590 vlan_id < VLAN_CFI_MASK, vlan_id,
591 port_num);
592 }
593
594 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr,
595 __always_unused void **context)
596 {
597 return set_roce_addr(to_mdev(attr->device), attr->port_num,
598 attr->index, &attr->gid, attr);
599 }
600
601 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
602 __always_unused void **context)
603 {
604 return set_roce_addr(to_mdev(attr->device), attr->port_num,
605 attr->index, NULL, attr);
606 }
607
608 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev,
609 const struct ib_gid_attr *attr)
610 {
611 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
612 return 0;
613
614 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
615 }
616
617 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
618 {
619 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
620 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
621 return 0;
622 }
623
624 enum {
625 MLX5_VPORT_ACCESS_METHOD_MAD,
626 MLX5_VPORT_ACCESS_METHOD_HCA,
627 MLX5_VPORT_ACCESS_METHOD_NIC,
628 };
629
630 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
631 {
632 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
633 return MLX5_VPORT_ACCESS_METHOD_MAD;
634
635 if (mlx5_ib_port_link_layer(ibdev, 1) ==
636 IB_LINK_LAYER_ETHERNET)
637 return MLX5_VPORT_ACCESS_METHOD_NIC;
638
639 return MLX5_VPORT_ACCESS_METHOD_HCA;
640 }
641
642 static void get_atomic_caps(struct mlx5_ib_dev *dev,
643 u8 atomic_size_qp,
644 struct ib_device_attr *props)
645 {
646 u8 tmp;
647 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
648 u8 atomic_req_8B_endianness_mode =
649 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
650
651 /* Check if HW supports 8 bytes standard atomic operations and capable
652 * of host endianness respond
653 */
654 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
655 if (((atomic_operations & tmp) == tmp) &&
656 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
657 (atomic_req_8B_endianness_mode)) {
658 props->atomic_cap = IB_ATOMIC_HCA;
659 } else {
660 props->atomic_cap = IB_ATOMIC_NONE;
661 }
662 }
663
664 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
665 struct ib_device_attr *props)
666 {
667 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
668
669 get_atomic_caps(dev, atomic_size_qp, props);
670 }
671
672 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
673 __be64 *sys_image_guid)
674 {
675 struct mlx5_ib_dev *dev = to_mdev(ibdev);
676 struct mlx5_core_dev *mdev = dev->mdev;
677 u64 tmp;
678 int err;
679
680 switch (mlx5_get_vport_access_method(ibdev)) {
681 case MLX5_VPORT_ACCESS_METHOD_MAD:
682 return mlx5_query_mad_ifc_system_image_guid(ibdev,
683 sys_image_guid);
684
685 case MLX5_VPORT_ACCESS_METHOD_HCA:
686 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
687 break;
688
689 case MLX5_VPORT_ACCESS_METHOD_NIC:
690 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
691 break;
692
693 default:
694 return -EINVAL;
695 }
696
697 if (!err)
698 *sys_image_guid = cpu_to_be64(tmp);
699
700 return err;
701
702 }
703
704 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
705 u16 *max_pkeys)
706 {
707 struct mlx5_ib_dev *dev = to_mdev(ibdev);
708 struct mlx5_core_dev *mdev = dev->mdev;
709
710 switch (mlx5_get_vport_access_method(ibdev)) {
711 case MLX5_VPORT_ACCESS_METHOD_MAD:
712 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
713
714 case MLX5_VPORT_ACCESS_METHOD_HCA:
715 case MLX5_VPORT_ACCESS_METHOD_NIC:
716 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
717 pkey_table_size));
718 return 0;
719
720 default:
721 return -EINVAL;
722 }
723 }
724
725 static int mlx5_query_vendor_id(struct ib_device *ibdev,
726 u32 *vendor_id)
727 {
728 struct mlx5_ib_dev *dev = to_mdev(ibdev);
729
730 switch (mlx5_get_vport_access_method(ibdev)) {
731 case MLX5_VPORT_ACCESS_METHOD_MAD:
732 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
733
734 case MLX5_VPORT_ACCESS_METHOD_HCA:
735 case MLX5_VPORT_ACCESS_METHOD_NIC:
736 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
737
738 default:
739 return -EINVAL;
740 }
741 }
742
743 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
744 __be64 *node_guid)
745 {
746 u64 tmp;
747 int err;
748
749 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
750 case MLX5_VPORT_ACCESS_METHOD_MAD:
751 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
752
753 case MLX5_VPORT_ACCESS_METHOD_HCA:
754 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
755 break;
756
757 case MLX5_VPORT_ACCESS_METHOD_NIC:
758 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
759 break;
760
761 default:
762 return -EINVAL;
763 }
764
765 if (!err)
766 *node_guid = cpu_to_be64(tmp);
767
768 return err;
769 }
770
771 struct mlx5_reg_node_desc {
772 u8 desc[IB_DEVICE_NODE_DESC_MAX];
773 };
774
775 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
776 {
777 struct mlx5_reg_node_desc in;
778
779 if (mlx5_use_mad_ifc(dev))
780 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
781
782 memset(&in, 0, sizeof(in));
783
784 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
785 sizeof(struct mlx5_reg_node_desc),
786 MLX5_REG_NODE_DESC, 0, 0);
787 }
788
789 static int mlx5_ib_query_device(struct ib_device *ibdev,
790 struct ib_device_attr *props,
791 struct ib_udata *uhw)
792 {
793 size_t uhw_outlen = (uhw) ? uhw->outlen : 0;
794 struct mlx5_ib_dev *dev = to_mdev(ibdev);
795 struct mlx5_core_dev *mdev = dev->mdev;
796 int err = -ENOMEM;
797 int max_sq_desc;
798 int max_rq_sg;
799 int max_sq_sg;
800 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
801 bool raw_support = !mlx5_core_mp_enabled(mdev);
802 struct mlx5_ib_query_device_resp resp = {};
803 size_t resp_len;
804 u64 max_tso;
805
806 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
807 if (uhw_outlen && uhw_outlen < resp_len)
808 return -EINVAL;
809
810 resp.response_length = resp_len;
811
812 if (uhw && uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
813 return -EINVAL;
814
815 memset(props, 0, sizeof(*props));
816 err = mlx5_query_system_image_guid(ibdev,
817 &props->sys_image_guid);
818 if (err)
819 return err;
820
821 props->max_pkeys = dev->pkey_table_len;
822
823 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
824 if (err)
825 return err;
826
827 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
828 (fw_rev_min(dev->mdev) << 16) |
829 fw_rev_sub(dev->mdev);
830 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
831 IB_DEVICE_PORT_ACTIVE_EVENT |
832 IB_DEVICE_SYS_IMAGE_GUID |
833 IB_DEVICE_RC_RNR_NAK_GEN;
834
835 if (MLX5_CAP_GEN(mdev, pkv))
836 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
837 if (MLX5_CAP_GEN(mdev, qkv))
838 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
839 if (MLX5_CAP_GEN(mdev, apm))
840 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
841 if (MLX5_CAP_GEN(mdev, xrc))
842 props->device_cap_flags |= IB_DEVICE_XRC;
843 if (MLX5_CAP_GEN(mdev, imaicl)) {
844 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
845 IB_DEVICE_MEM_WINDOW_TYPE_2B;
846 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
847 /* We support 'Gappy' memory registration too */
848 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
849 }
850 /* IB_WR_REG_MR always requires changing the entity size with UMR */
851 if (!MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled))
852 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
853 if (MLX5_CAP_GEN(mdev, sho)) {
854 props->device_cap_flags |= IB_DEVICE_INTEGRITY_HANDOVER;
855 /* At this stage no support for signature handover */
856 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
857 IB_PROT_T10DIF_TYPE_2 |
858 IB_PROT_T10DIF_TYPE_3;
859 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
860 IB_GUARD_T10DIF_CSUM;
861 }
862 if (MLX5_CAP_GEN(mdev, block_lb_mc))
863 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
864
865 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
866 if (MLX5_CAP_ETH(mdev, csum_cap)) {
867 /* Legacy bit to support old userspace libraries */
868 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
869 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
870 }
871
872 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
873 props->raw_packet_caps |=
874 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
875
876 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) {
877 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
878 if (max_tso) {
879 resp.tso_caps.max_tso = 1 << max_tso;
880 resp.tso_caps.supported_qpts |=
881 1 << IB_QPT_RAW_PACKET;
882 resp.response_length += sizeof(resp.tso_caps);
883 }
884 }
885
886 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) {
887 resp.rss_caps.rx_hash_function =
888 MLX5_RX_HASH_FUNC_TOEPLITZ;
889 resp.rss_caps.rx_hash_fields_mask =
890 MLX5_RX_HASH_SRC_IPV4 |
891 MLX5_RX_HASH_DST_IPV4 |
892 MLX5_RX_HASH_SRC_IPV6 |
893 MLX5_RX_HASH_DST_IPV6 |
894 MLX5_RX_HASH_SRC_PORT_TCP |
895 MLX5_RX_HASH_DST_PORT_TCP |
896 MLX5_RX_HASH_SRC_PORT_UDP |
897 MLX5_RX_HASH_DST_PORT_UDP |
898 MLX5_RX_HASH_INNER;
899 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
900 MLX5_ACCEL_IPSEC_CAP_DEVICE)
901 resp.rss_caps.rx_hash_fields_mask |=
902 MLX5_RX_HASH_IPSEC_SPI;
903 resp.response_length += sizeof(resp.rss_caps);
904 }
905 } else {
906 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen)
907 resp.response_length += sizeof(resp.tso_caps);
908 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen)
909 resp.response_length += sizeof(resp.rss_caps);
910 }
911
912 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
913 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
914 props->device_cap_flags |= IB_DEVICE_UD_TSO;
915 }
916
917 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
918 MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
919 raw_support)
920 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
921
922 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
923 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
924 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
925
926 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
927 MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
928 raw_support) {
929 /* Legacy bit to support old userspace libraries */
930 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
931 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
932 }
933
934 if (MLX5_CAP_DEV_MEM(mdev, memic)) {
935 props->max_dm_size =
936 MLX5_CAP_DEV_MEM(mdev, max_memic_size);
937 }
938
939 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
940 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
941
942 if (MLX5_CAP_GEN(mdev, end_pad))
943 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
944
945 props->vendor_part_id = mdev->pdev->device;
946 props->hw_ver = mdev->pdev->revision;
947
948 props->max_mr_size = ~0ull;
949 props->page_size_cap = ~(min_page_size - 1);
950 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
951 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
952 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
953 sizeof(struct mlx5_wqe_data_seg);
954 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
955 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
956 sizeof(struct mlx5_wqe_raddr_seg)) /
957 sizeof(struct mlx5_wqe_data_seg);
958 props->max_send_sge = max_sq_sg;
959 props->max_recv_sge = max_rq_sg;
960 props->max_sge_rd = MLX5_MAX_SGE_RD;
961 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
962 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
963 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
964 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
965 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
966 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
967 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
968 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
969 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
970 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
971 props->max_srq_sge = max_rq_sg - 1;
972 props->max_fast_reg_page_list_len =
973 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
974 props->max_pi_fast_reg_page_list_len =
975 props->max_fast_reg_page_list_len / 2;
976 props->max_sgl_rd =
977 MLX5_CAP_GEN(mdev, max_sgl_for_optimized_performance);
978 get_atomic_caps_qp(dev, props);
979 props->masked_atomic_cap = IB_ATOMIC_NONE;
980 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
981 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
982 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
983 props->max_mcast_grp;
984 props->max_ah = INT_MAX;
985 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
986 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
987
988 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
989 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT)
990 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
991 props->odp_caps = dev->odp_caps;
992 if (!uhw) {
993 /* ODP for kernel QPs is not implemented for receive
994 * WQEs and SRQ WQEs
995 */
996 props->odp_caps.per_transport_caps.rc_odp_caps &=
997 ~(IB_ODP_SUPPORT_READ |
998 IB_ODP_SUPPORT_SRQ_RECV);
999 props->odp_caps.per_transport_caps.uc_odp_caps &=
1000 ~(IB_ODP_SUPPORT_READ |
1001 IB_ODP_SUPPORT_SRQ_RECV);
1002 props->odp_caps.per_transport_caps.ud_odp_caps &=
1003 ~(IB_ODP_SUPPORT_READ |
1004 IB_ODP_SUPPORT_SRQ_RECV);
1005 props->odp_caps.per_transport_caps.xrc_odp_caps &=
1006 ~(IB_ODP_SUPPORT_READ |
1007 IB_ODP_SUPPORT_SRQ_RECV);
1008 }
1009 }
1010
1011 if (MLX5_CAP_GEN(mdev, cd))
1012 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
1013
1014 if (mlx5_core_is_vf(mdev))
1015 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
1016
1017 if (mlx5_ib_port_link_layer(ibdev, 1) ==
1018 IB_LINK_LAYER_ETHERNET && raw_support) {
1019 props->rss_caps.max_rwq_indirection_tables =
1020 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
1021 props->rss_caps.max_rwq_indirection_table_size =
1022 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
1023 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
1024 props->max_wq_type_rq =
1025 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
1026 }
1027
1028 if (MLX5_CAP_GEN(mdev, tag_matching)) {
1029 props->tm_caps.max_num_tags =
1030 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
1031 props->tm_caps.max_ops =
1032 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1033 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
1034 }
1035
1036 if (MLX5_CAP_GEN(mdev, tag_matching) &&
1037 MLX5_CAP_GEN(mdev, rndv_offload_rc)) {
1038 props->tm_caps.flags = IB_TM_CAP_RNDV_RC;
1039 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
1040 }
1041
1042 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
1043 props->cq_caps.max_cq_moderation_count =
1044 MLX5_MAX_CQ_COUNT;
1045 props->cq_caps.max_cq_moderation_period =
1046 MLX5_MAX_CQ_PERIOD;
1047 }
1048
1049 if (offsetofend(typeof(resp), cqe_comp_caps) <= uhw_outlen) {
1050 resp.response_length += sizeof(resp.cqe_comp_caps);
1051
1052 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) {
1053 resp.cqe_comp_caps.max_num =
1054 MLX5_CAP_GEN(dev->mdev,
1055 cqe_compression_max_num);
1056
1057 resp.cqe_comp_caps.supported_format =
1058 MLX5_IB_CQE_RES_FORMAT_HASH |
1059 MLX5_IB_CQE_RES_FORMAT_CSUM;
1060
1061 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
1062 resp.cqe_comp_caps.supported_format |=
1063 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX;
1064 }
1065 }
1066
1067 if (offsetofend(typeof(resp), packet_pacing_caps) <= uhw_outlen &&
1068 raw_support) {
1069 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
1070 MLX5_CAP_GEN(mdev, qos)) {
1071 resp.packet_pacing_caps.qp_rate_limit_max =
1072 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
1073 resp.packet_pacing_caps.qp_rate_limit_min =
1074 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
1075 resp.packet_pacing_caps.supported_qpts |=
1076 1 << IB_QPT_RAW_PACKET;
1077 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
1078 MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
1079 resp.packet_pacing_caps.cap_flags |=
1080 MLX5_IB_PP_SUPPORT_BURST;
1081 }
1082 resp.response_length += sizeof(resp.packet_pacing_caps);
1083 }
1084
1085 if (offsetofend(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes) <=
1086 uhw_outlen) {
1087 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
1088 resp.mlx5_ib_support_multi_pkt_send_wqes =
1089 MLX5_IB_ALLOW_MPW;
1090
1091 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1092 resp.mlx5_ib_support_multi_pkt_send_wqes |=
1093 MLX5_IB_SUPPORT_EMPW;
1094
1095 resp.response_length +=
1096 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1097 }
1098
1099 if (offsetofend(typeof(resp), flags) <= uhw_outlen) {
1100 resp.response_length += sizeof(resp.flags);
1101
1102 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1103 resp.flags |=
1104 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
1105
1106 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1107 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
1108 if (MLX5_CAP_GEN(mdev, qp_packet_based))
1109 resp.flags |=
1110 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE;
1111
1112 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT;
1113 }
1114
1115 if (offsetofend(typeof(resp), sw_parsing_caps) <= uhw_outlen) {
1116 resp.response_length += sizeof(resp.sw_parsing_caps);
1117 if (MLX5_CAP_ETH(mdev, swp)) {
1118 resp.sw_parsing_caps.sw_parsing_offloads |=
1119 MLX5_IB_SW_PARSING;
1120
1121 if (MLX5_CAP_ETH(mdev, swp_csum))
1122 resp.sw_parsing_caps.sw_parsing_offloads |=
1123 MLX5_IB_SW_PARSING_CSUM;
1124
1125 if (MLX5_CAP_ETH(mdev, swp_lso))
1126 resp.sw_parsing_caps.sw_parsing_offloads |=
1127 MLX5_IB_SW_PARSING_LSO;
1128
1129 if (resp.sw_parsing_caps.sw_parsing_offloads)
1130 resp.sw_parsing_caps.supported_qpts =
1131 BIT(IB_QPT_RAW_PACKET);
1132 }
1133 }
1134
1135 if (offsetofend(typeof(resp), striding_rq_caps) <= uhw_outlen &&
1136 raw_support) {
1137 resp.response_length += sizeof(resp.striding_rq_caps);
1138 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1139 resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1140 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1141 resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1142 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1143 if (MLX5_CAP_GEN(dev->mdev, ext_stride_num_range))
1144 resp.striding_rq_caps
1145 .min_single_wqe_log_num_of_strides =
1146 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1147 else
1148 resp.striding_rq_caps
1149 .min_single_wqe_log_num_of_strides =
1150 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1151 resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1152 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1153 resp.striding_rq_caps.supported_qpts =
1154 BIT(IB_QPT_RAW_PACKET);
1155 }
1156 }
1157
1158 if (offsetofend(typeof(resp), tunnel_offloads_caps) <= uhw_outlen) {
1159 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1160 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1161 resp.tunnel_offloads_caps |=
1162 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1163 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1164 resp.tunnel_offloads_caps |=
1165 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1166 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1167 resp.tunnel_offloads_caps |=
1168 MLX5_IB_TUNNELED_OFFLOADS_GRE;
1169 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre))
1170 resp.tunnel_offloads_caps |=
1171 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE;
1172 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp))
1173 resp.tunnel_offloads_caps |=
1174 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
1175 }
1176
1177 if (offsetofend(typeof(resp), dci_streams_caps) <= uhw_outlen) {
1178 resp.response_length += sizeof(resp.dci_streams_caps);
1179
1180 resp.dci_streams_caps.max_log_num_concurent =
1181 MLX5_CAP_GEN(mdev, log_max_dci_stream_channels);
1182
1183 resp.dci_streams_caps.max_log_num_errored =
1184 MLX5_CAP_GEN(mdev, log_max_dci_errored_streams);
1185 }
1186
1187 if (uhw_outlen) {
1188 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1189
1190 if (err)
1191 return err;
1192 }
1193
1194 return 0;
1195 }
1196
1197 static void translate_active_width(struct ib_device *ibdev, u16 active_width,
1198 u8 *ib_width)
1199 {
1200 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1201
1202 if (active_width & MLX5_PTYS_WIDTH_1X)
1203 *ib_width = IB_WIDTH_1X;
1204 else if (active_width & MLX5_PTYS_WIDTH_2X)
1205 *ib_width = IB_WIDTH_2X;
1206 else if (active_width & MLX5_PTYS_WIDTH_4X)
1207 *ib_width = IB_WIDTH_4X;
1208 else if (active_width & MLX5_PTYS_WIDTH_8X)
1209 *ib_width = IB_WIDTH_8X;
1210 else if (active_width & MLX5_PTYS_WIDTH_12X)
1211 *ib_width = IB_WIDTH_12X;
1212 else {
1213 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n",
1214 active_width);
1215 *ib_width = IB_WIDTH_4X;
1216 }
1217
1218 return;
1219 }
1220
1221 static int mlx5_mtu_to_ib_mtu(int mtu)
1222 {
1223 switch (mtu) {
1224 case 256: return 1;
1225 case 512: return 2;
1226 case 1024: return 3;
1227 case 2048: return 4;
1228 case 4096: return 5;
1229 default:
1230 pr_warn("invalid mtu\n");
1231 return -1;
1232 }
1233 }
1234
1235 enum ib_max_vl_num {
1236 __IB_MAX_VL_0 = 1,
1237 __IB_MAX_VL_0_1 = 2,
1238 __IB_MAX_VL_0_3 = 3,
1239 __IB_MAX_VL_0_7 = 4,
1240 __IB_MAX_VL_0_14 = 5,
1241 };
1242
1243 enum mlx5_vl_hw_cap {
1244 MLX5_VL_HW_0 = 1,
1245 MLX5_VL_HW_0_1 = 2,
1246 MLX5_VL_HW_0_2 = 3,
1247 MLX5_VL_HW_0_3 = 4,
1248 MLX5_VL_HW_0_4 = 5,
1249 MLX5_VL_HW_0_5 = 6,
1250 MLX5_VL_HW_0_6 = 7,
1251 MLX5_VL_HW_0_7 = 8,
1252 MLX5_VL_HW_0_14 = 15
1253 };
1254
1255 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1256 u8 *max_vl_num)
1257 {
1258 switch (vl_hw_cap) {
1259 case MLX5_VL_HW_0:
1260 *max_vl_num = __IB_MAX_VL_0;
1261 break;
1262 case MLX5_VL_HW_0_1:
1263 *max_vl_num = __IB_MAX_VL_0_1;
1264 break;
1265 case MLX5_VL_HW_0_3:
1266 *max_vl_num = __IB_MAX_VL_0_3;
1267 break;
1268 case MLX5_VL_HW_0_7:
1269 *max_vl_num = __IB_MAX_VL_0_7;
1270 break;
1271 case MLX5_VL_HW_0_14:
1272 *max_vl_num = __IB_MAX_VL_0_14;
1273 break;
1274
1275 default:
1276 return -EINVAL;
1277 }
1278
1279 return 0;
1280 }
1281
1282 static int mlx5_query_hca_port(struct ib_device *ibdev, u32 port,
1283 struct ib_port_attr *props)
1284 {
1285 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1286 struct mlx5_core_dev *mdev = dev->mdev;
1287 struct mlx5_hca_vport_context *rep;
1288 u16 max_mtu;
1289 u16 oper_mtu;
1290 int err;
1291 u16 ib_link_width_oper;
1292 u8 vl_hw_cap;
1293
1294 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1295 if (!rep) {
1296 err = -ENOMEM;
1297 goto out;
1298 }
1299
1300 /* props being zeroed by the caller, avoid zeroing it here */
1301
1302 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
1303 if (err)
1304 goto out;
1305
1306 props->lid = rep->lid;
1307 props->lmc = rep->lmc;
1308 props->sm_lid = rep->sm_lid;
1309 props->sm_sl = rep->sm_sl;
1310 props->state = rep->vport_state;
1311 props->phys_state = rep->port_physical_state;
1312 props->port_cap_flags = rep->cap_mask1;
1313 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1314 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1315 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1316 props->bad_pkey_cntr = rep->pkey_violation_counter;
1317 props->qkey_viol_cntr = rep->qkey_violation_counter;
1318 props->subnet_timeout = rep->subnet_timeout;
1319 props->init_type_reply = rep->init_type_reply;
1320
1321 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP)
1322 props->port_cap_flags2 = rep->cap_mask2;
1323
1324 err = mlx5_query_ib_port_oper(mdev, &ib_link_width_oper,
1325 &props->active_speed, port);
1326 if (err)
1327 goto out;
1328
1329 translate_active_width(ibdev, ib_link_width_oper, &props->active_width);
1330
1331 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
1332
1333 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
1334
1335 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
1336
1337 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
1338
1339 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1340 if (err)
1341 goto out;
1342
1343 err = translate_max_vl_num(ibdev, vl_hw_cap,
1344 &props->max_vl_num);
1345 out:
1346 kfree(rep);
1347 return err;
1348 }
1349
1350 int mlx5_ib_query_port(struct ib_device *ibdev, u32 port,
1351 struct ib_port_attr *props)
1352 {
1353 unsigned int count;
1354 int ret;
1355
1356 switch (mlx5_get_vport_access_method(ibdev)) {
1357 case MLX5_VPORT_ACCESS_METHOD_MAD:
1358 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1359 break;
1360
1361 case MLX5_VPORT_ACCESS_METHOD_HCA:
1362 ret = mlx5_query_hca_port(ibdev, port, props);
1363 break;
1364
1365 case MLX5_VPORT_ACCESS_METHOD_NIC:
1366 ret = mlx5_query_port_roce(ibdev, port, props);
1367 break;
1368
1369 default:
1370 ret = -EINVAL;
1371 }
1372
1373 if (!ret && props) {
1374 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1375 struct mlx5_core_dev *mdev;
1376 bool put_mdev = true;
1377
1378 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1379 if (!mdev) {
1380 /* If the port isn't affiliated yet query the master.
1381 * The master and slave will have the same values.
1382 */
1383 mdev = dev->mdev;
1384 port = 1;
1385 put_mdev = false;
1386 }
1387 count = mlx5_core_reserved_gids_count(mdev);
1388 if (put_mdev)
1389 mlx5_ib_put_native_port_mdev(dev, port);
1390 props->gid_tbl_len -= count;
1391 }
1392 return ret;
1393 }
1394
1395 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u32 port,
1396 struct ib_port_attr *props)
1397 {
1398 return mlx5_query_port_roce(ibdev, port, props);
1399 }
1400
1401 static int mlx5_ib_rep_query_pkey(struct ib_device *ibdev, u32 port, u16 index,
1402 u16 *pkey)
1403 {
1404 /* Default special Pkey for representor device port as per the
1405 * IB specification 1.3 section 10.9.1.2.
1406 */
1407 *pkey = 0xffff;
1408 return 0;
1409 }
1410
1411 static int mlx5_ib_query_gid(struct ib_device *ibdev, u32 port, int index,
1412 union ib_gid *gid)
1413 {
1414 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1415 struct mlx5_core_dev *mdev = dev->mdev;
1416
1417 switch (mlx5_get_vport_access_method(ibdev)) {
1418 case MLX5_VPORT_ACCESS_METHOD_MAD:
1419 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
1420
1421 case MLX5_VPORT_ACCESS_METHOD_HCA:
1422 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1423
1424 default:
1425 return -EINVAL;
1426 }
1427
1428 }
1429
1430 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u32 port,
1431 u16 index, u16 *pkey)
1432 {
1433 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1434 struct mlx5_core_dev *mdev;
1435 bool put_mdev = true;
1436 u32 mdev_port_num;
1437 int err;
1438
1439 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1440 if (!mdev) {
1441 /* The port isn't affiliated yet, get the PKey from the master
1442 * port. For RoCE the PKey tables will be the same.
1443 */
1444 put_mdev = false;
1445 mdev = dev->mdev;
1446 mdev_port_num = 1;
1447 }
1448
1449 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1450 index, pkey);
1451 if (put_mdev)
1452 mlx5_ib_put_native_port_mdev(dev, port);
1453
1454 return err;
1455 }
1456
1457 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u32 port, u16 index,
1458 u16 *pkey)
1459 {
1460 switch (mlx5_get_vport_access_method(ibdev)) {
1461 case MLX5_VPORT_ACCESS_METHOD_MAD:
1462 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1463
1464 case MLX5_VPORT_ACCESS_METHOD_HCA:
1465 case MLX5_VPORT_ACCESS_METHOD_NIC:
1466 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1467 default:
1468 return -EINVAL;
1469 }
1470 }
1471
1472 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1473 struct ib_device_modify *props)
1474 {
1475 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1476 struct mlx5_reg_node_desc in;
1477 struct mlx5_reg_node_desc out;
1478 int err;
1479
1480 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1481 return -EOPNOTSUPP;
1482
1483 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1484 return 0;
1485
1486 /*
1487 * If possible, pass node desc to FW, so it can generate
1488 * a 144 trap. If cmd fails, just ignore.
1489 */
1490 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1491 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
1492 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1493 if (err)
1494 return err;
1495
1496 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1497
1498 return err;
1499 }
1500
1501 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u32 port_num, u32 mask,
1502 u32 value)
1503 {
1504 struct mlx5_hca_vport_context ctx = {};
1505 struct mlx5_core_dev *mdev;
1506 u32 mdev_port_num;
1507 int err;
1508
1509 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1510 if (!mdev)
1511 return -ENODEV;
1512
1513 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
1514 if (err)
1515 goto out;
1516
1517 if (~ctx.cap_mask1_perm & mask) {
1518 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1519 mask, ctx.cap_mask1_perm);
1520 err = -EINVAL;
1521 goto out;
1522 }
1523
1524 ctx.cap_mask1 = value;
1525 ctx.cap_mask1_perm = mask;
1526 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1527 0, &ctx);
1528
1529 out:
1530 mlx5_ib_put_native_port_mdev(dev, port_num);
1531
1532 return err;
1533 }
1534
1535 static int mlx5_ib_modify_port(struct ib_device *ibdev, u32 port, int mask,
1536 struct ib_port_modify *props)
1537 {
1538 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1539 struct ib_port_attr attr;
1540 u32 tmp;
1541 int err;
1542 u32 change_mask;
1543 u32 value;
1544 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1545 IB_LINK_LAYER_INFINIBAND);
1546
1547 /* CM layer calls ib_modify_port() regardless of the link layer. For
1548 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1549 */
1550 if (!is_ib)
1551 return 0;
1552
1553 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1554 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1555 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1556 return set_port_caps_atomic(dev, port, change_mask, value);
1557 }
1558
1559 mutex_lock(&dev->cap_mask_mutex);
1560
1561 err = ib_query_port(ibdev, port, &attr);
1562 if (err)
1563 goto out;
1564
1565 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1566 ~props->clr_port_cap_mask;
1567
1568 err = mlx5_set_port_caps(dev->mdev, port, tmp);
1569
1570 out:
1571 mutex_unlock(&dev->cap_mask_mutex);
1572 return err;
1573 }
1574
1575 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1576 {
1577 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1578 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1579 }
1580
1581 static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1582 {
1583 /* Large page with non 4k uar support might limit the dynamic size */
1584 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096)
1585 return MLX5_MIN_DYN_BFREGS;
1586
1587 return MLX5_MAX_DYN_BFREGS;
1588 }
1589
1590 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1591 struct mlx5_ib_alloc_ucontext_req_v2 *req,
1592 struct mlx5_bfreg_info *bfregi)
1593 {
1594 int uars_per_sys_page;
1595 int bfregs_per_sys_page;
1596 int ref_bfregs = req->total_num_bfregs;
1597
1598 if (req->total_num_bfregs == 0)
1599 return -EINVAL;
1600
1601 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1602 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1603
1604 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1605 return -ENOMEM;
1606
1607 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1608 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1609 /* This holds the required static allocation asked by the user */
1610 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1611 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1612 return -EINVAL;
1613
1614 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1615 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1616 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1617 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1618
1619 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
1620 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1621 lib_uar_4k ? "yes" : "no", ref_bfregs,
1622 req->total_num_bfregs, bfregi->total_num_bfregs,
1623 bfregi->num_sys_pages);
1624
1625 return 0;
1626 }
1627
1628 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1629 {
1630 struct mlx5_bfreg_info *bfregi;
1631 int err;
1632 int i;
1633
1634 bfregi = &context->bfregi;
1635 for (i = 0; i < bfregi->num_static_sys_pages; i++) {
1636 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1637 if (err)
1638 goto error;
1639
1640 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1641 }
1642
1643 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1644 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1645
1646 return 0;
1647
1648 error:
1649 for (--i; i >= 0; i--)
1650 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1651 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1652
1653 return err;
1654 }
1655
1656 static void deallocate_uars(struct mlx5_ib_dev *dev,
1657 struct mlx5_ib_ucontext *context)
1658 {
1659 struct mlx5_bfreg_info *bfregi;
1660 int i;
1661
1662 bfregi = &context->bfregi;
1663 for (i = 0; i < bfregi->num_sys_pages; i++)
1664 if (i < bfregi->num_static_sys_pages ||
1665 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX)
1666 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1667 }
1668
1669 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
1670 {
1671 int err = 0;
1672
1673 mutex_lock(&dev->lb.mutex);
1674 if (td)
1675 dev->lb.user_td++;
1676 if (qp)
1677 dev->lb.qps++;
1678
1679 if (dev->lb.user_td == 2 ||
1680 dev->lb.qps == 1) {
1681 if (!dev->lb.enabled) {
1682 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1683 dev->lb.enabled = true;
1684 }
1685 }
1686
1687 mutex_unlock(&dev->lb.mutex);
1688
1689 return err;
1690 }
1691
1692 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
1693 {
1694 mutex_lock(&dev->lb.mutex);
1695 if (td)
1696 dev->lb.user_td--;
1697 if (qp)
1698 dev->lb.qps--;
1699
1700 if (dev->lb.user_td == 1 &&
1701 dev->lb.qps == 0) {
1702 if (dev->lb.enabled) {
1703 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1704 dev->lb.enabled = false;
1705 }
1706 }
1707
1708 mutex_unlock(&dev->lb.mutex);
1709 }
1710
1711 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn,
1712 u16 uid)
1713 {
1714 int err;
1715
1716 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1717 return 0;
1718
1719 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid);
1720 if (err)
1721 return err;
1722
1723 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1724 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1725 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1726 return err;
1727
1728 return mlx5_ib_enable_lb(dev, true, false);
1729 }
1730
1731 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn,
1732 u16 uid)
1733 {
1734 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1735 return;
1736
1737 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid);
1738
1739 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1740 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1741 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1742 return;
1743
1744 mlx5_ib_disable_lb(dev, true, false);
1745 }
1746
1747 static int set_ucontext_resp(struct ib_ucontext *uctx,
1748 struct mlx5_ib_alloc_ucontext_resp *resp)
1749 {
1750 struct ib_device *ibdev = uctx->device;
1751 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1752 struct mlx5_ib_ucontext *context = to_mucontext(uctx);
1753 struct mlx5_bfreg_info *bfregi = &context->bfregi;
1754 int err;
1755
1756 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1757 err = mlx5_cmd_dump_fill_mkey(dev->mdev,
1758 &resp->dump_fill_mkey);
1759 if (err)
1760 return err;
1761 resp->comp_mask |=
1762 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY;
1763 }
1764
1765 resp->qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1766 if (dev->wc_support)
1767 resp->bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev,
1768 log_bf_reg_size);
1769 resp->cache_line_size = cache_line_size();
1770 resp->max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1771 resp->max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1772 resp->max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1773 resp->max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1774 resp->max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1775 resp->cqe_version = context->cqe_version;
1776 resp->log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1777 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1778 resp->num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1779 MLX5_CAP_GEN(dev->mdev,
1780 num_of_uars_per_page) : 1;
1781
1782 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
1783 MLX5_ACCEL_IPSEC_CAP_DEVICE) {
1784 if (mlx5_get_flow_namespace(dev->mdev,
1785 MLX5_FLOW_NAMESPACE_EGRESS))
1786 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
1787 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
1788 MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
1789 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
1790 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
1791 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
1792 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
1793 MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
1794 resp->flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
1795 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */
1796 }
1797
1798 resp->tot_bfregs = bfregi->lib_uar_dyn ? 0 :
1799 bfregi->total_num_bfregs - bfregi->num_dyn_bfregs;
1800 resp->num_ports = dev->num_ports;
1801 resp->cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1802 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1803
1804 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1805 mlx5_query_min_inline(dev->mdev, &resp->eth_min_inline);
1806 resp->eth_min_inline++;
1807 }
1808
1809 if (dev->mdev->clock_info)
1810 resp->clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1811
1812 /*
1813 * We don't want to expose information from the PCI bar that is located
1814 * after 4096 bytes, so if the arch only supports larger pages, let's
1815 * pretend we don't support reading the HCA's core clock. This is also
1816 * forced by mmap function.
1817 */
1818 if (PAGE_SIZE <= 4096) {
1819 resp->comp_mask |=
1820 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1821 resp->hca_core_clock_offset =
1822 offsetof(struct mlx5_init_seg,
1823 internal_timer_h) % PAGE_SIZE;
1824 }
1825
1826 if (MLX5_CAP_GEN(dev->mdev, ece_support))
1827 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE;
1828
1829 if (rt_supported(MLX5_CAP_GEN(dev->mdev, sq_ts_format)) &&
1830 rt_supported(MLX5_CAP_GEN(dev->mdev, rq_ts_format)) &&
1831 rt_supported(MLX5_CAP_ROCE(dev->mdev, qp_ts_format)))
1832 resp->comp_mask |=
1833 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_TIME_TS;
1834
1835 resp->num_dyn_bfregs = bfregi->num_dyn_bfregs;
1836
1837 if (MLX5_CAP_GEN(dev->mdev, drain_sigerr))
1838 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS;
1839
1840 return 0;
1841 }
1842
1843 static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx,
1844 struct ib_udata *udata)
1845 {
1846 struct ib_device *ibdev = uctx->device;
1847 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1848 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1849 struct mlx5_ib_alloc_ucontext_resp resp = {};
1850 struct mlx5_ib_ucontext *context = to_mucontext(uctx);
1851 struct mlx5_bfreg_info *bfregi;
1852 int ver;
1853 int err;
1854 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1855 max_cqe_version);
1856 bool lib_uar_4k;
1857 bool lib_uar_dyn;
1858
1859 if (!dev->ib_active)
1860 return -EAGAIN;
1861
1862 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1863 ver = 0;
1864 else if (udata->inlen >= min_req_v2)
1865 ver = 2;
1866 else
1867 return -EINVAL;
1868
1869 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
1870 if (err)
1871 return err;
1872
1873 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX)
1874 return -EOPNOTSUPP;
1875
1876 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1877 return -EOPNOTSUPP;
1878
1879 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1880 MLX5_NON_FP_BFREGS_PER_UAR);
1881 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1882 return -EINVAL;
1883
1884 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
1885 lib_uar_dyn = req.lib_caps & MLX5_LIB_CAP_DYN_UAR;
1886 bfregi = &context->bfregi;
1887
1888 if (lib_uar_dyn) {
1889 bfregi->lib_uar_dyn = lib_uar_dyn;
1890 goto uar_done;
1891 }
1892
1893 /* updates req->total_num_bfregs */
1894 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
1895 if (err)
1896 goto out_ctx;
1897
1898 mutex_init(&bfregi->lock);
1899 bfregi->lib_uar_4k = lib_uar_4k;
1900 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
1901 GFP_KERNEL);
1902 if (!bfregi->count) {
1903 err = -ENOMEM;
1904 goto out_ctx;
1905 }
1906
1907 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1908 sizeof(*bfregi->sys_pages),
1909 GFP_KERNEL);
1910 if (!bfregi->sys_pages) {
1911 err = -ENOMEM;
1912 goto out_count;
1913 }
1914
1915 err = allocate_uars(dev, context);
1916 if (err)
1917 goto out_sys_pages;
1918
1919 uar_done:
1920 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) {
1921 err = mlx5_ib_devx_create(dev, true);
1922 if (err < 0)
1923 goto out_uars;
1924 context->devx_uid = err;
1925 }
1926
1927 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn,
1928 context->devx_uid);
1929 if (err)
1930 goto out_devx;
1931
1932 INIT_LIST_HEAD(&context->db_page_list);
1933 mutex_init(&context->db_page_mutex);
1934
1935 context->cqe_version = min_t(__u8,
1936 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1937 req.max_cqe_version);
1938
1939 err = set_ucontext_resp(uctx, &resp);
1940 if (err)
1941 goto out_mdev;
1942
1943 resp.response_length = min(udata->outlen, sizeof(resp));
1944 err = ib_copy_to_udata(udata, &resp, resp.response_length);
1945 if (err)
1946 goto out_mdev;
1947
1948 bfregi->ver = ver;
1949 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
1950 context->lib_caps = req.lib_caps;
1951 print_lib_caps(dev, context->lib_caps);
1952
1953 if (mlx5_ib_lag_should_assign_affinity(dev)) {
1954 u32 port = mlx5_core_native_port_num(dev->mdev) - 1;
1955
1956 atomic_set(&context->tx_port_affinity,
1957 atomic_add_return(
1958 1, &dev->port[port].roce.tx_port_affinity));
1959 }
1960
1961 return 0;
1962
1963 out_mdev:
1964 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
1965 out_devx:
1966 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX)
1967 mlx5_ib_devx_destroy(dev, context->devx_uid);
1968
1969 out_uars:
1970 deallocate_uars(dev, context);
1971
1972 out_sys_pages:
1973 kfree(bfregi->sys_pages);
1974
1975 out_count:
1976 kfree(bfregi->count);
1977
1978 out_ctx:
1979 return err;
1980 }
1981
1982 static int mlx5_ib_query_ucontext(struct ib_ucontext *ibcontext,
1983 struct uverbs_attr_bundle *attrs)
1984 {
1985 struct mlx5_ib_alloc_ucontext_resp uctx_resp = {};
1986 int ret;
1987
1988 ret = set_ucontext_resp(ibcontext, &uctx_resp);
1989 if (ret)
1990 return ret;
1991
1992 uctx_resp.response_length =
1993 min_t(size_t,
1994 uverbs_attr_get_len(attrs,
1995 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX),
1996 sizeof(uctx_resp));
1997
1998 ret = uverbs_copy_to_struct_or_zero(attrs,
1999 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX,
2000 &uctx_resp,
2001 sizeof(uctx_resp));
2002 return ret;
2003 }
2004
2005 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
2006 {
2007 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2008 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
2009 struct mlx5_bfreg_info *bfregi;
2010
2011 bfregi = &context->bfregi;
2012 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid);
2013
2014 if (context->devx_uid)
2015 mlx5_ib_devx_destroy(dev, context->devx_uid);
2016
2017 deallocate_uars(dev, context);
2018 kfree(bfregi->sys_pages);
2019 kfree(bfregi->count);
2020 }
2021
2022 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
2023 int uar_idx)
2024 {
2025 int fw_uars_per_page;
2026
2027 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
2028
2029 return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
2030 }
2031
2032 static u64 uar_index2paddress(struct mlx5_ib_dev *dev,
2033 int uar_idx)
2034 {
2035 unsigned int fw_uars_per_page;
2036
2037 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
2038 MLX5_UARS_IN_PAGE : 1;
2039
2040 return (dev->mdev->bar_addr + (uar_idx / fw_uars_per_page) * PAGE_SIZE);
2041 }
2042
2043 static int get_command(unsigned long offset)
2044 {
2045 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
2046 }
2047
2048 static int get_arg(unsigned long offset)
2049 {
2050 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
2051 }
2052
2053 static int get_index(unsigned long offset)
2054 {
2055 return get_arg(offset);
2056 }
2057
2058 /* Index resides in an extra byte to enable larger values than 255 */
2059 static int get_extended_index(unsigned long offset)
2060 {
2061 return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
2062 }
2063
2064
2065 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
2066 {
2067 }
2068
2069 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
2070 {
2071 switch (cmd) {
2072 case MLX5_IB_MMAP_WC_PAGE:
2073 return "WC";
2074 case MLX5_IB_MMAP_REGULAR_PAGE:
2075 return "best effort WC";
2076 case MLX5_IB_MMAP_NC_PAGE:
2077 return "NC";
2078 case MLX5_IB_MMAP_DEVICE_MEM:
2079 return "Device Memory";
2080 default:
2081 return NULL;
2082 }
2083 }
2084
2085 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
2086 struct vm_area_struct *vma,
2087 struct mlx5_ib_ucontext *context)
2088 {
2089 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) ||
2090 !(vma->vm_flags & VM_SHARED))
2091 return -EINVAL;
2092
2093 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
2094 return -EOPNOTSUPP;
2095
2096 if (vma->vm_flags & (VM_WRITE | VM_EXEC))
2097 return -EPERM;
2098 vma->vm_flags &= ~VM_MAYWRITE;
2099
2100 if (!dev->mdev->clock_info)
2101 return -EOPNOTSUPP;
2102
2103 return vm_insert_page(vma, vma->vm_start,
2104 virt_to_page(dev->mdev->clock_info));
2105 }
2106
2107 static void mlx5_ib_mmap_free(struct rdma_user_mmap_entry *entry)
2108 {
2109 struct mlx5_user_mmap_entry *mentry = to_mmmap(entry);
2110 struct mlx5_ib_dev *dev = to_mdev(entry->ucontext->device);
2111 struct mlx5_var_table *var_table = &dev->var_table;
2112
2113 switch (mentry->mmap_flag) {
2114 case MLX5_IB_MMAP_TYPE_MEMIC:
2115 case MLX5_IB_MMAP_TYPE_MEMIC_OP:
2116 mlx5_ib_dm_mmap_free(dev, mentry);
2117 break;
2118 case MLX5_IB_MMAP_TYPE_VAR:
2119 mutex_lock(&var_table->bitmap_lock);
2120 clear_bit(mentry->page_idx, var_table->bitmap);
2121 mutex_unlock(&var_table->bitmap_lock);
2122 kfree(mentry);
2123 break;
2124 case MLX5_IB_MMAP_TYPE_UAR_WC:
2125 case MLX5_IB_MMAP_TYPE_UAR_NC:
2126 mlx5_cmd_free_uar(dev->mdev, mentry->page_idx);
2127 kfree(mentry);
2128 break;
2129 default:
2130 WARN_ON(true);
2131 }
2132 }
2133
2134 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
2135 struct vm_area_struct *vma,
2136 struct mlx5_ib_ucontext *context)
2137 {
2138 struct mlx5_bfreg_info *bfregi = &context->bfregi;
2139 int err;
2140 unsigned long idx;
2141 phys_addr_t pfn;
2142 pgprot_t prot;
2143 u32 bfreg_dyn_idx = 0;
2144 u32 uar_index;
2145 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2146 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2147 bfregi->num_static_sys_pages;
2148
2149 if (bfregi->lib_uar_dyn)
2150 return -EINVAL;
2151
2152 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2153 return -EINVAL;
2154
2155 if (dyn_uar)
2156 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2157 else
2158 idx = get_index(vma->vm_pgoff);
2159
2160 if (idx >= max_valid_idx) {
2161 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2162 idx, max_valid_idx);
2163 return -EINVAL;
2164 }
2165
2166 switch (cmd) {
2167 case MLX5_IB_MMAP_WC_PAGE:
2168 case MLX5_IB_MMAP_ALLOC_WC:
2169 case MLX5_IB_MMAP_REGULAR_PAGE:
2170 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2171 prot = pgprot_writecombine(vma->vm_page_prot);
2172 break;
2173 case MLX5_IB_MMAP_NC_PAGE:
2174 prot = pgprot_noncached(vma->vm_page_prot);
2175 break;
2176 default:
2177 return -EINVAL;
2178 }
2179
2180 if (dyn_uar) {
2181 int uars_per_page;
2182
2183 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2184 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2185 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2186 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2187 bfreg_dyn_idx, bfregi->total_num_bfregs);
2188 return -EINVAL;
2189 }
2190
2191 mutex_lock(&bfregi->lock);
2192 /* Fail if uar already allocated, first bfreg index of each
2193 * page holds its count.
2194 */
2195 if (bfregi->count[bfreg_dyn_idx]) {
2196 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2197 mutex_unlock(&bfregi->lock);
2198 return -EINVAL;
2199 }
2200
2201 bfregi->count[bfreg_dyn_idx]++;
2202 mutex_unlock(&bfregi->lock);
2203
2204 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2205 if (err) {
2206 mlx5_ib_warn(dev, "UAR alloc failed\n");
2207 goto free_bfreg;
2208 }
2209 } else {
2210 uar_index = bfregi->sys_pages[idx];
2211 }
2212
2213 pfn = uar_index2pfn(dev, uar_index);
2214 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2215
2216 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE,
2217 prot, NULL);
2218 if (err) {
2219 mlx5_ib_err(dev,
2220 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n",
2221 err, mmap_cmd2str(cmd));
2222 goto err;
2223 }
2224
2225 if (dyn_uar)
2226 bfregi->sys_pages[idx] = uar_index;
2227 return 0;
2228
2229 err:
2230 if (!dyn_uar)
2231 return err;
2232
2233 mlx5_cmd_free_uar(dev->mdev, idx);
2234
2235 free_bfreg:
2236 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2237
2238 return err;
2239 }
2240
2241 static unsigned long mlx5_vma_to_pgoff(struct vm_area_struct *vma)
2242 {
2243 unsigned long idx;
2244 u8 command;
2245
2246 command = get_command(vma->vm_pgoff);
2247 idx = get_extended_index(vma->vm_pgoff);
2248
2249 return (command << 16 | idx);
2250 }
2251
2252 static int mlx5_ib_mmap_offset(struct mlx5_ib_dev *dev,
2253 struct vm_area_struct *vma,
2254 struct ib_ucontext *ucontext)
2255 {
2256 struct mlx5_user_mmap_entry *mentry;
2257 struct rdma_user_mmap_entry *entry;
2258 unsigned long pgoff;
2259 pgprot_t prot;
2260 phys_addr_t pfn;
2261 int ret;
2262
2263 pgoff = mlx5_vma_to_pgoff(vma);
2264 entry = rdma_user_mmap_entry_get_pgoff(ucontext, pgoff);
2265 if (!entry)
2266 return -EINVAL;
2267
2268 mentry = to_mmmap(entry);
2269 pfn = (mentry->address >> PAGE_SHIFT);
2270 if (mentry->mmap_flag == MLX5_IB_MMAP_TYPE_VAR ||
2271 mentry->mmap_flag == MLX5_IB_MMAP_TYPE_UAR_NC)
2272 prot = pgprot_noncached(vma->vm_page_prot);
2273 else
2274 prot = pgprot_writecombine(vma->vm_page_prot);
2275 ret = rdma_user_mmap_io(ucontext, vma, pfn,
2276 entry->npages * PAGE_SIZE,
2277 prot,
2278 entry);
2279 rdma_user_mmap_entry_put(&mentry->rdma_entry);
2280 return ret;
2281 }
2282
2283 static u64 mlx5_entry_to_mmap_offset(struct mlx5_user_mmap_entry *entry)
2284 {
2285 u64 cmd = (entry->rdma_entry.start_pgoff >> 16) & 0xFFFF;
2286 u64 index = entry->rdma_entry.start_pgoff & 0xFFFF;
2287
2288 return (((index >> 8) << 16) | (cmd << MLX5_IB_MMAP_CMD_SHIFT) |
2289 (index & 0xFF)) << PAGE_SHIFT;
2290 }
2291
2292 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2293 {
2294 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2295 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
2296 unsigned long command;
2297 phys_addr_t pfn;
2298
2299 command = get_command(vma->vm_pgoff);
2300 switch (command) {
2301 case MLX5_IB_MMAP_WC_PAGE:
2302 case MLX5_IB_MMAP_ALLOC_WC:
2303 if (!dev->wc_support)
2304 return -EPERM;
2305 fallthrough;
2306 case MLX5_IB_MMAP_NC_PAGE:
2307 case MLX5_IB_MMAP_REGULAR_PAGE:
2308 return uar_mmap(dev, command, vma, context);
2309
2310 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2311 return -ENOSYS;
2312
2313 case MLX5_IB_MMAP_CORE_CLOCK:
2314 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2315 return -EINVAL;
2316
2317 if (vma->vm_flags & VM_WRITE)
2318 return -EPERM;
2319 vma->vm_flags &= ~VM_MAYWRITE;
2320
2321 /* Don't expose to user-space information it shouldn't have */
2322 if (PAGE_SIZE > 4096)
2323 return -EOPNOTSUPP;
2324
2325 pfn = (dev->mdev->iseg_base +
2326 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2327 PAGE_SHIFT;
2328 return rdma_user_mmap_io(&context->ibucontext, vma, pfn,
2329 PAGE_SIZE,
2330 pgprot_noncached(vma->vm_page_prot),
2331 NULL);
2332 case MLX5_IB_MMAP_CLOCK_INFO:
2333 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
2334
2335 default:
2336 return mlx5_ib_mmap_offset(dev, vma, ibcontext);
2337 }
2338
2339 return 0;
2340 }
2341
2342 static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
2343 {
2344 struct mlx5_ib_pd *pd = to_mpd(ibpd);
2345 struct ib_device *ibdev = ibpd->device;
2346 struct mlx5_ib_alloc_pd_resp resp;
2347 int err;
2348 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {};
2349 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {};
2350 u16 uid = 0;
2351 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
2352 udata, struct mlx5_ib_ucontext, ibucontext);
2353
2354 uid = context ? context->devx_uid : 0;
2355 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2356 MLX5_SET(alloc_pd_in, in, uid, uid);
2357 err = mlx5_cmd_exec_inout(to_mdev(ibdev)->mdev, alloc_pd, in, out);
2358 if (err)
2359 return err;
2360
2361 pd->pdn = MLX5_GET(alloc_pd_out, out, pd);
2362 pd->uid = uid;
2363 if (udata) {
2364 resp.pdn = pd->pdn;
2365 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
2366 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid);
2367 return -EFAULT;
2368 }
2369 }
2370
2371 return 0;
2372 }
2373
2374 static int mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata)
2375 {
2376 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2377 struct mlx5_ib_pd *mpd = to_mpd(pd);
2378
2379 return mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid);
2380 }
2381
2382 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2383 {
2384 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2385 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
2386 int err;
2387 u16 uid;
2388
2389 uid = ibqp->pd ?
2390 to_mpd(ibqp->pd)->uid : 0;
2391
2392 if (mqp->flags & IB_QP_CREATE_SOURCE_QPN) {
2393 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
2394 return -EOPNOTSUPP;
2395 }
2396
2397 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
2398 if (err)
2399 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2400 ibqp->qp_num, gid->raw);
2401
2402 return err;
2403 }
2404
2405 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2406 {
2407 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2408 int err;
2409 u16 uid;
2410
2411 uid = ibqp->pd ?
2412 to_mpd(ibqp->pd)->uid : 0;
2413 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
2414 if (err)
2415 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2416 ibqp->qp_num, gid->raw);
2417
2418 return err;
2419 }
2420
2421 static int init_node_data(struct mlx5_ib_dev *dev)
2422 {
2423 int err;
2424
2425 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
2426 if (err)
2427 return err;
2428
2429 dev->mdev->rev_id = dev->mdev->pdev->revision;
2430
2431 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
2432 }
2433
2434 static ssize_t fw_pages_show(struct device *device,
2435 struct device_attribute *attr, char *buf)
2436 {
2437 struct mlx5_ib_dev *dev =
2438 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2439
2440 return sysfs_emit(buf, "%d\n", dev->mdev->priv.fw_pages);
2441 }
2442 static DEVICE_ATTR_RO(fw_pages);
2443
2444 static ssize_t reg_pages_show(struct device *device,
2445 struct device_attribute *attr, char *buf)
2446 {
2447 struct mlx5_ib_dev *dev =
2448 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2449
2450 return sysfs_emit(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
2451 }
2452 static DEVICE_ATTR_RO(reg_pages);
2453
2454 static ssize_t hca_type_show(struct device *device,
2455 struct device_attribute *attr, char *buf)
2456 {
2457 struct mlx5_ib_dev *dev =
2458 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2459
2460 return sysfs_emit(buf, "MT%d\n", dev->mdev->pdev->device);
2461 }
2462 static DEVICE_ATTR_RO(hca_type);
2463
2464 static ssize_t hw_rev_show(struct device *device,
2465 struct device_attribute *attr, char *buf)
2466 {
2467 struct mlx5_ib_dev *dev =
2468 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2469
2470 return sysfs_emit(buf, "%x\n", dev->mdev->rev_id);
2471 }
2472 static DEVICE_ATTR_RO(hw_rev);
2473
2474 static ssize_t board_id_show(struct device *device,
2475 struct device_attribute *attr, char *buf)
2476 {
2477 struct mlx5_ib_dev *dev =
2478 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev);
2479
2480 return sysfs_emit(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
2481 dev->mdev->board_id);
2482 }
2483 static DEVICE_ATTR_RO(board_id);
2484
2485 static struct attribute *mlx5_class_attributes[] = {
2486 &dev_attr_hw_rev.attr,
2487 &dev_attr_hca_type.attr,
2488 &dev_attr_board_id.attr,
2489 &dev_attr_fw_pages.attr,
2490 &dev_attr_reg_pages.attr,
2491 NULL,
2492 };
2493
2494 static const struct attribute_group mlx5_attr_group = {
2495 .attrs = mlx5_class_attributes,
2496 };
2497
2498 static void pkey_change_handler(struct work_struct *work)
2499 {
2500 struct mlx5_ib_port_resources *ports =
2501 container_of(work, struct mlx5_ib_port_resources,
2502 pkey_change_work);
2503
2504 if (!ports->gsi)
2505 /*
2506 * We got this event before device was fully configured
2507 * and MAD registration code wasn't called/finished yet.
2508 */
2509 return;
2510
2511 mlx5_ib_gsi_pkey_change(ports->gsi);
2512 }
2513
2514 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2515 {
2516 struct mlx5_ib_qp *mqp;
2517 struct mlx5_ib_cq *send_mcq, *recv_mcq;
2518 struct mlx5_core_cq *mcq;
2519 struct list_head cq_armed_list;
2520 unsigned long flags_qp;
2521 unsigned long flags_cq;
2522 unsigned long flags;
2523
2524 INIT_LIST_HEAD(&cq_armed_list);
2525
2526 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2527 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2528 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2529 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2530 if (mqp->sq.tail != mqp->sq.head) {
2531 send_mcq = to_mcq(mqp->ibqp.send_cq);
2532 spin_lock_irqsave(&send_mcq->lock, flags_cq);
2533 if (send_mcq->mcq.comp &&
2534 mqp->ibqp.send_cq->comp_handler) {
2535 if (!send_mcq->mcq.reset_notify_added) {
2536 send_mcq->mcq.reset_notify_added = 1;
2537 list_add_tail(&send_mcq->mcq.reset_notify,
2538 &cq_armed_list);
2539 }
2540 }
2541 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2542 }
2543 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2544 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2545 /* no handling is needed for SRQ */
2546 if (!mqp->ibqp.srq) {
2547 if (mqp->rq.tail != mqp->rq.head) {
2548 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2549 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2550 if (recv_mcq->mcq.comp &&
2551 mqp->ibqp.recv_cq->comp_handler) {
2552 if (!recv_mcq->mcq.reset_notify_added) {
2553 recv_mcq->mcq.reset_notify_added = 1;
2554 list_add_tail(&recv_mcq->mcq.reset_notify,
2555 &cq_armed_list);
2556 }
2557 }
2558 spin_unlock_irqrestore(&recv_mcq->lock,
2559 flags_cq);
2560 }
2561 }
2562 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2563 }
2564 /*At that point all inflight post send were put to be executed as of we
2565 * lock/unlock above locks Now need to arm all involved CQs.
2566 */
2567 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2568 mcq->comp(mcq, NULL);
2569 }
2570 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2571 }
2572
2573 static void delay_drop_handler(struct work_struct *work)
2574 {
2575 int err;
2576 struct mlx5_ib_delay_drop *delay_drop =
2577 container_of(work, struct mlx5_ib_delay_drop,
2578 delay_drop_work);
2579
2580 atomic_inc(&delay_drop->events_cnt);
2581
2582 mutex_lock(&delay_drop->lock);
2583 err = mlx5_core_set_delay_drop(delay_drop->dev, delay_drop->timeout);
2584 if (err) {
2585 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
2586 delay_drop->timeout);
2587 delay_drop->activate = false;
2588 }
2589 mutex_unlock(&delay_drop->lock);
2590 }
2591
2592 static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
2593 struct ib_event *ibev)
2594 {
2595 u32 port = (eqe->data.port.port >> 4) & 0xf;
2596
2597 switch (eqe->sub_type) {
2598 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT:
2599 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2600 IB_LINK_LAYER_ETHERNET)
2601 schedule_work(&ibdev->delay_drop.delay_drop_work);
2602 break;
2603 default: /* do nothing */
2604 return;
2605 }
2606 }
2607
2608 static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe,
2609 struct ib_event *ibev)
2610 {
2611 u32 port = (eqe->data.port.port >> 4) & 0xf;
2612
2613 ibev->element.port_num = port;
2614
2615 switch (eqe->sub_type) {
2616 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
2617 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
2618 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
2619 /* In RoCE, port up/down events are handled in
2620 * mlx5_netdev_event().
2621 */
2622 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2623 IB_LINK_LAYER_ETHERNET)
2624 return -EINVAL;
2625
2626 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ?
2627 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
2628 break;
2629
2630 case MLX5_PORT_CHANGE_SUBTYPE_LID:
2631 ibev->event = IB_EVENT_LID_CHANGE;
2632 break;
2633
2634 case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
2635 ibev->event = IB_EVENT_PKEY_CHANGE;
2636 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
2637 break;
2638
2639 case MLX5_PORT_CHANGE_SUBTYPE_GUID:
2640 ibev->event = IB_EVENT_GID_CHANGE;
2641 break;
2642
2643 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
2644 ibev->event = IB_EVENT_CLIENT_REREGISTER;
2645 break;
2646 default:
2647 return -EINVAL;
2648 }
2649
2650 return 0;
2651 }
2652
2653 static void mlx5_ib_handle_event(struct work_struct *_work)
2654 {
2655 struct mlx5_ib_event_work *work =
2656 container_of(_work, struct mlx5_ib_event_work, work);
2657 struct mlx5_ib_dev *ibdev;
2658 struct ib_event ibev;
2659 bool fatal = false;
2660
2661 if (work->is_slave) {
2662 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi);
2663 if (!ibdev)
2664 goto out;
2665 } else {
2666 ibdev = work->dev;
2667 }
2668
2669 switch (work->event) {
2670 case MLX5_DEV_EVENT_SYS_ERROR:
2671 ibev.event = IB_EVENT_DEVICE_FATAL;
2672 mlx5_ib_handle_internal_error(ibdev);
2673 ibev.element.port_num = (u8)(unsigned long)work->param;
2674 fatal = true;
2675 break;
2676 case MLX5_EVENT_TYPE_PORT_CHANGE:
2677 if (handle_port_change(ibdev, work->param, &ibev))
2678 goto out;
2679 break;
2680 case MLX5_EVENT_TYPE_GENERAL_EVENT:
2681 handle_general_event(ibdev, work->param, &ibev);
2682 fallthrough;
2683 default:
2684 goto out;
2685 }
2686
2687 ibev.device = &ibdev->ib_dev;
2688
2689 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) {
2690 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num);
2691 goto out;
2692 }
2693
2694 if (ibdev->ib_active)
2695 ib_dispatch_event(&ibev);
2696
2697 if (fatal)
2698 ibdev->ib_active = false;
2699 out:
2700 kfree(work);
2701 }
2702
2703 static int mlx5_ib_event(struct notifier_block *nb,
2704 unsigned long event, void *param)
2705 {
2706 struct mlx5_ib_event_work *work;
2707
2708 work = kmalloc(sizeof(*work), GFP_ATOMIC);
2709 if (!work)
2710 return NOTIFY_DONE;
2711
2712 INIT_WORK(&work->work, mlx5_ib_handle_event);
2713 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events);
2714 work->is_slave = false;
2715 work->param = param;
2716 work->event = event;
2717
2718 queue_work(mlx5_ib_event_wq, &work->work);
2719
2720 return NOTIFY_OK;
2721 }
2722
2723 static int mlx5_ib_event_slave_port(struct notifier_block *nb,
2724 unsigned long event, void *param)
2725 {
2726 struct mlx5_ib_event_work *work;
2727
2728 work = kmalloc(sizeof(*work), GFP_ATOMIC);
2729 if (!work)
2730 return NOTIFY_DONE;
2731
2732 INIT_WORK(&work->work, mlx5_ib_handle_event);
2733 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events);
2734 work->is_slave = true;
2735 work->param = param;
2736 work->event = event;
2737 queue_work(mlx5_ib_event_wq, &work->work);
2738
2739 return NOTIFY_OK;
2740 }
2741
2742 static int set_has_smi_cap(struct mlx5_ib_dev *dev)
2743 {
2744 struct mlx5_hca_vport_context vport_ctx;
2745 int err;
2746 int port;
2747
2748 for (port = 1; port <= ARRAY_SIZE(dev->port_caps); port++) {
2749 dev->port_caps[port - 1].has_smi = false;
2750 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
2751 MLX5_CAP_PORT_TYPE_IB) {
2752 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
2753 err = mlx5_query_hca_vport_context(dev->mdev, 0,
2754 port, 0,
2755 &vport_ctx);
2756 if (err) {
2757 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
2758 port, err);
2759 return err;
2760 }
2761 dev->port_caps[port - 1].has_smi =
2762 vport_ctx.has_smi;
2763 } else {
2764 dev->port_caps[port - 1].has_smi = true;
2765 }
2766 }
2767 }
2768 return 0;
2769 }
2770
2771 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2772 {
2773 unsigned int port;
2774
2775 rdma_for_each_port (&dev->ib_dev, port)
2776 mlx5_query_ext_port_caps(dev, port);
2777 }
2778
2779 static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
2780 {
2781 switch (umr_fence_cap) {
2782 case MLX5_CAP_UMR_FENCE_NONE:
2783 return MLX5_FENCE_MODE_NONE;
2784 case MLX5_CAP_UMR_FENCE_SMALL:
2785 return MLX5_FENCE_MODE_INITIATOR_SMALL;
2786 default:
2787 return MLX5_FENCE_MODE_STRONG_ORDERING;
2788 }
2789 }
2790
2791 static int mlx5_ib_dev_res_init(struct mlx5_ib_dev *dev)
2792 {
2793 struct mlx5_ib_resources *devr = &dev->devr;
2794 struct ib_srq_init_attr attr;
2795 struct ib_device *ibdev;
2796 struct ib_cq_init_attr cq_attr = {.cqe = 1};
2797 int port;
2798 int ret = 0;
2799
2800 ibdev = &dev->ib_dev;
2801
2802 if (!MLX5_CAP_GEN(dev->mdev, xrc))
2803 return -EOPNOTSUPP;
2804
2805 devr->p0 = rdma_zalloc_drv_obj(ibdev, ib_pd);
2806 if (!devr->p0)
2807 return -ENOMEM;
2808
2809 devr->p0->device = ibdev;
2810 devr->p0->uobject = NULL;
2811 atomic_set(&devr->p0->usecnt, 0);
2812
2813 ret = mlx5_ib_alloc_pd(devr->p0, NULL);
2814 if (ret)
2815 goto error0;
2816
2817 devr->c0 = rdma_zalloc_drv_obj(ibdev, ib_cq);
2818 if (!devr->c0) {
2819 ret = -ENOMEM;
2820 goto error1;
2821 }
2822
2823 devr->c0->device = &dev->ib_dev;
2824 atomic_set(&devr->c0->usecnt, 0);
2825
2826 ret = mlx5_ib_create_cq(devr->c0, &cq_attr, NULL);
2827 if (ret)
2828 goto err_create_cq;
2829
2830 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn0, 0);
2831 if (ret)
2832 goto error2;
2833
2834 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn1, 0);
2835 if (ret)
2836 goto error3;
2837
2838 memset(&attr, 0, sizeof(attr));
2839 attr.attr.max_sge = 1;
2840 attr.attr.max_wr = 1;
2841 attr.srq_type = IB_SRQT_XRC;
2842 attr.ext.cq = devr->c0;
2843
2844 devr->s0 = rdma_zalloc_drv_obj(ibdev, ib_srq);
2845 if (!devr->s0) {
2846 ret = -ENOMEM;
2847 goto error4;
2848 }
2849
2850 devr->s0->device = &dev->ib_dev;
2851 devr->s0->pd = devr->p0;
2852 devr->s0->srq_type = IB_SRQT_XRC;
2853 devr->s0->ext.cq = devr->c0;
2854 ret = mlx5_ib_create_srq(devr->s0, &attr, NULL);
2855 if (ret)
2856 goto err_create;
2857
2858 atomic_inc(&devr->s0->ext.cq->usecnt);
2859 atomic_inc(&devr->p0->usecnt);
2860 atomic_set(&devr->s0->usecnt, 0);
2861
2862 memset(&attr, 0, sizeof(attr));
2863 attr.attr.max_sge = 1;
2864 attr.attr.max_wr = 1;
2865 attr.srq_type = IB_SRQT_BASIC;
2866 devr->s1 = rdma_zalloc_drv_obj(ibdev, ib_srq);
2867 if (!devr->s1) {
2868 ret = -ENOMEM;
2869 goto error5;
2870 }
2871
2872 devr->s1->device = &dev->ib_dev;
2873 devr->s1->pd = devr->p0;
2874 devr->s1->srq_type = IB_SRQT_BASIC;
2875 devr->s1->ext.cq = devr->c0;
2876
2877 ret = mlx5_ib_create_srq(devr->s1, &attr, NULL);
2878 if (ret)
2879 goto error6;
2880
2881 atomic_inc(&devr->p0->usecnt);
2882 atomic_set(&devr->s1->usecnt, 0);
2883
2884 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port)
2885 INIT_WORK(&devr->ports[port].pkey_change_work,
2886 pkey_change_handler);
2887
2888 return 0;
2889
2890 error6:
2891 kfree(devr->s1);
2892 error5:
2893 mlx5_ib_destroy_srq(devr->s0, NULL);
2894 err_create:
2895 kfree(devr->s0);
2896 error4:
2897 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0);
2898 error3:
2899 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0);
2900 error2:
2901 mlx5_ib_destroy_cq(devr->c0, NULL);
2902 err_create_cq:
2903 kfree(devr->c0);
2904 error1:
2905 mlx5_ib_dealloc_pd(devr->p0, NULL);
2906 error0:
2907 kfree(devr->p0);
2908 return ret;
2909 }
2910
2911 static void mlx5_ib_dev_res_cleanup(struct mlx5_ib_dev *dev)
2912 {
2913 struct mlx5_ib_resources *devr = &dev->devr;
2914 int port;
2915
2916 /*
2917 * Make sure no change P_Key work items are still executing.
2918 *
2919 * At this stage, the mlx5_ib_event should be unregistered
2920 * and it ensures that no new works are added.
2921 */
2922 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port)
2923 cancel_work_sync(&devr->ports[port].pkey_change_work);
2924
2925 mlx5_ib_destroy_srq(devr->s1, NULL);
2926 kfree(devr->s1);
2927 mlx5_ib_destroy_srq(devr->s0, NULL);
2928 kfree(devr->s0);
2929 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0);
2930 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0);
2931 mlx5_ib_destroy_cq(devr->c0, NULL);
2932 kfree(devr->c0);
2933 mlx5_ib_dealloc_pd(devr->p0, NULL);
2934 kfree(devr->p0);
2935 }
2936
2937 static u32 get_core_cap_flags(struct ib_device *ibdev,
2938 struct mlx5_hca_vport_context *rep)
2939 {
2940 struct mlx5_ib_dev *dev = to_mdev(ibdev);
2941 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
2942 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
2943 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
2944 bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
2945 u32 ret = 0;
2946
2947 if (rep->grh_required)
2948 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED;
2949
2950 if (ll == IB_LINK_LAYER_INFINIBAND)
2951 return ret | RDMA_CORE_PORT_IBA_IB;
2952
2953 if (raw_support)
2954 ret |= RDMA_CORE_PORT_RAW_PACKET;
2955
2956 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
2957 return ret;
2958
2959 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
2960 return ret;
2961
2962 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
2963 ret |= RDMA_CORE_PORT_IBA_ROCE;
2964
2965 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
2966 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2967
2968 return ret;
2969 }
2970
2971 static int mlx5_port_immutable(struct ib_device *ibdev, u32 port_num,
2972 struct ib_port_immutable *immutable)
2973 {
2974 struct ib_port_attr attr;
2975 struct mlx5_ib_dev *dev = to_mdev(ibdev);
2976 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
2977 struct mlx5_hca_vport_context rep = {0};
2978 int err;
2979
2980 err = ib_query_port(ibdev, port_num, &attr);
2981 if (err)
2982 return err;
2983
2984 if (ll == IB_LINK_LAYER_INFINIBAND) {
2985 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0,
2986 &rep);
2987 if (err)
2988 return err;
2989 }
2990
2991 immutable->pkey_tbl_len = attr.pkey_tbl_len;
2992 immutable->gid_tbl_len = attr.gid_tbl_len;
2993 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep);
2994 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2995
2996 return 0;
2997 }
2998
2999 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u32 port_num,
3000 struct ib_port_immutable *immutable)
3001 {
3002 struct ib_port_attr attr;
3003 int err;
3004
3005 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
3006
3007 err = ib_query_port(ibdev, port_num, &attr);
3008 if (err)
3009 return err;
3010
3011 immutable->pkey_tbl_len = attr.pkey_tbl_len;
3012 immutable->gid_tbl_len = attr.gid_tbl_len;
3013 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
3014
3015 return 0;
3016 }
3017
3018 static void get_dev_fw_str(struct ib_device *ibdev, char *str)
3019 {
3020 struct mlx5_ib_dev *dev =
3021 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
3022 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
3023 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
3024 fw_rev_sub(dev->mdev));
3025 }
3026
3027 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
3028 {
3029 struct mlx5_core_dev *mdev = dev->mdev;
3030 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
3031 MLX5_FLOW_NAMESPACE_LAG);
3032 struct mlx5_flow_table *ft;
3033 int err;
3034
3035 if (!ns || !mlx5_lag_is_roce(mdev))
3036 return 0;
3037
3038 err = mlx5_cmd_create_vport_lag(mdev);
3039 if (err)
3040 return err;
3041
3042 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
3043 if (IS_ERR(ft)) {
3044 err = PTR_ERR(ft);
3045 goto err_destroy_vport_lag;
3046 }
3047
3048 dev->flow_db->lag_demux_ft = ft;
3049 dev->lag_active = true;
3050 return 0;
3051
3052 err_destroy_vport_lag:
3053 mlx5_cmd_destroy_vport_lag(mdev);
3054 return err;
3055 }
3056
3057 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
3058 {
3059 struct mlx5_core_dev *mdev = dev->mdev;
3060
3061 if (dev->lag_active) {
3062 dev->lag_active = false;
3063
3064 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
3065 dev->flow_db->lag_demux_ft = NULL;
3066
3067 mlx5_cmd_destroy_vport_lag(mdev);
3068 }
3069 }
3070
3071 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u32 port_num)
3072 {
3073 int err;
3074
3075 dev->port[port_num].roce.nb.notifier_call = mlx5_netdev_event;
3076 err = register_netdevice_notifier(&dev->port[port_num].roce.nb);
3077 if (err) {
3078 dev->port[port_num].roce.nb.notifier_call = NULL;
3079 return err;
3080 }
3081
3082 return 0;
3083 }
3084
3085 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u32 port_num)
3086 {
3087 if (dev->port[port_num].roce.nb.notifier_call) {
3088 unregister_netdevice_notifier(&dev->port[port_num].roce.nb);
3089 dev->port[port_num].roce.nb.notifier_call = NULL;
3090 }
3091 }
3092
3093 static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
3094 {
3095 int err;
3096
3097 err = mlx5_nic_vport_enable_roce(dev->mdev);
3098 if (err)
3099 return err;
3100
3101 err = mlx5_eth_lag_init(dev);
3102 if (err)
3103 goto err_disable_roce;
3104
3105 return 0;
3106
3107 err_disable_roce:
3108 mlx5_nic_vport_disable_roce(dev->mdev);
3109
3110 return err;
3111 }
3112
3113 static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
3114 {
3115 mlx5_eth_lag_cleanup(dev);
3116 mlx5_nic_vport_disable_roce(dev->mdev);
3117 }
3118
3119 static int mlx5_ib_rn_get_params(struct ib_device *device, u32 port_num,
3120 enum rdma_netdev_t type,
3121 struct rdma_netdev_alloc_params *params)
3122 {
3123 if (type != RDMA_NETDEV_IPOIB)
3124 return -EOPNOTSUPP;
3125
3126 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params);
3127 }
3128
3129 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
3130 size_t count, loff_t *pos)
3131 {
3132 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
3133 char lbuf[20];
3134 int len;
3135
3136 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
3137 return simple_read_from_buffer(buf, count, pos, lbuf, len);
3138 }
3139
3140 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
3141 size_t count, loff_t *pos)
3142 {
3143 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
3144 u32 timeout;
3145 u32 var;
3146
3147 if (kstrtouint_from_user(buf, count, 0, &var))
3148 return -EFAULT;
3149
3150 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
3151 1000);
3152 if (timeout != var)
3153 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
3154 timeout);
3155
3156 delay_drop->timeout = timeout;
3157
3158 return count;
3159 }
3160
3161 static const struct file_operations fops_delay_drop_timeout = {
3162 .owner = THIS_MODULE,
3163 .open = simple_open,
3164 .write = delay_drop_timeout_write,
3165 .read = delay_drop_timeout_read,
3166 };
3167
3168 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
3169 struct mlx5_ib_multiport_info *mpi)
3170 {
3171 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
3172 struct mlx5_ib_port *port = &ibdev->port[port_num];
3173 int comps;
3174 int err;
3175 int i;
3176
3177 lockdep_assert_held(&mlx5_ib_multiport_mutex);
3178
3179 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
3180
3181 spin_lock(&port->mp.mpi_lock);
3182 if (!mpi->ibdev) {
3183 spin_unlock(&port->mp.mpi_lock);
3184 return;
3185 }
3186
3187 mpi->ibdev = NULL;
3188
3189 spin_unlock(&port->mp.mpi_lock);
3190 if (mpi->mdev_events.notifier_call)
3191 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events);
3192 mpi->mdev_events.notifier_call = NULL;
3193 mlx5_remove_netdev_notifier(ibdev, port_num);
3194 spin_lock(&port->mp.mpi_lock);
3195
3196 comps = mpi->mdev_refcnt;
3197 if (comps) {
3198 mpi->unaffiliate = true;
3199 init_completion(&mpi->unref_comp);
3200 spin_unlock(&port->mp.mpi_lock);
3201
3202 for (i = 0; i < comps; i++)
3203 wait_for_completion(&mpi->unref_comp);
3204
3205 spin_lock(&port->mp.mpi_lock);
3206 mpi->unaffiliate = false;
3207 }
3208
3209 port->mp.mpi = NULL;
3210
3211 spin_unlock(&port->mp.mpi_lock);
3212
3213 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
3214
3215 mlx5_ib_dbg(ibdev, "unaffiliated port %u\n", port_num + 1);
3216 /* Log an error, still needed to cleanup the pointers and add
3217 * it back to the list.
3218 */
3219 if (err)
3220 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
3221 port_num + 1);
3222
3223 ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN;
3224 }
3225
3226 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
3227 struct mlx5_ib_multiport_info *mpi)
3228 {
3229 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
3230 int err;
3231
3232 lockdep_assert_held(&mlx5_ib_multiport_mutex);
3233
3234 spin_lock(&ibdev->port[port_num].mp.mpi_lock);
3235 if (ibdev->port[port_num].mp.mpi) {
3236 mlx5_ib_dbg(ibdev, "port %u already affiliated.\n",
3237 port_num + 1);
3238 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
3239 return false;
3240 }
3241
3242 ibdev->port[port_num].mp.mpi = mpi;
3243 mpi->ibdev = ibdev;
3244 mpi->mdev_events.notifier_call = NULL;
3245 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
3246
3247 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
3248 if (err)
3249 goto unbind;
3250
3251 err = mlx5_add_netdev_notifier(ibdev, port_num);
3252 if (err) {
3253 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
3254 port_num + 1);
3255 goto unbind;
3256 }
3257
3258 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port;
3259 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events);
3260
3261 mlx5_ib_init_cong_debugfs(ibdev, port_num);
3262
3263 return true;
3264
3265 unbind:
3266 mlx5_ib_unbind_slave_port(ibdev, mpi);
3267 return false;
3268 }
3269
3270 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
3271 {
3272 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3273 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
3274 port_num + 1);
3275 struct mlx5_ib_multiport_info *mpi;
3276 int err;
3277 u32 i;
3278
3279 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
3280 return 0;
3281
3282 err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
3283 &dev->sys_image_guid);
3284 if (err)
3285 return err;
3286
3287 err = mlx5_nic_vport_enable_roce(dev->mdev);
3288 if (err)
3289 return err;
3290
3291 mutex_lock(&mlx5_ib_multiport_mutex);
3292 for (i = 0; i < dev->num_ports; i++) {
3293 bool bound = false;
3294
3295 /* build a stub multiport info struct for the native port. */
3296 if (i == port_num) {
3297 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
3298 if (!mpi) {
3299 mutex_unlock(&mlx5_ib_multiport_mutex);
3300 mlx5_nic_vport_disable_roce(dev->mdev);
3301 return -ENOMEM;
3302 }
3303
3304 mpi->is_master = true;
3305 mpi->mdev = dev->mdev;
3306 mpi->sys_image_guid = dev->sys_image_guid;
3307 dev->port[i].mp.mpi = mpi;
3308 mpi->ibdev = dev;
3309 mpi = NULL;
3310 continue;
3311 }
3312
3313 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
3314 list) {
3315 if (dev->sys_image_guid == mpi->sys_image_guid &&
3316 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
3317 bound = mlx5_ib_bind_slave_port(dev, mpi);
3318 }
3319
3320 if (bound) {
3321 dev_dbg(mpi->mdev->device,
3322 "removing port from unaffiliated list.\n");
3323 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
3324 list_del(&mpi->list);
3325 break;
3326 }
3327 }
3328 if (!bound)
3329 mlx5_ib_dbg(dev, "no free port found for port %d\n",
3330 i + 1);
3331 }
3332
3333 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
3334 mutex_unlock(&mlx5_ib_multiport_mutex);
3335 return err;
3336 }
3337
3338 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
3339 {
3340 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3341 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
3342 port_num + 1);
3343 u32 i;
3344
3345 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
3346 return;
3347
3348 mutex_lock(&mlx5_ib_multiport_mutex);
3349 for (i = 0; i < dev->num_ports; i++) {
3350 if (dev->port[i].mp.mpi) {
3351 /* Destroy the native port stub */
3352 if (i == port_num) {
3353 kfree(dev->port[i].mp.mpi);
3354 dev->port[i].mp.mpi = NULL;
3355 } else {
3356 mlx5_ib_dbg(dev, "unbinding port_num: %u\n",
3357 i + 1);
3358 list_add_tail(&dev->port[i].mp.mpi->list,
3359 &mlx5_ib_unaffiliated_port_list);
3360 mlx5_ib_unbind_slave_port(dev,
3361 dev->port[i].mp.mpi);
3362 }
3363 }
3364 }
3365
3366 mlx5_ib_dbg(dev, "removing from devlist\n");
3367 list_del(&dev->ib_dev_list);
3368 mutex_unlock(&mlx5_ib_multiport_mutex);
3369
3370 mlx5_nic_vport_disable_roce(dev->mdev);
3371 }
3372
3373 static int mmap_obj_cleanup(struct ib_uobject *uobject,
3374 enum rdma_remove_reason why,
3375 struct uverbs_attr_bundle *attrs)
3376 {
3377 struct mlx5_user_mmap_entry *obj = uobject->object;
3378
3379 rdma_user_mmap_entry_remove(&obj->rdma_entry);
3380 return 0;
3381 }
3382
3383 static int mlx5_rdma_user_mmap_entry_insert(struct mlx5_ib_ucontext *c,
3384 struct mlx5_user_mmap_entry *entry,
3385 size_t length)
3386 {
3387 return rdma_user_mmap_entry_insert_range(
3388 &c->ibucontext, &entry->rdma_entry, length,
3389 (MLX5_IB_MMAP_OFFSET_START << 16),
3390 ((MLX5_IB_MMAP_OFFSET_END << 16) + (1UL << 16) - 1));
3391 }
3392
3393 static struct mlx5_user_mmap_entry *
3394 alloc_var_entry(struct mlx5_ib_ucontext *c)
3395 {
3396 struct mlx5_user_mmap_entry *entry;
3397 struct mlx5_var_table *var_table;
3398 u32 page_idx;
3399 int err;
3400
3401 var_table = &to_mdev(c->ibucontext.device)->var_table;
3402 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
3403 if (!entry)
3404 return ERR_PTR(-ENOMEM);
3405
3406 mutex_lock(&var_table->bitmap_lock);
3407 page_idx = find_first_zero_bit(var_table->bitmap,
3408 var_table->num_var_hw_entries);
3409 if (page_idx >= var_table->num_var_hw_entries) {
3410 err = -ENOSPC;
3411 mutex_unlock(&var_table->bitmap_lock);
3412 goto end;
3413 }
3414
3415 set_bit(page_idx, var_table->bitmap);
3416 mutex_unlock(&var_table->bitmap_lock);
3417
3418 entry->address = var_table->hw_start_addr +
3419 (page_idx * var_table->stride_size);
3420 entry->page_idx = page_idx;
3421 entry->mmap_flag = MLX5_IB_MMAP_TYPE_VAR;
3422
3423 err = mlx5_rdma_user_mmap_entry_insert(c, entry,
3424 var_table->stride_size);
3425 if (err)
3426 goto err_insert;
3427
3428 return entry;
3429
3430 err_insert:
3431 mutex_lock(&var_table->bitmap_lock);
3432 clear_bit(page_idx, var_table->bitmap);
3433 mutex_unlock(&var_table->bitmap_lock);
3434 end:
3435 kfree(entry);
3436 return ERR_PTR(err);
3437 }
3438
3439 static int UVERBS_HANDLER(MLX5_IB_METHOD_VAR_OBJ_ALLOC)(
3440 struct uverbs_attr_bundle *attrs)
3441 {
3442 struct ib_uobject *uobj = uverbs_attr_get_uobject(
3443 attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE);
3444 struct mlx5_ib_ucontext *c;
3445 struct mlx5_user_mmap_entry *entry;
3446 u64 mmap_offset;
3447 u32 length;
3448 int err;
3449
3450 c = to_mucontext(ib_uverbs_get_ucontext(attrs));
3451 if (IS_ERR(c))
3452 return PTR_ERR(c);
3453
3454 entry = alloc_var_entry(c);
3455 if (IS_ERR(entry))
3456 return PTR_ERR(entry);
3457
3458 mmap_offset = mlx5_entry_to_mmap_offset(entry);
3459 length = entry->rdma_entry.npages * PAGE_SIZE;
3460 uobj->object = entry;
3461 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE);
3462
3463 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET,
3464 &mmap_offset, sizeof(mmap_offset));
3465 if (err)
3466 return err;
3467
3468 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID,
3469 &entry->page_idx, sizeof(entry->page_idx));
3470 if (err)
3471 return err;
3472
3473 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH,
3474 &length, sizeof(length));
3475 return err;
3476 }
3477
3478 DECLARE_UVERBS_NAMED_METHOD(
3479 MLX5_IB_METHOD_VAR_OBJ_ALLOC,
3480 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE,
3481 MLX5_IB_OBJECT_VAR,
3482 UVERBS_ACCESS_NEW,
3483 UA_MANDATORY),
3484 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID,
3485 UVERBS_ATTR_TYPE(u32),
3486 UA_MANDATORY),
3487 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH,
3488 UVERBS_ATTR_TYPE(u32),
3489 UA_MANDATORY),
3490 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET,
3491 UVERBS_ATTR_TYPE(u64),
3492 UA_MANDATORY));
3493
3494 DECLARE_UVERBS_NAMED_METHOD_DESTROY(
3495 MLX5_IB_METHOD_VAR_OBJ_DESTROY,
3496 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_DESTROY_HANDLE,
3497 MLX5_IB_OBJECT_VAR,
3498 UVERBS_ACCESS_DESTROY,
3499 UA_MANDATORY));
3500
3501 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_VAR,
3502 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup),
3503 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_ALLOC),
3504 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_DESTROY));
3505
3506 static bool var_is_supported(struct ib_device *device)
3507 {
3508 struct mlx5_ib_dev *dev = to_mdev(device);
3509
3510 return (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
3511 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q);
3512 }
3513
3514 static struct mlx5_user_mmap_entry *
3515 alloc_uar_entry(struct mlx5_ib_ucontext *c,
3516 enum mlx5_ib_uapi_uar_alloc_type alloc_type)
3517 {
3518 struct mlx5_user_mmap_entry *entry;
3519 struct mlx5_ib_dev *dev;
3520 u32 uar_index;
3521 int err;
3522
3523 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
3524 if (!entry)
3525 return ERR_PTR(-ENOMEM);
3526
3527 dev = to_mdev(c->ibucontext.device);
3528 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
3529 if (err)
3530 goto end;
3531
3532 entry->page_idx = uar_index;
3533 entry->address = uar_index2paddress(dev, uar_index);
3534 if (alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF)
3535 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_WC;
3536 else
3537 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_NC;
3538
3539 err = mlx5_rdma_user_mmap_entry_insert(c, entry, PAGE_SIZE);
3540 if (err)
3541 goto err_insert;
3542
3543 return entry;
3544
3545 err_insert:
3546 mlx5_cmd_free_uar(dev->mdev, uar_index);
3547 end:
3548 kfree(entry);
3549 return ERR_PTR(err);
3550 }
3551
3552 static int UVERBS_HANDLER(MLX5_IB_METHOD_UAR_OBJ_ALLOC)(
3553 struct uverbs_attr_bundle *attrs)
3554 {
3555 struct ib_uobject *uobj = uverbs_attr_get_uobject(
3556 attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE);
3557 enum mlx5_ib_uapi_uar_alloc_type alloc_type;
3558 struct mlx5_ib_ucontext *c;
3559 struct mlx5_user_mmap_entry *entry;
3560 u64 mmap_offset;
3561 u32 length;
3562 int err;
3563
3564 c = to_mucontext(ib_uverbs_get_ucontext(attrs));
3565 if (IS_ERR(c))
3566 return PTR_ERR(c);
3567
3568 err = uverbs_get_const(&alloc_type, attrs,
3569 MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE);
3570 if (err)
3571 return err;
3572
3573 if (alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF &&
3574 alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC)
3575 return -EOPNOTSUPP;
3576
3577 if (!to_mdev(c->ibucontext.device)->wc_support &&
3578 alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF)
3579 return -EOPNOTSUPP;
3580
3581 entry = alloc_uar_entry(c, alloc_type);
3582 if (IS_ERR(entry))
3583 return PTR_ERR(entry);
3584
3585 mmap_offset = mlx5_entry_to_mmap_offset(entry);
3586 length = entry->rdma_entry.npages * PAGE_SIZE;
3587 uobj->object = entry;
3588 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE);
3589
3590 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET,
3591 &mmap_offset, sizeof(mmap_offset));
3592 if (err)
3593 return err;
3594
3595 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID,
3596 &entry->page_idx, sizeof(entry->page_idx));
3597 if (err)
3598 return err;
3599
3600 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH,
3601 &length, sizeof(length));
3602 return err;
3603 }
3604
3605 DECLARE_UVERBS_NAMED_METHOD(
3606 MLX5_IB_METHOD_UAR_OBJ_ALLOC,
3607 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE,
3608 MLX5_IB_OBJECT_UAR,
3609 UVERBS_ACCESS_NEW,
3610 UA_MANDATORY),
3611 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE,
3612 enum mlx5_ib_uapi_uar_alloc_type,
3613 UA_MANDATORY),
3614 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID,
3615 UVERBS_ATTR_TYPE(u32),
3616 UA_MANDATORY),
3617 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH,
3618 UVERBS_ATTR_TYPE(u32),
3619 UA_MANDATORY),
3620 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET,
3621 UVERBS_ATTR_TYPE(u64),
3622 UA_MANDATORY));
3623
3624 DECLARE_UVERBS_NAMED_METHOD_DESTROY(
3625 MLX5_IB_METHOD_UAR_OBJ_DESTROY,
3626 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_DESTROY_HANDLE,
3627 MLX5_IB_OBJECT_UAR,
3628 UVERBS_ACCESS_DESTROY,
3629 UA_MANDATORY));
3630
3631 DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_UAR,
3632 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup),
3633 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_ALLOC),
3634 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_DESTROY));
3635
3636 ADD_UVERBS_ATTRIBUTES_SIMPLE(
3637 mlx5_ib_flow_action,
3638 UVERBS_OBJECT_FLOW_ACTION,
3639 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE,
3640 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
3641 enum mlx5_ib_uapi_flow_action_flags));
3642
3643 ADD_UVERBS_ATTRIBUTES_SIMPLE(
3644 mlx5_ib_query_context,
3645 UVERBS_OBJECT_DEVICE,
3646 UVERBS_METHOD_QUERY_CONTEXT,
3647 UVERBS_ATTR_PTR_OUT(
3648 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX,
3649 UVERBS_ATTR_STRUCT(struct mlx5_ib_alloc_ucontext_resp,
3650 dump_fill_mkey),
3651 UA_MANDATORY));
3652
3653 static const struct uapi_definition mlx5_ib_defs[] = {
3654 UAPI_DEF_CHAIN(mlx5_ib_devx_defs),
3655 UAPI_DEF_CHAIN(mlx5_ib_flow_defs),
3656 UAPI_DEF_CHAIN(mlx5_ib_qos_defs),
3657 UAPI_DEF_CHAIN(mlx5_ib_std_types_defs),
3658 UAPI_DEF_CHAIN(mlx5_ib_dm_defs),
3659
3660 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_FLOW_ACTION,
3661 &mlx5_ib_flow_action),
3662 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DEVICE, &mlx5_ib_query_context),
3663 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_VAR,
3664 UAPI_DEF_IS_OBJ_SUPPORTED(var_is_supported)),
3665 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_UAR),
3666 {}
3667 };
3668
3669 static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
3670 {
3671 mlx5_ib_cleanup_multiport_master(dev);
3672 WARN_ON(!xa_empty(&dev->odp_mkeys));
3673 mutex_destroy(&dev->cap_mask_mutex);
3674 WARN_ON(!xa_empty(&dev->sig_mrs));
3675 WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES));
3676 }
3677
3678 static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
3679 {
3680 struct mlx5_core_dev *mdev = dev->mdev;
3681 int err;
3682 int i;
3683
3684 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
3685 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
3686 dev->ib_dev.phys_port_cnt = dev->num_ports;
3687 dev->ib_dev.dev.parent = mdev->device;
3688 dev->ib_dev.lag_flags = RDMA_LAG_FLAGS_HASH_ALL_SLAVES;
3689
3690 for (i = 0; i < dev->num_ports; i++) {
3691 spin_lock_init(&dev->port[i].mp.mpi_lock);
3692 rwlock_init(&dev->port[i].roce.netdev_lock);
3693 dev->port[i].roce.dev = dev;
3694 dev->port[i].roce.native_port_num = i + 1;
3695 dev->port[i].roce.last_port_state = IB_PORT_DOWN;
3696 }
3697
3698 err = mlx5_ib_init_multiport_master(dev);
3699 if (err)
3700 return err;
3701
3702 err = set_has_smi_cap(dev);
3703 if (err)
3704 goto err_mp;
3705
3706 err = mlx5_query_max_pkeys(&dev->ib_dev, &dev->pkey_table_len);
3707 if (err)
3708 goto err_mp;
3709
3710 if (mlx5_use_mad_ifc(dev))
3711 get_ext_port_caps(dev);
3712
3713 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_count(mdev);
3714
3715 mutex_init(&dev->cap_mask_mutex);
3716 INIT_LIST_HEAD(&dev->qp_list);
3717 spin_lock_init(&dev->reset_flow_resource_lock);
3718 xa_init(&dev->odp_mkeys);
3719 xa_init(&dev->sig_mrs);
3720 atomic_set(&dev->mkey_var, 0);
3721
3722 spin_lock_init(&dev->dm.lock);
3723 dev->dm.dev = mdev;
3724 return 0;
3725
3726 err_mp:
3727 mlx5_ib_cleanup_multiport_master(dev);
3728 return err;
3729 }
3730
3731 static int mlx5_ib_enable_driver(struct ib_device *dev)
3732 {
3733 struct mlx5_ib_dev *mdev = to_mdev(dev);
3734 int ret;
3735
3736 ret = mlx5_ib_test_wc(mdev);
3737 mlx5_ib_dbg(mdev, "Write-Combining %s",
3738 mdev->wc_support ? "supported" : "not supported");
3739
3740 return ret;
3741 }
3742
3743 static const struct ib_device_ops mlx5_ib_dev_ops = {
3744 .owner = THIS_MODULE,
3745 .driver_id = RDMA_DRIVER_MLX5,
3746 .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION,
3747
3748 .add_gid = mlx5_ib_add_gid,
3749 .alloc_mr = mlx5_ib_alloc_mr,
3750 .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity,
3751 .alloc_pd = mlx5_ib_alloc_pd,
3752 .alloc_ucontext = mlx5_ib_alloc_ucontext,
3753 .attach_mcast = mlx5_ib_mcg_attach,
3754 .check_mr_status = mlx5_ib_check_mr_status,
3755 .create_ah = mlx5_ib_create_ah,
3756 .create_cq = mlx5_ib_create_cq,
3757 .create_qp = mlx5_ib_create_qp,
3758 .create_srq = mlx5_ib_create_srq,
3759 .create_user_ah = mlx5_ib_create_ah,
3760 .dealloc_pd = mlx5_ib_dealloc_pd,
3761 .dealloc_ucontext = mlx5_ib_dealloc_ucontext,
3762 .del_gid = mlx5_ib_del_gid,
3763 .dereg_mr = mlx5_ib_dereg_mr,
3764 .destroy_ah = mlx5_ib_destroy_ah,
3765 .destroy_cq = mlx5_ib_destroy_cq,
3766 .destroy_qp = mlx5_ib_destroy_qp,
3767 .destroy_srq = mlx5_ib_destroy_srq,
3768 .detach_mcast = mlx5_ib_mcg_detach,
3769 .disassociate_ucontext = mlx5_ib_disassociate_ucontext,
3770 .drain_rq = mlx5_ib_drain_rq,
3771 .drain_sq = mlx5_ib_drain_sq,
3772 .device_group = &mlx5_attr_group,
3773 .enable_driver = mlx5_ib_enable_driver,
3774 .get_dev_fw_str = get_dev_fw_str,
3775 .get_dma_mr = mlx5_ib_get_dma_mr,
3776 .get_link_layer = mlx5_ib_port_link_layer,
3777 .map_mr_sg = mlx5_ib_map_mr_sg,
3778 .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi,
3779 .mmap = mlx5_ib_mmap,
3780 .mmap_free = mlx5_ib_mmap_free,
3781 .modify_cq = mlx5_ib_modify_cq,
3782 .modify_device = mlx5_ib_modify_device,
3783 .modify_port = mlx5_ib_modify_port,
3784 .modify_qp = mlx5_ib_modify_qp,
3785 .modify_srq = mlx5_ib_modify_srq,
3786 .poll_cq = mlx5_ib_poll_cq,
3787 .post_recv = mlx5_ib_post_recv_nodrain,
3788 .post_send = mlx5_ib_post_send_nodrain,
3789 .post_srq_recv = mlx5_ib_post_srq_recv,
3790 .process_mad = mlx5_ib_process_mad,
3791 .query_ah = mlx5_ib_query_ah,
3792 .query_device = mlx5_ib_query_device,
3793 .query_gid = mlx5_ib_query_gid,
3794 .query_pkey = mlx5_ib_query_pkey,
3795 .query_qp = mlx5_ib_query_qp,
3796 .query_srq = mlx5_ib_query_srq,
3797 .query_ucontext = mlx5_ib_query_ucontext,
3798 .reg_user_mr = mlx5_ib_reg_user_mr,
3799 .reg_user_mr_dmabuf = mlx5_ib_reg_user_mr_dmabuf,
3800 .req_notify_cq = mlx5_ib_arm_cq,
3801 .rereg_user_mr = mlx5_ib_rereg_user_mr,
3802 .resize_cq = mlx5_ib_resize_cq,
3803
3804 INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah),
3805 INIT_RDMA_OBJ_SIZE(ib_counters, mlx5_ib_mcounters, ibcntrs),
3806 INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq),
3807 INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd),
3808 INIT_RDMA_OBJ_SIZE(ib_qp, mlx5_ib_qp, ibqp),
3809 INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq),
3810 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext),
3811 };
3812
3813 static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = {
3814 .rdma_netdev_get_params = mlx5_ib_rn_get_params,
3815 };
3816
3817 static const struct ib_device_ops mlx5_ib_dev_sriov_ops = {
3818 .get_vf_config = mlx5_ib_get_vf_config,
3819 .get_vf_guid = mlx5_ib_get_vf_guid,
3820 .get_vf_stats = mlx5_ib_get_vf_stats,
3821 .set_vf_guid = mlx5_ib_set_vf_guid,
3822 .set_vf_link_state = mlx5_ib_set_vf_link_state,
3823 };
3824
3825 static const struct ib_device_ops mlx5_ib_dev_mw_ops = {
3826 .alloc_mw = mlx5_ib_alloc_mw,
3827 .dealloc_mw = mlx5_ib_dealloc_mw,
3828
3829 INIT_RDMA_OBJ_SIZE(ib_mw, mlx5_ib_mw, ibmw),
3830 };
3831
3832 static const struct ib_device_ops mlx5_ib_dev_xrc_ops = {
3833 .alloc_xrcd = mlx5_ib_alloc_xrcd,
3834 .dealloc_xrcd = mlx5_ib_dealloc_xrcd,
3835
3836 INIT_RDMA_OBJ_SIZE(ib_xrcd, mlx5_ib_xrcd, ibxrcd),
3837 };
3838
3839 static int mlx5_ib_init_var_table(struct mlx5_ib_dev *dev)
3840 {
3841 struct mlx5_core_dev *mdev = dev->mdev;
3842 struct mlx5_var_table *var_table = &dev->var_table;
3843 u8 log_doorbell_bar_size;
3844 u8 log_doorbell_stride;
3845 u64 bar_size;
3846
3847 log_doorbell_bar_size = MLX5_CAP_DEV_VDPA_EMULATION(mdev,
3848 log_doorbell_bar_size);
3849 log_doorbell_stride = MLX5_CAP_DEV_VDPA_EMULATION(mdev,
3850 log_doorbell_stride);
3851 var_table->hw_start_addr = dev->mdev->bar_addr +
3852 MLX5_CAP64_DEV_VDPA_EMULATION(mdev,
3853 doorbell_bar_offset);
3854 bar_size = (1ULL << log_doorbell_bar_size) * 4096;
3855 var_table->stride_size = 1ULL << log_doorbell_stride;
3856 var_table->num_var_hw_entries = div_u64(bar_size,
3857 var_table->stride_size);
3858 mutex_init(&var_table->bitmap_lock);
3859 var_table->bitmap = bitmap_zalloc(var_table->num_var_hw_entries,
3860 GFP_KERNEL);
3861 return (var_table->bitmap) ? 0 : -ENOMEM;
3862 }
3863
3864 static void mlx5_ib_stage_caps_cleanup(struct mlx5_ib_dev *dev)
3865 {
3866 bitmap_free(dev->var_table.bitmap);
3867 }
3868
3869 static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
3870 {
3871 struct mlx5_core_dev *mdev = dev->mdev;
3872 int err;
3873
3874 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
3875 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB))
3876 ib_set_device_ops(&dev->ib_dev,
3877 &mlx5_ib_dev_ipoib_enhanced_ops);
3878
3879 if (mlx5_core_is_pf(mdev))
3880 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops);
3881
3882 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
3883
3884 if (MLX5_CAP_GEN(mdev, imaicl))
3885 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops);
3886
3887 if (MLX5_CAP_GEN(mdev, xrc))
3888 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops);
3889
3890 if (MLX5_CAP_DEV_MEM(mdev, memic) ||
3891 MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
3892 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM)
3893 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops);
3894
3895 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops);
3896
3897 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS))
3898 dev->ib_dev.driver_def = mlx5_ib_defs;
3899
3900 err = init_node_data(dev);
3901 if (err)
3902 return err;
3903
3904 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
3905 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
3906 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
3907 mutex_init(&dev->lb.mutex);
3908
3909 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
3910 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) {
3911 err = mlx5_ib_init_var_table(dev);
3912 if (err)
3913 return err;
3914 }
3915
3916 dev->ib_dev.use_cq_dim = true;
3917
3918 return 0;
3919 }
3920
3921 static const struct ib_device_ops mlx5_ib_dev_port_ops = {
3922 .get_port_immutable = mlx5_port_immutable,
3923 .query_port = mlx5_ib_query_port,
3924 };
3925
3926 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
3927 {
3928 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops);
3929 return 0;
3930 }
3931
3932 static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = {
3933 .get_port_immutable = mlx5_port_rep_immutable,
3934 .query_port = mlx5_ib_rep_query_port,
3935 .query_pkey = mlx5_ib_rep_query_pkey,
3936 };
3937
3938 static int mlx5_ib_stage_raw_eth_non_default_cb(struct mlx5_ib_dev *dev)
3939 {
3940 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops);
3941 return 0;
3942 }
3943
3944 static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = {
3945 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table,
3946 .create_wq = mlx5_ib_create_wq,
3947 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table,
3948 .destroy_wq = mlx5_ib_destroy_wq,
3949 .get_netdev = mlx5_ib_get_netdev,
3950 .modify_wq = mlx5_ib_modify_wq,
3951
3952 INIT_RDMA_OBJ_SIZE(ib_rwq_ind_table, mlx5_ib_rwq_ind_table,
3953 ib_rwq_ind_tbl),
3954 };
3955
3956 static int mlx5_ib_roce_init(struct mlx5_ib_dev *dev)
3957 {
3958 struct mlx5_core_dev *mdev = dev->mdev;
3959 enum rdma_link_layer ll;
3960 int port_type_cap;
3961 u32 port_num = 0;
3962 int err;
3963
3964 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
3965 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
3966
3967 if (ll == IB_LINK_LAYER_ETHERNET) {
3968 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops);
3969
3970 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
3971
3972 /* Register only for native ports */
3973 err = mlx5_add_netdev_notifier(dev, port_num);
3974 if (err || dev->is_rep || !mlx5_is_roce_init_enabled(mdev))
3975 /*
3976 * We don't enable ETH interface for
3977 * 1. IB representors
3978 * 2. User disabled ROCE through devlink interface
3979 */
3980 return err;
3981
3982 err = mlx5_enable_eth(dev);
3983 if (err)
3984 goto cleanup;
3985 }
3986
3987 return 0;
3988 cleanup:
3989 mlx5_remove_netdev_notifier(dev, port_num);
3990 return err;
3991 }
3992
3993 static void mlx5_ib_roce_cleanup(struct mlx5_ib_dev *dev)
3994 {
3995 struct mlx5_core_dev *mdev = dev->mdev;
3996 enum rdma_link_layer ll;
3997 int port_type_cap;
3998 u32 port_num;
3999
4000 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
4001 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
4002
4003 if (ll == IB_LINK_LAYER_ETHERNET) {
4004 if (!dev->is_rep)
4005 mlx5_disable_eth(dev);
4006
4007 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
4008 mlx5_remove_netdev_notifier(dev, port_num);
4009 }
4010 }
4011
4012 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
4013 {
4014 mlx5_ib_init_cong_debugfs(dev,
4015 mlx5_core_native_port_num(dev->mdev) - 1);
4016 return 0;
4017 }
4018
4019 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
4020 {
4021 mlx5_ib_cleanup_cong_debugfs(dev,
4022 mlx5_core_native_port_num(dev->mdev) - 1);
4023 }
4024
4025 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
4026 {
4027 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
4028 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar);
4029 }
4030
4031 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
4032 {
4033 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
4034 }
4035
4036 static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
4037 {
4038 int err;
4039
4040 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
4041 if (err)
4042 return err;
4043
4044 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
4045 if (err)
4046 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4047
4048 return err;
4049 }
4050
4051 static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
4052 {
4053 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
4054 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
4055 }
4056
4057 static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
4058 {
4059 const char *name;
4060
4061 if (!mlx5_lag_is_roce(dev->mdev))
4062 name = "mlx5_%d";
4063 else
4064 name = "mlx5_bond_%d";
4065 return ib_register_device(&dev->ib_dev, name, &dev->mdev->pdev->dev);
4066 }
4067
4068 static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
4069 {
4070 int err;
4071
4072 err = mlx5_mr_cache_cleanup(dev);
4073 if (err)
4074 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
4075
4076 if (dev->umrc.qp)
4077 ib_destroy_qp(dev->umrc.qp);
4078 if (dev->umrc.cq)
4079 ib_free_cq(dev->umrc.cq);
4080 if (dev->umrc.pd)
4081 ib_dealloc_pd(dev->umrc.pd);
4082 }
4083
4084 static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
4085 {
4086 ib_unregister_device(&dev->ib_dev);
4087 }
4088
4089 enum {
4090 MAX_UMR_WR = 128,
4091 };
4092
4093 static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
4094 {
4095 struct ib_qp_init_attr *init_attr = NULL;
4096 struct ib_qp_attr *attr = NULL;
4097 struct ib_pd *pd;
4098 struct ib_cq *cq;
4099 struct ib_qp *qp;
4100 int ret;
4101
4102 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
4103 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
4104 if (!attr || !init_attr) {
4105 ret = -ENOMEM;
4106 goto error_0;
4107 }
4108
4109 pd = ib_alloc_pd(&dev->ib_dev, 0);
4110 if (IS_ERR(pd)) {
4111 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
4112 ret = PTR_ERR(pd);
4113 goto error_0;
4114 }
4115
4116 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
4117 if (IS_ERR(cq)) {
4118 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
4119 ret = PTR_ERR(cq);
4120 goto error_2;
4121 }
4122
4123 init_attr->send_cq = cq;
4124 init_attr->recv_cq = cq;
4125 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
4126 init_attr->cap.max_send_wr = MAX_UMR_WR;
4127 init_attr->cap.max_send_sge = 1;
4128 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
4129 init_attr->port_num = 1;
4130 qp = ib_create_qp(pd, init_attr);
4131 if (IS_ERR(qp)) {
4132 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
4133 ret = PTR_ERR(qp);
4134 goto error_3;
4135 }
4136
4137 attr->qp_state = IB_QPS_INIT;
4138 attr->port_num = 1;
4139 ret = ib_modify_qp(qp, attr,
4140 IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT);
4141 if (ret) {
4142 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
4143 goto error_4;
4144 }
4145
4146 memset(attr, 0, sizeof(*attr));
4147 attr->qp_state = IB_QPS_RTR;
4148 attr->path_mtu = IB_MTU_256;
4149
4150 ret = ib_modify_qp(qp, attr, IB_QP_STATE);
4151 if (ret) {
4152 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
4153 goto error_4;
4154 }
4155
4156 memset(attr, 0, sizeof(*attr));
4157 attr->qp_state = IB_QPS_RTS;
4158 ret = ib_modify_qp(qp, attr, IB_QP_STATE);
4159 if (ret) {
4160 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
4161 goto error_4;
4162 }
4163
4164 dev->umrc.qp = qp;
4165 dev->umrc.cq = cq;
4166 dev->umrc.pd = pd;
4167
4168 sema_init(&dev->umrc.sem, MAX_UMR_WR);
4169 ret = mlx5_mr_cache_init(dev);
4170 if (ret) {
4171 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
4172 goto error_4;
4173 }
4174
4175 kfree(attr);
4176 kfree(init_attr);
4177
4178 return 0;
4179
4180 error_4:
4181 ib_destroy_qp(qp);
4182 dev->umrc.qp = NULL;
4183
4184 error_3:
4185 ib_free_cq(cq);
4186 dev->umrc.cq = NULL;
4187
4188 error_2:
4189 ib_dealloc_pd(pd);
4190 dev->umrc.pd = NULL;
4191
4192 error_0:
4193 kfree(attr);
4194 kfree(init_attr);
4195 return ret;
4196 }
4197
4198 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
4199 {
4200 struct dentry *root;
4201
4202 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4203 return 0;
4204
4205 mutex_init(&dev->delay_drop.lock);
4206 dev->delay_drop.dev = dev;
4207 dev->delay_drop.activate = false;
4208 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
4209 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
4210 atomic_set(&dev->delay_drop.rqs_cnt, 0);
4211 atomic_set(&dev->delay_drop.events_cnt, 0);
4212
4213 if (!mlx5_debugfs_root)
4214 return 0;
4215
4216 root = debugfs_create_dir("delay_drop", dev->mdev->priv.dbg_root);
4217 dev->delay_drop.dir_debugfs = root;
4218
4219 debugfs_create_atomic_t("num_timeout_events", 0400, root,
4220 &dev->delay_drop.events_cnt);
4221 debugfs_create_atomic_t("num_rqs", 0400, root,
4222 &dev->delay_drop.rqs_cnt);
4223 debugfs_create_file("timeout", 0600, root, &dev->delay_drop,
4224 &fops_delay_drop_timeout);
4225 return 0;
4226 }
4227
4228 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
4229 {
4230 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
4231 return;
4232
4233 cancel_work_sync(&dev->delay_drop.delay_drop_work);
4234 if (!dev->delay_drop.dir_debugfs)
4235 return;
4236
4237 debugfs_remove_recursive(dev->delay_drop.dir_debugfs);
4238 dev->delay_drop.dir_debugfs = NULL;
4239 }
4240
4241 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev)
4242 {
4243 dev->mdev_events.notifier_call = mlx5_ib_event;
4244 mlx5_notifier_register(dev->mdev, &dev->mdev_events);
4245 return 0;
4246 }
4247
4248 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev)
4249 {
4250 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events);
4251 }
4252
4253 void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
4254 const struct mlx5_ib_profile *profile,
4255 int stage)
4256 {
4257 dev->ib_active = false;
4258
4259 /* Number of stages to cleanup */
4260 while (stage) {
4261 stage--;
4262 if (profile->stage[stage].cleanup)
4263 profile->stage[stage].cleanup(dev);
4264 }
4265
4266 kfree(dev->port);
4267 ib_dealloc_device(&dev->ib_dev);
4268 }
4269
4270 int __mlx5_ib_add(struct mlx5_ib_dev *dev,
4271 const struct mlx5_ib_profile *profile)
4272 {
4273 int err;
4274 int i;
4275
4276 dev->profile = profile;
4277
4278 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
4279 if (profile->stage[i].init) {
4280 err = profile->stage[i].init(dev);
4281 if (err)
4282 goto err_out;
4283 }
4284 }
4285
4286 dev->ib_active = true;
4287 return 0;
4288
4289 err_out:
4290 /* Clean up stages which were initialized */
4291 while (i) {
4292 i--;
4293 if (profile->stage[i].cleanup)
4294 profile->stage[i].cleanup(dev);
4295 }
4296 return -ENOMEM;
4297 }
4298
4299 static const struct mlx5_ib_profile pf_profile = {
4300 STAGE_CREATE(MLX5_IB_STAGE_INIT,
4301 mlx5_ib_stage_init_init,
4302 mlx5_ib_stage_init_cleanup),
4303 STAGE_CREATE(MLX5_IB_STAGE_FS,
4304 mlx5_ib_fs_init,
4305 mlx5_ib_fs_cleanup),
4306 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
4307 mlx5_ib_stage_caps_init,
4308 mlx5_ib_stage_caps_cleanup),
4309 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
4310 mlx5_ib_stage_non_default_cb,
4311 NULL),
4312 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
4313 mlx5_ib_roce_init,
4314 mlx5_ib_roce_cleanup),
4315 STAGE_CREATE(MLX5_IB_STAGE_QP,
4316 mlx5_init_qp_table,
4317 mlx5_cleanup_qp_table),
4318 STAGE_CREATE(MLX5_IB_STAGE_SRQ,
4319 mlx5_init_srq_table,
4320 mlx5_cleanup_srq_table),
4321 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
4322 mlx5_ib_dev_res_init,
4323 mlx5_ib_dev_res_cleanup),
4324 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
4325 mlx5_ib_stage_dev_notifier_init,
4326 mlx5_ib_stage_dev_notifier_cleanup),
4327 STAGE_CREATE(MLX5_IB_STAGE_ODP,
4328 mlx5_ib_odp_init_one,
4329 mlx5_ib_odp_cleanup_one),
4330 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
4331 mlx5_ib_counters_init,
4332 mlx5_ib_counters_cleanup),
4333 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
4334 mlx5_ib_stage_cong_debugfs_init,
4335 mlx5_ib_stage_cong_debugfs_cleanup),
4336 STAGE_CREATE(MLX5_IB_STAGE_UAR,
4337 mlx5_ib_stage_uar_init,
4338 mlx5_ib_stage_uar_cleanup),
4339 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
4340 mlx5_ib_stage_bfrag_init,
4341 mlx5_ib_stage_bfrag_cleanup),
4342 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
4343 NULL,
4344 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
4345 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
4346 mlx5_ib_devx_init,
4347 mlx5_ib_devx_cleanup),
4348 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
4349 mlx5_ib_stage_ib_reg_init,
4350 mlx5_ib_stage_ib_reg_cleanup),
4351 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
4352 mlx5_ib_stage_post_ib_reg_umr_init,
4353 NULL),
4354 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
4355 mlx5_ib_stage_delay_drop_init,
4356 mlx5_ib_stage_delay_drop_cleanup),
4357 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK,
4358 mlx5_ib_restrack_init,
4359 NULL),
4360 };
4361
4362 const struct mlx5_ib_profile raw_eth_profile = {
4363 STAGE_CREATE(MLX5_IB_STAGE_INIT,
4364 mlx5_ib_stage_init_init,
4365 mlx5_ib_stage_init_cleanup),
4366 STAGE_CREATE(MLX5_IB_STAGE_FS,
4367 mlx5_ib_fs_init,
4368 mlx5_ib_fs_cleanup),
4369 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
4370 mlx5_ib_stage_caps_init,
4371 mlx5_ib_stage_caps_cleanup),
4372 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
4373 mlx5_ib_stage_raw_eth_non_default_cb,
4374 NULL),
4375 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
4376 mlx5_ib_roce_init,
4377 mlx5_ib_roce_cleanup),
4378 STAGE_CREATE(MLX5_IB_STAGE_QP,
4379 mlx5_init_qp_table,
4380 mlx5_cleanup_qp_table),
4381 STAGE_CREATE(MLX5_IB_STAGE_SRQ,
4382 mlx5_init_srq_table,
4383 mlx5_cleanup_srq_table),
4384 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
4385 mlx5_ib_dev_res_init,
4386 mlx5_ib_dev_res_cleanup),
4387 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER,
4388 mlx5_ib_stage_dev_notifier_init,
4389 mlx5_ib_stage_dev_notifier_cleanup),
4390 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
4391 mlx5_ib_counters_init,
4392 mlx5_ib_counters_cleanup),
4393 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
4394 mlx5_ib_stage_cong_debugfs_init,
4395 mlx5_ib_stage_cong_debugfs_cleanup),
4396 STAGE_CREATE(MLX5_IB_STAGE_UAR,
4397 mlx5_ib_stage_uar_init,
4398 mlx5_ib_stage_uar_cleanup),
4399 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
4400 mlx5_ib_stage_bfrag_init,
4401 mlx5_ib_stage_bfrag_cleanup),
4402 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
4403 NULL,
4404 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
4405 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID,
4406 mlx5_ib_devx_init,
4407 mlx5_ib_devx_cleanup),
4408 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
4409 mlx5_ib_stage_ib_reg_init,
4410 mlx5_ib_stage_ib_reg_cleanup),
4411 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
4412 mlx5_ib_stage_post_ib_reg_umr_init,
4413 NULL),
4414 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK,
4415 mlx5_ib_restrack_init,
4416 NULL),
4417 };
4418
4419 static int mlx5r_mp_probe(struct auxiliary_device *adev,
4420 const struct auxiliary_device_id *id)
4421 {
4422 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev);
4423 struct mlx5_core_dev *mdev = idev->mdev;
4424 struct mlx5_ib_multiport_info *mpi;
4425 struct mlx5_ib_dev *dev;
4426 bool bound = false;
4427 int err;
4428
4429 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
4430 if (!mpi)
4431 return -ENOMEM;
4432
4433 mpi->mdev = mdev;
4434 err = mlx5_query_nic_vport_system_image_guid(mdev,
4435 &mpi->sys_image_guid);
4436 if (err) {
4437 kfree(mpi);
4438 return err;
4439 }
4440
4441 mutex_lock(&mlx5_ib_multiport_mutex);
4442 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
4443 if (dev->sys_image_guid == mpi->sys_image_guid)
4444 bound = mlx5_ib_bind_slave_port(dev, mpi);
4445
4446 if (bound) {
4447 rdma_roce_rescan_device(&dev->ib_dev);
4448 mpi->ibdev->ib_active = true;
4449 break;
4450 }
4451 }
4452
4453 if (!bound) {
4454 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
4455 dev_dbg(mdev->device,
4456 "no suitable IB device found to bind to, added to unaffiliated list.\n");
4457 }
4458 mutex_unlock(&mlx5_ib_multiport_mutex);
4459
4460 dev_set_drvdata(&adev->dev, mpi);
4461 return 0;
4462 }
4463
4464 static void mlx5r_mp_remove(struct auxiliary_device *adev)
4465 {
4466 struct mlx5_ib_multiport_info *mpi;
4467
4468 mpi = dev_get_drvdata(&adev->dev);
4469 mutex_lock(&mlx5_ib_multiport_mutex);
4470 if (mpi->ibdev)
4471 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
4472 list_del(&mpi->list);
4473 mutex_unlock(&mlx5_ib_multiport_mutex);
4474 kfree(mpi);
4475 }
4476
4477 static int mlx5r_probe(struct auxiliary_device *adev,
4478 const struct auxiliary_device_id *id)
4479 {
4480 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev);
4481 struct mlx5_core_dev *mdev = idev->mdev;
4482 const struct mlx5_ib_profile *profile;
4483 int port_type_cap, num_ports, ret;
4484 enum rdma_link_layer ll;
4485 struct mlx5_ib_dev *dev;
4486
4487 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
4488 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
4489
4490 num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
4491 MLX5_CAP_GEN(mdev, num_vhca_ports));
4492 dev = ib_alloc_device(mlx5_ib_dev, ib_dev);
4493 if (!dev)
4494 return -ENOMEM;
4495 dev->port = kcalloc(num_ports, sizeof(*dev->port),
4496 GFP_KERNEL);
4497 if (!dev->port) {
4498 ib_dealloc_device(&dev->ib_dev);
4499 return -ENOMEM;
4500 }
4501
4502 dev->mdev = mdev;
4503 dev->num_ports = num_ports;
4504
4505 if (ll == IB_LINK_LAYER_ETHERNET && !mlx5_is_roce_init_enabled(mdev))
4506 profile = &raw_eth_profile;
4507 else
4508 profile = &pf_profile;
4509
4510 ret = __mlx5_ib_add(dev, profile);
4511 if (ret) {
4512 kfree(dev->port);
4513 ib_dealloc_device(&dev->ib_dev);
4514 return ret;
4515 }
4516
4517 dev_set_drvdata(&adev->dev, dev);
4518 return 0;
4519 }
4520
4521 static void mlx5r_remove(struct auxiliary_device *adev)
4522 {
4523 struct mlx5_ib_dev *dev;
4524
4525 dev = dev_get_drvdata(&adev->dev);
4526 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
4527 }
4528
4529 static const struct auxiliary_device_id mlx5r_mp_id_table[] = {
4530 { .name = MLX5_ADEV_NAME ".multiport", },
4531 {},
4532 };
4533
4534 static const struct auxiliary_device_id mlx5r_id_table[] = {
4535 { .name = MLX5_ADEV_NAME ".rdma", },
4536 {},
4537 };
4538
4539 MODULE_DEVICE_TABLE(auxiliary, mlx5r_mp_id_table);
4540 MODULE_DEVICE_TABLE(auxiliary, mlx5r_id_table);
4541
4542 static struct auxiliary_driver mlx5r_mp_driver = {
4543 .name = "multiport",
4544 .probe = mlx5r_mp_probe,
4545 .remove = mlx5r_mp_remove,
4546 .id_table = mlx5r_mp_id_table,
4547 };
4548
4549 static struct auxiliary_driver mlx5r_driver = {
4550 .name = "rdma",
4551 .probe = mlx5r_probe,
4552 .remove = mlx5r_remove,
4553 .id_table = mlx5r_id_table,
4554 };
4555
4556 static int __init mlx5_ib_init(void)
4557 {
4558 int ret;
4559
4560 xlt_emergency_page = (void *)__get_free_page(GFP_KERNEL);
4561 if (!xlt_emergency_page)
4562 return -ENOMEM;
4563
4564 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
4565 if (!mlx5_ib_event_wq) {
4566 free_page((unsigned long)xlt_emergency_page);
4567 return -ENOMEM;
4568 }
4569
4570 mlx5_ib_odp_init();
4571 ret = mlx5r_rep_init();
4572 if (ret)
4573 goto rep_err;
4574 ret = auxiliary_driver_register(&mlx5r_mp_driver);
4575 if (ret)
4576 goto mp_err;
4577 ret = auxiliary_driver_register(&mlx5r_driver);
4578 if (ret)
4579 goto drv_err;
4580 return 0;
4581
4582 drv_err:
4583 auxiliary_driver_unregister(&mlx5r_mp_driver);
4584 mp_err:
4585 mlx5r_rep_cleanup();
4586 rep_err:
4587 destroy_workqueue(mlx5_ib_event_wq);
4588 free_page((unsigned long)xlt_emergency_page);
4589 return ret;
4590 }
4591
4592 static void __exit mlx5_ib_cleanup(void)
4593 {
4594 auxiliary_driver_unregister(&mlx5r_driver);
4595 auxiliary_driver_unregister(&mlx5r_mp_driver);
4596 mlx5r_rep_cleanup();
4597
4598 destroy_workqueue(mlx5_ib_event_wq);
4599 free_page((unsigned long)xlt_emergency_page);
4600 }
4601
4602 module_init(mlx5_ib_init);
4603 module_exit(mlx5_ib_cleanup);
Ubuntu Jammy Linux kernel mirror